1 /* 2 * Copyright (c) 2015-2020 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef __CE_REG_H__ 21 #define __CE_REG_H__ 22 23 #define COPY_ENGINE_ID(COPY_ENGINE_BASE_ADDRESS) ((COPY_ENGINE_BASE_ADDRESS \ 24 - CE0_BASE_ADDRESS)/(CE1_BASE_ADDRESS - CE0_BASE_ADDRESS)) 25 26 #define DST_WR_INDEX_ADDRESS (scn->target_ce_def->d_DST_WR_INDEX_ADDRESS) 27 #define SRC_WATERMARK_ADDRESS (scn->target_ce_def->d_SRC_WATERMARK_ADDRESS) 28 #define SRC_WATERMARK_LOW_MASK (scn->target_ce_def->d_SRC_WATERMARK_LOW_MASK) 29 #define SRC_WATERMARK_HIGH_MASK (scn->target_ce_def->d_SRC_WATERMARK_HIGH_MASK) 30 #define DST_WATERMARK_LOW_MASK (scn->target_ce_def->d_DST_WATERMARK_LOW_MASK) 31 #define DST_WATERMARK_HIGH_MASK (scn->target_ce_def->d_DST_WATERMARK_HIGH_MASK) 32 #define CURRENT_SRRI_ADDRESS (scn->target_ce_def->d_CURRENT_SRRI_ADDRESS) 33 #define CURRENT_DRRI_ADDRESS (scn->target_ce_def->d_CURRENT_DRRI_ADDRESS) 34 35 #define SHADOW_VALUE0 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_0) 36 #define SHADOW_VALUE1 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_1) 37 #define SHADOW_VALUE2 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_2) 38 #define SHADOW_VALUE3 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_3) 39 #define SHADOW_VALUE4 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_4) 40 #define SHADOW_VALUE5 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_5) 41 #define SHADOW_VALUE6 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_6) 42 #define SHADOW_VALUE7 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_7) 43 #define SHADOW_VALUE8 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_8) 44 #define SHADOW_VALUE9 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_9) 45 #define SHADOW_VALUE10 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_10) 46 #define SHADOW_VALUE11 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_11) 47 #define SHADOW_VALUE12 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_12) 48 #define SHADOW_VALUE13 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_13) 49 #define SHADOW_VALUE14 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_14) 50 #define SHADOW_VALUE15 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_15) 51 #define SHADOW_VALUE16 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_16) 52 #define SHADOW_VALUE17 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_17) 53 #define SHADOW_VALUE18 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_18) 54 #define SHADOW_VALUE19 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_19) 55 #define SHADOW_VALUE20 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_20) 56 #define SHADOW_VALUE21 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_21) 57 #define SHADOW_VALUE22 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_22) 58 #define SHADOW_VALUE23 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_23) 59 #define SHADOW_ADDRESS0 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_0) 60 #define SHADOW_ADDRESS1 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_1) 61 #define SHADOW_ADDRESS2 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_2) 62 #define SHADOW_ADDRESS3 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_3) 63 #define SHADOW_ADDRESS4 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_4) 64 #define SHADOW_ADDRESS5 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_5) 65 #define SHADOW_ADDRESS6 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_6) 66 #define SHADOW_ADDRESS7 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_7) 67 #define SHADOW_ADDRESS8 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_8) 68 #define SHADOW_ADDRESS9 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_9) 69 #define SHADOW_ADDRESS10 \ 70 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_10) 71 #define SHADOW_ADDRESS11 \ 72 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_11) 73 #define SHADOW_ADDRESS12 \ 74 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_12) 75 #define SHADOW_ADDRESS13 \ 76 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_13) 77 #define SHADOW_ADDRESS14 \ 78 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_14) 79 #define SHADOW_ADDRESS15 \ 80 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_15) 81 #define SHADOW_ADDRESS16 \ 82 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_16) 83 #define SHADOW_ADDRESS17 \ 84 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_17) 85 #define SHADOW_ADDRESS18 \ 86 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_18) 87 #define SHADOW_ADDRESS19 \ 88 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_19) 89 #define SHADOW_ADDRESS20 \ 90 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_20) 91 #define SHADOW_ADDRESS21 \ 92 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_21) 93 #define SHADOW_ADDRESS22 \ 94 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_22) 95 #define SHADOW_ADDRESS23 \ 96 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_23) 97 98 #define SHADOW_ADDRESS(i) \ 99 (SHADOW_ADDRESS0 + i*(SHADOW_ADDRESS1-SHADOW_ADDRESS0)) 100 101 #define HOST_IS_SRC_RING_HIGH_WATERMARK_MASK \ 102 (scn->target_ce_def->d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK) 103 #define HOST_IS_SRC_RING_LOW_WATERMARK_MASK \ 104 (scn->target_ce_def->d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK) 105 #define HOST_IS_DST_RING_HIGH_WATERMARK_MASK \ 106 (scn->target_ce_def->d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK) 107 #define HOST_IS_DST_RING_LOW_WATERMARK_MASK \ 108 (scn->target_ce_def->d_HOST_IS_DST_RING_LOW_WATERMARK_MASK) 109 #define MISC_IS_ADDRESS (scn->target_ce_def->d_MISC_IS_ADDRESS) 110 #define HOST_IS_COPY_COMPLETE_MASK \ 111 (scn->target_ce_def->d_HOST_IS_COPY_COMPLETE_MASK) 112 #define CE_WRAPPER_BASE_ADDRESS (scn->target_ce_def->d_CE_WRAPPER_BASE_ADDRESS) 113 #define CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS \ 114 (scn->target_ce_def->d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS) 115 #define CE_DDR_ADDRESS_FOR_RRI_LOW \ 116 (scn->target_ce_def->d_CE_DDR_ADDRESS_FOR_RRI_LOW) 117 #define CE_DDR_ADDRESS_FOR_RRI_HIGH \ 118 (scn->target_ce_def->d_CE_DDR_ADDRESS_FOR_RRI_HIGH) 119 #define HOST_IE_COPY_COMPLETE_MASK \ 120 (scn->target_ce_def->d_HOST_IE_COPY_COMPLETE_MASK) 121 #define SR_BA_ADDRESS (scn->target_ce_def->d_SR_BA_ADDRESS) 122 #define SR_BA_ADDRESS_HIGH (scn->target_ce_def->d_SR_BA_ADDRESS_HIGH) 123 #define SR_SIZE_ADDRESS (scn->target_ce_def->d_SR_SIZE_ADDRESS) 124 #define CE_CTRL1_ADDRESS (scn->target_ce_def->d_CE_CTRL1_ADDRESS) 125 #define CE_CTRL1_DMAX_LENGTH_MASK \ 126 (scn->target_ce_def->d_CE_CTRL1_DMAX_LENGTH_MASK) 127 #define DR_BA_ADDRESS (scn->target_ce_def->d_DR_BA_ADDRESS) 128 #define DR_BA_ADDRESS_HIGH (scn->target_ce_def->d_DR_BA_ADDRESS_HIGH) 129 #define DR_SIZE_ADDRESS (scn->target_ce_def->d_DR_SIZE_ADDRESS) 130 #define CE_CMD_REGISTER (scn->target_ce_def->d_CE_CMD_REGISTER) 131 #define CE_MSI_ADDRESS (scn->target_ce_def->d_CE_MSI_ADDRESS) 132 #define CE_MSI_ADDRESS_HIGH (scn->target_ce_def->d_CE_MSI_ADDRESS_HIGH) 133 #define CE_MSI_DATA (scn->target_ce_def->d_CE_MSI_DATA) 134 #define CE_MSI_ENABLE_BIT (scn->target_ce_def->d_CE_MSI_ENABLE_BIT) 135 #define MISC_IE_ADDRESS (scn->target_ce_def->d_MISC_IE_ADDRESS) 136 #define MISC_IS_AXI_ERR_MASK (scn->target_ce_def->d_MISC_IS_AXI_ERR_MASK) 137 #define MISC_IS_DST_ADDR_ERR_MASK \ 138 (scn->target_ce_def->d_MISC_IS_DST_ADDR_ERR_MASK) 139 #define MISC_IS_SRC_LEN_ERR_MASK \ 140 (scn->target_ce_def->d_MISC_IS_SRC_LEN_ERR_MASK) 141 #define MISC_IS_DST_MAX_LEN_VIO_MASK \ 142 (scn->target_ce_def->d_MISC_IS_DST_MAX_LEN_VIO_MASK) 143 #define MISC_IS_DST_RING_OVERFLOW_MASK \ 144 (scn->target_ce_def->d_MISC_IS_DST_RING_OVERFLOW_MASK) 145 #define MISC_IS_SRC_RING_OVERFLOW_MASK \ 146 (scn->target_ce_def->d_MISC_IS_SRC_RING_OVERFLOW_MASK) 147 #define SRC_WATERMARK_LOW_LSB (scn->target_ce_def->d_SRC_WATERMARK_LOW_LSB) 148 #define SRC_WATERMARK_HIGH_LSB (scn->target_ce_def->d_SRC_WATERMARK_HIGH_LSB) 149 #define DST_WATERMARK_LOW_LSB (scn->target_ce_def->d_DST_WATERMARK_LOW_LSB) 150 #define DST_WATERMARK_HIGH_LSB (scn->target_ce_def->d_DST_WATERMARK_HIGH_LSB) 151 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK \ 152 (scn->target_ce_def->d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK) 153 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB \ 154 (scn->target_ce_def->d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB) 155 #define CE_CTRL1_DMAX_LENGTH_LSB \ 156 (scn->target_ce_def->d_CE_CTRL1_DMAX_LENGTH_LSB) 157 #define CE_CTRL1_IDX_UPD_EN (scn->target_ce_def->d_CE_CTRL1_IDX_UPD_EN_MASK) 158 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK \ 159 (scn->target_ce_def->d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) 160 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK \ 161 (scn->target_ce_def->d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK) 162 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB \ 163 (scn->target_ce_def->d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB) 164 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB \ 165 (scn->target_ce_def->d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB) 166 #define WLAN_DEBUG_INPUT_SEL_OFFSET \ 167 (scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_OFFSET) 168 #define WLAN_DEBUG_INPUT_SEL_SRC_MSB \ 169 (scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_SRC_MSB) 170 #define WLAN_DEBUG_INPUT_SEL_SRC_LSB \ 171 (scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_SRC_LSB) 172 #define WLAN_DEBUG_INPUT_SEL_SRC_MASK \ 173 (scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_SRC_MASK) 174 #define WLAN_DEBUG_CONTROL_OFFSET (scn->targetdef->d_WLAN_DEBUG_CONTROL_OFFSET) 175 #define WLAN_DEBUG_CONTROL_ENABLE_MSB \ 176 (scn->targetdef->d_WLAN_DEBUG_CONTROL_ENABLE_MSB) 177 #define WLAN_DEBUG_CONTROL_ENABLE_LSB \ 178 (scn->targetdef->d_WLAN_DEBUG_CONTROL_ENABLE_LSB) 179 #define WLAN_DEBUG_CONTROL_ENABLE_MASK \ 180 (scn->targetdef->d_WLAN_DEBUG_CONTROL_ENABLE_MASK) 181 #define WLAN_DEBUG_OUT_OFFSET (scn->targetdef->d_WLAN_DEBUG_OUT_OFFSET) 182 #define WLAN_DEBUG_OUT_DATA_MSB (scn->targetdef->d_WLAN_DEBUG_OUT_DATA_MSB) 183 #define WLAN_DEBUG_OUT_DATA_LSB (scn->targetdef->d_WLAN_DEBUG_OUT_DATA_LSB) 184 #define WLAN_DEBUG_OUT_DATA_MASK (scn->targetdef->d_WLAN_DEBUG_OUT_DATA_MASK) 185 #define AMBA_DEBUG_BUS_OFFSET (scn->targetdef->d_AMBA_DEBUG_BUS_OFFSET) 186 #define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB \ 187 (scn->targetdef->d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB) 188 #define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB \ 189 (scn->targetdef->d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB) 190 #define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK \ 191 (scn->targetdef->d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK) 192 #define AMBA_DEBUG_BUS_SEL_MSB (scn->targetdef->d_AMBA_DEBUG_BUS_SEL_MSB) 193 #define AMBA_DEBUG_BUS_SEL_LSB (scn->targetdef->d_AMBA_DEBUG_BUS_SEL_LSB) 194 #define AMBA_DEBUG_BUS_SEL_MASK (scn->targetdef->d_AMBA_DEBUG_BUS_SEL_MASK) 195 #define CE_WRAPPER_DEBUG_OFFSET \ 196 (scn->target_ce_def->d_CE_WRAPPER_DEBUG_OFFSET) 197 #define CE_WRAPPER_DEBUG_SEL_MSB \ 198 (scn->target_ce_def->d_CE_WRAPPER_DEBUG_SEL_MSB) 199 #define CE_WRAPPER_DEBUG_SEL_LSB \ 200 (scn->target_ce_def->d_CE_WRAPPER_DEBUG_SEL_LSB) 201 #define CE_WRAPPER_DEBUG_SEL_MASK \ 202 (scn->target_ce_def->d_CE_WRAPPER_DEBUG_SEL_MASK) 203 #define CE_DEBUG_OFFSET (scn->target_ce_def->d_CE_DEBUG_OFFSET) 204 #define CE_DEBUG_SEL_MSB (scn->target_ce_def->d_CE_DEBUG_SEL_MSB) 205 #define CE_DEBUG_SEL_LSB (scn->target_ce_def->d_CE_DEBUG_SEL_LSB) 206 #define CE_DEBUG_SEL_MASK (scn->target_ce_def->d_CE_DEBUG_SEL_MASK) 207 #define HOST_IE_ADDRESS (scn->target_ce_def->d_HOST_IE_ADDRESS) 208 #define HOST_IE_REG1_CE_LSB (scn->target_ce_def->d_HOST_IE_REG1_CE_LSB) 209 #define HOST_IE_ADDRESS_2 (scn->target_ce_def->d_HOST_IE_ADDRESS_2) 210 #define HOST_IE_REG2_CE_LSB (scn->target_ce_def->d_HOST_IE_REG2_CE_LSB) 211 #define HOST_IE_ADDRESS_3 (scn->target_ce_def->d_HOST_IE_ADDRESS_3) 212 #define HOST_IE_REG3_CE_LSB (scn->target_ce_def->d_HOST_IE_REG3_CE_LSB) 213 #define HOST_IS_ADDRESS (scn->target_ce_def->d_HOST_IS_ADDRESS) 214 #define HOST_CE_ADDRESS (scn->target_ce_def->d_HOST_CE_ADDRESS) 215 #define HOST_CMEM_ADDRESS (scn->target_ce_def->d_HOST_CMEM_ADDRESS) 216 217 #define SRC_WATERMARK_LOW_SET(x) \ 218 (((x) << SRC_WATERMARK_LOW_LSB) & SRC_WATERMARK_LOW_MASK) 219 #define SRC_WATERMARK_HIGH_SET(x) \ 220 (((x) << SRC_WATERMARK_HIGH_LSB) & SRC_WATERMARK_HIGH_MASK) 221 #define DST_WATERMARK_LOW_SET(x) \ 222 (((x) << DST_WATERMARK_LOW_LSB) & DST_WATERMARK_LOW_MASK) 223 #define DST_WATERMARK_HIGH_SET(x) \ 224 (((x) << DST_WATERMARK_HIGH_LSB) & DST_WATERMARK_HIGH_MASK) 225 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET(x) \ 226 (((x) & CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK) >> \ 227 CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB) 228 #define CE_CTRL1_DMAX_LENGTH_SET(x) \ 229 (((x) << CE_CTRL1_DMAX_LENGTH_LSB) & CE_CTRL1_DMAX_LENGTH_MASK) 230 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SET(x) \ 231 (((x) << CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB) & \ 232 CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) 233 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_SET(x) \ 234 (((x) << CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB) & \ 235 CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK) 236 #define WLAN_DEBUG_INPUT_SEL_SRC_GET(x) \ 237 (((x) & WLAN_DEBUG_INPUT_SEL_SRC_MASK) >> \ 238 WLAN_DEBUG_INPUT_SEL_SRC_LSB) 239 #define WLAN_DEBUG_INPUT_SEL_SRC_SET(x) \ 240 (((x) << WLAN_DEBUG_INPUT_SEL_SRC_LSB) & \ 241 WLAN_DEBUG_INPUT_SEL_SRC_MASK) 242 #define WLAN_DEBUG_CONTROL_ENABLE_GET(x) \ 243 (((x) & WLAN_DEBUG_CONTROL_ENABLE_MASK) >> \ 244 WLAN_DEBUG_CONTROL_ENABLE_LSB) 245 #define WLAN_DEBUG_CONTROL_ENABLE_SET(x) \ 246 (((x) << WLAN_DEBUG_CONTROL_ENABLE_LSB) & \ 247 WLAN_DEBUG_CONTROL_ENABLE_MASK) 248 #define WLAN_DEBUG_OUT_DATA_GET(x) \ 249 (((x) & WLAN_DEBUG_OUT_DATA_MASK) >> WLAN_DEBUG_OUT_DATA_LSB) 250 #define WLAN_DEBUG_OUT_DATA_SET(x) \ 251 (((x) << WLAN_DEBUG_OUT_DATA_LSB) & WLAN_DEBUG_OUT_DATA_MASK) 252 #define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_GET(x) \ 253 (((x) & AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK) >> \ 254 AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB) 255 #define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_SET(x) \ 256 (((x) << AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB) & \ 257 AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK) 258 #define AMBA_DEBUG_BUS_SEL_GET(x) \ 259 (((x) & AMBA_DEBUG_BUS_SEL_MASK) >> AMBA_DEBUG_BUS_SEL_LSB) 260 #define AMBA_DEBUG_BUS_SEL_SET(x) \ 261 (((x) << AMBA_DEBUG_BUS_SEL_LSB) & AMBA_DEBUG_BUS_SEL_MASK) 262 #define CE_WRAPPER_DEBUG_SEL_GET(x) \ 263 (((x) & CE_WRAPPER_DEBUG_SEL_MASK) >> CE_WRAPPER_DEBUG_SEL_LSB) 264 #define CE_WRAPPER_DEBUG_SEL_SET(x) \ 265 (((x) << CE_WRAPPER_DEBUG_SEL_LSB) & CE_WRAPPER_DEBUG_SEL_MASK) 266 #define CE_DEBUG_SEL_GET(x) (((x) & CE_DEBUG_SEL_MASK) >> CE_DEBUG_SEL_LSB) 267 #define CE_DEBUG_SEL_SET(x) (((x) << CE_DEBUG_SEL_LSB) & CE_DEBUG_SEL_MASK) 268 #define HOST_IE_REG1_CE_BIT(_ce_id) (1 << (_ce_id + HOST_IE_REG1_CE_LSB)) 269 #define HOST_IE_REG2_CE_BIT(_ce_id) (1 << (_ce_id + HOST_IE_REG2_CE_LSB)) 270 #define HOST_IE_REG3_CE_BIT(_ce_id) (1 << (_ce_id + HOST_IE_REG3_CE_LSB)) 271 272 uint32_t DEBUG_CE_SRC_RING_READ_IDX_GET(struct hif_softc *scn, 273 uint32_t CE_ctrl_addr); 274 uint32_t DEBUG_CE_DEST_RING_READ_IDX_GET(struct hif_softc *scn, 275 uint32_t CE_ctrl_addr); 276 277 #define BITS0_TO_31(val) ((uint32_t)((uint64_t)(val)\ 278 & (uint64_t)(0xFFFFFFFF))) 279 #define BITS32_TO_35(val) ((uint32_t)(((uint64_t)(val)\ 280 & (uint64_t)(0xF00000000))>>32)) 281 282 #define VADDR_FOR_CE(scn, CE_ctrl_addr)\ 283 ((scn->vaddr_rri_on_ddr) + COPY_ENGINE_ID(CE_ctrl_addr)) 284 285 #define SRRI_FROM_DDR_ADDR(addr) ((*(addr)) & 0xFFFF) 286 #define DRRI_FROM_DDR_ADDR(addr) (((*(addr))>>16) & 0xFFFF) 287 288 #define CE_SRC_RING_READ_IDX_GET_FROM_REGISTER(scn, CE_ctrl_addr) \ 289 A_TARGET_READ(scn, (CE_ctrl_addr) + CURRENT_SRRI_ADDRESS) 290 #define CE_DEST_RING_READ_IDX_GET_FROM_REGISTER(scn, CE_ctrl_addr) \ 291 A_TARGET_READ(scn, (CE_ctrl_addr) + CURRENT_DRRI_ADDRESS) 292 293 #ifdef ADRASTEA_RRI_ON_DDR 294 #ifdef SHADOW_REG_DEBUG 295 #define CE_SRC_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr)\ 296 DEBUG_CE_SRC_RING_READ_IDX_GET(scn, CE_ctrl_addr) 297 #define CE_DEST_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr)\ 298 DEBUG_CE_DEST_RING_READ_IDX_GET(scn, CE_ctrl_addr) 299 #else 300 #define CE_SRC_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr)\ 301 SRRI_FROM_DDR_ADDR(VADDR_FOR_CE(scn, CE_ctrl_addr)) 302 #define CE_DEST_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr)\ 303 DRRI_FROM_DDR_ADDR(VADDR_FOR_CE(scn, CE_ctrl_addr)) 304 #endif 305 306 unsigned int hif_get_src_ring_read_index(struct hif_softc *scn, 307 uint32_t CE_ctrl_addr); 308 unsigned int hif_get_dst_ring_read_index(struct hif_softc *scn, 309 uint32_t CE_ctrl_addr); 310 311 #define CE_SRC_RING_READ_IDX_GET(scn, CE_ctrl_addr)\ 312 hif_get_src_ring_read_index(scn, CE_ctrl_addr) 313 #define CE_DEST_RING_READ_IDX_GET(scn, CE_ctrl_addr)\ 314 hif_get_dst_ring_read_index(scn, CE_ctrl_addr) 315 #else 316 #define CE_SRC_RING_READ_IDX_GET(scn, CE_ctrl_addr) \ 317 CE_SRC_RING_READ_IDX_GET_FROM_REGISTER(scn, CE_ctrl_addr) 318 #define CE_DEST_RING_READ_IDX_GET(scn, CE_ctrl_addr)\ 319 CE_DEST_RING_READ_IDX_GET_FROM_REGISTER(scn, CE_ctrl_addr) 320 321 /** 322 * if RRI on DDR is not enabled, get idx from ddr defaults to 323 * using the register value & force wake must be used for 324 * non interrupt processing. 325 */ 326 #define CE_SRC_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr)\ 327 A_TARGET_READ(scn, (CE_ctrl_addr) + CURRENT_SRRI_ADDRESS) 328 #endif 329 330 #define CE_SRC_RING_BASE_ADDR_SET(scn, CE_ctrl_addr, addr) \ 331 A_TARGET_WRITE(scn, (CE_ctrl_addr) + SR_BA_ADDRESS, (addr)) 332 333 #define CE_SRC_RING_BASE_ADDR_HIGH_SET(scn, CE_ctrl_addr, addr) \ 334 A_TARGET_WRITE(scn, (CE_ctrl_addr) + SR_BA_ADDRESS_HIGH, (addr)) 335 336 #define CE_SRC_RING_BASE_ADDR_HIGH_GET(scn, CE_ctrl_addr) \ 337 A_TARGET_READ(scn, (CE_ctrl_addr) + SR_BA_ADDRESS_HIGH) 338 339 #define CE_SRC_RING_SZ_SET(scn, CE_ctrl_addr, n) \ 340 A_TARGET_WRITE(scn, (CE_ctrl_addr) + SR_SIZE_ADDRESS, (n)) 341 342 #define CE_SRC_RING_DMAX_SET(scn, CE_ctrl_addr, n) \ 343 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS, \ 344 (A_TARGET_READ(scn, (CE_ctrl_addr) + \ 345 CE_CTRL1_ADDRESS) & ~CE_CTRL1_DMAX_LENGTH_MASK) | \ 346 CE_CTRL1_DMAX_LENGTH_SET(n)) 347 348 #define CE_IDX_UPD_EN_SET(scn, CE_ctrl_addr) \ 349 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS, \ 350 (A_TARGET_READ(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS) \ 351 | CE_CTRL1_IDX_UPD_EN)) 352 353 #define CE_CMD_REGISTER_GET(scn, CE_ctrl_addr) \ 354 A_TARGET_READ(scn, (CE_ctrl_addr) + CE_CMD_REGISTER) 355 356 #define CE_CMD_REGISTER_SET(scn, CE_ctrl_addr, n) \ 357 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_CMD_REGISTER, n) 358 359 #define CE_MSI_ADDR_LOW_SET(scn, CE_ctrl_addr, addr) \ 360 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_MSI_ADDRESS, (addr)) 361 362 #define CE_MSI_ADDR_HIGH_SET(scn, CE_ctrl_addr, addr) \ 363 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_MSI_ADDRESS_HIGH, (addr)) 364 365 #define CE_MSI_DATA_SET(scn, CE_ctrl_addr, data) \ 366 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_MSI_DATA, (data)) 367 368 #define CE_CTRL_REGISTER1_SET(scn, CE_ctrl_addr, val) \ 369 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS, val) 370 371 #define CE_CTRL_REGISTER1_GET(scn, CE_ctrl_addr) \ 372 A_TARGET_READ(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS) 373 374 #define CE_SRC_RING_BYTE_SWAP_SET(scn, CE_ctrl_addr, n) \ 375 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS, \ 376 (A_TARGET_READ(scn, \ 377 (CE_ctrl_addr) + CE_CTRL1_ADDRESS) \ 378 & ~CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) | \ 379 CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SET(n)) 380 381 #define CE_DEST_RING_BYTE_SWAP_SET(scn, CE_ctrl_addr, n) \ 382 A_TARGET_WRITE(scn, (CE_ctrl_addr)+CE_CTRL1_ADDRESS, \ 383 (A_TARGET_READ(scn, \ 384 (CE_ctrl_addr) + CE_CTRL1_ADDRESS) \ 385 & ~CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK) | \ 386 CE_CTRL1_DST_RING_BYTE_SWAP_EN_SET(n)) 387 388 389 #define CE_DEST_RING_BASE_ADDR_SET(scn, CE_ctrl_addr, addr) \ 390 A_TARGET_WRITE(scn, (CE_ctrl_addr) + DR_BA_ADDRESS, (addr)) 391 392 #define CE_DEST_RING_BASE_ADDR_HIGH_SET(scn, CE_ctrl_addr, addr) \ 393 A_TARGET_WRITE(scn, (CE_ctrl_addr) + DR_BA_ADDRESS_HIGH, (addr)) 394 395 #define CE_DEST_RING_BASE_ADDR_HIGH_GET(scn, CE_ctrl_addr) \ 396 A_TARGET_READ(scn, (CE_ctrl_addr) + DR_BA_ADDRESS_HIGH) 397 398 #define CE_DEST_RING_SZ_SET(scn, CE_ctrl_addr, n) \ 399 A_TARGET_WRITE(scn, (CE_ctrl_addr) + DR_SIZE_ADDRESS, (n)) 400 401 #define CE_SRC_RING_HIGHMARK_SET(scn, CE_ctrl_addr, n) \ 402 A_TARGET_WRITE(scn, (CE_ctrl_addr) + SRC_WATERMARK_ADDRESS, \ 403 (A_TARGET_READ(scn, \ 404 (CE_ctrl_addr) + SRC_WATERMARK_ADDRESS) \ 405 & ~SRC_WATERMARK_HIGH_MASK) | \ 406 SRC_WATERMARK_HIGH_SET(n)) 407 408 #define CE_SRC_RING_LOWMARK_SET(scn, CE_ctrl_addr, n) \ 409 A_TARGET_WRITE(scn, (CE_ctrl_addr) + SRC_WATERMARK_ADDRESS, \ 410 (A_TARGET_READ(scn, \ 411 (CE_ctrl_addr) + SRC_WATERMARK_ADDRESS) \ 412 & ~SRC_WATERMARK_LOW_MASK) | \ 413 SRC_WATERMARK_LOW_SET(n)) 414 415 #define CE_DEST_RING_HIGHMARK_SET(scn, CE_ctrl_addr, n) \ 416 A_TARGET_WRITE(scn, (CE_ctrl_addr) + DST_WATERMARK_ADDRESS, \ 417 (A_TARGET_READ(scn, \ 418 (CE_ctrl_addr) + DST_WATERMARK_ADDRESS) \ 419 & ~DST_WATERMARK_HIGH_MASK) | \ 420 DST_WATERMARK_HIGH_SET(n)) 421 422 #define CE_DEST_RING_LOWMARK_SET(scn, CE_ctrl_addr, n) \ 423 A_TARGET_WRITE(scn, (CE_ctrl_addr) + DST_WATERMARK_ADDRESS, \ 424 (A_TARGET_READ(scn, \ 425 (CE_ctrl_addr) + DST_WATERMARK_ADDRESS) \ 426 & ~DST_WATERMARK_LOW_MASK) | \ 427 DST_WATERMARK_LOW_SET(n)) 428 429 #define CE_COPY_COMPLETE_INTR_ENABLE(scn, CE_ctrl_addr) \ 430 A_TARGET_WRITE(scn, (CE_ctrl_addr) + HOST_IE_ADDRESS, \ 431 A_TARGET_READ(scn, \ 432 (CE_ctrl_addr) + HOST_IE_ADDRESS) | \ 433 HOST_IE_COPY_COMPLETE_MASK) 434 435 #define CE_COPY_COMPLETE_INTR_DISABLE(scn, CE_ctrl_addr) \ 436 A_TARGET_WRITE(scn, (CE_ctrl_addr) + HOST_IE_ADDRESS, \ 437 A_TARGET_READ(scn, \ 438 (CE_ctrl_addr) + HOST_IE_ADDRESS) \ 439 & ~HOST_IE_COPY_COMPLETE_MASK) 440 441 #define CE_BASE_ADDRESS(CE_id) \ 442 CE0_BASE_ADDRESS + ((CE1_BASE_ADDRESS - \ 443 CE0_BASE_ADDRESS)*(CE_id)) 444 445 #define CE_WATERMARK_INTR_ENABLE(scn, CE_ctrl_addr) \ 446 A_TARGET_WRITE(scn, (CE_ctrl_addr) + HOST_IE_ADDRESS, \ 447 A_TARGET_READ(scn, \ 448 (CE_ctrl_addr) + HOST_IE_ADDRESS) | \ 449 CE_WATERMARK_MASK) 450 451 #define CE_WATERMARK_INTR_DISABLE(scn, CE_ctrl_addr) \ 452 A_TARGET_WRITE(scn, (CE_ctrl_addr) + HOST_IE_ADDRESS, \ 453 A_TARGET_READ(scn, \ 454 (CE_ctrl_addr) + HOST_IE_ADDRESS) \ 455 & ~CE_WATERMARK_MASK) 456 457 #define CE_ERROR_INTR_ENABLE(scn, CE_ctrl_addr) \ 458 A_TARGET_WRITE(scn, (CE_ctrl_addr) + MISC_IE_ADDRESS, \ 459 A_TARGET_READ(scn, \ 460 (CE_ctrl_addr) + MISC_IE_ADDRESS) | CE_ERROR_MASK) 461 462 #define CE_MISC_INT_STATUS_GET(scn, CE_ctrl_addr) \ 463 A_TARGET_READ(scn, (CE_ctrl_addr) + MISC_IS_ADDRESS) 464 465 #define CE_ENGINE_INT_STATUS_GET(scn, CE_ctrl_addr) \ 466 A_TARGET_READ(scn, (CE_ctrl_addr) + HOST_IS_ADDRESS) 467 468 #define CE_ENGINE_INT_STATUS_CLEAR(scn, CE_ctrl_addr, mask) \ 469 A_TARGET_WRITE(scn, (CE_ctrl_addr) + HOST_IS_ADDRESS, (mask)) 470 471 #define CE_WATERMARK_MASK (HOST_IS_SRC_RING_LOW_WATERMARK_MASK | \ 472 HOST_IS_SRC_RING_HIGH_WATERMARK_MASK | \ 473 HOST_IS_DST_RING_LOW_WATERMARK_MASK | \ 474 HOST_IS_DST_RING_HIGH_WATERMARK_MASK) 475 476 #define CE_ERROR_MASK (MISC_IS_AXI_ERR_MASK | \ 477 MISC_IS_DST_ADDR_ERR_MASK | \ 478 MISC_IS_SRC_LEN_ERR_MASK | \ 479 MISC_IS_DST_MAX_LEN_VIO_MASK | \ 480 MISC_IS_DST_RING_OVERFLOW_MASK | \ 481 MISC_IS_SRC_RING_OVERFLOW_MASK) 482 483 #define CE_SRC_RING_TO_DESC(baddr, idx) \ 484 (&(((struct CE_src_desc *)baddr)[idx])) 485 #define CE_DEST_RING_TO_DESC(baddr, idx) \ 486 (&(((struct CE_dest_desc *)baddr)[idx])) 487 488 /* Ring arithmetic (modulus number of entries in ring, which is a pwr of 2). */ 489 #define CE_RING_DELTA(nentries_mask, fromidx, toidx) \ 490 (((int)(toidx)-(int)(fromidx)) & (nentries_mask)) 491 492 #define CE_RING_IDX_INCR(nentries_mask, idx) \ 493 (((idx) + 1) & (nentries_mask)) 494 495 #define CE_RING_IDX_ADD(nentries_mask, idx, num) \ 496 (((idx) + (num)) & (nentries_mask)) 497 498 #define CE_INTERRUPT_SUMMARY(scn) \ 499 CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET( \ 500 A_TARGET_READ(scn, CE_WRAPPER_BASE_ADDRESS + \ 501 CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS)) 502 503 #define READ_CE_DDR_ADDRESS_FOR_RRI_LOW(scn) \ 504 (A_TARGET_READ(scn, \ 505 CE_WRAPPER_BASE_ADDRESS + CE_DDR_ADDRESS_FOR_RRI_LOW)) 506 507 #define READ_CE_DDR_ADDRESS_FOR_RRI_HIGH(scn) \ 508 (A_TARGET_READ(scn, \ 509 CE_WRAPPER_BASE_ADDRESS + CE_DDR_ADDRESS_FOR_RRI_HIGH)) 510 511 #define WRITE_CE_DDR_ADDRESS_FOR_RRI_LOW(scn, val) \ 512 (A_TARGET_WRITE(scn, \ 513 CE_WRAPPER_BASE_ADDRESS + CE_DDR_ADDRESS_FOR_RRI_LOW, \ 514 val)) 515 516 #define WRITE_CE_DDR_ADDRESS_FOR_RRI_HIGH(scn, val) \ 517 (A_TARGET_WRITE(scn, \ 518 CE_WRAPPER_BASE_ADDRESS + CE_DDR_ADDRESS_FOR_RRI_HIGH, \ 519 val)) 520 521 /*Macro to increment CE packet errors*/ 522 #define OL_ATH_CE_PKT_ERROR_COUNT_INCR(_scn, _ce_ecode) \ 523 do { if (_ce_ecode == CE_RING_DELTA_FAIL) \ 524 (_scn->pkt_stats.ce_ring_delta_fail_count) \ 525 += 1; } while (0) 526 527 /* Given a Copy Engine's ID, determine the interrupt number for that 528 * copy engine's interrupts. 529 */ 530 #define CE_ID_TO_INUM(id) (A_INUM_CE0_COPY_COMP_BASE + (id)) 531 #define CE_INUM_TO_ID(inum) ((inum) - A_INUM_CE0_COPY_COMP_BASE) 532 #define CE0_BASE_ADDRESS (scn->target_ce_def->d_CE0_BASE_ADDRESS) 533 #define CE1_BASE_ADDRESS (scn->target_ce_def->d_CE1_BASE_ADDRESS) 534 535 536 #ifdef ADRASTEA_SHADOW_REGISTERS 537 #define NUM_SHADOW_REGISTERS 24 538 u32 shadow_sr_wr_ind_addr(struct hif_softc *scn, u32 ctrl_addr); 539 u32 shadow_dst_wr_ind_addr(struct hif_softc *scn, u32 ctrl_addr); 540 #endif 541 542 543 #ifdef ADRASTEA_SHADOW_REGISTERS 544 #define CE_SRC_RING_WRITE_IDX_SET(scn, CE_ctrl_addr, n) \ 545 A_TARGET_WRITE(scn, shadow_sr_wr_ind_addr(scn, CE_ctrl_addr), n) 546 #define CE_DEST_RING_WRITE_IDX_SET(scn, CE_ctrl_addr, n) \ 547 A_TARGET_WRITE(scn, shadow_dst_wr_ind_addr(scn, CE_ctrl_addr), n) 548 549 #else 550 551 #define CE_SRC_RING_WRITE_IDX_SET(scn, CE_ctrl_addr, n) \ 552 A_TARGET_WRITE(scn, (CE_ctrl_addr) + SR_WR_INDEX_ADDRESS, (n)) 553 #define CE_DEST_RING_WRITE_IDX_SET(scn, CE_ctrl_addr, n) \ 554 A_TARGET_WRITE(scn, (CE_ctrl_addr) + DST_WR_INDEX_ADDRESS, (n)) 555 #endif 556 557 /* The write index read is only needed durring initialization because 558 * we keep track of the index that was last written. Thus the register 559 * is the only hardware supported location to read the initial value from. 560 */ 561 #define CE_SRC_RING_WRITE_IDX_GET_FROM_REGISTER(scn, CE_ctrl_addr) \ 562 A_TARGET_READ(scn, (CE_ctrl_addr) + SR_WR_INDEX_ADDRESS) 563 #define CE_DEST_RING_WRITE_IDX_GET_FROM_REGISTER(scn, CE_ctrl_addr) \ 564 A_TARGET_READ(scn, (CE_ctrl_addr) + DST_WR_INDEX_ADDRESS) 565 566 #endif /* __CE_REG_H__ */ 567