1 /* 2 * Copyright (c) 2015-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef __CE_REG_H__ 20 #define __CE_REG_H__ 21 22 #define COPY_ENGINE_ID(COPY_ENGINE_BASE_ADDRESS) ((COPY_ENGINE_BASE_ADDRESS \ 23 - CE0_BASE_ADDRESS)/(CE1_BASE_ADDRESS - CE0_BASE_ADDRESS)) 24 25 #define DST_WR_INDEX_ADDRESS (scn->target_ce_def->d_DST_WR_INDEX_ADDRESS) 26 #define SRC_WATERMARK_ADDRESS (scn->target_ce_def->d_SRC_WATERMARK_ADDRESS) 27 #define SRC_WATERMARK_LOW_MASK (scn->target_ce_def->d_SRC_WATERMARK_LOW_MASK) 28 #define SRC_WATERMARK_HIGH_MASK (scn->target_ce_def->d_SRC_WATERMARK_HIGH_MASK) 29 #define DST_WATERMARK_LOW_MASK (scn->target_ce_def->d_DST_WATERMARK_LOW_MASK) 30 #define DST_WATERMARK_HIGH_MASK (scn->target_ce_def->d_DST_WATERMARK_HIGH_MASK) 31 #define CURRENT_SRRI_ADDRESS (scn->target_ce_def->d_CURRENT_SRRI_ADDRESS) 32 #define CURRENT_DRRI_ADDRESS (scn->target_ce_def->d_CURRENT_DRRI_ADDRESS) 33 34 #define SHADOW_VALUE0 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_0) 35 #define SHADOW_VALUE1 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_1) 36 #define SHADOW_VALUE2 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_2) 37 #define SHADOW_VALUE3 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_3) 38 #define SHADOW_VALUE4 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_4) 39 #define SHADOW_VALUE5 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_5) 40 #define SHADOW_VALUE6 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_6) 41 #define SHADOW_VALUE7 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_7) 42 #define SHADOW_VALUE8 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_8) 43 #define SHADOW_VALUE9 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_9) 44 #define SHADOW_VALUE10 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_10) 45 #define SHADOW_VALUE11 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_11) 46 #define SHADOW_VALUE12 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_12) 47 #define SHADOW_VALUE13 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_13) 48 #define SHADOW_VALUE14 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_14) 49 #define SHADOW_VALUE15 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_15) 50 #define SHADOW_VALUE16 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_16) 51 #define SHADOW_VALUE17 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_17) 52 #define SHADOW_VALUE18 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_18) 53 #define SHADOW_VALUE19 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_19) 54 #define SHADOW_VALUE20 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_20) 55 #define SHADOW_VALUE21 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_21) 56 #define SHADOW_VALUE22 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_22) 57 #define SHADOW_VALUE23 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_23) 58 #define SHADOW_ADDRESS0 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_0) 59 #define SHADOW_ADDRESS1 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_1) 60 #define SHADOW_ADDRESS2 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_2) 61 #define SHADOW_ADDRESS3 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_3) 62 #define SHADOW_ADDRESS4 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_4) 63 #define SHADOW_ADDRESS5 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_5) 64 #define SHADOW_ADDRESS6 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_6) 65 #define SHADOW_ADDRESS7 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_7) 66 #define SHADOW_ADDRESS8 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_8) 67 #define SHADOW_ADDRESS9 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_9) 68 #define SHADOW_ADDRESS10 \ 69 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_10) 70 #define SHADOW_ADDRESS11 \ 71 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_11) 72 #define SHADOW_ADDRESS12 \ 73 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_12) 74 #define SHADOW_ADDRESS13 \ 75 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_13) 76 #define SHADOW_ADDRESS14 \ 77 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_14) 78 #define SHADOW_ADDRESS15 \ 79 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_15) 80 #define SHADOW_ADDRESS16 \ 81 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_16) 82 #define SHADOW_ADDRESS17 \ 83 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_17) 84 #define SHADOW_ADDRESS18 \ 85 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_18) 86 #define SHADOW_ADDRESS19 \ 87 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_19) 88 #define SHADOW_ADDRESS20 \ 89 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_20) 90 #define SHADOW_ADDRESS21 \ 91 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_21) 92 #define SHADOW_ADDRESS22 \ 93 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_22) 94 #define SHADOW_ADDRESS23 \ 95 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_23) 96 97 #define SHADOW_ADDRESS(i) \ 98 (SHADOW_ADDRESS0 + i*(SHADOW_ADDRESS1-SHADOW_ADDRESS0)) 99 100 #define HOST_IS_SRC_RING_HIGH_WATERMARK_MASK \ 101 (scn->target_ce_def->d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK) 102 #define HOST_IS_SRC_RING_LOW_WATERMARK_MASK \ 103 (scn->target_ce_def->d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK) 104 #define HOST_IS_DST_RING_HIGH_WATERMARK_MASK \ 105 (scn->target_ce_def->d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK) 106 #define HOST_IS_DST_RING_LOW_WATERMARK_MASK \ 107 (scn->target_ce_def->d_HOST_IS_DST_RING_LOW_WATERMARK_MASK) 108 #define MISC_IS_ADDRESS (scn->target_ce_def->d_MISC_IS_ADDRESS) 109 #define HOST_IS_COPY_COMPLETE_MASK \ 110 (scn->target_ce_def->d_HOST_IS_COPY_COMPLETE_MASK) 111 #define CE_WRAPPER_BASE_ADDRESS (scn->target_ce_def->d_CE_WRAPPER_BASE_ADDRESS) 112 #define CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS \ 113 (scn->target_ce_def->d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS) 114 #define CE_DDR_ADDRESS_FOR_RRI_LOW \ 115 (scn->target_ce_def->d_CE_DDR_ADDRESS_FOR_RRI_LOW) 116 #define CE_DDR_ADDRESS_FOR_RRI_HIGH \ 117 (scn->target_ce_def->d_CE_DDR_ADDRESS_FOR_RRI_HIGH) 118 #define HOST_IE_COPY_COMPLETE_MASK \ 119 (scn->target_ce_def->d_HOST_IE_COPY_COMPLETE_MASK) 120 #define SR_BA_ADDRESS (scn->target_ce_def->d_SR_BA_ADDRESS) 121 #define SR_BA_ADDRESS_HIGH (scn->target_ce_def->d_SR_BA_ADDRESS_HIGH) 122 #define SR_SIZE_ADDRESS (scn->target_ce_def->d_SR_SIZE_ADDRESS) 123 #define CE_CTRL1_ADDRESS (scn->target_ce_def->d_CE_CTRL1_ADDRESS) 124 #define CE_CTRL1_DMAX_LENGTH_MASK \ 125 (scn->target_ce_def->d_CE_CTRL1_DMAX_LENGTH_MASK) 126 #define DR_BA_ADDRESS (scn->target_ce_def->d_DR_BA_ADDRESS) 127 #define DR_BA_ADDRESS_HIGH (scn->target_ce_def->d_DR_BA_ADDRESS_HIGH) 128 #define DR_SIZE_ADDRESS (scn->target_ce_def->d_DR_SIZE_ADDRESS) 129 #define CE_CMD_REGISTER (scn->target_ce_def->d_CE_CMD_REGISTER) 130 #define CE_MSI_ADDRESS (scn->target_ce_def->d_CE_MSI_ADDRESS) 131 #define CE_MSI_ADDRESS_HIGH (scn->target_ce_def->d_CE_MSI_ADDRESS_HIGH) 132 #define CE_MSI_DATA (scn->target_ce_def->d_CE_MSI_DATA) 133 #define CE_MSI_ENABLE_BIT (scn->target_ce_def->d_CE_MSI_ENABLE_BIT) 134 #define MISC_IE_ADDRESS (scn->target_ce_def->d_MISC_IE_ADDRESS) 135 #define MISC_IS_AXI_ERR_MASK (scn->target_ce_def->d_MISC_IS_AXI_ERR_MASK) 136 #define MISC_IS_DST_ADDR_ERR_MASK \ 137 (scn->target_ce_def->d_MISC_IS_DST_ADDR_ERR_MASK) 138 #define MISC_IS_SRC_LEN_ERR_MASK \ 139 (scn->target_ce_def->d_MISC_IS_SRC_LEN_ERR_MASK) 140 #define MISC_IS_DST_MAX_LEN_VIO_MASK \ 141 (scn->target_ce_def->d_MISC_IS_DST_MAX_LEN_VIO_MASK) 142 #define MISC_IS_DST_RING_OVERFLOW_MASK \ 143 (scn->target_ce_def->d_MISC_IS_DST_RING_OVERFLOW_MASK) 144 #define MISC_IS_SRC_RING_OVERFLOW_MASK \ 145 (scn->target_ce_def->d_MISC_IS_SRC_RING_OVERFLOW_MASK) 146 #define SRC_WATERMARK_LOW_LSB (scn->target_ce_def->d_SRC_WATERMARK_LOW_LSB) 147 #define SRC_WATERMARK_HIGH_LSB (scn->target_ce_def->d_SRC_WATERMARK_HIGH_LSB) 148 #define DST_WATERMARK_LOW_LSB (scn->target_ce_def->d_DST_WATERMARK_LOW_LSB) 149 #define DST_WATERMARK_HIGH_LSB (scn->target_ce_def->d_DST_WATERMARK_HIGH_LSB) 150 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK \ 151 (scn->target_ce_def->d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK) 152 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB \ 153 (scn->target_ce_def->d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB) 154 #define CE_CTRL1_DMAX_LENGTH_LSB \ 155 (scn->target_ce_def->d_CE_CTRL1_DMAX_LENGTH_LSB) 156 #define CE_CTRL1_IDX_UPD_EN (scn->target_ce_def->d_CE_CTRL1_IDX_UPD_EN_MASK) 157 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK \ 158 (scn->target_ce_def->d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) 159 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK \ 160 (scn->target_ce_def->d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK) 161 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB \ 162 (scn->target_ce_def->d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB) 163 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB \ 164 (scn->target_ce_def->d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB) 165 #define WLAN_DEBUG_INPUT_SEL_OFFSET \ 166 (scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_OFFSET) 167 #define WLAN_DEBUG_INPUT_SEL_SRC_MSB \ 168 (scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_SRC_MSB) 169 #define WLAN_DEBUG_INPUT_SEL_SRC_LSB \ 170 (scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_SRC_LSB) 171 #define WLAN_DEBUG_INPUT_SEL_SRC_MASK \ 172 (scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_SRC_MASK) 173 #define WLAN_DEBUG_CONTROL_OFFSET (scn->targetdef->d_WLAN_DEBUG_CONTROL_OFFSET) 174 #define WLAN_DEBUG_CONTROL_ENABLE_MSB \ 175 (scn->targetdef->d_WLAN_DEBUG_CONTROL_ENABLE_MSB) 176 #define WLAN_DEBUG_CONTROL_ENABLE_LSB \ 177 (scn->targetdef->d_WLAN_DEBUG_CONTROL_ENABLE_LSB) 178 #define WLAN_DEBUG_CONTROL_ENABLE_MASK \ 179 (scn->targetdef->d_WLAN_DEBUG_CONTROL_ENABLE_MASK) 180 #define WLAN_DEBUG_OUT_OFFSET (scn->targetdef->d_WLAN_DEBUG_OUT_OFFSET) 181 #define WLAN_DEBUG_OUT_DATA_MSB (scn->targetdef->d_WLAN_DEBUG_OUT_DATA_MSB) 182 #define WLAN_DEBUG_OUT_DATA_LSB (scn->targetdef->d_WLAN_DEBUG_OUT_DATA_LSB) 183 #define WLAN_DEBUG_OUT_DATA_MASK (scn->targetdef->d_WLAN_DEBUG_OUT_DATA_MASK) 184 #define AMBA_DEBUG_BUS_OFFSET (scn->targetdef->d_AMBA_DEBUG_BUS_OFFSET) 185 #define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB \ 186 (scn->targetdef->d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB) 187 #define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB \ 188 (scn->targetdef->d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB) 189 #define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK \ 190 (scn->targetdef->d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK) 191 #define AMBA_DEBUG_BUS_SEL_MSB (scn->targetdef->d_AMBA_DEBUG_BUS_SEL_MSB) 192 #define AMBA_DEBUG_BUS_SEL_LSB (scn->targetdef->d_AMBA_DEBUG_BUS_SEL_LSB) 193 #define AMBA_DEBUG_BUS_SEL_MASK (scn->targetdef->d_AMBA_DEBUG_BUS_SEL_MASK) 194 #define CE_WRAPPER_DEBUG_OFFSET \ 195 (scn->target_ce_def->d_CE_WRAPPER_DEBUG_OFFSET) 196 #define CE_WRAPPER_DEBUG_SEL_MSB \ 197 (scn->target_ce_def->d_CE_WRAPPER_DEBUG_SEL_MSB) 198 #define CE_WRAPPER_DEBUG_SEL_LSB \ 199 (scn->target_ce_def->d_CE_WRAPPER_DEBUG_SEL_LSB) 200 #define CE_WRAPPER_DEBUG_SEL_MASK \ 201 (scn->target_ce_def->d_CE_WRAPPER_DEBUG_SEL_MASK) 202 #define CE_DEBUG_OFFSET (scn->target_ce_def->d_CE_DEBUG_OFFSET) 203 #define CE_DEBUG_SEL_MSB (scn->target_ce_def->d_CE_DEBUG_SEL_MSB) 204 #define CE_DEBUG_SEL_LSB (scn->target_ce_def->d_CE_DEBUG_SEL_LSB) 205 #define CE_DEBUG_SEL_MASK (scn->target_ce_def->d_CE_DEBUG_SEL_MASK) 206 #define HOST_IE_ADDRESS (scn->target_ce_def->d_HOST_IE_ADDRESS) 207 #define HOST_IE_REG1_CE_LSB (scn->target_ce_def->d_HOST_IE_REG1_CE_LSB) 208 #define HOST_IE_ADDRESS_2 (scn->target_ce_def->d_HOST_IE_ADDRESS_2) 209 #define HOST_IE_REG2_CE_LSB (scn->target_ce_def->d_HOST_IE_REG2_CE_LSB) 210 #define HOST_IE_ADDRESS_3 (scn->target_ce_def->d_HOST_IE_ADDRESS_3) 211 #define HOST_IE_REG3_CE_LSB (scn->target_ce_def->d_HOST_IE_REG3_CE_LSB) 212 #define HOST_IS_ADDRESS (scn->target_ce_def->d_HOST_IS_ADDRESS) 213 #define HOST_CE_ADDRESS (scn->target_ce_def->d_HOST_CE_ADDRESS) 214 215 #define SRC_WATERMARK_LOW_SET(x) \ 216 (((x) << SRC_WATERMARK_LOW_LSB) & SRC_WATERMARK_LOW_MASK) 217 #define SRC_WATERMARK_HIGH_SET(x) \ 218 (((x) << SRC_WATERMARK_HIGH_LSB) & SRC_WATERMARK_HIGH_MASK) 219 #define DST_WATERMARK_LOW_SET(x) \ 220 (((x) << DST_WATERMARK_LOW_LSB) & DST_WATERMARK_LOW_MASK) 221 #define DST_WATERMARK_HIGH_SET(x) \ 222 (((x) << DST_WATERMARK_HIGH_LSB) & DST_WATERMARK_HIGH_MASK) 223 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET(x) \ 224 (((x) & CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK) >> \ 225 CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB) 226 #define CE_CTRL1_DMAX_LENGTH_SET(x) \ 227 (((x) << CE_CTRL1_DMAX_LENGTH_LSB) & CE_CTRL1_DMAX_LENGTH_MASK) 228 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SET(x) \ 229 (((x) << CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB) & \ 230 CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) 231 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_SET(x) \ 232 (((x) << CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB) & \ 233 CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK) 234 #define WLAN_DEBUG_INPUT_SEL_SRC_GET(x) \ 235 (((x) & WLAN_DEBUG_INPUT_SEL_SRC_MASK) >> \ 236 WLAN_DEBUG_INPUT_SEL_SRC_LSB) 237 #define WLAN_DEBUG_INPUT_SEL_SRC_SET(x) \ 238 (((x) << WLAN_DEBUG_INPUT_SEL_SRC_LSB) & \ 239 WLAN_DEBUG_INPUT_SEL_SRC_MASK) 240 #define WLAN_DEBUG_CONTROL_ENABLE_GET(x) \ 241 (((x) & WLAN_DEBUG_CONTROL_ENABLE_MASK) >> \ 242 WLAN_DEBUG_CONTROL_ENABLE_LSB) 243 #define WLAN_DEBUG_CONTROL_ENABLE_SET(x) \ 244 (((x) << WLAN_DEBUG_CONTROL_ENABLE_LSB) & \ 245 WLAN_DEBUG_CONTROL_ENABLE_MASK) 246 #define WLAN_DEBUG_OUT_DATA_GET(x) \ 247 (((x) & WLAN_DEBUG_OUT_DATA_MASK) >> WLAN_DEBUG_OUT_DATA_LSB) 248 #define WLAN_DEBUG_OUT_DATA_SET(x) \ 249 (((x) << WLAN_DEBUG_OUT_DATA_LSB) & WLAN_DEBUG_OUT_DATA_MASK) 250 #define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_GET(x) \ 251 (((x) & AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK) >> \ 252 AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB) 253 #define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_SET(x) \ 254 (((x) << AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB) & \ 255 AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK) 256 #define AMBA_DEBUG_BUS_SEL_GET(x) \ 257 (((x) & AMBA_DEBUG_BUS_SEL_MASK) >> AMBA_DEBUG_BUS_SEL_LSB) 258 #define AMBA_DEBUG_BUS_SEL_SET(x) \ 259 (((x) << AMBA_DEBUG_BUS_SEL_LSB) & AMBA_DEBUG_BUS_SEL_MASK) 260 #define CE_WRAPPER_DEBUG_SEL_GET(x) \ 261 (((x) & CE_WRAPPER_DEBUG_SEL_MASK) >> CE_WRAPPER_DEBUG_SEL_LSB) 262 #define CE_WRAPPER_DEBUG_SEL_SET(x) \ 263 (((x) << CE_WRAPPER_DEBUG_SEL_LSB) & CE_WRAPPER_DEBUG_SEL_MASK) 264 #define CE_DEBUG_SEL_GET(x) (((x) & CE_DEBUG_SEL_MASK) >> CE_DEBUG_SEL_LSB) 265 #define CE_DEBUG_SEL_SET(x) (((x) << CE_DEBUG_SEL_LSB) & CE_DEBUG_SEL_MASK) 266 #define HOST_IE_REG1_CE_BIT(_ce_id) (1 << (_ce_id + HOST_IE_REG1_CE_LSB)) 267 #define HOST_IE_REG2_CE_BIT(_ce_id) (1 << (_ce_id + HOST_IE_REG2_CE_LSB)) 268 #define HOST_IE_REG3_CE_BIT(_ce_id) (1 << (_ce_id + HOST_IE_REG3_CE_LSB)) 269 270 uint32_t DEBUG_CE_SRC_RING_READ_IDX_GET(struct hif_softc *scn, 271 uint32_t CE_ctrl_addr); 272 uint32_t DEBUG_CE_DEST_RING_READ_IDX_GET(struct hif_softc *scn, 273 uint32_t CE_ctrl_addr); 274 275 #define BITS0_TO_31(val) ((uint32_t)((uint64_t)(val)\ 276 & (uint64_t)(0xFFFFFFFF))) 277 #define BITS32_TO_35(val) ((uint32_t)(((uint64_t)(val)\ 278 & (uint64_t)(0xF00000000))>>32)) 279 280 #define VADDR_FOR_CE(scn, CE_ctrl_addr)\ 281 ((scn->vaddr_rri_on_ddr) + COPY_ENGINE_ID(CE_ctrl_addr)) 282 283 #define SRRI_FROM_DDR_ADDR(addr) ((*(addr)) & 0xFFFF) 284 #define DRRI_FROM_DDR_ADDR(addr) (((*(addr))>>16) & 0xFFFF) 285 286 #define CE_SRC_RING_READ_IDX_GET_FROM_REGISTER(scn, CE_ctrl_addr) \ 287 A_TARGET_READ(scn, (CE_ctrl_addr) + CURRENT_SRRI_ADDRESS) 288 #define CE_DEST_RING_READ_IDX_GET_FROM_REGISTER(scn, CE_ctrl_addr) \ 289 A_TARGET_READ(scn, (CE_ctrl_addr) + CURRENT_DRRI_ADDRESS) 290 291 #ifdef ADRASTEA_RRI_ON_DDR 292 #ifdef SHADOW_REG_DEBUG 293 #define CE_SRC_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr)\ 294 DEBUG_CE_SRC_RING_READ_IDX_GET(scn, CE_ctrl_addr) 295 #define CE_DEST_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr)\ 296 DEBUG_CE_DEST_RING_READ_IDX_GET(scn, CE_ctrl_addr) 297 #else 298 #define CE_SRC_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr)\ 299 SRRI_FROM_DDR_ADDR(VADDR_FOR_CE(scn, CE_ctrl_addr)) 300 #define CE_DEST_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr)\ 301 DRRI_FROM_DDR_ADDR(VADDR_FOR_CE(scn, CE_ctrl_addr)) 302 #endif 303 304 unsigned int hif_get_src_ring_read_index(struct hif_softc *scn, 305 uint32_t CE_ctrl_addr); 306 unsigned int hif_get_dst_ring_read_index(struct hif_softc *scn, 307 uint32_t CE_ctrl_addr); 308 309 #define CE_SRC_RING_READ_IDX_GET(scn, CE_ctrl_addr)\ 310 hif_get_src_ring_read_index(scn, CE_ctrl_addr) 311 #define CE_DEST_RING_READ_IDX_GET(scn, CE_ctrl_addr)\ 312 hif_get_dst_ring_read_index(scn, CE_ctrl_addr) 313 #else 314 #define CE_SRC_RING_READ_IDX_GET(scn, CE_ctrl_addr) \ 315 CE_SRC_RING_READ_IDX_GET_FROM_REGISTER(scn, CE_ctrl_addr) 316 #define CE_DEST_RING_READ_IDX_GET(scn, CE_ctrl_addr)\ 317 CE_DEST_RING_READ_IDX_GET_FROM_REGISTER(scn, CE_ctrl_addr) 318 319 /** 320 * if RRI on DDR is not enabled, get idx from ddr defaults to 321 * using the register value & force wake must be used for 322 * non interrupt processing. 323 */ 324 #define CE_SRC_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr)\ 325 A_TARGET_READ(scn, (CE_ctrl_addr) + CURRENT_SRRI_ADDRESS) 326 #endif 327 328 #define CE_SRC_RING_BASE_ADDR_SET(scn, CE_ctrl_addr, addr) \ 329 A_TARGET_WRITE(scn, (CE_ctrl_addr) + SR_BA_ADDRESS, (addr)) 330 331 #define CE_SRC_RING_BASE_ADDR_HIGH_SET(scn, CE_ctrl_addr, addr) \ 332 A_TARGET_WRITE(scn, (CE_ctrl_addr) + SR_BA_ADDRESS_HIGH, (addr)) 333 334 #define CE_SRC_RING_BASE_ADDR_HIGH_GET(scn, CE_ctrl_addr) \ 335 A_TARGET_READ(scn, (CE_ctrl_addr) + SR_BA_ADDRESS_HIGH) 336 337 #define CE_SRC_RING_SZ_SET(scn, CE_ctrl_addr, n) \ 338 A_TARGET_WRITE(scn, (CE_ctrl_addr) + SR_SIZE_ADDRESS, (n)) 339 340 #define CE_SRC_RING_DMAX_SET(scn, CE_ctrl_addr, n) \ 341 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS, \ 342 (A_TARGET_READ(scn, (CE_ctrl_addr) + \ 343 CE_CTRL1_ADDRESS) & ~CE_CTRL1_DMAX_LENGTH_MASK) | \ 344 CE_CTRL1_DMAX_LENGTH_SET(n)) 345 346 #define CE_IDX_UPD_EN_SET(scn, CE_ctrl_addr) \ 347 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS, \ 348 (A_TARGET_READ(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS) \ 349 | CE_CTRL1_IDX_UPD_EN)) 350 351 #define CE_CMD_REGISTER_GET(scn, CE_ctrl_addr) \ 352 A_TARGET_READ(scn, (CE_ctrl_addr) + CE_CMD_REGISTER) 353 354 #define CE_CMD_REGISTER_SET(scn, CE_ctrl_addr, n) \ 355 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_CMD_REGISTER, n) 356 357 #define CE_MSI_ADDR_LOW_SET(scn, CE_ctrl_addr, addr) \ 358 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_MSI_ADDRESS, (addr)) 359 360 #define CE_MSI_ADDR_HIGH_SET(scn, CE_ctrl_addr, addr) \ 361 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_MSI_ADDRESS_HIGH, (addr)) 362 363 #define CE_MSI_DATA_SET(scn, CE_ctrl_addr, data) \ 364 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_MSI_DATA, (data)) 365 366 #define CE_CTRL_REGISTER1_SET(scn, CE_ctrl_addr, val) \ 367 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS, val) 368 369 #define CE_CTRL_REGISTER1_GET(scn, CE_ctrl_addr) \ 370 A_TARGET_READ(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS) 371 372 #define CE_SRC_RING_BYTE_SWAP_SET(scn, CE_ctrl_addr, n) \ 373 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS, \ 374 (A_TARGET_READ(scn, \ 375 (CE_ctrl_addr) + CE_CTRL1_ADDRESS) \ 376 & ~CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) | \ 377 CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SET(n)) 378 379 #define CE_DEST_RING_BYTE_SWAP_SET(scn, CE_ctrl_addr, n) \ 380 A_TARGET_WRITE(scn, (CE_ctrl_addr)+CE_CTRL1_ADDRESS, \ 381 (A_TARGET_READ(scn, \ 382 (CE_ctrl_addr) + CE_CTRL1_ADDRESS) \ 383 & ~CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK) | \ 384 CE_CTRL1_DST_RING_BYTE_SWAP_EN_SET(n)) 385 386 387 #define CE_DEST_RING_BASE_ADDR_SET(scn, CE_ctrl_addr, addr) \ 388 A_TARGET_WRITE(scn, (CE_ctrl_addr) + DR_BA_ADDRESS, (addr)) 389 390 #define CE_DEST_RING_BASE_ADDR_HIGH_SET(scn, CE_ctrl_addr, addr) \ 391 A_TARGET_WRITE(scn, (CE_ctrl_addr) + DR_BA_ADDRESS_HIGH, (addr)) 392 393 #define CE_DEST_RING_BASE_ADDR_HIGH_GET(scn, CE_ctrl_addr) \ 394 A_TARGET_READ(scn, (CE_ctrl_addr) + DR_BA_ADDRESS_HIGH) 395 396 #define CE_DEST_RING_SZ_SET(scn, CE_ctrl_addr, n) \ 397 A_TARGET_WRITE(scn, (CE_ctrl_addr) + DR_SIZE_ADDRESS, (n)) 398 399 #define CE_SRC_RING_HIGHMARK_SET(scn, CE_ctrl_addr, n) \ 400 A_TARGET_WRITE(scn, (CE_ctrl_addr) + SRC_WATERMARK_ADDRESS, \ 401 (A_TARGET_READ(scn, \ 402 (CE_ctrl_addr) + SRC_WATERMARK_ADDRESS) \ 403 & ~SRC_WATERMARK_HIGH_MASK) | \ 404 SRC_WATERMARK_HIGH_SET(n)) 405 406 #define CE_SRC_RING_LOWMARK_SET(scn, CE_ctrl_addr, n) \ 407 A_TARGET_WRITE(scn, (CE_ctrl_addr) + SRC_WATERMARK_ADDRESS, \ 408 (A_TARGET_READ(scn, \ 409 (CE_ctrl_addr) + SRC_WATERMARK_ADDRESS) \ 410 & ~SRC_WATERMARK_LOW_MASK) | \ 411 SRC_WATERMARK_LOW_SET(n)) 412 413 #define CE_DEST_RING_HIGHMARK_SET(scn, CE_ctrl_addr, n) \ 414 A_TARGET_WRITE(scn, (CE_ctrl_addr) + DST_WATERMARK_ADDRESS, \ 415 (A_TARGET_READ(scn, \ 416 (CE_ctrl_addr) + DST_WATERMARK_ADDRESS) \ 417 & ~DST_WATERMARK_HIGH_MASK) | \ 418 DST_WATERMARK_HIGH_SET(n)) 419 420 #define CE_DEST_RING_LOWMARK_SET(scn, CE_ctrl_addr, n) \ 421 A_TARGET_WRITE(scn, (CE_ctrl_addr) + DST_WATERMARK_ADDRESS, \ 422 (A_TARGET_READ(scn, \ 423 (CE_ctrl_addr) + DST_WATERMARK_ADDRESS) \ 424 & ~DST_WATERMARK_LOW_MASK) | \ 425 DST_WATERMARK_LOW_SET(n)) 426 427 #define CE_COPY_COMPLETE_INTR_ENABLE(scn, CE_ctrl_addr) \ 428 A_TARGET_WRITE(scn, (CE_ctrl_addr) + HOST_IE_ADDRESS, \ 429 A_TARGET_READ(scn, \ 430 (CE_ctrl_addr) + HOST_IE_ADDRESS) | \ 431 HOST_IE_COPY_COMPLETE_MASK) 432 433 #define CE_COPY_COMPLETE_INTR_DISABLE(scn, CE_ctrl_addr) \ 434 A_TARGET_WRITE(scn, (CE_ctrl_addr) + HOST_IE_ADDRESS, \ 435 A_TARGET_READ(scn, \ 436 (CE_ctrl_addr) + HOST_IE_ADDRESS) \ 437 & ~HOST_IE_COPY_COMPLETE_MASK) 438 439 #define CE_BASE_ADDRESS(CE_id) \ 440 CE0_BASE_ADDRESS + ((CE1_BASE_ADDRESS - \ 441 CE0_BASE_ADDRESS)*(CE_id)) 442 443 #define CE_WATERMARK_INTR_ENABLE(scn, CE_ctrl_addr) \ 444 A_TARGET_WRITE(scn, (CE_ctrl_addr) + HOST_IE_ADDRESS, \ 445 A_TARGET_READ(scn, \ 446 (CE_ctrl_addr) + HOST_IE_ADDRESS) | \ 447 CE_WATERMARK_MASK) 448 449 #define CE_WATERMARK_INTR_DISABLE(scn, CE_ctrl_addr) \ 450 A_TARGET_WRITE(scn, (CE_ctrl_addr) + HOST_IE_ADDRESS, \ 451 A_TARGET_READ(scn, \ 452 (CE_ctrl_addr) + HOST_IE_ADDRESS) \ 453 & ~CE_WATERMARK_MASK) 454 455 #define CE_ERROR_INTR_ENABLE(scn, CE_ctrl_addr) \ 456 A_TARGET_WRITE(scn, (CE_ctrl_addr) + MISC_IE_ADDRESS, \ 457 A_TARGET_READ(scn, \ 458 (CE_ctrl_addr) + MISC_IE_ADDRESS) | CE_ERROR_MASK) 459 460 #define CE_MISC_INT_STATUS_GET(scn, CE_ctrl_addr) \ 461 A_TARGET_READ(scn, (CE_ctrl_addr) + MISC_IS_ADDRESS) 462 463 #define CE_ENGINE_INT_STATUS_GET(scn, CE_ctrl_addr) \ 464 A_TARGET_READ(scn, (CE_ctrl_addr) + HOST_IS_ADDRESS) 465 466 #define CE_ENGINE_INT_STATUS_CLEAR(scn, CE_ctrl_addr, mask) \ 467 A_TARGET_WRITE(scn, (CE_ctrl_addr) + HOST_IS_ADDRESS, (mask)) 468 469 #define CE_WATERMARK_MASK (HOST_IS_SRC_RING_LOW_WATERMARK_MASK | \ 470 HOST_IS_SRC_RING_HIGH_WATERMARK_MASK | \ 471 HOST_IS_DST_RING_LOW_WATERMARK_MASK | \ 472 HOST_IS_DST_RING_HIGH_WATERMARK_MASK) 473 474 #define CE_ERROR_MASK (MISC_IS_AXI_ERR_MASK | \ 475 MISC_IS_DST_ADDR_ERR_MASK | \ 476 MISC_IS_SRC_LEN_ERR_MASK | \ 477 MISC_IS_DST_MAX_LEN_VIO_MASK | \ 478 MISC_IS_DST_RING_OVERFLOW_MASK | \ 479 MISC_IS_SRC_RING_OVERFLOW_MASK) 480 481 #define CE_SRC_RING_TO_DESC(baddr, idx) \ 482 (&(((struct CE_src_desc *)baddr)[idx])) 483 #define CE_DEST_RING_TO_DESC(baddr, idx) \ 484 (&(((struct CE_dest_desc *)baddr)[idx])) 485 486 /* Ring arithmetic (modulus number of entries in ring, which is a pwr of 2). */ 487 #define CE_RING_DELTA(nentries_mask, fromidx, toidx) \ 488 (((int)(toidx)-(int)(fromidx)) & (nentries_mask)) 489 490 #define CE_RING_IDX_INCR(nentries_mask, idx) \ 491 (((idx) + 1) & (nentries_mask)) 492 493 #define CE_RING_IDX_ADD(nentries_mask, idx, num) \ 494 (((idx) + (num)) & (nentries_mask)) 495 496 #define CE_INTERRUPT_SUMMARY(scn) \ 497 CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET( \ 498 A_TARGET_READ(scn, CE_WRAPPER_BASE_ADDRESS + \ 499 CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS)) 500 501 #define READ_CE_DDR_ADDRESS_FOR_RRI_LOW(scn) \ 502 (A_TARGET_READ(scn, \ 503 CE_WRAPPER_BASE_ADDRESS + CE_DDR_ADDRESS_FOR_RRI_LOW)) 504 505 #define READ_CE_DDR_ADDRESS_FOR_RRI_HIGH(scn) \ 506 (A_TARGET_READ(scn, \ 507 CE_WRAPPER_BASE_ADDRESS + CE_DDR_ADDRESS_FOR_RRI_HIGH)) 508 509 #define WRITE_CE_DDR_ADDRESS_FOR_RRI_LOW(scn, val) \ 510 (A_TARGET_WRITE(scn, \ 511 CE_WRAPPER_BASE_ADDRESS + CE_DDR_ADDRESS_FOR_RRI_LOW, \ 512 val)) 513 514 #define WRITE_CE_DDR_ADDRESS_FOR_RRI_HIGH(scn, val) \ 515 (A_TARGET_WRITE(scn, \ 516 CE_WRAPPER_BASE_ADDRESS + CE_DDR_ADDRESS_FOR_RRI_HIGH, \ 517 val)) 518 519 /*Macro to increment CE packet errors*/ 520 #define OL_ATH_CE_PKT_ERROR_COUNT_INCR(_scn, _ce_ecode) \ 521 do { if (_ce_ecode == CE_RING_DELTA_FAIL) \ 522 (_scn->pkt_stats.ce_ring_delta_fail_count) \ 523 += 1; } while (0) 524 525 /* Given a Copy Engine's ID, determine the interrupt number for that 526 * copy engine's interrupts. 527 */ 528 #define CE_ID_TO_INUM(id) (A_INUM_CE0_COPY_COMP_BASE + (id)) 529 #define CE_INUM_TO_ID(inum) ((inum) - A_INUM_CE0_COPY_COMP_BASE) 530 #define CE0_BASE_ADDRESS (scn->target_ce_def->d_CE0_BASE_ADDRESS) 531 #define CE1_BASE_ADDRESS (scn->target_ce_def->d_CE1_BASE_ADDRESS) 532 533 534 #ifdef ADRASTEA_SHADOW_REGISTERS 535 #define NUM_SHADOW_REGISTERS 24 536 u32 shadow_sr_wr_ind_addr(struct hif_softc *scn, u32 ctrl_addr); 537 u32 shadow_dst_wr_ind_addr(struct hif_softc *scn, u32 ctrl_addr); 538 #endif 539 540 541 #ifdef ADRASTEA_SHADOW_REGISTERS 542 #define CE_SRC_RING_WRITE_IDX_SET(scn, CE_ctrl_addr, n) \ 543 A_TARGET_WRITE(scn, shadow_sr_wr_ind_addr(scn, CE_ctrl_addr), n) 544 #define CE_DEST_RING_WRITE_IDX_SET(scn, CE_ctrl_addr, n) \ 545 A_TARGET_WRITE(scn, shadow_dst_wr_ind_addr(scn, CE_ctrl_addr), n) 546 547 #else 548 549 #define CE_SRC_RING_WRITE_IDX_SET(scn, CE_ctrl_addr, n) \ 550 A_TARGET_WRITE(scn, (CE_ctrl_addr) + SR_WR_INDEX_ADDRESS, (n)) 551 #define CE_DEST_RING_WRITE_IDX_SET(scn, CE_ctrl_addr, n) \ 552 A_TARGET_WRITE(scn, (CE_ctrl_addr) + DST_WR_INDEX_ADDRESS, (n)) 553 #endif 554 555 /* The write index read is only needed durring initialization because 556 * we keep track of the index that was last written. Thus the register 557 * is the only hardware supported location to read the initial value from. 558 */ 559 #define CE_SRC_RING_WRITE_IDX_GET_FROM_REGISTER(scn, CE_ctrl_addr) \ 560 A_TARGET_READ(scn, (CE_ctrl_addr) + SR_WR_INDEX_ADDRESS) 561 #define CE_DEST_RING_WRITE_IDX_GET_FROM_REGISTER(scn, CE_ctrl_addr) \ 562 A_TARGET_READ(scn, (CE_ctrl_addr) + DST_WR_INDEX_ADDRESS) 563 564 #endif /* __CE_REG_H__ */ 565