1 /* 2 * Copyright (c) 2015-2017 The Linux Foundation. All rights reserved. 3 * 4 * Previously licensed under the ISC license by Qualcomm Atheros, Inc. 5 * 6 * 7 * Permission to use, copy, modify, and/or distribute this software for 8 * any purpose with or without fee is hereby granted, provided that the 9 * above copyright notice and this permission notice appear in all 10 * copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 13 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 14 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 15 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 16 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 17 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 18 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 19 * PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /* 23 * This file was originally distributed by Qualcomm Atheros, Inc. 24 * under proprietary terms before Copyright ownership was assigned 25 * to the Linux Foundation. 26 */ 27 28 #ifndef __CE_H__ 29 #define __CE_H__ 30 31 #include "qdf_atomic.h" 32 #include "qdf_lock.h" 33 #include "hif_main.h" 34 #include "qdf_util.h" 35 36 #define CE_HTT_T2H_MSG 1 37 #define CE_HTT_H2T_MSG 4 38 39 #define CE_OFFSET 0x00000400 40 #define CE_USEFUL_SIZE 0x00000058 41 #define CE_ALL_BITMAP 0xFFFF 42 43 /** 44 * enum ce_id_type 45 * 46 * @ce_id_type: Copy engine ID 47 */ 48 enum ce_id_type { 49 CE_ID_0, 50 CE_ID_1, 51 CE_ID_2, 52 CE_ID_3, 53 CE_ID_4, 54 CE_ID_5, 55 CE_ID_6, 56 CE_ID_7, 57 CE_ID_8, 58 CE_ID_9, 59 CE_ID_10, 60 CE_ID_11, 61 CE_ID_MAX 62 }; 63 64 #ifdef CONFIG_WIN 65 #define QWLAN_VERSIONSTR "WIN" 66 #endif 67 68 enum ol_ath_hif_pkt_ecodes { 69 HIF_PIPE_NO_RESOURCE = 0 70 }; 71 72 struct HIF_CE_state; 73 74 /* Per-pipe state. */ 75 struct HIF_CE_pipe_info { 76 /* Handle of underlying Copy Engine */ 77 struct CE_handle *ce_hdl; 78 79 /* Our pipe number; facilitiates use of pipe_info ptrs. */ 80 uint8_t pipe_num; 81 82 /* Convenience back pointer to HIF_CE_state. */ 83 struct HIF_CE_state *HIF_CE_state; 84 85 /* Instantaneous number of receive buffers that should be posted */ 86 atomic_t recv_bufs_needed; 87 qdf_size_t buf_sz; 88 qdf_spinlock_t recv_bufs_needed_lock; 89 90 qdf_spinlock_t completion_freeq_lock; 91 /* Limit the number of outstanding send requests. */ 92 int num_sends_allowed; 93 94 /* adding three counts for debugging ring buffer errors */ 95 uint32_t nbuf_alloc_err_count; 96 uint32_t nbuf_dma_err_count; 97 uint32_t nbuf_ce_enqueue_err_count; 98 struct hif_msg_callbacks pipe_callbacks; 99 }; 100 101 /** 102 * struct ce_tasklet_entry 103 * 104 * @intr_tq: intr_tq 105 * @ce_id: ce_id 106 * @inited: inited 107 * @hif_ce_state: hif_ce_state 108 * @from_irq: from_irq 109 */ 110 struct ce_tasklet_entry { 111 struct tasklet_struct intr_tq; 112 enum ce_id_type ce_id; 113 bool inited; 114 void *hif_ce_state; 115 }; 116 117 struct hif_ext_group_entry { 118 uint32_t numirq; 119 uint32_t irq[HIF_MAX_GRP_IRQ]; 120 uint32_t grp_id; 121 void *context; 122 ext_intr_handler handler; 123 struct tasklet_struct intr_tq; 124 bool configured; 125 bool inited; 126 void *hif_state; 127 }; 128 129 struct ce_intr_stats { 130 uint32_t ce_per_cpu[CE_COUNT_MAX][QDF_MAX_AVAILABLE_CPU]; 131 }; 132 133 struct HIF_CE_state { 134 struct hif_softc ol_sc; 135 bool started; 136 struct ce_tasklet_entry tasklets[CE_COUNT_MAX]; 137 struct hif_ext_group_entry hif_ext_group[HIF_MAX_GROUP]; 138 uint32_t hif_num_extgroup; 139 qdf_spinlock_t keep_awake_lock; 140 qdf_spinlock_t irq_reg_lock; 141 unsigned int keep_awake_count; 142 bool verified_awake; 143 bool fake_sleep; 144 qdf_timer_t sleep_timer; 145 bool sleep_timer_init; 146 qdf_time_t sleep_ticks; 147 uint32_t ce_register_irq_done; 148 149 struct CE_pipe_config *target_ce_config; 150 struct CE_attr *host_ce_config; 151 uint32_t target_ce_config_sz; 152 /* Per-pipe state. */ 153 struct HIF_CE_pipe_info pipe_info[CE_COUNT_MAX]; 154 /* to be activated after BMI_DONE */ 155 struct hif_msg_callbacks msg_callbacks_pending; 156 /* current msg callbacks in use */ 157 struct hif_msg_callbacks msg_callbacks_current; 158 159 /* Target address used to signal a pending firmware event */ 160 uint32_t fw_indicator_address; 161 162 /* Copy Engine used for Diagnostic Accesses */ 163 struct CE_handle *ce_diag; 164 struct ce_intr_stats stats; 165 struct ce_ops *ce_services; 166 }; 167 168 /* 169 * HIA Map Definition 170 */ 171 struct host_interest_area_t { 172 uint32_t hi_interconnect_state; 173 uint32_t hi_early_alloc; 174 uint32_t hi_option_flag2; 175 uint32_t hi_board_data; 176 uint32_t hi_board_data_initialized; 177 uint32_t hi_failure_state; 178 uint32_t hi_rddi_msi_num; 179 uint32_t hi_pcie_perst_couple_en; 180 uint32_t hi_sw_protocol_version; 181 }; 182 183 struct shadow_reg_cfg { 184 uint16_t ce_id; 185 uint16_t reg_offset; 186 }; 187 188 struct shadow_reg_v2_cfg { 189 uint32_t reg_value; 190 }; 191 192 void hif_ce_stop(struct hif_softc *scn); 193 int hif_dump_ce_registers(struct hif_softc *scn); 194 void 195 hif_ce_dump_target_memory(struct hif_softc *scn, void *ramdump_base, 196 uint32_t address, uint32_t size); 197 198 #ifdef IPA_OFFLOAD 199 void hif_ce_ipa_get_ce_resource(struct hif_softc *scn, 200 qdf_dma_addr_t *ce_sr_base_paddr, 201 uint32_t *ce_sr_ring_size, 202 qdf_dma_addr_t *ce_reg_paddr); 203 #else 204 static inline 205 void hif_ce_ipa_get_ce_resource(struct hif_softc *scn, 206 qdf_dma_addr_t *ce_sr_base_paddr, 207 uint32_t *ce_sr_ring_size, 208 qdf_dma_addr_t *ce_reg_paddr) 209 { 210 return; 211 } 212 213 #endif 214 int hif_wlan_enable(struct hif_softc *scn); 215 void hif_wlan_disable(struct hif_softc *scn); 216 void hif_get_target_ce_config(struct hif_softc *scn, 217 struct CE_pipe_config **target_ce_config_ret, 218 int *target_ce_config_sz_ret, 219 struct service_to_pipe **target_service_to_ce_map_ret, 220 int *target_service_to_ce_map_sz_ret, 221 struct shadow_reg_cfg **target_shadow_reg_cfg_v1_ret, 222 int *shadow_cfg_v1_sz_ret); 223 224 #endif /* __CE_H__ */ 225