1 /* 2 * Copyright (c) 2015-2019 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef __CE_H__ 20 #define __CE_H__ 21 22 #include "qdf_atomic.h" 23 #include "qdf_lock.h" 24 #include "hif_main.h" 25 #include "qdf_util.h" 26 #include "hif_exec.h" 27 28 #ifndef DATA_CE_SW_INDEX_NO_INLINE_UPDATE 29 #define DATA_CE_UPDATE_SWINDEX(x, scn, addr) \ 30 (x = CE_SRC_RING_READ_IDX_GET_FROM_DDR(scn, addr)) 31 #else 32 #define DATA_CE_UPDATE_SWINDEX(x, scn, addr) 33 #endif 34 35 /* 36 * Number of times to check for any pending tx/rx completion on 37 * a copy engine, this count should be big enough. Once we hit 38 * this threashold we'll not check for any Tx/Rx comlpetion in same 39 * interrupt handling. Note that this threashold is only used for 40 * Rx interrupt processing, this can be used tor Tx as well if we 41 * suspect any infinite loop in checking for pending Tx completion. 42 */ 43 #define CE_TXRX_COMP_CHECK_THRESHOLD 20 44 45 #define CE_HTT_T2H_MSG 1 46 #define CE_HTT_H2T_MSG 4 47 48 #define CE_OFFSET 0x00000400 49 #define CE_USEFUL_SIZE 0x00000058 50 #define CE_ALL_BITMAP 0xFFFF 51 52 /** 53 * enum ce_id_type 54 * 55 * @ce_id_type: Copy engine ID 56 */ 57 enum ce_id_type { 58 CE_ID_0, 59 CE_ID_1, 60 CE_ID_2, 61 CE_ID_3, 62 CE_ID_4, 63 CE_ID_5, 64 CE_ID_6, 65 CE_ID_7, 66 CE_ID_8, 67 CE_ID_9, 68 CE_ID_10, 69 CE_ID_11, 70 CE_ID_MAX 71 }; 72 73 enum ce_target_type { 74 CE_SVC_LEGACY, 75 CE_SVC_SRNG, 76 CE_MAX_TARGET_TYPE 77 }; 78 79 enum ol_ath_hif_pkt_ecodes { 80 HIF_PIPE_NO_RESOURCE = 0 81 }; 82 83 struct HIF_CE_state; 84 85 /* Per-pipe state. */ 86 struct HIF_CE_pipe_info { 87 /* Handle of underlying Copy Engine */ 88 struct CE_handle *ce_hdl; 89 90 /* Our pipe number; facilitiates use of pipe_info ptrs. */ 91 uint8_t pipe_num; 92 93 /* Convenience back pointer to HIF_CE_state. */ 94 struct HIF_CE_state *HIF_CE_state; 95 96 /* Instantaneous number of receive buffers that should be posted */ 97 atomic_t recv_bufs_needed; 98 qdf_size_t buf_sz; 99 qdf_spinlock_t recv_bufs_needed_lock; 100 101 qdf_spinlock_t completion_freeq_lock; 102 /* Limit the number of outstanding send requests. */ 103 int num_sends_allowed; 104 105 /* adding three counts for debugging ring buffer errors */ 106 uint32_t nbuf_alloc_err_count; 107 uint32_t nbuf_dma_err_count; 108 uint32_t nbuf_ce_enqueue_err_count; 109 struct hif_msg_callbacks pipe_callbacks; 110 }; 111 112 /** 113 * struct ce_tasklet_entry 114 * 115 * @intr_tq: intr_tq 116 * @ce_id: ce_id 117 * @inited: inited 118 * @hif_ce_state: hif_ce_state 119 * @from_irq: from_irq 120 */ 121 struct ce_tasklet_entry { 122 struct tasklet_struct intr_tq; 123 enum ce_id_type ce_id; 124 bool inited; 125 void *hif_ce_state; 126 }; 127 128 static inline bool hif_dummy_grp_done(struct hif_exec_context *grp_entry, int 129 work_done) 130 { 131 return true; 132 } 133 134 extern struct hif_execution_ops tasklet_sched_ops; 135 extern struct hif_execution_ops napi_sched_ops; 136 137 struct ce_stats { 138 uint32_t ce_per_cpu[CE_COUNT_MAX][QDF_MAX_AVAILABLE_CPU]; 139 }; 140 141 struct HIF_CE_state { 142 struct hif_softc ol_sc; 143 bool started; 144 struct ce_tasklet_entry tasklets[CE_COUNT_MAX]; 145 struct hif_exec_context *hif_ext_group[HIF_MAX_GROUP]; 146 uint32_t hif_num_extgroup; 147 qdf_spinlock_t keep_awake_lock; 148 qdf_spinlock_t irq_reg_lock; 149 unsigned int keep_awake_count; 150 bool verified_awake; 151 bool fake_sleep; 152 qdf_timer_t sleep_timer; 153 bool sleep_timer_init; 154 qdf_time_t sleep_ticks; 155 uint32_t ce_register_irq_done; 156 157 struct CE_pipe_config *target_ce_config; 158 struct CE_attr *host_ce_config; 159 uint32_t target_ce_config_sz; 160 /* Per-pipe state. */ 161 struct HIF_CE_pipe_info pipe_info[CE_COUNT_MAX]; 162 /* to be activated after BMI_DONE */ 163 struct hif_msg_callbacks msg_callbacks_pending; 164 /* current msg callbacks in use */ 165 struct hif_msg_callbacks msg_callbacks_current; 166 167 /* Target address used to signal a pending firmware event */ 168 uint32_t fw_indicator_address; 169 170 /* Copy Engine used for Diagnostic Accesses */ 171 struct CE_handle *ce_diag; 172 struct ce_stats stats; 173 struct ce_ops *ce_services; 174 }; 175 176 /* 177 * HIA Map Definition 178 */ 179 struct host_interest_area_t { 180 uint32_t hi_interconnect_state; 181 uint32_t hi_early_alloc; 182 uint32_t hi_option_flag2; 183 uint32_t hi_board_data; 184 uint32_t hi_board_data_initialized; 185 uint32_t hi_failure_state; 186 uint32_t hi_rddi_msi_num; 187 uint32_t hi_pcie_perst_couple_en; 188 uint32_t hi_sw_protocol_version; 189 }; 190 191 struct shadow_reg_cfg { 192 uint16_t ce_id; 193 uint16_t reg_offset; 194 }; 195 196 struct shadow_reg_v2_cfg { 197 uint32_t reg_value; 198 }; 199 200 #ifdef CONFIG_BYPASS_QMI 201 202 #define FW_SHARED_MEM (2 * 1024 * 1024) 203 204 #ifdef QCN7605_SUPPORT 205 struct msi_cfg { 206 u16 ce_id; 207 u16 msi_vector; 208 } qdf_packed; 209 210 struct ce_info { 211 u32 rri_over_ddr_low_paddr; 212 u32 rri_over_ddr_high_paddr; 213 struct msi_cfg cfg[CE_COUNT_MAX]; 214 } qdf_packed; 215 #endif 216 #endif 217 218 void hif_ce_stop(struct hif_softc *scn); 219 int hif_dump_ce_registers(struct hif_softc *scn); 220 void 221 hif_ce_dump_target_memory(struct hif_softc *scn, void *ramdump_base, 222 uint32_t address, uint32_t size); 223 224 #ifdef IPA_OFFLOAD 225 void hif_ce_ipa_get_ce_resource(struct hif_softc *scn, 226 qdf_shared_mem_t **ce_sr, 227 uint32_t *ce_sr_ring_size, 228 qdf_dma_addr_t *ce_reg_paddr); 229 #else 230 static inline 231 void hif_ce_ipa_get_ce_resource(struct hif_softc *scn, 232 qdf_shared_mem_t **ce_sr, 233 uint32_t *ce_sr_ring_size, 234 qdf_dma_addr_t *ce_reg_paddr) 235 { 236 } 237 238 #endif 239 int hif_wlan_enable(struct hif_softc *scn); 240 void ce_enable_polling(void *cestate); 241 void ce_disable_polling(void *cestate); 242 void hif_wlan_disable(struct hif_softc *scn); 243 void hif_get_target_ce_config(struct hif_softc *scn, 244 struct CE_pipe_config **target_ce_config_ret, 245 uint32_t *target_ce_config_sz_ret, 246 struct service_to_pipe **target_service_to_ce_map_ret, 247 uint32_t *target_service_to_ce_map_sz_ret, 248 struct shadow_reg_cfg **target_shadow_reg_cfg_v1_ret, 249 uint32_t *shadow_cfg_v1_sz_ret); 250 251 #ifdef WLAN_FEATURE_EPPING 252 void hif_ce_prepare_epping_config(struct HIF_CE_state *hif_state); 253 void hif_select_epping_service_to_pipe_map(struct service_to_pipe 254 **tgt_svc_map_to_use, 255 uint32_t *sz_tgt_svc_map_to_use); 256 257 #else 258 static inline 259 void hif_ce_prepare_epping_config(struct HIF_CE_state *hif_state) 260 { } 261 static inline 262 void hif_select_epping_service_to_pipe_map(struct service_to_pipe 263 **tgt_svc_map_to_use, 264 uint32_t *sz_tgt_svc_map_to_use) 265 { } 266 #endif 267 268 void ce_service_register_module(enum ce_target_type target_type, 269 struct ce_ops* (*ce_attach)(void)); 270 271 #endif /* __CE_H__ */ 272