1 /* 2 * Copyright (c) 2013-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include "targcfg.h" 21 #include "qdf_lock.h" 22 #include "qdf_status.h" 23 #include "qdf_status.h" 24 #include <qdf_atomic.h> /* qdf_atomic_read */ 25 #include <targaddrs.h> 26 #include "hif_io32.h" 27 #include <hif.h> 28 #include <target_type.h> 29 #include "regtable.h" 30 #define ATH_MODULE_NAME hif 31 #include <a_debug.h> 32 #include "hif_main.h" 33 #include "ce_api.h" 34 #include "qdf_trace.h" 35 #include "pld_common.h" 36 #include "hif_debug.h" 37 #include "ce_internal.h" 38 #include "ce_reg.h" 39 #include "ce_assignment.h" 40 #include "ce_tasklet.h" 41 #include "qdf_module.h" 42 43 #define CE_POLL_TIMEOUT 10 /* ms */ 44 45 #define AGC_DUMP 1 46 #define CHANINFO_DUMP 2 47 #define BB_WATCHDOG_DUMP 3 48 #ifdef CONFIG_ATH_PCIE_ACCESS_DEBUG 49 #define PCIE_ACCESS_DUMP 4 50 #endif 51 #include "mp_dev.h" 52 #ifdef HIF_CE_LOG_INFO 53 #include "qdf_hang_event_notifier.h" 54 #endif 55 56 #if (defined(QCA_WIFI_QCA8074) || defined(QCA_WIFI_QCA6290) || \ 57 defined(QCA_WIFI_QCA6018) || defined(QCA_WIFI_QCA5018) || \ 58 defined(QCA_WIFI_KIWI) || defined(QCA_WIFI_QCA5332) || \ 59 defined(QCA_WIFI_QCA9574)) && !defined(QCA_WIFI_SUPPORT_SRNG) 60 #define QCA_WIFI_SUPPORT_SRNG 61 #endif 62 63 #ifdef QCA_WIFI_SUPPORT_SRNG 64 #include <hal_api.h> 65 #endif 66 67 /* Forward references */ 68 QDF_STATUS hif_post_recv_buffers_for_pipe(struct HIF_CE_pipe_info *pipe_info); 69 70 /* 71 * Fix EV118783, poll to check whether a BMI response comes 72 * other than waiting for the interruption which may be lost. 73 */ 74 /* #define BMI_RSP_POLLING */ 75 #define BMI_RSP_TO_MILLISEC 1000 76 77 #ifdef CONFIG_BYPASS_QMI 78 #define BYPASS_QMI 1 79 #else 80 #define BYPASS_QMI 0 81 #endif 82 83 #ifdef ENABLE_10_4_FW_HDR 84 #if (ENABLE_10_4_FW_HDR == 1) 85 #define WDI_IPA_SERVICE_GROUP 5 86 #define WDI_IPA_TX_SVC MAKE_SERVICE_ID(WDI_IPA_SERVICE_GROUP, 0) 87 #define HTT_DATA2_MSG_SVC MAKE_SERVICE_ID(HTT_SERVICE_GROUP, 1) 88 #define HTT_DATA3_MSG_SVC MAKE_SERVICE_ID(HTT_SERVICE_GROUP, 2) 89 #endif /* ENABLE_10_4_FW_HDR == 1 */ 90 #endif /* ENABLE_10_4_FW_HDR */ 91 92 static void hif_config_rri_on_ddr(struct hif_softc *scn); 93 94 /** 95 * hif_target_access_log_dump() - dump access log 96 * 97 * dump access log 98 * 99 * Return: n/a 100 */ 101 #ifdef CONFIG_ATH_PCIE_ACCESS_DEBUG 102 static void hif_target_access_log_dump(void) 103 { 104 hif_target_dump_access_log(); 105 } 106 #endif 107 108 /* 109 * This structure contains the interrupt index for each Copy engine 110 * for various number of MSIs available in the system. 111 */ 112 static struct ce_int_assignment ce_int_context[NUM_CE_CONTEXT] = { 113 /* Default configuration */ 114 {{ CE_INTERRUPT_IDX(0), 115 CE_INTERRUPT_IDX(1), 116 CE_INTERRUPT_IDX(2), 117 CE_INTERRUPT_IDX(3), 118 CE_INTERRUPT_IDX(4), 119 CE_INTERRUPT_IDX(5), 120 CE_INTERRUPT_IDX(6), 121 CE_INTERRUPT_IDX(7), 122 CE_INTERRUPT_IDX(8), 123 CE_INTERRUPT_IDX(9), 124 CE_INTERRUPT_IDX(10), 125 CE_INTERRUPT_IDX(11), 126 #ifdef QCA_WIFI_QCN9224 127 CE_INTERRUPT_IDX(12), 128 CE_INTERRUPT_IDX(13), 129 CE_INTERRUPT_IDX(14), 130 CE_INTERRUPT_IDX(15), 131 #endif 132 } }, 133 /* Interrupt assignment for 1 MSI combination */ 134 {{ CE_INTERRUPT_IDX(0), 135 CE_INTERRUPT_IDX(0), 136 CE_INTERRUPT_IDX(0), 137 CE_INTERRUPT_IDX(0), 138 CE_INTERRUPT_IDX(0), 139 CE_INTERRUPT_IDX(0), 140 CE_INTERRUPT_IDX(0), 141 CE_INTERRUPT_IDX(0), 142 CE_INTERRUPT_IDX(0), 143 CE_INTERRUPT_IDX(0), 144 CE_INTERRUPT_IDX(0), 145 CE_INTERRUPT_IDX(0), 146 #ifdef QCA_WIFI_QCN9224 147 CE_INTERRUPT_IDX(0), 148 CE_INTERRUPT_IDX(0), 149 CE_INTERRUPT_IDX(0), 150 CE_INTERRUPT_IDX(0), 151 #endif 152 } }, 153 /* Interrupt assignment for 2 MSI combination */ 154 {{ CE_INTERRUPT_IDX(0), 155 CE_INTERRUPT_IDX(1), 156 CE_INTERRUPT_IDX(0), 157 CE_INTERRUPT_IDX(1), 158 CE_INTERRUPT_IDX(0), 159 CE_INTERRUPT_IDX(1), 160 CE_INTERRUPT_IDX(0), 161 CE_INTERRUPT_IDX(0), 162 CE_INTERRUPT_IDX(0), 163 CE_INTERRUPT_IDX(0), 164 CE_INTERRUPT_IDX(0), 165 CE_INTERRUPT_IDX(0), 166 #ifdef QCA_WIFI_QCN9224 167 CE_INTERRUPT_IDX(0), 168 CE_INTERRUPT_IDX(0), 169 CE_INTERRUPT_IDX(0), 170 CE_INTERRUPT_IDX(0), 171 #endif 172 } }, 173 /* Interrupt assignment for 3 MSI combination */ 174 {{ CE_INTERRUPT_IDX(0), 175 CE_INTERRUPT_IDX(1), 176 CE_INTERRUPT_IDX(2), 177 CE_INTERRUPT_IDX(1), 178 CE_INTERRUPT_IDX(0), 179 CE_INTERRUPT_IDX(1), 180 CE_INTERRUPT_IDX(0), 181 CE_INTERRUPT_IDX(0), 182 CE_INTERRUPT_IDX(0), 183 CE_INTERRUPT_IDX(0), 184 CE_INTERRUPT_IDX(0), 185 CE_INTERRUPT_IDX(0), 186 #ifdef QCA_WIFI_QCN9224 187 CE_INTERRUPT_IDX(0), 188 CE_INTERRUPT_IDX(0), 189 CE_INTERRUPT_IDX(0), 190 CE_INTERRUPT_IDX(0), 191 #endif 192 } }, 193 /* Interrupt assignment for 4 MSI combination */ 194 {{ CE_INTERRUPT_IDX(0), 195 CE_INTERRUPT_IDX(1), 196 CE_INTERRUPT_IDX(2), 197 CE_INTERRUPT_IDX(3), 198 CE_INTERRUPT_IDX(0), 199 CE_INTERRUPT_IDX(1), 200 CE_INTERRUPT_IDX(0), 201 CE_INTERRUPT_IDX(0), 202 CE_INTERRUPT_IDX(0), 203 CE_INTERRUPT_IDX(0), 204 CE_INTERRUPT_IDX(0), 205 CE_INTERRUPT_IDX(0), 206 #ifdef QCA_WIFI_QCN9224 207 CE_INTERRUPT_IDX(0), 208 CE_INTERRUPT_IDX(0), 209 CE_INTERRUPT_IDX(0), 210 CE_INTERRUPT_IDX(0), 211 #endif 212 } }, 213 /* Interrupt assignment for 5 MSI combination */ 214 {{ CE_INTERRUPT_IDX(0), 215 CE_INTERRUPT_IDX(1), 216 CE_INTERRUPT_IDX(2), 217 CE_INTERRUPT_IDX(3), 218 CE_INTERRUPT_IDX(0), 219 CE_INTERRUPT_IDX(4), 220 CE_INTERRUPT_IDX(0), 221 CE_INTERRUPT_IDX(0), 222 CE_INTERRUPT_IDX(0), 223 CE_INTERRUPT_IDX(0), 224 CE_INTERRUPT_IDX(0), 225 CE_INTERRUPT_IDX(0), 226 #ifdef QCA_WIFI_QCN9224 227 CE_INTERRUPT_IDX(0), 228 CE_INTERRUPT_IDX(0), 229 CE_INTERRUPT_IDX(0), 230 CE_INTERRUPT_IDX(0), 231 #endif 232 } }, 233 /* Interrupt assignment for 6 MSI combination */ 234 {{ CE_INTERRUPT_IDX(0), 235 CE_INTERRUPT_IDX(1), 236 CE_INTERRUPT_IDX(2), 237 CE_INTERRUPT_IDX(3), 238 CE_INTERRUPT_IDX(4), 239 CE_INTERRUPT_IDX(5), 240 CE_INTERRUPT_IDX(0), 241 CE_INTERRUPT_IDX(0), 242 CE_INTERRUPT_IDX(0), 243 CE_INTERRUPT_IDX(0), 244 CE_INTERRUPT_IDX(0), 245 CE_INTERRUPT_IDX(0), 246 #ifdef QCA_WIFI_QCN9224 247 CE_INTERRUPT_IDX(0), 248 CE_INTERRUPT_IDX(0), 249 CE_INTERRUPT_IDX(0), 250 CE_INTERRUPT_IDX(0), 251 #endif 252 } }, 253 /* Interrupt assignment for 7 MSI combination */ 254 {{ CE_INTERRUPT_IDX(0), 255 CE_INTERRUPT_IDX(1), 256 CE_INTERRUPT_IDX(2), 257 CE_INTERRUPT_IDX(3), 258 CE_INTERRUPT_IDX(4), 259 CE_INTERRUPT_IDX(5), 260 CE_INTERRUPT_IDX(6), 261 CE_INTERRUPT_IDX(0), 262 CE_INTERRUPT_IDX(0), 263 CE_INTERRUPT_IDX(0), 264 CE_INTERRUPT_IDX(0), 265 CE_INTERRUPT_IDX(0), 266 #ifdef QCA_WIFI_QCN9224 267 CE_INTERRUPT_IDX(0), 268 CE_INTERRUPT_IDX(0), 269 CE_INTERRUPT_IDX(0), 270 CE_INTERRUPT_IDX(0), 271 #endif 272 } }, 273 /* Interrupt assignment for 8 MSI combination */ 274 {{ CE_INTERRUPT_IDX(0), 275 CE_INTERRUPT_IDX(1), 276 CE_INTERRUPT_IDX(2), 277 CE_INTERRUPT_IDX(3), 278 CE_INTERRUPT_IDX(4), 279 CE_INTERRUPT_IDX(5), 280 CE_INTERRUPT_IDX(6), 281 CE_INTERRUPT_IDX(7), 282 CE_INTERRUPT_IDX(0), 283 CE_INTERRUPT_IDX(0), 284 CE_INTERRUPT_IDX(0), 285 CE_INTERRUPT_IDX(0), 286 #ifdef QCA_WIFI_QCN9224 287 CE_INTERRUPT_IDX(0), 288 CE_INTERRUPT_IDX(0), 289 CE_INTERRUPT_IDX(0), 290 CE_INTERRUPT_IDX(0), 291 #endif 292 } }, 293 /* Interrupt assignment for 9 MSI combination */ 294 {{ CE_INTERRUPT_IDX(0), 295 CE_INTERRUPT_IDX(1), 296 CE_INTERRUPT_IDX(2), 297 CE_INTERRUPT_IDX(3), 298 CE_INTERRUPT_IDX(4), 299 CE_INTERRUPT_IDX(5), 300 CE_INTERRUPT_IDX(6), 301 CE_INTERRUPT_IDX(7), 302 CE_INTERRUPT_IDX(8), 303 CE_INTERRUPT_IDX(0), 304 CE_INTERRUPT_IDX(0), 305 CE_INTERRUPT_IDX(0), 306 #ifdef QCA_WIFI_QCN9224 307 CE_INTERRUPT_IDX(0), 308 CE_INTERRUPT_IDX(0), 309 CE_INTERRUPT_IDX(0), 310 CE_INTERRUPT_IDX(0), 311 #endif 312 } }, 313 /* Interrupt assignment for 10 MSI combination */ 314 {{ CE_INTERRUPT_IDX(0), 315 CE_INTERRUPT_IDX(1), 316 CE_INTERRUPT_IDX(2), 317 CE_INTERRUPT_IDX(3), 318 CE_INTERRUPT_IDX(4), 319 CE_INTERRUPT_IDX(5), 320 CE_INTERRUPT_IDX(6), 321 CE_INTERRUPT_IDX(7), 322 CE_INTERRUPT_IDX(8), 323 CE_INTERRUPT_IDX(9), 324 CE_INTERRUPT_IDX(0), 325 CE_INTERRUPT_IDX(0), 326 #ifdef QCA_WIFI_QCN9224 327 CE_INTERRUPT_IDX(0), 328 CE_INTERRUPT_IDX(0), 329 CE_INTERRUPT_IDX(0), 330 CE_INTERRUPT_IDX(0), 331 #endif 332 } }, 333 /* Interrupt assignment for 11 MSI combination */ 334 {{ CE_INTERRUPT_IDX(0), 335 CE_INTERRUPT_IDX(1), 336 CE_INTERRUPT_IDX(2), 337 CE_INTERRUPT_IDX(3), 338 CE_INTERRUPT_IDX(4), 339 CE_INTERRUPT_IDX(5), 340 CE_INTERRUPT_IDX(6), 341 CE_INTERRUPT_IDX(7), 342 CE_INTERRUPT_IDX(8), 343 CE_INTERRUPT_IDX(9), 344 CE_INTERRUPT_IDX(10), 345 CE_INTERRUPT_IDX(0), 346 #ifdef QCA_WIFI_QCN9224 347 CE_INTERRUPT_IDX(0), 348 CE_INTERRUPT_IDX(0), 349 CE_INTERRUPT_IDX(0), 350 CE_INTERRUPT_IDX(0), 351 #endif 352 } }, 353 /* Interrupt assignment for 12 MSI combination */ 354 {{ CE_INTERRUPT_IDX(0), 355 CE_INTERRUPT_IDX(1), 356 CE_INTERRUPT_IDX(2), 357 CE_INTERRUPT_IDX(3), 358 CE_INTERRUPT_IDX(4), 359 CE_INTERRUPT_IDX(5), 360 CE_INTERRUPT_IDX(6), 361 CE_INTERRUPT_IDX(7), 362 CE_INTERRUPT_IDX(8), 363 CE_INTERRUPT_IDX(9), 364 CE_INTERRUPT_IDX(10), 365 CE_INTERRUPT_IDX(11), 366 #ifdef QCA_WIFI_QCN9224 367 CE_INTERRUPT_IDX(0), 368 CE_INTERRUPT_IDX(0), 369 CE_INTERRUPT_IDX(0), 370 CE_INTERRUPT_IDX(0), 371 #endif 372 } }, 373 #ifdef QCA_WIFI_QCN9224 374 /* Interrupt assignment for 13 MSI combination */ 375 {{ CE_INTERRUPT_IDX(0), 376 CE_INTERRUPT_IDX(1), 377 CE_INTERRUPT_IDX(2), 378 CE_INTERRUPT_IDX(3), 379 CE_INTERRUPT_IDX(4), 380 CE_INTERRUPT_IDX(5), 381 CE_INTERRUPT_IDX(6), 382 CE_INTERRUPT_IDX(7), 383 CE_INTERRUPT_IDX(8), 384 CE_INTERRUPT_IDX(9), 385 CE_INTERRUPT_IDX(10), 386 CE_INTERRUPT_IDX(11), 387 CE_INTERRUPT_IDX(12), 388 CE_INTERRUPT_IDX(0), 389 CE_INTERRUPT_IDX(0), 390 CE_INTERRUPT_IDX(0), 391 } }, 392 /* Interrupt assignment for 14 MSI combination */ 393 {{ CE_INTERRUPT_IDX(0), 394 CE_INTERRUPT_IDX(1), 395 CE_INTERRUPT_IDX(2), 396 CE_INTERRUPT_IDX(3), 397 CE_INTERRUPT_IDX(4), 398 CE_INTERRUPT_IDX(5), 399 CE_INTERRUPT_IDX(6), 400 CE_INTERRUPT_IDX(7), 401 CE_INTERRUPT_IDX(8), 402 CE_INTERRUPT_IDX(9), 403 CE_INTERRUPT_IDX(10), 404 CE_INTERRUPT_IDX(11), 405 CE_INTERRUPT_IDX(12), 406 CE_INTERRUPT_IDX(13), 407 CE_INTERRUPT_IDX(0), 408 CE_INTERRUPT_IDX(0), 409 } }, 410 /* Interrupt assignment for 15 MSI combination */ 411 {{ CE_INTERRUPT_IDX(0), 412 CE_INTERRUPT_IDX(1), 413 CE_INTERRUPT_IDX(2), 414 CE_INTERRUPT_IDX(3), 415 CE_INTERRUPT_IDX(4), 416 CE_INTERRUPT_IDX(5), 417 CE_INTERRUPT_IDX(6), 418 CE_INTERRUPT_IDX(7), 419 CE_INTERRUPT_IDX(8), 420 CE_INTERRUPT_IDX(9), 421 CE_INTERRUPT_IDX(10), 422 CE_INTERRUPT_IDX(11), 423 CE_INTERRUPT_IDX(12), 424 CE_INTERRUPT_IDX(13), 425 CE_INTERRUPT_IDX(14), 426 CE_INTERRUPT_IDX(0), 427 } }, 428 /* Interrupt assignment for 16 MSI combination */ 429 {{ CE_INTERRUPT_IDX(0), 430 CE_INTERRUPT_IDX(1), 431 CE_INTERRUPT_IDX(2), 432 CE_INTERRUPT_IDX(3), 433 CE_INTERRUPT_IDX(4), 434 CE_INTERRUPT_IDX(5), 435 CE_INTERRUPT_IDX(6), 436 CE_INTERRUPT_IDX(7), 437 CE_INTERRUPT_IDX(8), 438 CE_INTERRUPT_IDX(9), 439 CE_INTERRUPT_IDX(10), 440 CE_INTERRUPT_IDX(11), 441 CE_INTERRUPT_IDX(12), 442 CE_INTERRUPT_IDX(13), 443 CE_INTERRUPT_IDX(14), 444 CE_INTERRUPT_IDX(15), 445 } }, 446 #endif 447 }; 448 449 450 void hif_trigger_dump(struct hif_opaque_softc *hif_ctx, 451 uint8_t cmd_id, bool start) 452 { 453 struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); 454 455 switch (cmd_id) { 456 case AGC_DUMP: 457 if (start) 458 priv_start_agc(scn); 459 else 460 priv_dump_agc(scn); 461 break; 462 case CHANINFO_DUMP: 463 if (start) 464 priv_start_cap_chaninfo(scn); 465 else 466 priv_dump_chaninfo(scn); 467 break; 468 case BB_WATCHDOG_DUMP: 469 priv_dump_bbwatchdog(scn); 470 break; 471 #ifdef CONFIG_ATH_PCIE_ACCESS_DEBUG 472 case PCIE_ACCESS_DUMP: 473 hif_target_access_log_dump(); 474 break; 475 #endif 476 default: 477 hif_err("Invalid htc dump command: %d", cmd_id); 478 break; 479 } 480 } 481 482 static void ce_poll_timeout(void *arg) 483 { 484 struct CE_state *CE_state = (struct CE_state *)arg; 485 486 if (CE_state->timer_inited) { 487 ce_per_engine_service(CE_state->scn, CE_state->id); 488 qdf_timer_mod(&CE_state->poll_timer, CE_POLL_TIMEOUT); 489 } 490 } 491 492 static unsigned int roundup_pwr2(unsigned int n) 493 { 494 int i; 495 unsigned int test_pwr2; 496 497 if (!(n & (n - 1))) 498 return n; /* already a power of 2 */ 499 500 test_pwr2 = 4; 501 for (i = 0; i < 29; i++) { 502 if (test_pwr2 > n) 503 return test_pwr2; 504 test_pwr2 = test_pwr2 << 1; 505 } 506 507 QDF_ASSERT(0); /* n too large */ 508 return 0; 509 } 510 511 #define ADRASTEA_SRC_WR_INDEX_OFFSET 0x3C 512 #define ADRASTEA_DST_WR_INDEX_OFFSET 0x40 513 514 static struct shadow_reg_cfg target_shadow_reg_cfg_map[] = { 515 { 0, ADRASTEA_SRC_WR_INDEX_OFFSET}, 516 { 3, ADRASTEA_SRC_WR_INDEX_OFFSET}, 517 { 4, ADRASTEA_SRC_WR_INDEX_OFFSET}, 518 { 5, ADRASTEA_SRC_WR_INDEX_OFFSET}, 519 { 7, ADRASTEA_SRC_WR_INDEX_OFFSET}, 520 { 1, ADRASTEA_DST_WR_INDEX_OFFSET}, 521 { 2, ADRASTEA_DST_WR_INDEX_OFFSET}, 522 { 7, ADRASTEA_DST_WR_INDEX_OFFSET}, 523 { 8, ADRASTEA_DST_WR_INDEX_OFFSET}, 524 #ifdef QCA_WIFI_3_0_ADRASTEA 525 { 9, ADRASTEA_DST_WR_INDEX_OFFSET}, 526 { 10, ADRASTEA_DST_WR_INDEX_OFFSET}, 527 { 11, ADRASTEA_DST_WR_INDEX_OFFSET}, 528 #endif 529 }; 530 531 #ifdef QCN7605_SUPPORT 532 static struct shadow_reg_cfg target_shadow_reg_cfg_map_qcn7605[] = { 533 { 0, ADRASTEA_SRC_WR_INDEX_OFFSET}, 534 { 4, ADRASTEA_SRC_WR_INDEX_OFFSET}, 535 { 5, ADRASTEA_SRC_WR_INDEX_OFFSET}, 536 { 3, ADRASTEA_DST_WR_INDEX_OFFSET}, 537 { 1, ADRASTEA_DST_WR_INDEX_OFFSET}, 538 { 2, ADRASTEA_DST_WR_INDEX_OFFSET}, 539 { 7, ADRASTEA_DST_WR_INDEX_OFFSET}, 540 { 8, ADRASTEA_DST_WR_INDEX_OFFSET}, 541 }; 542 #endif 543 544 #ifdef WLAN_FEATURE_EPPING 545 static struct shadow_reg_cfg target_shadow_reg_cfg_epping[] = { 546 { 0, ADRASTEA_SRC_WR_INDEX_OFFSET}, 547 { 3, ADRASTEA_SRC_WR_INDEX_OFFSET}, 548 { 4, ADRASTEA_SRC_WR_INDEX_OFFSET}, 549 { 7, ADRASTEA_SRC_WR_INDEX_OFFSET}, 550 { 1, ADRASTEA_DST_WR_INDEX_OFFSET}, 551 { 2, ADRASTEA_DST_WR_INDEX_OFFSET}, 552 { 5, ADRASTEA_DST_WR_INDEX_OFFSET}, 553 { 7, ADRASTEA_DST_WR_INDEX_OFFSET}, 554 { 8, ADRASTEA_DST_WR_INDEX_OFFSET}, 555 }; 556 #endif 557 558 /* CE_PCI TABLE */ 559 /* 560 * NOTE: the table below is out of date, though still a useful reference. 561 * Refer to target_service_to_ce_map and hif_map_service_to_pipe for the actual 562 * mapping of HTC services to HIF pipes. 563 */ 564 /* 565 * This authoritative table defines Copy Engine configuration and the mapping 566 * of services/endpoints to CEs. A subset of this information is passed to 567 * the Target during startup as a prerequisite to entering BMI phase. 568 * See: 569 * target_service_to_ce_map - Target-side mapping 570 * hif_map_service_to_pipe - Host-side mapping 571 * target_ce_config - Target-side configuration 572 * host_ce_config - Host-side configuration 573 ============================================================================ 574 Purpose | Service / Endpoint | CE | Dire | Xfer | Xfer 575 | | | ctio | Size | Frequency 576 | | | n | | 577 ============================================================================ 578 tx | HTT_DATA (downlink) | CE 0 | h->t | medium - | very frequent 579 descriptor | | | | O(100B) | and regular 580 download | | | | | 581 ---------------------------------------------------------------------------- 582 rx | HTT_DATA (uplink) | CE 1 | t->h | small - | frequent and 583 indication | | | | O(10B) | regular 584 upload | | | | | 585 ---------------------------------------------------------------------------- 586 MSDU | DATA_BK (uplink) | CE 2 | t->h | large - | rare 587 upload | | | | O(1000B) | (frequent 588 e.g. noise | | | | | during IP1.0 589 packets | | | | | testing) 590 ---------------------------------------------------------------------------- 591 MSDU | DATA_BK (downlink) | CE 3 | h->t | large - | very rare 592 download | | | | O(1000B) | (frequent 593 e.g. | | | | | during IP1.0 594 misdirecte | | | | | testing) 595 d EAPOL | | | | | 596 packets | | | | | 597 ---------------------------------------------------------------------------- 598 n/a | DATA_BE, DATA_VI | CE 2 | t->h | | never(?) 599 | DATA_VO (uplink) | | | | 600 ---------------------------------------------------------------------------- 601 n/a | DATA_BE, DATA_VI | CE 3 | h->t | | never(?) 602 | DATA_VO (downlink) | | | | 603 ---------------------------------------------------------------------------- 604 WMI events | WMI_CONTROL (uplink) | CE 4 | t->h | medium - | infrequent 605 | | | | O(100B) | 606 ---------------------------------------------------------------------------- 607 WMI | WMI_CONTROL | CE 5 | h->t | medium - | infrequent 608 messages | (downlink) | | | O(100B) | 609 | | | | | 610 ---------------------------------------------------------------------------- 611 n/a | HTC_CTRL_RSVD, | CE 1 | t->h | | never(?) 612 | HTC_RAW_STREAMS | | | | 613 | (uplink) | | | | 614 ---------------------------------------------------------------------------- 615 n/a | HTC_CTRL_RSVD, | CE 0 | h->t | | never(?) 616 | HTC_RAW_STREAMS | | | | 617 | (downlink) | | | | 618 ---------------------------------------------------------------------------- 619 diag | none (raw CE) | CE 7 | t<>h | 4 | Diag Window 620 | | | | | infrequent 621 ============================================================================ 622 */ 623 624 /* 625 * Map from service/endpoint to Copy Engine. 626 * This table is derived from the CE_PCI TABLE, above. 627 * It is passed to the Target at startup for use by firmware. 628 */ 629 static struct service_to_pipe target_service_to_ce_map_wlan[] = { 630 { 631 WMI_DATA_VO_SVC, 632 PIPEDIR_OUT, /* out = UL = host -> target */ 633 3, 634 }, 635 { 636 WMI_DATA_VO_SVC, 637 PIPEDIR_IN, /* in = DL = target -> host */ 638 2, 639 }, 640 { 641 WMI_DATA_BK_SVC, 642 PIPEDIR_OUT, /* out = UL = host -> target */ 643 3, 644 }, 645 { 646 WMI_DATA_BK_SVC, 647 PIPEDIR_IN, /* in = DL = target -> host */ 648 2, 649 }, 650 { 651 WMI_DATA_BE_SVC, 652 PIPEDIR_OUT, /* out = UL = host -> target */ 653 3, 654 }, 655 { 656 WMI_DATA_BE_SVC, 657 PIPEDIR_IN, /* in = DL = target -> host */ 658 2, 659 }, 660 { 661 WMI_DATA_VI_SVC, 662 PIPEDIR_OUT, /* out = UL = host -> target */ 663 3, 664 }, 665 { 666 WMI_DATA_VI_SVC, 667 PIPEDIR_IN, /* in = DL = target -> host */ 668 2, 669 }, 670 { 671 WMI_CONTROL_SVC, 672 PIPEDIR_OUT, /* out = UL = host -> target */ 673 3, 674 }, 675 { 676 WMI_CONTROL_SVC, 677 PIPEDIR_IN, /* in = DL = target -> host */ 678 2, 679 }, 680 { 681 HTC_CTRL_RSVD_SVC, 682 PIPEDIR_OUT, /* out = UL = host -> target */ 683 0, /* could be moved to 3 (share with WMI) */ 684 }, 685 { 686 HTC_CTRL_RSVD_SVC, 687 PIPEDIR_IN, /* in = DL = target -> host */ 688 2, 689 }, 690 { 691 HTC_RAW_STREAMS_SVC, /* not currently used */ 692 PIPEDIR_OUT, /* out = UL = host -> target */ 693 0, 694 }, 695 { 696 HTC_RAW_STREAMS_SVC, /* not currently used */ 697 PIPEDIR_IN, /* in = DL = target -> host */ 698 2, 699 }, 700 { 701 HTT_DATA_MSG_SVC, 702 PIPEDIR_OUT, /* out = UL = host -> target */ 703 4, 704 }, 705 { 706 HTT_DATA_MSG_SVC, 707 PIPEDIR_IN, /* in = DL = target -> host */ 708 1, 709 }, 710 { 711 WDI_IPA_TX_SVC, 712 PIPEDIR_OUT, /* in = DL = target -> host */ 713 5, 714 }, 715 #if defined(QCA_WIFI_3_0_ADRASTEA) 716 { 717 HTT_DATA2_MSG_SVC, 718 PIPEDIR_IN, /* in = DL = target -> host */ 719 9, 720 }, 721 { 722 HTT_DATA3_MSG_SVC, 723 PIPEDIR_IN, /* in = DL = target -> host */ 724 10, 725 }, 726 { 727 PACKET_LOG_SVC, 728 PIPEDIR_IN, /* in = DL = target -> host */ 729 11, 730 }, 731 #endif 732 /* (Additions here) */ 733 734 { /* Must be last */ 735 0, 736 0, 737 0, 738 }, 739 }; 740 741 /* PIPEDIR_OUT = HOST to Target */ 742 /* PIPEDIR_IN = TARGET to HOST */ 743 #if (defined(QCA_WIFI_QCA8074)) 744 static struct service_to_pipe target_service_to_ce_map_qca8074[] = { 745 { WMI_DATA_VO_SVC, PIPEDIR_OUT, 3, }, 746 { WMI_DATA_VO_SVC, PIPEDIR_IN, 2, }, 747 { WMI_DATA_BK_SVC, PIPEDIR_OUT, 3, }, 748 { WMI_DATA_BK_SVC, PIPEDIR_IN, 2, }, 749 { WMI_DATA_BE_SVC, PIPEDIR_OUT, 3, }, 750 { WMI_DATA_BE_SVC, PIPEDIR_IN, 2, }, 751 { WMI_DATA_VI_SVC, PIPEDIR_OUT, 3, }, 752 { WMI_DATA_VI_SVC, PIPEDIR_IN, 2, }, 753 { WMI_CONTROL_SVC, PIPEDIR_OUT, 3, }, 754 { WMI_CONTROL_SVC, PIPEDIR_IN, 2, }, 755 { WMI_CONTROL_SVC_WMAC1, PIPEDIR_OUT, 7}, 756 { WMI_CONTROL_SVC_WMAC1, PIPEDIR_IN, 2}, 757 { HTC_CTRL_RSVD_SVC, PIPEDIR_OUT, 0, }, 758 { HTC_CTRL_RSVD_SVC, PIPEDIR_IN, 1, }, 759 { HTC_RAW_STREAMS_SVC, PIPEDIR_OUT, 0}, 760 { HTC_RAW_STREAMS_SVC, PIPEDIR_IN, 1 }, 761 { HTT_DATA_MSG_SVC, PIPEDIR_OUT, 4, }, 762 { HTT_DATA_MSG_SVC, PIPEDIR_IN, 1, }, 763 { PACKET_LOG_SVC, PIPEDIR_IN, 5, }, 764 /* (Additions here) */ 765 { 0, 0, 0, }, 766 }; 767 #else 768 static struct service_to_pipe target_service_to_ce_map_qca8074[] = { 769 }; 770 #endif 771 772 #if (defined(QCA_WIFI_QCA9574)) 773 static struct service_to_pipe target_service_to_ce_map_qca9574[] = { 774 { WMI_DATA_VO_SVC, PIPEDIR_OUT, 3, }, 775 { WMI_DATA_VO_SVC, PIPEDIR_IN, 2, }, 776 { WMI_DATA_BK_SVC, PIPEDIR_OUT, 3, }, 777 { WMI_DATA_BK_SVC, PIPEDIR_IN, 2, }, 778 { WMI_DATA_BE_SVC, PIPEDIR_OUT, 3, }, 779 { WMI_DATA_BE_SVC, PIPEDIR_IN, 2, }, 780 { WMI_DATA_VI_SVC, PIPEDIR_OUT, 3, }, 781 { WMI_DATA_VI_SVC, PIPEDIR_IN, 2, }, 782 { WMI_CONTROL_SVC, PIPEDIR_OUT, 3, }, 783 { WMI_CONTROL_SVC, PIPEDIR_IN, 2, }, 784 { WMI_CONTROL_SVC_WMAC1, PIPEDIR_OUT, 7}, 785 { WMI_CONTROL_SVC_WMAC1, PIPEDIR_IN, 2}, 786 { HTC_CTRL_RSVD_SVC, PIPEDIR_OUT, 0, }, 787 { HTC_CTRL_RSVD_SVC, PIPEDIR_IN, 1, }, 788 { HTC_RAW_STREAMS_SVC, PIPEDIR_OUT, 0}, 789 { HTC_RAW_STREAMS_SVC, PIPEDIR_IN, 1 }, 790 { HTT_DATA_MSG_SVC, PIPEDIR_OUT, 4, }, 791 { HTT_DATA_MSG_SVC, PIPEDIR_IN, 1, }, 792 { PACKET_LOG_SVC, PIPEDIR_IN, 5, }, 793 /* (Additions here) */ 794 { 0, 0, 0, }, 795 }; 796 #else 797 static struct service_to_pipe target_service_to_ce_map_qca9574[] = { 798 }; 799 #endif 800 801 #if (defined(QCA_WIFI_QCA8074V2)) 802 static struct service_to_pipe target_service_to_ce_map_qca8074_v2[] = { 803 { WMI_DATA_VO_SVC, PIPEDIR_OUT, 3, }, 804 { WMI_DATA_VO_SVC, PIPEDIR_IN, 2, }, 805 { WMI_DATA_BK_SVC, PIPEDIR_OUT, 3, }, 806 { WMI_DATA_BK_SVC, PIPEDIR_IN, 2, }, 807 { WMI_DATA_BE_SVC, PIPEDIR_OUT, 3, }, 808 { WMI_DATA_BE_SVC, PIPEDIR_IN, 2, }, 809 { WMI_DATA_VI_SVC, PIPEDIR_OUT, 3, }, 810 { WMI_DATA_VI_SVC, PIPEDIR_IN, 2, }, 811 { WMI_CONTROL_SVC, PIPEDIR_OUT, 3, }, 812 { WMI_CONTROL_SVC, PIPEDIR_IN, 2, }, 813 { WMI_CONTROL_SVC_WMAC1, PIPEDIR_OUT, 7}, 814 { WMI_CONTROL_SVC_WMAC1, PIPEDIR_IN, 2}, 815 { WMI_CONTROL_SVC_WMAC2, PIPEDIR_OUT, 9}, 816 { WMI_CONTROL_SVC_WMAC2, PIPEDIR_IN, 2}, 817 { HTC_CTRL_RSVD_SVC, PIPEDIR_OUT, 0, }, 818 { HTC_CTRL_RSVD_SVC, PIPEDIR_IN, 1, }, 819 { HTC_RAW_STREAMS_SVC, PIPEDIR_OUT, 0}, 820 { HTC_RAW_STREAMS_SVC, PIPEDIR_IN, 1 }, 821 { HTT_DATA_MSG_SVC, PIPEDIR_OUT, 4, }, 822 { HTT_DATA_MSG_SVC, PIPEDIR_IN, 1, }, 823 { PACKET_LOG_SVC, PIPEDIR_IN, 5, }, 824 /* (Additions here) */ 825 { 0, 0, 0, }, 826 }; 827 #else 828 static struct service_to_pipe target_service_to_ce_map_qca8074_v2[] = { 829 }; 830 #endif 831 832 #if (defined(QCA_WIFI_QCA6018)) 833 static struct service_to_pipe target_service_to_ce_map_qca6018[] = { 834 { WMI_DATA_VO_SVC, PIPEDIR_OUT, 3, }, 835 { WMI_DATA_VO_SVC, PIPEDIR_IN, 2, }, 836 { WMI_DATA_BK_SVC, PIPEDIR_OUT, 3, }, 837 { WMI_DATA_BK_SVC, PIPEDIR_IN, 2, }, 838 { WMI_DATA_BE_SVC, PIPEDIR_OUT, 3, }, 839 { WMI_DATA_BE_SVC, PIPEDIR_IN, 2, }, 840 { WMI_DATA_VI_SVC, PIPEDIR_OUT, 3, }, 841 { WMI_DATA_VI_SVC, PIPEDIR_IN, 2, }, 842 { WMI_CONTROL_SVC, PIPEDIR_OUT, 3, }, 843 { WMI_CONTROL_SVC, PIPEDIR_IN, 2, }, 844 { WMI_CONTROL_SVC_WMAC1, PIPEDIR_OUT, 7}, 845 { WMI_CONTROL_SVC_WMAC1, PIPEDIR_IN, 2}, 846 { HTC_CTRL_RSVD_SVC, PIPEDIR_OUT, 0, }, 847 { HTC_CTRL_RSVD_SVC, PIPEDIR_IN, 1, }, 848 { HTC_RAW_STREAMS_SVC, PIPEDIR_OUT, 0}, 849 { HTC_RAW_STREAMS_SVC, PIPEDIR_IN, 1 }, 850 { HTT_DATA_MSG_SVC, PIPEDIR_OUT, 4, }, 851 { HTT_DATA_MSG_SVC, PIPEDIR_IN, 1, }, 852 { PACKET_LOG_SVC, PIPEDIR_IN, 5, }, 853 /* (Additions here) */ 854 { 0, 0, 0, }, 855 }; 856 #else 857 static struct service_to_pipe target_service_to_ce_map_qca6018[] = { 858 }; 859 #endif 860 861 #if (defined(QCA_WIFI_QCN9000)) 862 static struct service_to_pipe target_service_to_ce_map_qcn9000[] = { 863 { WMI_DATA_VO_SVC, PIPEDIR_OUT, 3, }, 864 { WMI_DATA_VO_SVC, PIPEDIR_IN, 2, }, 865 { WMI_DATA_BK_SVC, PIPEDIR_OUT, 3, }, 866 { WMI_DATA_BK_SVC, PIPEDIR_IN, 2, }, 867 { WMI_DATA_BE_SVC, PIPEDIR_OUT, 3, }, 868 { WMI_DATA_BE_SVC, PIPEDIR_IN, 2, }, 869 { WMI_DATA_VI_SVC, PIPEDIR_OUT, 3, }, 870 { WMI_DATA_VI_SVC, PIPEDIR_IN, 2, }, 871 { WMI_CONTROL_SVC, PIPEDIR_OUT, 3, }, 872 { WMI_CONTROL_SVC, PIPEDIR_IN, 2, }, 873 { HTC_CTRL_RSVD_SVC, PIPEDIR_OUT, 0, }, 874 { HTC_CTRL_RSVD_SVC, PIPEDIR_IN, 1, }, 875 { HTC_RAW_STREAMS_SVC, PIPEDIR_OUT, 0}, 876 { HTC_RAW_STREAMS_SVC, PIPEDIR_IN, 1 }, 877 { HTT_DATA_MSG_SVC, PIPEDIR_OUT, 4, }, 878 { HTT_DATA_MSG_SVC, PIPEDIR_IN, 1, }, 879 { PACKET_LOG_SVC, PIPEDIR_IN, 5, }, 880 /* (Additions here) */ 881 { 0, 0, 0, }, 882 }; 883 #else 884 static struct service_to_pipe target_service_to_ce_map_qcn9000[] = { 885 }; 886 #endif 887 888 #if (defined(QCA_WIFI_QCA5332)) 889 static struct service_to_pipe target_service_to_ce_map_qca5332[] = { 890 { WMI_DATA_VO_SVC, PIPEDIR_OUT, 3, }, 891 { WMI_DATA_VO_SVC, PIPEDIR_IN, 2, }, 892 { WMI_DATA_BK_SVC, PIPEDIR_OUT, 3, }, 893 { WMI_DATA_BK_SVC, PIPEDIR_IN, 2, }, 894 { WMI_DATA_BE_SVC, PIPEDIR_OUT, 3, }, 895 { WMI_DATA_BE_SVC, PIPEDIR_IN, 2, }, 896 { WMI_DATA_VI_SVC, PIPEDIR_OUT, 3, }, 897 { WMI_DATA_VI_SVC, PIPEDIR_IN, 2, }, 898 { WMI_CONTROL_SVC, PIPEDIR_OUT, 3, }, 899 { WMI_CONTROL_SVC, PIPEDIR_IN, 2, }, 900 { HTC_CTRL_RSVD_SVC, PIPEDIR_OUT, 0, }, 901 { HTC_CTRL_RSVD_SVC, PIPEDIR_IN, 1, }, 902 { HTC_RAW_STREAMS_SVC, PIPEDIR_OUT, 0}, 903 { HTC_RAW_STREAMS_SVC, PIPEDIR_IN, 1 }, 904 { HTT_DATA_MSG_SVC, PIPEDIR_OUT, 4, }, 905 { HTT_DATA_MSG_SVC, PIPEDIR_IN, 1, }, 906 { PACKET_LOG_SVC, PIPEDIR_IN, 5, }, 907 #ifdef WLAN_DIAG_AND_DBR_OVER_SEPARATE_CE 908 { WMI_CONTROL_DIAG_SVC, PIPEDIR_IN, 9, }, 909 { WMI_CONTROL_DBR_SVC, PIPEDIR_IN, 9, }, 910 #endif 911 /* (Additions here) */ 912 { 0, 0, 0, }, 913 }; 914 #else 915 static struct service_to_pipe target_service_to_ce_map_qca5332[] = { 916 }; 917 #endif 918 919 #if (defined(QCA_WIFI_QCN9224)) 920 static struct service_to_pipe target_service_to_ce_map_qcn9224[] = { 921 { WMI_DATA_VO_SVC, PIPEDIR_OUT, 3, }, 922 { WMI_DATA_VO_SVC, PIPEDIR_IN, 2, }, 923 { WMI_DATA_BK_SVC, PIPEDIR_OUT, 3, }, 924 { WMI_DATA_BK_SVC, PIPEDIR_IN, 2, }, 925 { WMI_DATA_BE_SVC, PIPEDIR_OUT, 3, }, 926 { WMI_DATA_BE_SVC, PIPEDIR_IN, 2, }, 927 { WMI_DATA_VI_SVC, PIPEDIR_OUT, 3, }, 928 { WMI_DATA_VI_SVC, PIPEDIR_IN, 2, }, 929 { WMI_CONTROL_SVC, PIPEDIR_OUT, 3, }, 930 { WMI_CONTROL_SVC, PIPEDIR_IN, 2, }, 931 { HTC_CTRL_RSVD_SVC, PIPEDIR_OUT, 0, }, 932 { HTC_CTRL_RSVD_SVC, PIPEDIR_IN, 1, }, 933 { HTC_RAW_STREAMS_SVC, PIPEDIR_OUT, 0}, 934 { HTC_RAW_STREAMS_SVC, PIPEDIR_IN, 1 }, 935 { HTT_DATA_MSG_SVC, PIPEDIR_OUT, 4, }, 936 { HTT_DATA_MSG_SVC, PIPEDIR_IN, 1, }, 937 { WMI_CONTROL_SVC_WMAC1, PIPEDIR_OUT, 7, }, 938 { WMI_CONTROL_SVC_WMAC1, PIPEDIR_IN, 2, }, 939 { PACKET_LOG_SVC, PIPEDIR_IN, 5, }, 940 { WMI_CONTROL_DIAG_SVC, PIPEDIR_IN, 14, }, 941 { WMI_CONTROL_DBR_SVC, PIPEDIR_IN, 14, }, 942 /* (Additions here) */ 943 { 0, 0, 0, }, 944 }; 945 #endif 946 947 #if defined(QCA_WIFI_QCA5018) || defined(QCA_WIFI_QCN9160) 948 static struct service_to_pipe target_service_to_ce_map_qca5018[] = { 949 { WMI_DATA_VO_SVC, PIPEDIR_OUT, 3, }, 950 { WMI_DATA_VO_SVC, PIPEDIR_IN, 2, }, 951 { WMI_DATA_BK_SVC, PIPEDIR_OUT, 3, }, 952 { WMI_DATA_BK_SVC, PIPEDIR_IN, 2, }, 953 { WMI_DATA_BE_SVC, PIPEDIR_OUT, 3, }, 954 { WMI_DATA_BE_SVC, PIPEDIR_IN, 2, }, 955 { WMI_DATA_VI_SVC, PIPEDIR_OUT, 3, }, 956 { WMI_DATA_VI_SVC, PIPEDIR_IN, 2, }, 957 { WMI_CONTROL_SVC, PIPEDIR_OUT, 3, }, 958 { WMI_CONTROL_SVC, PIPEDIR_IN, 2, }, 959 { HTC_CTRL_RSVD_SVC, PIPEDIR_OUT, 0, }, 960 { HTC_CTRL_RSVD_SVC, PIPEDIR_IN, 1, }, 961 { HTC_RAW_STREAMS_SVC, PIPEDIR_OUT, 0}, 962 { HTC_RAW_STREAMS_SVC, PIPEDIR_IN, 1 }, 963 { HTT_DATA_MSG_SVC, PIPEDIR_OUT, 4, }, 964 { HTT_DATA_MSG_SVC, PIPEDIR_IN, 1, }, 965 { PACKET_LOG_SVC, PIPEDIR_IN, 5, }, 966 /* (Additions here) */ 967 { 0, 0, 0, }, 968 }; 969 #else 970 static struct service_to_pipe target_service_to_ce_map_qca5018[] = { 971 }; 972 #endif 973 974 /* PIPEDIR_OUT = HOST to Target */ 975 /* PIPEDIR_IN = TARGET to HOST */ 976 #ifdef QCN7605_SUPPORT 977 static struct service_to_pipe target_service_to_ce_map_qcn7605[] = { 978 { WMI_DATA_VO_SVC, PIPEDIR_OUT, 0, }, 979 { WMI_DATA_VO_SVC, PIPEDIR_IN, 2, }, 980 { WMI_DATA_BK_SVC, PIPEDIR_OUT, 0, }, 981 { WMI_DATA_BK_SVC, PIPEDIR_IN, 2, }, 982 { WMI_DATA_BE_SVC, PIPEDIR_OUT, 0, }, 983 { WMI_DATA_BE_SVC, PIPEDIR_IN, 2, }, 984 { WMI_DATA_VI_SVC, PIPEDIR_OUT, 0, }, 985 { WMI_DATA_VI_SVC, PIPEDIR_IN, 2, }, 986 { WMI_CONTROL_SVC, PIPEDIR_OUT, 0, }, 987 { WMI_CONTROL_SVC, PIPEDIR_IN, 2, }, 988 { HTC_CTRL_RSVD_SVC, PIPEDIR_OUT, 0, }, 989 { HTC_CTRL_RSVD_SVC, PIPEDIR_IN, 2, }, 990 { HTC_RAW_STREAMS_SVC, PIPEDIR_OUT, 0, }, 991 { HTC_RAW_STREAMS_SVC, PIPEDIR_IN, 2, }, 992 { HTT_DATA_MSG_SVC, PIPEDIR_OUT, 4, }, 993 { HTT_DATA_MSG_SVC, PIPEDIR_IN, 1, }, 994 { HTT_DATA2_MSG_SVC, PIPEDIR_IN, 3, }, 995 #ifdef IPA_OFFLOAD 996 { WDI_IPA_TX_SVC, PIPEDIR_OUT, 5, }, 997 #else 998 { HTT_DATA3_MSG_SVC, PIPEDIR_IN, 8, }, 999 #endif 1000 { PACKET_LOG_SVC, PIPEDIR_IN, 7, }, 1001 /* (Additions here) */ 1002 { 0, 0, 0, }, 1003 }; 1004 #endif 1005 1006 #if (defined(QCA_WIFI_QCA6290)) 1007 #ifdef QCA_6290_AP_MODE 1008 static struct service_to_pipe target_service_to_ce_map_qca6290[] = { 1009 { WMI_DATA_VO_SVC, PIPEDIR_OUT, 3, }, 1010 { WMI_DATA_VO_SVC, PIPEDIR_IN , 2, }, 1011 { WMI_DATA_BK_SVC, PIPEDIR_OUT, 3, }, 1012 { WMI_DATA_BK_SVC, PIPEDIR_IN , 2, }, 1013 { WMI_DATA_BE_SVC, PIPEDIR_OUT, 3, }, 1014 { WMI_DATA_BE_SVC, PIPEDIR_IN , 2, }, 1015 { WMI_DATA_VI_SVC, PIPEDIR_OUT, 3, }, 1016 { WMI_DATA_VI_SVC, PIPEDIR_IN , 2, }, 1017 { WMI_CONTROL_SVC, PIPEDIR_OUT, 3, }, 1018 { WMI_CONTROL_SVC, PIPEDIR_IN , 2, }, 1019 { HTC_CTRL_RSVD_SVC, PIPEDIR_OUT, 0, }, 1020 { HTC_CTRL_RSVD_SVC, PIPEDIR_IN , 2, }, 1021 { HTT_DATA_MSG_SVC, PIPEDIR_OUT, 4, }, 1022 { HTT_DATA_MSG_SVC, PIPEDIR_IN , 1, }, 1023 { WMI_CONTROL_SVC_WMAC1, PIPEDIR_OUT, 7}, 1024 { WMI_CONTROL_SVC_WMAC1, PIPEDIR_IN, 2}, 1025 { PACKET_LOG_SVC, PIPEDIR_IN, 5, }, 1026 /* (Additions here) */ 1027 { 0, 0, 0, }, 1028 }; 1029 #else 1030 static struct service_to_pipe target_service_to_ce_map_qca6290[] = { 1031 { WMI_DATA_VO_SVC, PIPEDIR_OUT, 3, }, 1032 { WMI_DATA_VO_SVC, PIPEDIR_IN, 2, }, 1033 { WMI_DATA_BK_SVC, PIPEDIR_OUT, 3, }, 1034 { WMI_DATA_BK_SVC, PIPEDIR_IN, 2, }, 1035 { WMI_DATA_BE_SVC, PIPEDIR_OUT, 3, }, 1036 { WMI_DATA_BE_SVC, PIPEDIR_IN, 2, }, 1037 { WMI_DATA_VI_SVC, PIPEDIR_OUT, 3, }, 1038 { WMI_DATA_VI_SVC, PIPEDIR_IN, 2, }, 1039 { WMI_CONTROL_SVC, PIPEDIR_OUT, 3, }, 1040 { WMI_CONTROL_SVC, PIPEDIR_IN, 2, }, 1041 { HTC_CTRL_RSVD_SVC, PIPEDIR_OUT, 0, }, 1042 { HTC_CTRL_RSVD_SVC, PIPEDIR_IN, 2, }, 1043 { HTT_DATA_MSG_SVC, PIPEDIR_OUT, 4, }, 1044 { HTT_DATA_MSG_SVC, PIPEDIR_IN, 1, }, 1045 /* (Additions here) */ 1046 { 0, 0, 0, }, 1047 }; 1048 #endif 1049 #else 1050 static struct service_to_pipe target_service_to_ce_map_qca6290[] = { 1051 }; 1052 #endif 1053 1054 #if (defined(QCA_WIFI_QCA6390)) 1055 static struct service_to_pipe target_service_to_ce_map_qca6390[] = { 1056 { WMI_DATA_VO_SVC, PIPEDIR_OUT, 3, }, 1057 { WMI_DATA_VO_SVC, PIPEDIR_IN, 2, }, 1058 { WMI_DATA_BK_SVC, PIPEDIR_OUT, 3, }, 1059 { WMI_DATA_BK_SVC, PIPEDIR_IN, 2, }, 1060 { WMI_DATA_BE_SVC, PIPEDIR_OUT, 3, }, 1061 { WMI_DATA_BE_SVC, PIPEDIR_IN, 2, }, 1062 { WMI_DATA_VI_SVC, PIPEDIR_OUT, 3, }, 1063 { WMI_DATA_VI_SVC, PIPEDIR_IN, 2, }, 1064 { WMI_CONTROL_SVC, PIPEDIR_OUT, 3, }, 1065 { WMI_CONTROL_SVC, PIPEDIR_IN, 2, }, 1066 { HTC_CTRL_RSVD_SVC, PIPEDIR_OUT, 0, }, 1067 { HTC_CTRL_RSVD_SVC, PIPEDIR_IN, 2, }, 1068 { HTT_DATA_MSG_SVC, PIPEDIR_OUT, 4, }, 1069 { HTT_DATA_MSG_SVC, PIPEDIR_IN, 1, }, 1070 { PACKET_LOG_SVC, PIPEDIR_IN, 5, }, 1071 /* (Additions here) */ 1072 { 0, 0, 0, }, 1073 }; 1074 #else 1075 static struct service_to_pipe target_service_to_ce_map_qca6390[] = { 1076 }; 1077 #endif 1078 1079 static struct service_to_pipe target_service_to_ce_map_qca6490[] = { 1080 { WMI_DATA_VO_SVC, PIPEDIR_OUT, 3, }, 1081 { WMI_DATA_VO_SVC, PIPEDIR_IN, 2, }, 1082 { WMI_DATA_BK_SVC, PIPEDIR_OUT, 3, }, 1083 { WMI_DATA_BK_SVC, PIPEDIR_IN, 2, }, 1084 { WMI_DATA_BE_SVC, PIPEDIR_OUT, 3, }, 1085 { WMI_DATA_BE_SVC, PIPEDIR_IN, 2, }, 1086 { WMI_DATA_VI_SVC, PIPEDIR_OUT, 3, }, 1087 { WMI_DATA_VI_SVC, PIPEDIR_IN, 2, }, 1088 { WMI_CONTROL_SVC, PIPEDIR_OUT, 3, }, 1089 { WMI_CONTROL_SVC, PIPEDIR_IN, 2, }, 1090 { HTC_CTRL_RSVD_SVC, PIPEDIR_OUT, 0, }, 1091 { HTC_CTRL_RSVD_SVC, PIPEDIR_IN, 2, }, 1092 { HTT_DATA_MSG_SVC, PIPEDIR_OUT, 4, }, 1093 { HTT_DATA_MSG_SVC, PIPEDIR_IN, 1, }, 1094 { PACKET_LOG_SVC, PIPEDIR_IN, 5, }, 1095 /* (Additions here) */ 1096 { 0, 0, 0, }, 1097 }; 1098 1099 #if (defined(QCA_WIFI_QCA6750)) 1100 static struct service_to_pipe target_service_to_ce_map_qca6750[] = { 1101 { WMI_DATA_VO_SVC, PIPEDIR_OUT, 3, }, 1102 { WMI_DATA_VO_SVC, PIPEDIR_IN, 2, }, 1103 { WMI_DATA_BK_SVC, PIPEDIR_OUT, 3, }, 1104 { WMI_DATA_BK_SVC, PIPEDIR_IN, 2, }, 1105 { WMI_DATA_BE_SVC, PIPEDIR_OUT, 3, }, 1106 { WMI_DATA_BE_SVC, PIPEDIR_IN, 2, }, 1107 { WMI_DATA_VI_SVC, PIPEDIR_OUT, 3, }, 1108 { WMI_DATA_VI_SVC, PIPEDIR_IN, 2, }, 1109 { WMI_CONTROL_SVC, PIPEDIR_OUT, 3, }, 1110 { WMI_CONTROL_SVC, PIPEDIR_IN, 2, }, 1111 { HTC_CTRL_RSVD_SVC, PIPEDIR_OUT, 0, }, 1112 { HTC_CTRL_RSVD_SVC, PIPEDIR_IN, 2, }, 1113 { HTT_DATA_MSG_SVC, PIPEDIR_OUT, 4, }, 1114 { HTT_DATA_MSG_SVC, PIPEDIR_IN, 1, }, 1115 { PACKET_LOG_SVC, PIPEDIR_IN, 5, }, 1116 #ifdef WLAN_FEATURE_WMI_DIAG_OVER_CE7 1117 { WMI_CONTROL_DIAG_SVC, PIPEDIR_IN, 7, }, 1118 #endif 1119 /* (Additions here) */ 1120 { 0, 0, 0, }, 1121 }; 1122 #else 1123 static struct service_to_pipe target_service_to_ce_map_qca6750[] = { 1124 }; 1125 #endif 1126 1127 #if (defined(QCA_WIFI_KIWI)) 1128 #ifdef FEATURE_DIRECT_LINK 1129 static struct service_to_pipe target_service_to_ce_map_kiwi_direct_link[] = { 1130 { WMI_DATA_VO_SVC, PIPEDIR_OUT, 3, }, 1131 { WMI_DATA_VO_SVC, PIPEDIR_IN, 2, }, 1132 { WMI_DATA_BK_SVC, PIPEDIR_OUT, 3, }, 1133 { WMI_DATA_BK_SVC, PIPEDIR_IN, 2, }, 1134 { WMI_DATA_BE_SVC, PIPEDIR_OUT, 3, }, 1135 { WMI_DATA_BE_SVC, PIPEDIR_IN, 2, }, 1136 { WMI_DATA_VI_SVC, PIPEDIR_OUT, 3, }, 1137 { WMI_DATA_VI_SVC, PIPEDIR_IN, 2, }, 1138 { WMI_CONTROL_SVC, PIPEDIR_OUT, 3, }, 1139 { WMI_CONTROL_SVC, PIPEDIR_IN, 2, }, 1140 { HTC_CTRL_RSVD_SVC, PIPEDIR_OUT, 4, }, 1141 { HTC_CTRL_RSVD_SVC, PIPEDIR_IN, 2, }, 1142 { HTT_DATA_MSG_SVC, PIPEDIR_OUT, 4, }, 1143 { HTT_DATA_MSG_SVC, PIPEDIR_IN, 1, }, 1144 #ifdef WLAN_FEATURE_WMI_DIAG_OVER_CE7 1145 { WMI_CONTROL_DIAG_SVC, PIPEDIR_IN, 7, }, 1146 #endif 1147 { LPASS_DATA_MSG_SVC, PIPEDIR_OUT, 0, }, 1148 { LPASS_DATA_MSG_SVC, PIPEDIR_IN, 5, }, 1149 /* (Additions here) */ 1150 { 0, 0, 0, }, 1151 }; 1152 #endif 1153 1154 static struct service_to_pipe target_service_to_ce_map_kiwi[] = { 1155 { WMI_DATA_VO_SVC, PIPEDIR_OUT, 3, }, 1156 { WMI_DATA_VO_SVC, PIPEDIR_IN, 2, }, 1157 { WMI_DATA_BK_SVC, PIPEDIR_OUT, 3, }, 1158 { WMI_DATA_BK_SVC, PIPEDIR_IN, 2, }, 1159 { WMI_DATA_BE_SVC, PIPEDIR_OUT, 3, }, 1160 { WMI_DATA_BE_SVC, PIPEDIR_IN, 2, }, 1161 { WMI_DATA_VI_SVC, PIPEDIR_OUT, 3, }, 1162 { WMI_DATA_VI_SVC, PIPEDIR_IN, 2, }, 1163 { WMI_CONTROL_SVC, PIPEDIR_OUT, 3, }, 1164 { WMI_CONTROL_SVC, PIPEDIR_IN, 2, }, 1165 { HTC_CTRL_RSVD_SVC, PIPEDIR_OUT, 0, }, 1166 { HTC_CTRL_RSVD_SVC, PIPEDIR_IN, 2, }, 1167 { HTT_DATA_MSG_SVC, PIPEDIR_OUT, 4, }, 1168 { HTT_DATA_MSG_SVC, PIPEDIR_IN, 1, }, 1169 #ifdef WLAN_FEATURE_WMI_DIAG_OVER_CE7 1170 { WMI_CONTROL_DIAG_SVC, PIPEDIR_IN, 7, }, 1171 #endif 1172 /* (Additions here) */ 1173 { 0, 0, 0, }, 1174 }; 1175 #else 1176 static struct service_to_pipe target_service_to_ce_map_kiwi[] = { 1177 }; 1178 #endif 1179 1180 static struct service_to_pipe target_service_to_ce_map_ar900b[] = { 1181 { 1182 WMI_DATA_VO_SVC, 1183 PIPEDIR_OUT, /* out = UL = host -> target */ 1184 3, 1185 }, 1186 { 1187 WMI_DATA_VO_SVC, 1188 PIPEDIR_IN, /* in = DL = target -> host */ 1189 2, 1190 }, 1191 { 1192 WMI_DATA_BK_SVC, 1193 PIPEDIR_OUT, /* out = UL = host -> target */ 1194 3, 1195 }, 1196 { 1197 WMI_DATA_BK_SVC, 1198 PIPEDIR_IN, /* in = DL = target -> host */ 1199 2, 1200 }, 1201 { 1202 WMI_DATA_BE_SVC, 1203 PIPEDIR_OUT, /* out = UL = host -> target */ 1204 3, 1205 }, 1206 { 1207 WMI_DATA_BE_SVC, 1208 PIPEDIR_IN, /* in = DL = target -> host */ 1209 2, 1210 }, 1211 { 1212 WMI_DATA_VI_SVC, 1213 PIPEDIR_OUT, /* out = UL = host -> target */ 1214 3, 1215 }, 1216 { 1217 WMI_DATA_VI_SVC, 1218 PIPEDIR_IN, /* in = DL = target -> host */ 1219 2, 1220 }, 1221 { 1222 WMI_CONTROL_SVC, 1223 PIPEDIR_OUT, /* out = UL = host -> target */ 1224 3, 1225 }, 1226 { 1227 WMI_CONTROL_SVC, 1228 PIPEDIR_IN, /* in = DL = target -> host */ 1229 2, 1230 }, 1231 { 1232 HTC_CTRL_RSVD_SVC, 1233 PIPEDIR_OUT, /* out = UL = host -> target */ 1234 0, /* could be moved to 3 (share with WMI) */ 1235 }, 1236 { 1237 HTC_CTRL_RSVD_SVC, 1238 PIPEDIR_IN, /* in = DL = target -> host */ 1239 1, 1240 }, 1241 { 1242 HTC_RAW_STREAMS_SVC, /* not currently used */ 1243 PIPEDIR_OUT, /* out = UL = host -> target */ 1244 0, 1245 }, 1246 { 1247 HTC_RAW_STREAMS_SVC, /* not currently used */ 1248 PIPEDIR_IN, /* in = DL = target -> host */ 1249 1, 1250 }, 1251 { 1252 HTT_DATA_MSG_SVC, 1253 PIPEDIR_OUT, /* out = UL = host -> target */ 1254 4, 1255 }, 1256 #ifdef WLAN_FEATURE_FASTPATH 1257 { 1258 HTT_DATA_MSG_SVC, 1259 PIPEDIR_IN, /* in = DL = target -> host */ 1260 5, 1261 }, 1262 #else /* WLAN_FEATURE_FASTPATH */ 1263 { 1264 HTT_DATA_MSG_SVC, 1265 PIPEDIR_IN, /* in = DL = target -> host */ 1266 1, 1267 }, 1268 #endif /* WLAN_FEATURE_FASTPATH */ 1269 1270 /* (Additions here) */ 1271 1272 { /* Must be last */ 1273 0, 1274 0, 1275 0, 1276 }, 1277 }; 1278 1279 static struct shadow_reg_cfg *target_shadow_reg_cfg = target_shadow_reg_cfg_map; 1280 static int shadow_cfg_sz = sizeof(target_shadow_reg_cfg_map); 1281 1282 #ifdef WLAN_FEATURE_EPPING 1283 static struct service_to_pipe target_service_to_ce_map_wlan_epping[] = { 1284 {WMI_DATA_VO_SVC, PIPEDIR_OUT, 3,}, /* out = UL = host -> target */ 1285 {WMI_DATA_VO_SVC, PIPEDIR_IN, 2,}, /* in = DL = target -> host */ 1286 {WMI_DATA_BK_SVC, PIPEDIR_OUT, 4,}, /* out = UL = host -> target */ 1287 {WMI_DATA_BK_SVC, PIPEDIR_IN, 1,}, /* in = DL = target -> host */ 1288 {WMI_DATA_BE_SVC, PIPEDIR_OUT, 3,}, /* out = UL = host -> target */ 1289 {WMI_DATA_BE_SVC, PIPEDIR_IN, 2,}, /* in = DL = target -> host */ 1290 {WMI_DATA_VI_SVC, PIPEDIR_OUT, 3,}, /* out = UL = host -> target */ 1291 {WMI_DATA_VI_SVC, PIPEDIR_IN, 2,}, /* in = DL = target -> host */ 1292 {WMI_CONTROL_SVC, PIPEDIR_OUT, 3,}, /* out = UL = host -> target */ 1293 {WMI_CONTROL_SVC, PIPEDIR_IN, 2,}, /* in = DL = target -> host */ 1294 {HTC_CTRL_RSVD_SVC, PIPEDIR_OUT, 0,}, /* out = UL = host -> target */ 1295 {HTC_CTRL_RSVD_SVC, PIPEDIR_IN, 2,}, /* in = DL = target -> host */ 1296 {HTC_RAW_STREAMS_SVC, PIPEDIR_OUT, 0,}, /* out = UL = host -> target */ 1297 {HTC_RAW_STREAMS_SVC, PIPEDIR_IN, 2,}, /* in = DL = target -> host */ 1298 {HTT_DATA_MSG_SVC, PIPEDIR_OUT, 4,}, /* out = UL = host -> target */ 1299 {HTT_DATA_MSG_SVC, PIPEDIR_IN, 1,}, /* in = DL = target -> host */ 1300 {0, 0, 0,}, /* Must be last */ 1301 }; 1302 1303 void hif_select_epping_service_to_pipe_map(struct service_to_pipe 1304 **tgt_svc_map_to_use, 1305 uint32_t *sz_tgt_svc_map_to_use) 1306 { 1307 *tgt_svc_map_to_use = target_service_to_ce_map_wlan_epping; 1308 *sz_tgt_svc_map_to_use = 1309 sizeof(target_service_to_ce_map_wlan_epping); 1310 } 1311 #endif 1312 1313 #ifdef QCN7605_SUPPORT 1314 static inline 1315 void hif_select_ce_map_qcn7605(struct service_to_pipe **tgt_svc_map_to_use, 1316 uint32_t *sz_tgt_svc_map_to_use) 1317 { 1318 *tgt_svc_map_to_use = target_service_to_ce_map_qcn7605; 1319 *sz_tgt_svc_map_to_use = sizeof(target_service_to_ce_map_qcn7605); 1320 } 1321 #else 1322 static inline 1323 void hif_select_ce_map_qcn7605(struct service_to_pipe **tgt_svc_map_to_use, 1324 uint32_t *sz_tgt_svc_map_to_use) 1325 { 1326 hif_err("QCN7605 not supported"); 1327 } 1328 #endif 1329 1330 #ifdef QCA_WIFI_QCN9224 1331 static 1332 void hif_set_ce_config_qcn9224(struct hif_softc *scn, 1333 struct HIF_CE_state *hif_state) 1334 { 1335 hif_state->host_ce_config = host_ce_config_wlan_qcn9224; 1336 hif_state->target_ce_config = target_ce_config_wlan_qcn9224; 1337 hif_state->target_ce_config_sz = 1338 sizeof(target_ce_config_wlan_qcn9224); 1339 scn->ce_count = QCN_9224_CE_COUNT; 1340 scn->ini_cfg.disable_wake_irq = 1; 1341 } 1342 1343 static 1344 void hif_select_ce_map_qcn9224(struct service_to_pipe **tgt_svc_map_to_use, 1345 uint32_t *sz_tgt_svc_map_to_use) 1346 { 1347 *tgt_svc_map_to_use = target_service_to_ce_map_qcn9224; 1348 *sz_tgt_svc_map_to_use = sizeof(target_service_to_ce_map_qcn9224); 1349 } 1350 #else 1351 static inline 1352 void hif_set_ce_config_qcn9224(struct hif_softc *scn, 1353 struct HIF_CE_state *hif_state) 1354 { 1355 hif_err("QCN9224 not supported"); 1356 } 1357 1358 static inline 1359 void hif_select_ce_map_qcn9224(struct service_to_pipe **tgt_svc_map_to_use, 1360 uint32_t *sz_tgt_svc_map_to_use) 1361 { 1362 hif_err("QCN9224 not supported"); 1363 } 1364 #endif 1365 1366 #ifdef FEATURE_DIRECT_LINK 1367 /** 1368 * hif_select_service_to_pipe_map_kiwi() - Select service to CE map 1369 * configuration for Kiwi 1370 * @scn: HIF context 1371 * @tgt_svc_map_to_use: returned service map 1372 * @sz_tgt_svc_map_to_use: returned length of the service map 1373 * 1374 * Return: None 1375 */ 1376 static inline void 1377 hif_select_service_to_pipe_map_kiwi(struct hif_softc *scn, 1378 struct service_to_pipe **tgt_svc_map_to_use, 1379 uint32_t *sz_tgt_svc_map_to_use) 1380 { 1381 if (pld_is_direct_link_supported(scn->qdf_dev->dev)) { 1382 *tgt_svc_map_to_use = target_service_to_ce_map_kiwi_direct_link; 1383 *sz_tgt_svc_map_to_use = 1384 sizeof(target_service_to_ce_map_kiwi_direct_link); 1385 } else { 1386 *tgt_svc_map_to_use = target_service_to_ce_map_kiwi; 1387 *sz_tgt_svc_map_to_use = sizeof(target_service_to_ce_map_kiwi); 1388 } 1389 } 1390 #else 1391 static inline void 1392 hif_select_service_to_pipe_map_kiwi(struct hif_softc *scn, 1393 struct service_to_pipe **tgt_svc_map_to_use, 1394 uint32_t *sz_tgt_svc_map_to_use) 1395 { 1396 *tgt_svc_map_to_use = target_service_to_ce_map_kiwi; 1397 *sz_tgt_svc_map_to_use = sizeof(target_service_to_ce_map_kiwi); 1398 } 1399 #endif 1400 1401 static void hif_select_service_to_pipe_map(struct hif_softc *scn, 1402 struct service_to_pipe **tgt_svc_map_to_use, 1403 uint32_t *sz_tgt_svc_map_to_use) 1404 { 1405 uint32_t mode = hif_get_conparam(scn); 1406 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 1407 struct hif_target_info *tgt_info = &scn->target_info; 1408 1409 if (QDF_IS_EPPING_ENABLED(mode)) { 1410 hif_select_epping_service_to_pipe_map(tgt_svc_map_to_use, 1411 sz_tgt_svc_map_to_use); 1412 } else { 1413 switch (tgt_info->target_type) { 1414 default: 1415 *tgt_svc_map_to_use = target_service_to_ce_map_wlan; 1416 *sz_tgt_svc_map_to_use = 1417 sizeof(target_service_to_ce_map_wlan); 1418 break; 1419 case TARGET_TYPE_QCN7605: 1420 hif_select_ce_map_qcn7605(tgt_svc_map_to_use, 1421 sz_tgt_svc_map_to_use); 1422 break; 1423 case TARGET_TYPE_AR900B: 1424 case TARGET_TYPE_QCA9984: 1425 case TARGET_TYPE_QCA9888: 1426 case TARGET_TYPE_AR9888: 1427 case TARGET_TYPE_AR9888V2: 1428 *tgt_svc_map_to_use = target_service_to_ce_map_ar900b; 1429 *sz_tgt_svc_map_to_use = 1430 sizeof(target_service_to_ce_map_ar900b); 1431 break; 1432 case TARGET_TYPE_QCA6290: 1433 *tgt_svc_map_to_use = target_service_to_ce_map_qca6290; 1434 *sz_tgt_svc_map_to_use = 1435 sizeof(target_service_to_ce_map_qca6290); 1436 break; 1437 case TARGET_TYPE_QCA6390: 1438 *tgt_svc_map_to_use = target_service_to_ce_map_qca6390; 1439 *sz_tgt_svc_map_to_use = 1440 sizeof(target_service_to_ce_map_qca6390); 1441 break; 1442 case TARGET_TYPE_QCA6490: 1443 *tgt_svc_map_to_use = target_service_to_ce_map_qca6490; 1444 *sz_tgt_svc_map_to_use = 1445 sizeof(target_service_to_ce_map_qca6490); 1446 break; 1447 case TARGET_TYPE_QCA6750: 1448 *tgt_svc_map_to_use = target_service_to_ce_map_qca6750; 1449 *sz_tgt_svc_map_to_use = 1450 sizeof(target_service_to_ce_map_qca6750); 1451 break; 1452 case TARGET_TYPE_KIWI: 1453 case TARGET_TYPE_MANGO: 1454 hif_select_service_to_pipe_map_kiwi(scn, 1455 tgt_svc_map_to_use, 1456 sz_tgt_svc_map_to_use); 1457 break; 1458 case TARGET_TYPE_QCA8074: 1459 *tgt_svc_map_to_use = target_service_to_ce_map_qca8074; 1460 *sz_tgt_svc_map_to_use = 1461 sizeof(target_service_to_ce_map_qca8074); 1462 break; 1463 case TARGET_TYPE_QCA8074V2: 1464 *tgt_svc_map_to_use = 1465 target_service_to_ce_map_qca8074_v2; 1466 *sz_tgt_svc_map_to_use = 1467 sizeof(target_service_to_ce_map_qca8074_v2); 1468 break; 1469 case TARGET_TYPE_QCA9574: 1470 *tgt_svc_map_to_use = 1471 target_service_to_ce_map_qca9574; 1472 *sz_tgt_svc_map_to_use = 1473 sizeof(target_service_to_ce_map_qca9574); 1474 break; 1475 case TARGET_TYPE_QCA6018: 1476 *tgt_svc_map_to_use = 1477 target_service_to_ce_map_qca6018; 1478 *sz_tgt_svc_map_to_use = 1479 sizeof(target_service_to_ce_map_qca6018); 1480 break; 1481 case TARGET_TYPE_QCN9000: 1482 *tgt_svc_map_to_use = 1483 target_service_to_ce_map_qcn9000; 1484 *sz_tgt_svc_map_to_use = 1485 sizeof(target_service_to_ce_map_qcn9000); 1486 break; 1487 case TARGET_TYPE_QCN9224: 1488 hif_select_ce_map_qcn9224(tgt_svc_map_to_use, 1489 sz_tgt_svc_map_to_use); 1490 break; 1491 case TARGET_TYPE_QCA5332: 1492 *tgt_svc_map_to_use = target_service_to_ce_map_qca5332; 1493 *sz_tgt_svc_map_to_use = 1494 sizeof(target_service_to_ce_map_qca5332); 1495 break; 1496 case TARGET_TYPE_QCA5018: 1497 case TARGET_TYPE_QCN6122: 1498 case TARGET_TYPE_QCN9160: 1499 *tgt_svc_map_to_use = 1500 target_service_to_ce_map_qca5018; 1501 *sz_tgt_svc_map_to_use = 1502 sizeof(target_service_to_ce_map_qca5018); 1503 break; 1504 } 1505 } 1506 hif_state->tgt_svc_map = *tgt_svc_map_to_use; 1507 hif_state->sz_tgt_svc_map = *sz_tgt_svc_map_to_use / 1508 sizeof(struct service_to_pipe); 1509 } 1510 1511 /** 1512 * ce_mark_datapath() - marks the ce_state->htt_rx_data accordingly 1513 * @ce_state : pointer to the state context of the CE 1514 * 1515 * Description: 1516 * Sets htt_rx_data attribute of the state structure if the 1517 * CE serves one of the HTT DATA services. 1518 * 1519 * Return: 1520 * false (attribute set to false) 1521 * true (attribute set to true); 1522 */ 1523 static bool ce_mark_datapath(struct CE_state *ce_state) 1524 { 1525 struct service_to_pipe *svc_map; 1526 uint32_t map_sz, map_len; 1527 int i; 1528 bool rc = false; 1529 1530 if (ce_state) { 1531 hif_select_service_to_pipe_map(ce_state->scn, &svc_map, 1532 &map_sz); 1533 1534 map_len = map_sz / sizeof(struct service_to_pipe); 1535 for (i = 0; i < map_len; i++) { 1536 if ((svc_map[i].pipenum == ce_state->id) && 1537 ((svc_map[i].service_id == HTT_DATA_MSG_SVC) || 1538 (svc_map[i].service_id == HTT_DATA2_MSG_SVC) || 1539 (svc_map[i].service_id == HTT_DATA3_MSG_SVC))) { 1540 /* HTT CEs are unidirectional */ 1541 if (svc_map[i].pipedir == PIPEDIR_IN) 1542 ce_state->htt_rx_data = true; 1543 else 1544 ce_state->htt_tx_data = true; 1545 rc = true; 1546 } 1547 } 1548 } 1549 return rc; 1550 } 1551 1552 /** 1553 * hif_get_max_wmi_ep() - Get max WMI EPs configured in target svc map 1554 * @hif_ctx: hif opaque handle 1555 * 1556 * Description: 1557 * Gets number of WMI EPs configured in target svc map. Since EP map 1558 * include IN and OUT direction pipes, count only OUT pipes to get EPs 1559 * configured for WMI service. 1560 * 1561 * Return: 1562 * uint8_t: count for WMI eps in target svc map 1563 */ 1564 uint8_t hif_get_max_wmi_ep(struct hif_opaque_softc *hif_ctx) 1565 { 1566 struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); 1567 struct service_to_pipe *svc_map; 1568 uint32_t map_sz, map_len; 1569 int i; 1570 uint8_t wmi_ep_count = 0; 1571 1572 hif_select_service_to_pipe_map(scn, &svc_map, 1573 &map_sz); 1574 map_len = map_sz / sizeof(struct service_to_pipe); 1575 1576 for (i = 0; i < map_len; i++) { 1577 /* Count number of WMI EPs based on out direction */ 1578 if ((svc_map[i].pipedir == PIPEDIR_OUT) && 1579 ((svc_map[i].service_id == WMI_CONTROL_SVC) || 1580 (svc_map[i].service_id == WMI_CONTROL_SVC_WMAC1) || 1581 (svc_map[i].service_id == WMI_CONTROL_SVC_WMAC2))) { 1582 wmi_ep_count++; 1583 } 1584 } 1585 1586 return wmi_ep_count; 1587 } 1588 1589 /** 1590 * ce_ring_test_initial_indexes() - tests the initial ce ring indexes 1591 * @ce_id: ce in question 1592 * @ring: ring state being examined 1593 * @type: "src_ring" or "dest_ring" string for identifying the ring 1594 * 1595 * Warns on non-zero index values. 1596 * Causes a kernel panic if the ring is not empty during initialization. 1597 */ 1598 static void ce_ring_test_initial_indexes(int ce_id, struct CE_ring_state *ring, 1599 char *type) 1600 { 1601 if (ring->write_index != 0 || ring->sw_index != 0) 1602 hif_err("ce %d, %s, initial sw_index = %d, initial write_index =%d", 1603 ce_id, type, ring->sw_index, ring->write_index); 1604 if (ring->write_index != ring->sw_index) 1605 QDF_BUG(0); 1606 } 1607 1608 #ifdef IPA_OFFLOAD 1609 /** 1610 * ce_alloc_desc_ring() - Allocate copyengine descriptor ring 1611 * @scn: softc instance 1612 * @CE_id: ce in question 1613 * @base_addr: pointer to copyengine ring base address 1614 * @ce_ring: copyengine instance 1615 * @nentries: number of entries should be allocated 1616 * @desc_size: ce desc size 1617 * 1618 * Return: QDF_STATUS_SUCCESS - for success 1619 */ 1620 static QDF_STATUS ce_alloc_desc_ring(struct hif_softc *scn, unsigned int CE_id, 1621 qdf_dma_addr_t *base_addr, 1622 struct CE_ring_state *ce_ring, 1623 unsigned int nentries, uint32_t desc_size) 1624 { 1625 if ((CE_id == HIF_PCI_IPA_UC_ASSIGNED_CE) && 1626 !ce_srng_based(scn)) { 1627 if (!scn->ipa_ce_ring) { 1628 scn->ipa_ce_ring = qdf_mem_shared_mem_alloc( 1629 scn->qdf_dev, 1630 nentries * desc_size + CE_DESC_RING_ALIGN); 1631 if (!scn->ipa_ce_ring) { 1632 hif_err( 1633 "Failed to allocate memory for IPA ce ring"); 1634 return QDF_STATUS_E_NOMEM; 1635 } 1636 } 1637 *base_addr = qdf_mem_get_dma_addr(scn->qdf_dev, 1638 &scn->ipa_ce_ring->mem_info); 1639 ce_ring->base_addr_owner_space_unaligned = 1640 scn->ipa_ce_ring->vaddr; 1641 } else { 1642 ce_ring->base_addr_owner_space_unaligned = 1643 hif_mem_alloc_consistent_unaligned 1644 (scn, 1645 (nentries * desc_size + 1646 CE_DESC_RING_ALIGN), 1647 base_addr, 1648 ce_ring->hal_ring_type, 1649 &ce_ring->is_ring_prealloc); 1650 1651 if (!ce_ring->base_addr_owner_space_unaligned) { 1652 hif_err("Failed to allocate DMA memory for ce ring id: %u", 1653 CE_id); 1654 return QDF_STATUS_E_NOMEM; 1655 } 1656 } 1657 return QDF_STATUS_SUCCESS; 1658 } 1659 1660 /** 1661 * ce_free_desc_ring() - Frees copyengine descriptor ring 1662 * @scn: softc instance 1663 * @CE_id: ce in question 1664 * @ce_ring: copyengine instance 1665 * @desc_size: ce desc size 1666 * 1667 * Return: None 1668 */ 1669 static void ce_free_desc_ring(struct hif_softc *scn, unsigned int CE_id, 1670 struct CE_ring_state *ce_ring, uint32_t desc_size) 1671 { 1672 if ((CE_id == HIF_PCI_IPA_UC_ASSIGNED_CE) && 1673 !ce_srng_based(scn)) { 1674 if (scn->ipa_ce_ring) { 1675 qdf_mem_shared_mem_free(scn->qdf_dev, 1676 scn->ipa_ce_ring); 1677 scn->ipa_ce_ring = NULL; 1678 } 1679 ce_ring->base_addr_owner_space_unaligned = NULL; 1680 } else { 1681 hif_mem_free_consistent_unaligned 1682 (scn, 1683 ce_ring->nentries * desc_size + CE_DESC_RING_ALIGN, 1684 ce_ring->base_addr_owner_space_unaligned, 1685 ce_ring->base_addr_CE_space, 0, 1686 ce_ring->is_ring_prealloc); 1687 ce_ring->base_addr_owner_space_unaligned = NULL; 1688 } 1689 } 1690 #else 1691 static QDF_STATUS ce_alloc_desc_ring(struct hif_softc *scn, unsigned int CE_id, 1692 qdf_dma_addr_t *base_addr, 1693 struct CE_ring_state *ce_ring, 1694 unsigned int nentries, uint32_t desc_size) 1695 { 1696 ce_ring->base_addr_owner_space_unaligned = 1697 hif_mem_alloc_consistent_unaligned 1698 (scn, 1699 (nentries * desc_size + 1700 CE_DESC_RING_ALIGN), 1701 base_addr, 1702 ce_ring->hal_ring_type, 1703 &ce_ring->is_ring_prealloc); 1704 1705 if (!ce_ring->base_addr_owner_space_unaligned) { 1706 hif_err("Failed to allocate DMA memory for ce ring id: %u", 1707 CE_id); 1708 return QDF_STATUS_E_NOMEM; 1709 } 1710 return QDF_STATUS_SUCCESS; 1711 } 1712 1713 static void ce_free_desc_ring(struct hif_softc *scn, unsigned int CE_id, 1714 struct CE_ring_state *ce_ring, uint32_t desc_size) 1715 { 1716 hif_mem_free_consistent_unaligned 1717 (scn, 1718 ce_ring->nentries * desc_size + CE_DESC_RING_ALIGN, 1719 ce_ring->base_addr_owner_space_unaligned, 1720 ce_ring->base_addr_CE_space, 0, 1721 ce_ring->is_ring_prealloc); 1722 ce_ring->base_addr_owner_space_unaligned = NULL; 1723 } 1724 #endif /* IPA_OFFLOAD */ 1725 1726 /* 1727 * TODO: Need to explore the possibility of having this as part of a 1728 * target context instead of a global array. 1729 */ 1730 static struct ce_ops* (*ce_attach_register[CE_MAX_TARGET_TYPE])(void); 1731 1732 void ce_service_register_module(enum ce_target_type target_type, 1733 struct ce_ops* (*ce_attach)(void)) 1734 { 1735 if (target_type < CE_MAX_TARGET_TYPE) 1736 ce_attach_register[target_type] = ce_attach; 1737 } 1738 1739 qdf_export_symbol(ce_service_register_module); 1740 1741 /** 1742 * ce_srng_based() - Does this target use srng 1743 * @scn: pointer to the state context of the CE 1744 * 1745 * Description: 1746 * returns true if the target is SRNG based 1747 * 1748 * Return: 1749 * false (attribute set to false) 1750 * true (attribute set to true); 1751 */ 1752 bool ce_srng_based(struct hif_softc *scn) 1753 { 1754 struct hif_opaque_softc *hif_hdl = GET_HIF_OPAQUE_HDL(scn); 1755 struct hif_target_info *tgt_info = hif_get_target_info_handle(hif_hdl); 1756 1757 switch (tgt_info->target_type) { 1758 case TARGET_TYPE_QCA8074: 1759 case TARGET_TYPE_QCA8074V2: 1760 case TARGET_TYPE_QCA6290: 1761 case TARGET_TYPE_QCA6390: 1762 case TARGET_TYPE_QCA6490: 1763 case TARGET_TYPE_QCA6750: 1764 case TARGET_TYPE_QCA6018: 1765 case TARGET_TYPE_QCN9000: 1766 case TARGET_TYPE_QCN6122: 1767 case TARGET_TYPE_QCN9160: 1768 case TARGET_TYPE_QCA5018: 1769 case TARGET_TYPE_KIWI: 1770 case TARGET_TYPE_MANGO: 1771 case TARGET_TYPE_QCN9224: 1772 case TARGET_TYPE_QCA9574: 1773 case TARGET_TYPE_QCA5332: 1774 return true; 1775 default: 1776 return false; 1777 } 1778 return false; 1779 } 1780 qdf_export_symbol(ce_srng_based); 1781 1782 #ifdef QCA_WIFI_SUPPORT_SRNG 1783 static struct ce_ops *ce_services_attach(struct hif_softc *scn) 1784 { 1785 struct ce_ops *ops = NULL; 1786 1787 if (ce_srng_based(scn)) { 1788 if (ce_attach_register[CE_SVC_SRNG]) 1789 ops = ce_attach_register[CE_SVC_SRNG](); 1790 } else if (ce_attach_register[CE_SVC_LEGACY]) { 1791 ops = ce_attach_register[CE_SVC_LEGACY](); 1792 } 1793 1794 return ops; 1795 } 1796 1797 1798 #else /* QCA_LITHIUM */ 1799 static struct ce_ops *ce_services_attach(struct hif_softc *scn) 1800 { 1801 if (ce_attach_register[CE_SVC_LEGACY]) 1802 return ce_attach_register[CE_SVC_LEGACY](); 1803 1804 return NULL; 1805 } 1806 #endif /* QCA_LITHIUM */ 1807 1808 static void hif_prepare_hal_shadow_register_cfg(struct hif_softc *scn, 1809 struct pld_shadow_reg_v2_cfg **shadow_config, 1810 int *num_shadow_registers_configured) { 1811 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 1812 1813 hif_state->ce_services->ce_prepare_shadow_register_v2_cfg( 1814 scn, shadow_config, num_shadow_registers_configured); 1815 1816 return; 1817 } 1818 1819 #ifdef CONFIG_SHADOW_V3 1820 static inline void 1821 hif_prepare_hal_shadow_reg_cfg_v3(struct hif_softc *scn, 1822 struct pld_wlan_enable_cfg *cfg) 1823 { 1824 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 1825 1826 if (!hif_state->ce_services->ce_prepare_shadow_register_v3_cfg) 1827 return; 1828 1829 hif_state->ce_services->ce_prepare_shadow_register_v3_cfg( 1830 scn, &cfg->shadow_reg_v3_cfg, 1831 &cfg->num_shadow_reg_v3_cfg); 1832 } 1833 #else 1834 static inline void 1835 hif_prepare_hal_shadow_reg_cfg_v3(struct hif_softc *scn, 1836 struct pld_wlan_enable_cfg *cfg) 1837 { 1838 } 1839 #endif 1840 1841 static inline uint32_t ce_get_desc_size(struct hif_softc *scn, 1842 uint8_t ring_type) 1843 { 1844 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 1845 1846 return hif_state->ce_services->ce_get_desc_size(ring_type); 1847 } 1848 1849 #ifdef QCA_WIFI_SUPPORT_SRNG 1850 static inline int32_t ce_ring_type_to_hal_ring_type(uint32_t ce_ring_type) 1851 { 1852 switch (ce_ring_type) { 1853 case CE_RING_SRC: 1854 return CE_SRC; 1855 case CE_RING_DEST: 1856 return CE_DST; 1857 case CE_RING_STATUS: 1858 return CE_DST_STATUS; 1859 default: 1860 return -EINVAL; 1861 } 1862 } 1863 #else 1864 static int32_t ce_ring_type_to_hal_ring_type(uint32_t ce_ring_type) 1865 { 1866 return 0; 1867 } 1868 #endif 1869 static struct CE_ring_state *ce_alloc_ring_state(struct CE_state *CE_state, 1870 uint8_t ring_type, uint32_t nentries) 1871 { 1872 uint32_t ce_nbytes; 1873 char *ptr; 1874 qdf_dma_addr_t base_addr; 1875 struct CE_ring_state *ce_ring; 1876 uint32_t desc_size; 1877 struct hif_softc *scn = CE_state->scn; 1878 1879 ce_nbytes = sizeof(struct CE_ring_state) 1880 + (nentries * sizeof(void *)); 1881 ptr = qdf_mem_malloc(ce_nbytes); 1882 if (!ptr) 1883 return NULL; 1884 1885 ce_ring = (struct CE_ring_state *)ptr; 1886 ptr += sizeof(struct CE_ring_state); 1887 ce_ring->nentries = nentries; 1888 ce_ring->nentries_mask = nentries - 1; 1889 1890 ce_ring->low_water_mark_nentries = 0; 1891 ce_ring->high_water_mark_nentries = nentries; 1892 ce_ring->per_transfer_context = (void **)ptr; 1893 ce_ring->hal_ring_type = ce_ring_type_to_hal_ring_type(ring_type); 1894 1895 desc_size = ce_get_desc_size(scn, ring_type); 1896 1897 /* Legacy platforms that do not support cache 1898 * coherent DMA are unsupported 1899 */ 1900 if (ce_alloc_desc_ring(scn, CE_state->id, &base_addr, 1901 ce_ring, nentries, 1902 desc_size) != 1903 QDF_STATUS_SUCCESS) { 1904 hif_err("ring has no DMA mem"); 1905 qdf_mem_free(ce_ring); 1906 return NULL; 1907 } 1908 ce_ring->base_addr_CE_space_unaligned = base_addr; 1909 1910 /* Correctly initialize memory to 0 to 1911 * prevent garbage data crashing system 1912 * when download firmware 1913 */ 1914 qdf_mem_zero(ce_ring->base_addr_owner_space_unaligned, 1915 nentries * desc_size + 1916 CE_DESC_RING_ALIGN); 1917 1918 if (ce_ring->base_addr_CE_space_unaligned & (CE_DESC_RING_ALIGN - 1)) { 1919 1920 ce_ring->base_addr_CE_space = 1921 (ce_ring->base_addr_CE_space_unaligned + 1922 CE_DESC_RING_ALIGN - 1) & ~(CE_DESC_RING_ALIGN - 1); 1923 1924 ce_ring->base_addr_owner_space = (void *) 1925 (((size_t) ce_ring->base_addr_owner_space_unaligned + 1926 CE_DESC_RING_ALIGN - 1) & ~(CE_DESC_RING_ALIGN - 1)); 1927 } else { 1928 ce_ring->base_addr_CE_space = 1929 ce_ring->base_addr_CE_space_unaligned; 1930 ce_ring->base_addr_owner_space = 1931 ce_ring->base_addr_owner_space_unaligned; 1932 } 1933 1934 return ce_ring; 1935 } 1936 1937 static int ce_ring_setup(struct hif_softc *scn, uint8_t ring_type, 1938 uint32_t ce_id, struct CE_ring_state *ring, 1939 struct CE_attr *attr) 1940 { 1941 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 1942 1943 return hif_state->ce_services->ce_ring_setup(scn, ring_type, ce_id, 1944 ring, attr); 1945 } 1946 1947 static void ce_srng_cleanup(struct hif_softc *scn, struct CE_state *CE_state, 1948 uint8_t ring_type) 1949 { 1950 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 1951 1952 if (hif_state->ce_services->ce_srng_cleanup) 1953 hif_state->ce_services->ce_srng_cleanup(scn, 1954 CE_state, ring_type); 1955 } 1956 1957 int hif_ce_bus_early_suspend(struct hif_softc *scn) 1958 { 1959 uint8_t ul_pipe, dl_pipe; 1960 int ce_id, status, ul_is_polled, dl_is_polled; 1961 struct CE_state *ce_state; 1962 1963 status = hif_map_service_to_pipe(&scn->osc, WMI_CONTROL_SVC, 1964 &ul_pipe, &dl_pipe, 1965 &ul_is_polled, &dl_is_polled); 1966 if (status) { 1967 hif_err("pipe_mapping failure"); 1968 return status; 1969 } 1970 1971 for (ce_id = 0; ce_id < scn->ce_count; ce_id++) { 1972 if (ce_id == ul_pipe) 1973 continue; 1974 if (ce_id == dl_pipe) 1975 continue; 1976 1977 ce_state = scn->ce_id_to_state[ce_id]; 1978 qdf_spin_lock_bh(&ce_state->ce_index_lock); 1979 if (ce_state->state == CE_RUNNING) 1980 ce_state->state = CE_PAUSED; 1981 qdf_spin_unlock_bh(&ce_state->ce_index_lock); 1982 } 1983 1984 return status; 1985 } 1986 1987 int hif_ce_bus_late_resume(struct hif_softc *scn) 1988 { 1989 int ce_id; 1990 struct CE_state *ce_state; 1991 int write_index = 0; 1992 bool index_updated; 1993 1994 for (ce_id = 0; ce_id < scn->ce_count; ce_id++) { 1995 ce_state = scn->ce_id_to_state[ce_id]; 1996 qdf_spin_lock_bh(&ce_state->ce_index_lock); 1997 if (ce_state->state == CE_PENDING) { 1998 write_index = ce_state->src_ring->write_index; 1999 CE_SRC_RING_WRITE_IDX_SET(scn, ce_state->ctrl_addr, 2000 write_index); 2001 ce_state->state = CE_RUNNING; 2002 index_updated = true; 2003 } else { 2004 index_updated = false; 2005 } 2006 2007 if (ce_state->state == CE_PAUSED) 2008 ce_state->state = CE_RUNNING; 2009 qdf_spin_unlock_bh(&ce_state->ce_index_lock); 2010 2011 if (index_updated) 2012 hif_record_ce_desc_event(scn, ce_id, 2013 RESUME_WRITE_INDEX_UPDATE, 2014 NULL, NULL, write_index, 0); 2015 } 2016 2017 return 0; 2018 } 2019 2020 /** 2021 * ce_oom_recovery() - try to recover rx ce from oom condition 2022 * @context: CE_state of the CE with oom rx ring 2023 * 2024 * the executing work Will continue to be rescheduled until 2025 * at least 1 descriptor is successfully posted to the rx ring. 2026 * 2027 * return: none 2028 */ 2029 static void ce_oom_recovery(void *context) 2030 { 2031 struct CE_state *ce_state = context; 2032 struct hif_softc *scn = ce_state->scn; 2033 struct HIF_CE_state *ce_softc = HIF_GET_CE_STATE(scn); 2034 struct HIF_CE_pipe_info *pipe_info = 2035 &ce_softc->pipe_info[ce_state->id]; 2036 2037 hif_post_recv_buffers_for_pipe(pipe_info); 2038 } 2039 2040 #ifdef HIF_CE_DEBUG_DATA_BUF 2041 /** 2042 * alloc_mem_ce_debug_hist_data() - Allocate mem for the data pointed by 2043 * the CE descriptors. 2044 * Allocate HIF_CE_HISTORY_MAX records by CE_DEBUG_MAX_DATA_BUF_SIZE 2045 * @scn: hif scn handle 2046 * @ce_id: Copy Engine Id 2047 * 2048 * Return: QDF_STATUS 2049 */ 2050 QDF_STATUS alloc_mem_ce_debug_hist_data(struct hif_softc *scn, uint32_t ce_id) 2051 { 2052 struct hif_ce_desc_event *event = NULL; 2053 struct hif_ce_desc_event *hist_ev = NULL; 2054 uint32_t index = 0; 2055 2056 hist_ev = 2057 (struct hif_ce_desc_event *)scn->hif_ce_desc_hist.hist_ev[ce_id]; 2058 2059 if (!hist_ev) 2060 return QDF_STATUS_E_NOMEM; 2061 2062 scn->hif_ce_desc_hist.data_enable[ce_id] = true; 2063 for (index = 0; index < HIF_CE_HISTORY_MAX; index++) { 2064 event = &hist_ev[index]; 2065 event->data = 2066 (uint8_t *)qdf_mem_malloc(CE_DEBUG_MAX_DATA_BUF_SIZE); 2067 if (!event->data) { 2068 hif_err_rl("ce debug data alloc failed"); 2069 scn->hif_ce_desc_hist.data_enable[ce_id] = false; 2070 return QDF_STATUS_E_NOMEM; 2071 } 2072 } 2073 return QDF_STATUS_SUCCESS; 2074 } 2075 2076 /** 2077 * free_mem_ce_debug_hist_data() - Free mem of the data pointed by 2078 * the CE descriptors. 2079 * @scn: hif scn handle 2080 * @ce_id: Copy Engine Id 2081 * 2082 * Return: 2083 */ 2084 void free_mem_ce_debug_hist_data(struct hif_softc *scn, uint32_t ce_id) 2085 { 2086 struct hif_ce_desc_event *event = NULL; 2087 struct hif_ce_desc_event *hist_ev = NULL; 2088 uint32_t index = 0; 2089 2090 hist_ev = 2091 (struct hif_ce_desc_event *)scn->hif_ce_desc_hist.hist_ev[ce_id]; 2092 2093 if (!hist_ev) 2094 return; 2095 2096 for (index = 0; index < HIF_CE_HISTORY_MAX; index++) { 2097 event = &hist_ev[index]; 2098 if (event->data) 2099 qdf_mem_free(event->data); 2100 event->data = NULL; 2101 event = NULL; 2102 } 2103 2104 } 2105 #endif /* HIF_CE_DEBUG_DATA_BUF */ 2106 2107 #ifndef HIF_CE_DEBUG_DATA_DYNAMIC_BUF 2108 #if defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF) 2109 2110 /* define below variables for crashscope parse */ 2111 struct hif_ce_desc_event *hif_ce_desc_history[CE_COUNT_MAX]; 2112 uint32_t hif_ce_history_max = HIF_CE_HISTORY_MAX; 2113 2114 /* 2115 * for debug build, it will enable ce history for all ce, but for 2116 * perf build(if CONFIG_SLUB_DEBUG_ON is N), it only enable for 2117 * ce2(wmi event) & ce3(wmi cmd) history. 2118 */ 2119 #if defined(CONFIG_SLUB_DEBUG_ON) 2120 #define CE_DESC_HISTORY_BUFF_CNT CE_COUNT_MAX 2121 #define IS_CE_DEBUG_ONLY_FOR_CRIT_CE 0 2122 #else 2123 /* CE2, CE3, CE7 */ 2124 #define CE_DESC_HISTORY_BUFF_CNT 3 2125 #define IS_CE_DEBUG_ONLY_FOR_CRIT_CE (BIT(2) | BIT(3) | BIT(7)) 2126 #endif 2127 struct hif_ce_desc_event 2128 hif_ce_desc_history_buff[CE_DESC_HISTORY_BUFF_CNT][HIF_CE_HISTORY_MAX]; 2129 2130 static struct hif_ce_desc_event * 2131 hif_ce_debug_history_buf_get(struct hif_softc *scn, unsigned int ce_id) 2132 { 2133 struct ce_desc_hist *ce_hist = &scn->hif_ce_desc_hist; 2134 2135 hif_debug("get ce debug buffer ce_id %u, only_ce2/ce3=0x%x, idx=%u", 2136 ce_id, IS_CE_DEBUG_ONLY_FOR_CRIT_CE, 2137 ce_hist->ce_id_hist_map[ce_id]); 2138 if (IS_CE_DEBUG_ONLY_FOR_CRIT_CE && 2139 (ce_id == CE_ID_2 || ce_id == CE_ID_3 || ce_id == CE_ID_7)) { 2140 uint8_t idx = ce_hist->ce_id_hist_map[ce_id]; 2141 2142 hif_ce_desc_history[ce_id] = hif_ce_desc_history_buff[idx]; 2143 } else { 2144 hif_ce_desc_history[ce_id] = 2145 hif_ce_desc_history_buff[ce_id]; 2146 } 2147 2148 return hif_ce_desc_history[ce_id]; 2149 } 2150 2151 /** 2152 * alloc_mem_ce_debug_history() - Allocate CE descriptor history 2153 * @scn: hif scn handle 2154 * @ce_id: Copy Engine Id 2155 * @src_nentries: source ce ring entries 2156 * Return: QDF_STATUS 2157 */ 2158 static QDF_STATUS 2159 alloc_mem_ce_debug_history(struct hif_softc *scn, unsigned int ce_id, 2160 uint32_t src_nentries) 2161 { 2162 struct ce_desc_hist *ce_hist = &scn->hif_ce_desc_hist; 2163 QDF_STATUS status = QDF_STATUS_SUCCESS; 2164 2165 /* For perf build, return directly for non ce2/ce3 */ 2166 if (IS_CE_DEBUG_ONLY_FOR_CRIT_CE && 2167 ce_id != CE_ID_2 && 2168 ce_id != CE_ID_3 && 2169 ce_id != CE_ID_7) { 2170 ce_hist->enable[ce_id] = false; 2171 ce_hist->data_enable[ce_id] = false; 2172 return QDF_STATUS_SUCCESS; 2173 } 2174 2175 ce_hist->hist_ev[ce_id] = hif_ce_debug_history_buf_get(scn, ce_id); 2176 ce_hist->enable[ce_id] = true; 2177 2178 if (src_nentries) { 2179 status = alloc_mem_ce_debug_hist_data(scn, ce_id); 2180 if (status != QDF_STATUS_SUCCESS) { 2181 ce_hist->enable[ce_id] = false; 2182 ce_hist->hist_ev[ce_id] = NULL; 2183 return status; 2184 } 2185 } else { 2186 ce_hist->data_enable[ce_id] = false; 2187 } 2188 2189 return QDF_STATUS_SUCCESS; 2190 } 2191 2192 /** 2193 * free_mem_ce_debug_history() - Free CE descriptor history 2194 * @scn: hif scn handle 2195 * @ce_id: Copy Engine Id 2196 * 2197 * Return: None 2198 */ 2199 static void free_mem_ce_debug_history(struct hif_softc *scn, unsigned int ce_id) 2200 { 2201 struct ce_desc_hist *ce_hist = &scn->hif_ce_desc_hist; 2202 2203 if (!ce_hist->enable[ce_id]) 2204 return; 2205 2206 ce_hist->enable[ce_id] = false; 2207 if (ce_hist->data_enable[ce_id]) { 2208 ce_hist->data_enable[ce_id] = false; 2209 free_mem_ce_debug_hist_data(scn, ce_id); 2210 } 2211 ce_hist->hist_ev[ce_id] = NULL; 2212 } 2213 #else 2214 static inline QDF_STATUS 2215 alloc_mem_ce_debug_history(struct hif_softc *scn, unsigned int CE_id, 2216 uint32_t src_nentries) 2217 { 2218 return QDF_STATUS_SUCCESS; 2219 } 2220 2221 static inline void 2222 free_mem_ce_debug_history(struct hif_softc *scn, unsigned int CE_id) { } 2223 #endif /* (HIF_CONFIG_SLUB_DEBUG_ON) || (HIF_CE_DEBUG_DATA_BUF) */ 2224 #else 2225 #if defined(HIF_CE_DEBUG_DATA_BUF) 2226 2227 static QDF_STATUS 2228 alloc_mem_ce_debug_history(struct hif_softc *scn, unsigned int CE_id, 2229 uint32_t src_nentries) 2230 { 2231 scn->hif_ce_desc_hist.hist_ev[CE_id] = (struct hif_ce_desc_event *) 2232 qdf_mem_malloc(HIF_CE_HISTORY_MAX * sizeof(struct hif_ce_desc_event)); 2233 2234 if (!scn->hif_ce_desc_hist.hist_ev[CE_id]) { 2235 scn->hif_ce_desc_hist.enable[CE_id] = 0; 2236 return QDF_STATUS_E_NOMEM; 2237 } else { 2238 scn->hif_ce_desc_hist.enable[CE_id] = 1; 2239 return QDF_STATUS_SUCCESS; 2240 } 2241 } 2242 2243 static void free_mem_ce_debug_history(struct hif_softc *scn, unsigned int CE_id) 2244 { 2245 struct ce_desc_hist *ce_hist = &scn->hif_ce_desc_hist; 2246 struct hif_ce_desc_event *hist_ev = ce_hist->hist_ev[CE_id]; 2247 2248 if (!hist_ev) 2249 return; 2250 2251 if (ce_hist->data_enable[CE_id]) { 2252 ce_hist->data_enable[CE_id] = false; 2253 free_mem_ce_debug_hist_data(scn, CE_id); 2254 } 2255 2256 ce_hist->enable[CE_id] = false; 2257 qdf_mem_free(ce_hist->hist_ev[CE_id]); 2258 ce_hist->hist_ev[CE_id] = NULL; 2259 } 2260 2261 #else 2262 2263 static inline QDF_STATUS 2264 alloc_mem_ce_debug_history(struct hif_softc *scn, unsigned int CE_id, 2265 uint32_t src_nentries) 2266 { 2267 return QDF_STATUS_SUCCESS; 2268 } 2269 2270 static inline void 2271 free_mem_ce_debug_history(struct hif_softc *scn, unsigned int CE_id) { } 2272 #endif /* HIF_CE_DEBUG_DATA_BUF */ 2273 #endif /* HIF_CE_DEBUG_DATA_DYNAMIC_BUF */ 2274 2275 #if defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF) 2276 /** 2277 * reset_ce_debug_history() - reset the index and ce id used for dumping the 2278 * CE records on the console using sysfs. 2279 * @scn: hif scn handle 2280 * 2281 * Return: 2282 */ 2283 static inline void reset_ce_debug_history(struct hif_softc *scn) 2284 { 2285 struct ce_desc_hist *ce_hist = &scn->hif_ce_desc_hist; 2286 /* Initialise the CE debug history sysfs interface inputs ce_id and 2287 * index. Disable data storing 2288 */ 2289 ce_hist->hist_index = 0; 2290 ce_hist->hist_id = 0; 2291 } 2292 #else /* defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF) */ 2293 static inline void reset_ce_debug_history(struct hif_softc *scn) { } 2294 #endif /*defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF) */ 2295 2296 void ce_enable_polling(void *cestate) 2297 { 2298 struct CE_state *CE_state = (struct CE_state *)cestate; 2299 2300 if (CE_state && CE_state->attr_flags & CE_ATTR_ENABLE_POLL) 2301 CE_state->timer_inited = true; 2302 } 2303 2304 void ce_disable_polling(void *cestate) 2305 { 2306 struct CE_state *CE_state = (struct CE_state *)cestate; 2307 2308 if (CE_state && CE_state->attr_flags & CE_ATTR_ENABLE_POLL) 2309 CE_state->timer_inited = false; 2310 } 2311 2312 /* 2313 * Initialize a Copy Engine based on caller-supplied attributes. 2314 * This may be called once to initialize both source and destination 2315 * rings or it may be called twice for separate source and destination 2316 * initialization. It may be that only one side or the other is 2317 * initialized by software/firmware. 2318 * 2319 * This should be called during the initialization sequence before 2320 * interrupts are enabled, so we don't have to worry about thread safety. 2321 */ 2322 struct CE_handle *ce_init(struct hif_softc *scn, 2323 unsigned int CE_id, struct CE_attr *attr) 2324 { 2325 struct CE_state *CE_state; 2326 uint32_t ctrl_addr; 2327 unsigned int nentries; 2328 bool malloc_CE_state = false; 2329 bool malloc_src_ring = false; 2330 int status; 2331 QDF_STATUS mem_status = QDF_STATUS_SUCCESS; 2332 2333 QDF_ASSERT(CE_id < scn->ce_count); 2334 ctrl_addr = CE_BASE_ADDRESS(CE_id); 2335 CE_state = scn->ce_id_to_state[CE_id]; 2336 2337 if (!CE_state) { 2338 CE_state = 2339 (struct CE_state *)qdf_mem_malloc(sizeof(*CE_state)); 2340 if (!CE_state) 2341 return NULL; 2342 2343 malloc_CE_state = true; 2344 qdf_spinlock_create(&CE_state->ce_index_lock); 2345 #ifdef CE_TASKLET_SCHEDULE_ON_FULL 2346 qdf_spinlock_create(&CE_state->ce_interrupt_lock); 2347 #endif 2348 2349 CE_state->id = CE_id; 2350 CE_state->ctrl_addr = ctrl_addr; 2351 CE_state->state = CE_RUNNING; 2352 CE_state->attr_flags = attr->flags; 2353 } 2354 CE_state->scn = scn; 2355 CE_state->service = ce_engine_service_reg; 2356 2357 qdf_atomic_init(&CE_state->rx_pending); 2358 if (!attr) { 2359 /* Already initialized; caller wants the handle */ 2360 return (struct CE_handle *)CE_state; 2361 } 2362 2363 if (CE_state->src_sz_max) 2364 QDF_ASSERT(CE_state->src_sz_max == attr->src_sz_max); 2365 else 2366 CE_state->src_sz_max = attr->src_sz_max; 2367 2368 ce_init_ce_desc_event_log(scn, CE_id, 2369 attr->src_nentries + attr->dest_nentries); 2370 2371 /* source ring setup */ 2372 nentries = attr->src_nentries; 2373 if (nentries) { 2374 struct CE_ring_state *src_ring; 2375 2376 nentries = roundup_pwr2(nentries); 2377 if (CE_state->src_ring) { 2378 QDF_ASSERT(CE_state->src_ring->nentries == nentries); 2379 } else { 2380 src_ring = CE_state->src_ring = 2381 ce_alloc_ring_state(CE_state, 2382 CE_RING_SRC, 2383 nentries); 2384 if (!src_ring) { 2385 /* cannot allocate src ring. If the 2386 * CE_state is allocated locally free 2387 * CE_State and return error. 2388 */ 2389 hif_err("src ring has no mem"); 2390 if (malloc_CE_state) { 2391 /* allocated CE_state locally */ 2392 qdf_mem_free(CE_state); 2393 malloc_CE_state = false; 2394 } 2395 return NULL; 2396 } 2397 /* we can allocate src ring. Mark that the src ring is 2398 * allocated locally 2399 */ 2400 malloc_src_ring = true; 2401 2402 /* 2403 * Also allocate a shadow src ring in 2404 * regular mem to use for faster access. 2405 */ 2406 src_ring->shadow_base_unaligned = 2407 qdf_mem_malloc(nentries * 2408 sizeof(struct CE_src_desc) + 2409 CE_DESC_RING_ALIGN); 2410 if (!src_ring->shadow_base_unaligned) 2411 goto error_no_dma_mem; 2412 2413 src_ring->shadow_base = (struct CE_src_desc *) 2414 (((size_t) src_ring->shadow_base_unaligned + 2415 CE_DESC_RING_ALIGN - 1) & 2416 ~(CE_DESC_RING_ALIGN - 1)); 2417 2418 status = ce_ring_setup(scn, CE_RING_SRC, CE_id, 2419 src_ring, attr); 2420 if (status < 0) 2421 goto error_target_access; 2422 ce_ring_test_initial_indexes(CE_id, src_ring, 2423 "src_ring"); 2424 } 2425 } 2426 2427 /* destination ring setup */ 2428 nentries = attr->dest_nentries; 2429 if (nentries) { 2430 struct CE_ring_state *dest_ring; 2431 2432 nentries = roundup_pwr2(nentries); 2433 if (CE_state->dest_ring) { 2434 QDF_ASSERT(CE_state->dest_ring->nentries == nentries); 2435 } else { 2436 dest_ring = CE_state->dest_ring = 2437 ce_alloc_ring_state(CE_state, 2438 CE_RING_DEST, 2439 nentries); 2440 if (!dest_ring) { 2441 /* cannot allocate dst ring. If the CE_state 2442 * or src ring is allocated locally free 2443 * CE_State and src ring and return error. 2444 */ 2445 hif_err("dest ring has no mem"); 2446 goto error_no_dma_mem; 2447 } 2448 2449 status = ce_ring_setup(scn, CE_RING_DEST, CE_id, 2450 dest_ring, attr); 2451 if (status < 0) 2452 goto error_target_access; 2453 2454 ce_ring_test_initial_indexes(CE_id, dest_ring, 2455 "dest_ring"); 2456 2457 /* For srng based target, init status ring here */ 2458 if (ce_srng_based(CE_state->scn)) { 2459 CE_state->status_ring = 2460 ce_alloc_ring_state(CE_state, 2461 CE_RING_STATUS, 2462 nentries); 2463 if (!CE_state->status_ring) { 2464 /*Allocation failed. Cleanup*/ 2465 qdf_mem_free(CE_state->dest_ring); 2466 if (malloc_src_ring) { 2467 qdf_mem_free 2468 (CE_state->src_ring); 2469 CE_state->src_ring = NULL; 2470 malloc_src_ring = false; 2471 } 2472 if (malloc_CE_state) { 2473 /* allocated CE_state locally */ 2474 scn->ce_id_to_state[CE_id] = 2475 NULL; 2476 qdf_mem_free(CE_state); 2477 malloc_CE_state = false; 2478 } 2479 2480 return NULL; 2481 } 2482 2483 status = ce_ring_setup(scn, CE_RING_STATUS, 2484 CE_id, CE_state->status_ring, 2485 attr); 2486 if (status < 0) 2487 goto error_target_access; 2488 2489 } 2490 2491 /* epping */ 2492 /* poll timer */ 2493 if (CE_state->attr_flags & CE_ATTR_ENABLE_POLL) { 2494 qdf_timer_init(scn->qdf_dev, 2495 &CE_state->poll_timer, 2496 ce_poll_timeout, 2497 CE_state, 2498 QDF_TIMER_TYPE_WAKE_APPS); 2499 ce_enable_polling(CE_state); 2500 qdf_timer_mod(&CE_state->poll_timer, 2501 CE_POLL_TIMEOUT); 2502 } 2503 } 2504 } 2505 2506 if (!ce_srng_based(scn)) { 2507 /* Enable CE error interrupts */ 2508 if (Q_TARGET_ACCESS_BEGIN(scn) < 0) 2509 goto error_target_access; 2510 CE_ERROR_INTR_ENABLE(scn, ctrl_addr); 2511 if (Q_TARGET_ACCESS_END(scn) < 0) 2512 goto error_target_access; 2513 } 2514 2515 qdf_create_work(scn->qdf_dev, &CE_state->oom_allocation_work, 2516 ce_oom_recovery, CE_state); 2517 2518 /* update the htt_data attribute */ 2519 ce_mark_datapath(CE_state); 2520 scn->ce_id_to_state[CE_id] = CE_state; 2521 2522 mem_status = alloc_mem_ce_debug_history(scn, CE_id, attr->src_nentries); 2523 if (mem_status != QDF_STATUS_SUCCESS) 2524 goto error_target_access; 2525 2526 return (struct CE_handle *)CE_state; 2527 2528 error_target_access: 2529 error_no_dma_mem: 2530 ce_fini((struct CE_handle *)CE_state); 2531 return NULL; 2532 } 2533 2534 /** 2535 * hif_is_polled_mode_enabled - API to query if polling is enabled on all CEs 2536 * @hif_ctx: HIF Context 2537 * 2538 * API to check if polling is enabled on all CEs. Returns true when polling 2539 * is enabled on all CEs. 2540 * 2541 * Return: bool 2542 */ 2543 bool hif_is_polled_mode_enabled(struct hif_opaque_softc *hif_ctx) 2544 { 2545 struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); 2546 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 2547 struct CE_attr *attr; 2548 int id; 2549 2550 for (id = 0; id < scn->ce_count; id++) { 2551 attr = &hif_state->host_ce_config[id]; 2552 if (attr && (attr->dest_nentries) && 2553 !(attr->flags & CE_ATTR_ENABLE_POLL)) 2554 return false; 2555 } 2556 return true; 2557 } 2558 qdf_export_symbol(hif_is_polled_mode_enabled); 2559 2560 static int hif_get_pktlog_ce_num(struct hif_softc *scn) 2561 { 2562 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 2563 int id; 2564 2565 for (id = 0; id < hif_state->sz_tgt_svc_map; id++) { 2566 if (hif_state->tgt_svc_map[id].service_id == PACKET_LOG_SVC) 2567 return hif_state->tgt_svc_map[id].pipenum; 2568 } 2569 return -EINVAL; 2570 } 2571 2572 #ifdef WLAN_FEATURE_FASTPATH 2573 /** 2574 * hif_enable_fastpath() - Update that we have enabled fastpath mode 2575 * @hif_ctx: HIF context 2576 * 2577 * For use in data path 2578 * 2579 * Return: void 2580 */ 2581 void hif_enable_fastpath(struct hif_opaque_softc *hif_ctx) 2582 { 2583 struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); 2584 2585 if (ce_srng_based(scn)) { 2586 hif_warn("srng rings do not support fastpath"); 2587 return; 2588 } 2589 hif_debug("Enabling fastpath mode"); 2590 scn->fastpath_mode_on = true; 2591 } 2592 2593 /** 2594 * hif_is_fastpath_mode_enabled - API to query if fasthpath mode is enabled 2595 * @hif_ctx: HIF Context 2596 * 2597 * For use in data path to skip HTC 2598 * 2599 * Return: bool 2600 */ 2601 bool hif_is_fastpath_mode_enabled(struct hif_opaque_softc *hif_ctx) 2602 { 2603 struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); 2604 2605 return scn->fastpath_mode_on; 2606 } 2607 2608 /** 2609 * hif_get_ce_handle - API to get CE handle for FastPath mode 2610 * @hif_ctx: HIF Context 2611 * @id: CopyEngine Id 2612 * 2613 * API to return CE handle for fastpath mode 2614 * 2615 * Return: void 2616 */ 2617 void *hif_get_ce_handle(struct hif_opaque_softc *hif_ctx, int id) 2618 { 2619 struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); 2620 2621 return scn->ce_id_to_state[id]; 2622 } 2623 qdf_export_symbol(hif_get_ce_handle); 2624 2625 /** 2626 * ce_h2t_tx_ce_cleanup() - Place holder function for H2T CE cleanup. 2627 * No processing is required inside this function. 2628 * @ce_hdl: Cope engine handle 2629 * Using an assert, this function makes sure that, 2630 * the TX CE has been processed completely. 2631 * 2632 * This is called while dismantling CE structures. No other thread 2633 * should be using these structures while dismantling is occurring 2634 * therefore no locking is needed. 2635 * 2636 * Return: none 2637 */ 2638 void ce_h2t_tx_ce_cleanup(struct CE_handle *ce_hdl) 2639 { 2640 struct CE_state *ce_state = (struct CE_state *)ce_hdl; 2641 struct CE_ring_state *src_ring = ce_state->src_ring; 2642 struct hif_softc *sc = ce_state->scn; 2643 uint32_t sw_index, write_index; 2644 2645 if (hif_is_nss_wifi_enabled(sc)) 2646 return; 2647 2648 if (sc->fastpath_mode_on && ce_state->htt_tx_data) { 2649 hif_debug("Fastpath mode ON, Cleaning up HTT Tx CE"); 2650 sw_index = src_ring->sw_index; 2651 write_index = src_ring->sw_index; 2652 2653 /* At this point Tx CE should be clean */ 2654 qdf_assert_always(sw_index == write_index); 2655 } 2656 } 2657 2658 /** 2659 * ce_t2h_msg_ce_cleanup() - Cleanup buffers on the t2h datapath msg queue. 2660 * @ce_hdl: Handle to CE 2661 * 2662 * These buffers are never allocated on the fly, but 2663 * are allocated only once during HIF start and freed 2664 * only once during HIF stop. 2665 * NOTE: 2666 * The assumption here is there is no in-flight DMA in progress 2667 * currently, so that buffers can be freed up safely. 2668 * 2669 * Return: NONE 2670 */ 2671 void ce_t2h_msg_ce_cleanup(struct CE_handle *ce_hdl) 2672 { 2673 struct CE_state *ce_state = (struct CE_state *)ce_hdl; 2674 struct CE_ring_state *dst_ring = ce_state->dest_ring; 2675 qdf_nbuf_t nbuf; 2676 int i; 2677 2678 if (ce_state->scn->fastpath_mode_on == false) 2679 return; 2680 2681 if (!ce_state->htt_rx_data) 2682 return; 2683 2684 /* 2685 * when fastpath_mode is on and for datapath CEs. Unlike other CE's, 2686 * this CE is completely full: does not leave one blank space, to 2687 * distinguish between empty queue & full queue. So free all the 2688 * entries. 2689 */ 2690 for (i = 0; i < dst_ring->nentries; i++) { 2691 nbuf = dst_ring->per_transfer_context[i]; 2692 2693 /* 2694 * The reasons for doing this check are: 2695 * 1) Protect against calling cleanup before allocating buffers 2696 * 2) In a corner case, FASTPATH_mode_on may be set, but we 2697 * could have a partially filled ring, because of a memory 2698 * allocation failure in the middle of allocating ring. 2699 * This check accounts for that case, checking 2700 * fastpath_mode_on flag or started flag would not have 2701 * covered that case. This is not in performance path, 2702 * so OK to do this. 2703 */ 2704 if (nbuf) { 2705 qdf_nbuf_unmap_single(ce_state->scn->qdf_dev, nbuf, 2706 QDF_DMA_FROM_DEVICE); 2707 qdf_nbuf_free(nbuf); 2708 } 2709 } 2710 } 2711 2712 /** 2713 * hif_update_fastpath_recv_bufs_cnt() - Increments the Rx buf count by 1 2714 * @scn: HIF handle 2715 * 2716 * Datapath Rx CEs are special case, where we reuse all the message buffers. 2717 * Hence we have to post all the entries in the pipe, even, in the beginning 2718 * unlike for other CE pipes where one less than dest_nentries are filled in 2719 * the beginning. 2720 * 2721 * Return: None 2722 */ 2723 static void hif_update_fastpath_recv_bufs_cnt(struct hif_softc *scn) 2724 { 2725 int pipe_num; 2726 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 2727 2728 if (scn->fastpath_mode_on == false) 2729 return; 2730 2731 for (pipe_num = 0; pipe_num < scn->ce_count; pipe_num++) { 2732 struct HIF_CE_pipe_info *pipe_info = 2733 &hif_state->pipe_info[pipe_num]; 2734 struct CE_state *ce_state = 2735 scn->ce_id_to_state[pipe_info->pipe_num]; 2736 2737 if (ce_state->htt_rx_data) 2738 atomic_inc(&pipe_info->recv_bufs_needed); 2739 } 2740 } 2741 #else 2742 static inline void hif_update_fastpath_recv_bufs_cnt(struct hif_softc *scn) 2743 { 2744 } 2745 2746 static inline bool ce_is_fastpath_enabled(struct hif_softc *scn) 2747 { 2748 return false; 2749 } 2750 #endif /* WLAN_FEATURE_FASTPATH */ 2751 2752 void ce_fini(struct CE_handle *copyeng) 2753 { 2754 struct CE_state *CE_state = (struct CE_state *)copyeng; 2755 unsigned int CE_id = CE_state->id; 2756 struct hif_softc *scn = CE_state->scn; 2757 uint32_t desc_size; 2758 2759 bool inited = CE_state->timer_inited; 2760 CE_state->state = CE_UNUSED; 2761 scn->ce_id_to_state[CE_id] = NULL; 2762 /* Set the flag to false first to stop processing in ce_poll_timeout */ 2763 ce_disable_polling(CE_state); 2764 2765 qdf_lro_deinit(CE_state->lro_data); 2766 2767 if (CE_state->src_ring) { 2768 /* Cleanup the datapath Tx ring */ 2769 ce_h2t_tx_ce_cleanup(copyeng); 2770 2771 desc_size = ce_get_desc_size(scn, CE_RING_SRC); 2772 if (CE_state->src_ring->shadow_base_unaligned) 2773 qdf_mem_free(CE_state->src_ring->shadow_base_unaligned); 2774 if (CE_state->src_ring->base_addr_owner_space_unaligned) 2775 ce_free_desc_ring(scn, CE_state->id, 2776 CE_state->src_ring, 2777 desc_size); 2778 ce_srng_cleanup(scn, CE_state, CE_RING_SRC); 2779 qdf_mem_free(CE_state->src_ring); 2780 } 2781 if (CE_state->dest_ring) { 2782 /* Cleanup the datapath Rx ring */ 2783 ce_t2h_msg_ce_cleanup(copyeng); 2784 2785 desc_size = ce_get_desc_size(scn, CE_RING_DEST); 2786 if (CE_state->dest_ring->base_addr_owner_space_unaligned) 2787 ce_free_desc_ring(scn, CE_state->id, 2788 CE_state->dest_ring, 2789 desc_size); 2790 ce_srng_cleanup(scn, CE_state, CE_RING_DEST); 2791 qdf_mem_free(CE_state->dest_ring); 2792 2793 /* epping */ 2794 if (inited) { 2795 qdf_timer_free(&CE_state->poll_timer); 2796 } 2797 } 2798 if ((ce_srng_based(CE_state->scn)) && (CE_state->status_ring)) { 2799 /* Cleanup the datapath Tx ring */ 2800 ce_h2t_tx_ce_cleanup(copyeng); 2801 2802 if (CE_state->status_ring->shadow_base_unaligned) 2803 qdf_mem_free( 2804 CE_state->status_ring->shadow_base_unaligned); 2805 2806 desc_size = ce_get_desc_size(scn, CE_RING_STATUS); 2807 if (CE_state->status_ring->base_addr_owner_space_unaligned) 2808 ce_free_desc_ring(scn, CE_state->id, 2809 CE_state->status_ring, 2810 desc_size); 2811 ce_srng_cleanup(scn, CE_state, CE_RING_STATUS); 2812 qdf_mem_free(CE_state->status_ring); 2813 } 2814 2815 free_mem_ce_debug_history(scn, CE_id); 2816 reset_ce_debug_history(scn); 2817 ce_deinit_ce_desc_event_log(scn, CE_id); 2818 2819 qdf_spinlock_destroy(&CE_state->ce_index_lock); 2820 #ifdef CE_TASKLET_SCHEDULE_ON_FULL 2821 qdf_spinlock_destroy(&CE_state->ce_interrupt_lock); 2822 #endif 2823 qdf_mem_free(CE_state); 2824 } 2825 2826 void hif_detach_htc(struct hif_opaque_softc *hif_ctx) 2827 { 2828 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(hif_ctx); 2829 2830 qdf_mem_zero(&hif_state->msg_callbacks_pending, 2831 sizeof(hif_state->msg_callbacks_pending)); 2832 qdf_mem_zero(&hif_state->msg_callbacks_current, 2833 sizeof(hif_state->msg_callbacks_current)); 2834 } 2835 2836 /* Send the first nbytes bytes of the buffer */ 2837 QDF_STATUS 2838 hif_send_head(struct hif_opaque_softc *hif_ctx, 2839 uint8_t pipe, unsigned int transfer_id, unsigned int nbytes, 2840 qdf_nbuf_t nbuf, unsigned int data_attr) 2841 { 2842 struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); 2843 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(hif_ctx); 2844 struct HIF_CE_pipe_info *pipe_info = &(hif_state->pipe_info[pipe]); 2845 struct CE_handle *ce_hdl = pipe_info->ce_hdl; 2846 int bytes = nbytes, nfrags = 0; 2847 struct ce_sendlist sendlist; 2848 int i = 0; 2849 QDF_STATUS status; 2850 unsigned int mux_id = 0; 2851 2852 if (nbytes > qdf_nbuf_len(nbuf)) { 2853 hif_err("nbytes: %d nbuf_len: %d", nbytes, 2854 (uint32_t)qdf_nbuf_len(nbuf)); 2855 QDF_ASSERT(0); 2856 } 2857 2858 transfer_id = 2859 (mux_id & MUX_ID_MASK) | 2860 (transfer_id & TRANSACTION_ID_MASK); 2861 data_attr &= DESC_DATA_FLAG_MASK; 2862 /* 2863 * The common case involves sending multiple fragments within a 2864 * single download (the tx descriptor and the tx frame header). 2865 * So, optimize for the case of multiple fragments by not even 2866 * checking whether it's necessary to use a sendlist. 2867 * The overhead of using a sendlist for a single buffer download 2868 * is not a big deal, since it happens rarely (for WMI messages). 2869 */ 2870 ce_sendlist_init(&sendlist); 2871 do { 2872 qdf_dma_addr_t frag_paddr; 2873 int frag_bytes; 2874 2875 frag_paddr = qdf_nbuf_get_frag_paddr(nbuf, nfrags); 2876 frag_bytes = qdf_nbuf_get_frag_len(nbuf, nfrags); 2877 /* 2878 * Clear the packet offset for all but the first CE desc. 2879 */ 2880 if (i++ > 0) 2881 data_attr &= ~QDF_CE_TX_PKT_OFFSET_BIT_M; 2882 2883 status = ce_sendlist_buf_add(&sendlist, frag_paddr, 2884 frag_bytes > 2885 bytes ? bytes : frag_bytes, 2886 qdf_nbuf_get_frag_is_wordstream 2887 (nbuf, 2888 nfrags) ? 0 : 2889 CE_SEND_FLAG_SWAP_DISABLE, 2890 data_attr); 2891 if (status != QDF_STATUS_SUCCESS) { 2892 hif_err("frag_num: %d larger than limit (status=%d)", 2893 nfrags, status); 2894 return status; 2895 } 2896 bytes -= frag_bytes; 2897 nfrags++; 2898 } while (bytes > 0); 2899 2900 /* Make sure we have resources to handle this request */ 2901 qdf_spin_lock_bh(&pipe_info->completion_freeq_lock); 2902 if (pipe_info->num_sends_allowed < nfrags) { 2903 qdf_spin_unlock_bh(&pipe_info->completion_freeq_lock); 2904 ce_pkt_error_count_incr(hif_state, HIF_PIPE_NO_RESOURCE); 2905 return QDF_STATUS_E_RESOURCES; 2906 } 2907 pipe_info->num_sends_allowed -= nfrags; 2908 qdf_spin_unlock_bh(&pipe_info->completion_freeq_lock); 2909 2910 if (qdf_unlikely(!ce_hdl)) { 2911 hif_err("CE handle is null"); 2912 return A_ERROR; 2913 } 2914 2915 QDF_NBUF_UPDATE_TX_PKT_COUNT(nbuf, QDF_NBUF_TX_PKT_HIF); 2916 DPTRACE(qdf_dp_trace(nbuf, QDF_DP_TRACE_HIF_PACKET_PTR_RECORD, 2917 QDF_TRACE_DEFAULT_PDEV_ID, qdf_nbuf_data_addr(nbuf), 2918 sizeof(qdf_nbuf_data(nbuf)), QDF_TX)); 2919 status = ce_sendlist_send(ce_hdl, nbuf, &sendlist, transfer_id); 2920 QDF_ASSERT(status == QDF_STATUS_SUCCESS); 2921 2922 return status; 2923 } 2924 2925 void hif_send_complete_check(struct hif_opaque_softc *hif_ctx, uint8_t pipe, 2926 int force) 2927 { 2928 struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); 2929 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(hif_ctx); 2930 2931 if (!force) { 2932 int resources; 2933 /* 2934 * Decide whether to actually poll for completions, or just 2935 * wait for a later chance. If there seem to be plenty of 2936 * resources left, then just wait, since checking involves 2937 * reading a CE register, which is a relatively expensive 2938 * operation. 2939 */ 2940 resources = hif_get_free_queue_number(hif_ctx, pipe); 2941 /* 2942 * If at least 50% of the total resources are still available, 2943 * don't bother checking again yet. 2944 */ 2945 if (resources > (hif_state->host_ce_config[pipe].src_nentries >> 2946 1)) 2947 return; 2948 } 2949 #ifdef ATH_11AC_TXCOMPACT 2950 ce_per_engine_servicereap(scn, pipe); 2951 #else 2952 ce_per_engine_service(scn, pipe); 2953 #endif 2954 } 2955 2956 #if defined(CE_TASKLET_SCHEDULE_ON_FULL) && defined(CE_TASKLET_DEBUG_ENABLE) 2957 #define CE_RING_FULL_THRESHOLD_TIME 3000000 2958 #define CE_RING_FULL_THRESHOLD 1024 2959 /* This function is called from htc_send path. If there is no resourse to send 2960 * packet via HTC, then check if interrupts are not processed from that 2961 * CE for last 3 seconds. If so, schedule a tasklet to reap available entries. 2962 * Also if Queue has reached 1024 entries within 3 seconds, then also schedule 2963 * tasklet. 2964 */ 2965 void hif_schedule_ce_tasklet(struct hif_opaque_softc *hif_ctx, uint8_t pipe) 2966 { 2967 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(hif_ctx); 2968 int64_t diff_time = qdf_get_log_timestamp_usecs() - 2969 hif_state->stats.tasklet_sched_entry_ts[pipe]; 2970 2971 hif_state->stats.ce_ring_full_count[pipe]++; 2972 2973 if (diff_time >= CE_RING_FULL_THRESHOLD_TIME || 2974 hif_state->stats.ce_ring_full_count[pipe] >= 2975 CE_RING_FULL_THRESHOLD) { 2976 hif_state->stats.ce_ring_full_count[pipe] = 0; 2977 hif_state->stats.ce_manual_tasklet_schedule_count[pipe]++; 2978 hif_state->stats.ce_last_manual_tasklet_schedule_ts[pipe] = 2979 qdf_get_log_timestamp_usecs(); 2980 ce_dispatch_interrupt(pipe, &hif_state->tasklets[pipe]); 2981 } 2982 } 2983 #else 2984 void hif_schedule_ce_tasklet(struct hif_opaque_softc *hif_ctx, uint8_t pipe) 2985 { 2986 } 2987 #endif 2988 2989 uint16_t 2990 hif_get_free_queue_number(struct hif_opaque_softc *hif_ctx, uint8_t pipe) 2991 { 2992 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(hif_ctx); 2993 struct HIF_CE_pipe_info *pipe_info = &(hif_state->pipe_info[pipe]); 2994 uint16_t rv; 2995 2996 qdf_spin_lock_bh(&pipe_info->completion_freeq_lock); 2997 rv = pipe_info->num_sends_allowed; 2998 qdf_spin_unlock_bh(&pipe_info->completion_freeq_lock); 2999 return rv; 3000 } 3001 3002 /* Called by lower (CE) layer when a send to Target completes. */ 3003 static void 3004 hif_pci_ce_send_done(struct CE_handle *copyeng, void *ce_context, 3005 void *transfer_context, qdf_dma_addr_t CE_data, 3006 unsigned int nbytes, unsigned int transfer_id, 3007 unsigned int sw_index, unsigned int hw_index, 3008 unsigned int toeplitz_hash_result) 3009 { 3010 struct HIF_CE_pipe_info *pipe_info = 3011 (struct HIF_CE_pipe_info *)ce_context; 3012 unsigned int sw_idx = sw_index, hw_idx = hw_index; 3013 struct hif_msg_callbacks *msg_callbacks = 3014 &pipe_info->pipe_callbacks; 3015 3016 do { 3017 /* 3018 * The upper layer callback will be triggered 3019 * when last fragment is complteted. 3020 */ 3021 if (transfer_context != CE_SENDLIST_ITEM_CTXT) 3022 msg_callbacks->txCompletionHandler( 3023 msg_callbacks->Context, 3024 transfer_context, transfer_id, 3025 toeplitz_hash_result); 3026 3027 qdf_spin_lock_bh(&pipe_info->completion_freeq_lock); 3028 pipe_info->num_sends_allowed++; 3029 qdf_spin_unlock_bh(&pipe_info->completion_freeq_lock); 3030 } while (ce_completed_send_next(copyeng, 3031 &ce_context, &transfer_context, 3032 &CE_data, &nbytes, &transfer_id, 3033 &sw_idx, &hw_idx, 3034 &toeplitz_hash_result) == QDF_STATUS_SUCCESS); 3035 } 3036 3037 /** 3038 * hif_ce_do_recv(): send message from copy engine to upper layers 3039 * @msg_callbacks: structure containing callback and callback context 3040 * @netbuf: skb containing message 3041 * @nbytes: number of bytes in the message 3042 * @pipe_info: used for the pipe_number info 3043 * 3044 * Checks the packet length, configures the length in the netbuff, 3045 * and calls the upper layer callback. 3046 * 3047 * return: None 3048 */ 3049 static inline void hif_ce_do_recv(struct hif_msg_callbacks *msg_callbacks, 3050 qdf_nbuf_t netbuf, int nbytes, 3051 struct HIF_CE_pipe_info *pipe_info) { 3052 if (nbytes <= pipe_info->buf_sz) { 3053 qdf_nbuf_set_pktlen(netbuf, nbytes); 3054 msg_callbacks-> 3055 rxCompletionHandler(msg_callbacks->Context, 3056 netbuf, pipe_info->pipe_num); 3057 } else { 3058 hif_err("Invalid Rx msg buf: %pK nbytes: %d", netbuf, nbytes); 3059 qdf_nbuf_free(netbuf); 3060 } 3061 } 3062 3063 /* Called by lower (CE) layer when data is received from the Target. */ 3064 static void 3065 hif_pci_ce_recv_data(struct CE_handle *copyeng, void *ce_context, 3066 void *transfer_context, qdf_dma_addr_t CE_data, 3067 unsigned int nbytes, unsigned int transfer_id, 3068 unsigned int flags) 3069 { 3070 struct HIF_CE_pipe_info *pipe_info = 3071 (struct HIF_CE_pipe_info *)ce_context; 3072 struct HIF_CE_state *hif_state = pipe_info->HIF_CE_state; 3073 struct CE_state *ce_state = (struct CE_state *) copyeng; 3074 struct hif_softc *scn = HIF_GET_SOFTC(hif_state); 3075 struct hif_msg_callbacks *msg_callbacks = &pipe_info->pipe_callbacks; 3076 3077 do { 3078 hif_rtpm_record_ce_last_busy_evt(scn, ce_state->id); 3079 hif_rtpm_mark_last_busy(HIF_RTPM_ID_CE); 3080 qdf_nbuf_unmap_single(scn->qdf_dev, 3081 (qdf_nbuf_t) transfer_context, 3082 QDF_DMA_FROM_DEVICE); 3083 3084 atomic_inc(&pipe_info->recv_bufs_needed); 3085 hif_post_recv_buffers_for_pipe(pipe_info); 3086 if (scn->target_status == TARGET_STATUS_RESET) 3087 qdf_nbuf_free(transfer_context); 3088 else 3089 hif_ce_do_recv(msg_callbacks, transfer_context, 3090 nbytes, pipe_info); 3091 3092 /* Set up force_break flag if num of receices reaches 3093 * MAX_NUM_OF_RECEIVES 3094 */ 3095 ce_state->receive_count++; 3096 if (qdf_unlikely(hif_ce_service_should_yield(scn, ce_state))) { 3097 ce_state->force_break = 1; 3098 break; 3099 } 3100 } while (ce_completed_recv_next(copyeng, &ce_context, &transfer_context, 3101 &CE_data, &nbytes, &transfer_id, 3102 &flags) == QDF_STATUS_SUCCESS); 3103 3104 } 3105 3106 /* TBDXXX: Set CE High Watermark; invoke txResourceAvailHandler in response */ 3107 3108 void 3109 hif_post_init(struct hif_opaque_softc *hif_ctx, void *unused, 3110 struct hif_msg_callbacks *callbacks) 3111 { 3112 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(hif_ctx); 3113 3114 #ifdef CONFIG_ATH_PCIE_ACCESS_DEBUG 3115 spin_lock_init(&pcie_access_log_lock); 3116 #endif 3117 /* Save callbacks for later installation */ 3118 qdf_mem_copy(&hif_state->msg_callbacks_pending, callbacks, 3119 sizeof(hif_state->msg_callbacks_pending)); 3120 3121 } 3122 3123 static int hif_completion_thread_startup_by_ceid(struct HIF_CE_state *hif_state, 3124 int pipe_num) 3125 { 3126 struct CE_attr attr; 3127 struct hif_softc *scn = HIF_GET_SOFTC(hif_state); 3128 struct hif_msg_callbacks *hif_msg_callbacks = 3129 &hif_state->msg_callbacks_current; 3130 struct HIF_CE_pipe_info *pipe_info; 3131 struct CE_state *ce_state; 3132 3133 if (pipe_num >= CE_COUNT_MAX) 3134 return -EINVAL; 3135 3136 pipe_info = &hif_state->pipe_info[pipe_num]; 3137 ce_state = scn->ce_id_to_state[pipe_num]; 3138 3139 if (!hif_msg_callbacks || 3140 !hif_msg_callbacks->rxCompletionHandler || 3141 !hif_msg_callbacks->txCompletionHandler) { 3142 hif_err("%s: no completion handler registered", __func__); 3143 return -EFAULT; 3144 } 3145 3146 attr = hif_state->host_ce_config[pipe_num]; 3147 if (attr.src_nentries) { 3148 /* pipe used to send to target */ 3149 hif_debug("%s: pipe_num:%d pipe_info:0x%pK\n", 3150 __func__, pipe_num, pipe_info); 3151 ce_send_cb_register(pipe_info->ce_hdl, 3152 hif_pci_ce_send_done, pipe_info, 3153 attr.flags & CE_ATTR_DISABLE_INTR); 3154 pipe_info->num_sends_allowed = attr.src_nentries - 1; 3155 } 3156 if (attr.dest_nentries) { 3157 hif_debug("%s: pipe_num:%d pipe_info:0x%pK\n", 3158 __func__, pipe_num, pipe_info); 3159 /* pipe used to receive from target */ 3160 ce_recv_cb_register(pipe_info->ce_hdl, 3161 hif_pci_ce_recv_data, pipe_info, 3162 attr.flags & CE_ATTR_DISABLE_INTR); 3163 } 3164 3165 if (attr.src_nentries) 3166 qdf_spinlock_create(&pipe_info->completion_freeq_lock); 3167 3168 if (!(ce_state->attr_flags & CE_ATTR_INIT_ON_DEMAND)) 3169 qdf_mem_copy(&pipe_info->pipe_callbacks, hif_msg_callbacks, 3170 sizeof(pipe_info->pipe_callbacks)); 3171 3172 return 0; 3173 } 3174 3175 static int hif_completion_thread_startup(struct HIF_CE_state *hif_state) 3176 { 3177 struct CE_handle *ce_diag = hif_state->ce_diag; 3178 int pipe_num, ret; 3179 struct hif_softc *scn = HIF_GET_SOFTC(hif_state); 3180 3181 /* daemonize("hif_compl_thread"); */ 3182 3183 if (scn->ce_count == 0) { 3184 hif_err("ce_count is 0"); 3185 return -EINVAL; 3186 } 3187 3188 3189 A_TARGET_ACCESS_LIKELY(scn); 3190 for (pipe_num = 0; pipe_num < scn->ce_count; pipe_num++) { 3191 struct HIF_CE_pipe_info *pipe_info; 3192 3193 pipe_info = &hif_state->pipe_info[pipe_num]; 3194 if (pipe_info->ce_hdl == ce_diag) 3195 continue; /* Handle Diagnostic CE specially */ 3196 3197 ret = hif_completion_thread_startup_by_ceid(hif_state, 3198 pipe_num); 3199 if (ret < 0) 3200 return ret; 3201 3202 } 3203 3204 A_TARGET_ACCESS_UNLIKELY(scn); 3205 return 0; 3206 } 3207 3208 /* 3209 * Install pending msg callbacks. 3210 * 3211 * TBDXXX: This hack is needed because upper layers install msg callbacks 3212 * for use with HTC before BMI is done; yet this HIF implementation 3213 * needs to continue to use BMI msg callbacks. Really, upper layers 3214 * should not register HTC callbacks until AFTER BMI phase. 3215 */ 3216 static void hif_msg_callbacks_install(struct hif_softc *scn) 3217 { 3218 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 3219 3220 qdf_mem_copy(&hif_state->msg_callbacks_current, 3221 &hif_state->msg_callbacks_pending, 3222 sizeof(hif_state->msg_callbacks_pending)); 3223 } 3224 3225 void hif_get_default_pipe(struct hif_opaque_softc *hif_hdl, uint8_t *ULPipe, 3226 uint8_t *DLPipe) 3227 { 3228 int ul_is_polled, dl_is_polled; 3229 3230 (void)hif_map_service_to_pipe(hif_hdl, HTC_CTRL_RSVD_SVC, 3231 ULPipe, DLPipe, &ul_is_polled, &dl_is_polled); 3232 } 3233 3234 /** 3235 * hif_dump_pipe_debug_count() - Log error count 3236 * @scn: hif_softc pointer. 3237 * 3238 * Output the pipe error counts of each pipe to log file 3239 * 3240 * Return: N/A 3241 */ 3242 void hif_dump_pipe_debug_count(struct hif_softc *scn) 3243 { 3244 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 3245 int pipe_num; 3246 3247 if (!hif_state) { 3248 hif_err("hif_state is NULL"); 3249 return; 3250 } 3251 for (pipe_num = 0; pipe_num < scn->ce_count; pipe_num++) { 3252 struct HIF_CE_pipe_info *pipe_info; 3253 3254 pipe_info = &hif_state->pipe_info[pipe_num]; 3255 3256 if (pipe_info->nbuf_alloc_err_count > 0 || 3257 pipe_info->nbuf_dma_err_count > 0 || 3258 pipe_info->nbuf_ce_enqueue_err_count) 3259 hif_err( 3260 "pipe_id = %d, recv_bufs_needed = %d, nbuf_alloc_err_count = %u, nbuf_dma_err_count = %u, nbuf_ce_enqueue_err_count = %u", 3261 pipe_info->pipe_num, 3262 atomic_read(&pipe_info->recv_bufs_needed), 3263 pipe_info->nbuf_alloc_err_count, 3264 pipe_info->nbuf_dma_err_count, 3265 pipe_info->nbuf_ce_enqueue_err_count); 3266 } 3267 } 3268 3269 static void hif_post_recv_buffers_failure(struct HIF_CE_pipe_info *pipe_info, 3270 void *nbuf, uint32_t *error_cnt, 3271 enum hif_ce_event_type failure_type, 3272 const char *failure_type_string) 3273 { 3274 int bufs_needed_tmp = atomic_inc_return(&pipe_info->recv_bufs_needed); 3275 struct CE_state *CE_state = (struct CE_state *)pipe_info->ce_hdl; 3276 struct hif_softc *scn = HIF_GET_SOFTC(pipe_info->HIF_CE_state); 3277 int ce_id = CE_state->id; 3278 uint32_t error_cnt_tmp; 3279 3280 qdf_spin_lock_bh(&pipe_info->recv_bufs_needed_lock); 3281 error_cnt_tmp = ++(*error_cnt); 3282 qdf_spin_unlock_bh(&pipe_info->recv_bufs_needed_lock); 3283 hif_debug("pipe_num: %d, needed: %d, err_cnt: %u, fail_type: %s", 3284 pipe_info->pipe_num, bufs_needed_tmp, error_cnt_tmp, 3285 failure_type_string); 3286 hif_record_ce_desc_event(scn, ce_id, failure_type, 3287 NULL, nbuf, bufs_needed_tmp, 0); 3288 /* if we fail to allocate the last buffer for an rx pipe, 3289 * there is no trigger to refill the ce and we will 3290 * eventually crash 3291 */ 3292 if (bufs_needed_tmp == CE_state->dest_ring->nentries - 1 || 3293 (ce_srng_based(scn) && 3294 bufs_needed_tmp == CE_state->dest_ring->nentries - 2)) 3295 qdf_sched_work(scn->qdf_dev, &CE_state->oom_allocation_work); 3296 3297 } 3298 3299 3300 3301 3302 QDF_STATUS hif_post_recv_buffers_for_pipe(struct HIF_CE_pipe_info *pipe_info) 3303 { 3304 struct CE_handle *ce_hdl; 3305 qdf_size_t buf_sz; 3306 struct hif_softc *scn = HIF_GET_SOFTC(pipe_info->HIF_CE_state); 3307 QDF_STATUS status; 3308 uint32_t bufs_posted = 0; 3309 unsigned int ce_id; 3310 3311 buf_sz = pipe_info->buf_sz; 3312 if (buf_sz == 0) { 3313 /* Unused Copy Engine */ 3314 return QDF_STATUS_SUCCESS; 3315 } 3316 3317 ce_hdl = pipe_info->ce_hdl; 3318 ce_id = ((struct CE_state *)ce_hdl)->id; 3319 3320 qdf_spin_lock_bh(&pipe_info->recv_bufs_needed_lock); 3321 while (atomic_read(&pipe_info->recv_bufs_needed) > 0) { 3322 qdf_dma_addr_t CE_data; /* CE space buffer address */ 3323 qdf_nbuf_t nbuf; 3324 3325 atomic_dec(&pipe_info->recv_bufs_needed); 3326 qdf_spin_unlock_bh(&pipe_info->recv_bufs_needed_lock); 3327 3328 hif_record_ce_desc_event(scn, ce_id, 3329 HIF_RX_DESC_PRE_NBUF_ALLOC, NULL, NULL, 3330 0, 0); 3331 nbuf = qdf_nbuf_alloc(scn->qdf_dev, buf_sz, 0, 4, false); 3332 if (!nbuf) { 3333 hif_post_recv_buffers_failure(pipe_info, nbuf, 3334 &pipe_info->nbuf_alloc_err_count, 3335 HIF_RX_NBUF_ALLOC_FAILURE, 3336 "HIF_RX_NBUF_ALLOC_FAILURE"); 3337 return QDF_STATUS_E_NOMEM; 3338 } 3339 3340 hif_record_ce_desc_event(scn, ce_id, 3341 HIF_RX_DESC_PRE_NBUF_MAP, NULL, nbuf, 3342 0, 0); 3343 /* 3344 * qdf_nbuf_peek_header(nbuf, &data, &unused); 3345 * CE_data = dma_map_single(dev, data, buf_sz, ); 3346 * DMA_FROM_DEVICE); 3347 */ 3348 status = qdf_nbuf_map_single(scn->qdf_dev, nbuf, 3349 QDF_DMA_FROM_DEVICE); 3350 3351 if (qdf_unlikely(status != QDF_STATUS_SUCCESS)) { 3352 hif_post_recv_buffers_failure(pipe_info, nbuf, 3353 &pipe_info->nbuf_dma_err_count, 3354 HIF_RX_NBUF_MAP_FAILURE, 3355 "HIF_RX_NBUF_MAP_FAILURE"); 3356 qdf_nbuf_free(nbuf); 3357 return status; 3358 } 3359 3360 CE_data = qdf_nbuf_get_frag_paddr(nbuf, 0); 3361 hif_record_ce_desc_event(scn, ce_id, 3362 HIF_RX_DESC_POST_NBUF_MAP, NULL, nbuf, 3363 0, 0); 3364 qdf_mem_dma_sync_single_for_device(scn->qdf_dev, CE_data, 3365 buf_sz, DMA_FROM_DEVICE); 3366 status = ce_recv_buf_enqueue(ce_hdl, (void *)nbuf, CE_data); 3367 if (qdf_unlikely(status != QDF_STATUS_SUCCESS)) { 3368 hif_post_recv_buffers_failure(pipe_info, nbuf, 3369 &pipe_info->nbuf_ce_enqueue_err_count, 3370 HIF_RX_NBUF_ENQUEUE_FAILURE, 3371 "HIF_RX_NBUF_ENQUEUE_FAILURE"); 3372 3373 qdf_nbuf_unmap_single(scn->qdf_dev, nbuf, 3374 QDF_DMA_FROM_DEVICE); 3375 qdf_nbuf_free(nbuf); 3376 return status; 3377 } 3378 3379 qdf_spin_lock_bh(&pipe_info->recv_bufs_needed_lock); 3380 bufs_posted++; 3381 } 3382 pipe_info->nbuf_alloc_err_count = 3383 (pipe_info->nbuf_alloc_err_count > bufs_posted) ? 3384 pipe_info->nbuf_alloc_err_count - bufs_posted : 0; 3385 pipe_info->nbuf_dma_err_count = 3386 (pipe_info->nbuf_dma_err_count > bufs_posted) ? 3387 pipe_info->nbuf_dma_err_count - bufs_posted : 0; 3388 pipe_info->nbuf_ce_enqueue_err_count = 3389 (pipe_info->nbuf_ce_enqueue_err_count > bufs_posted) ? 3390 pipe_info->nbuf_ce_enqueue_err_count - bufs_posted : 0; 3391 3392 qdf_spin_unlock_bh(&pipe_info->recv_bufs_needed_lock); 3393 3394 return QDF_STATUS_SUCCESS; 3395 } 3396 3397 /* 3398 * Try to post all desired receive buffers for all pipes. 3399 * Returns 0 for non fastpath rx copy engine as 3400 * oom_allocation_work will be scheduled to recover any 3401 * failures, non-zero if unable to completely replenish 3402 * receive buffers for fastpath rx Copy engine. 3403 */ 3404 static QDF_STATUS hif_post_recv_buffers(struct hif_softc *scn) 3405 { 3406 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 3407 int pipe_num; 3408 struct CE_state *ce_state = NULL; 3409 QDF_STATUS qdf_status; 3410 3411 A_TARGET_ACCESS_LIKELY(scn); 3412 for (pipe_num = 0; pipe_num < scn->ce_count; pipe_num++) { 3413 struct HIF_CE_pipe_info *pipe_info; 3414 3415 ce_state = scn->ce_id_to_state[pipe_num]; 3416 pipe_info = &hif_state->pipe_info[pipe_num]; 3417 3418 if (!ce_state) 3419 continue; 3420 3421 /* Do not init dynamic CEs, during initial load */ 3422 if (ce_state->attr_flags & CE_ATTR_INIT_ON_DEMAND) 3423 continue; 3424 3425 if (hif_is_nss_wifi_enabled(scn) && 3426 ce_state && (ce_state->htt_rx_data)) 3427 continue; 3428 3429 qdf_status = hif_post_recv_buffers_for_pipe(pipe_info); 3430 if (!QDF_IS_STATUS_SUCCESS(qdf_status) && ce_state && 3431 ce_state->htt_rx_data && 3432 scn->fastpath_mode_on) { 3433 A_TARGET_ACCESS_UNLIKELY(scn); 3434 return qdf_status; 3435 } 3436 } 3437 3438 A_TARGET_ACCESS_UNLIKELY(scn); 3439 3440 return QDF_STATUS_SUCCESS; 3441 } 3442 3443 QDF_STATUS hif_start(struct hif_opaque_softc *hif_ctx) 3444 { 3445 struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); 3446 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 3447 QDF_STATUS qdf_status = QDF_STATUS_SUCCESS; 3448 3449 hif_update_fastpath_recv_bufs_cnt(scn); 3450 3451 hif_msg_callbacks_install(scn); 3452 3453 if (hif_completion_thread_startup(hif_state)) 3454 return QDF_STATUS_E_FAILURE; 3455 3456 /* enable buffer cleanup */ 3457 hif_state->started = true; 3458 3459 /* Post buffers once to start things off. */ 3460 qdf_status = hif_post_recv_buffers(scn); 3461 if (!QDF_IS_STATUS_SUCCESS(qdf_status)) { 3462 /* cleanup is done in hif_ce_disable */ 3463 hif_err("Failed to post buffers"); 3464 return qdf_status; 3465 } 3466 3467 return qdf_status; 3468 } 3469 3470 static void hif_recv_buffer_cleanup_on_pipe(struct HIF_CE_pipe_info *pipe_info) 3471 { 3472 struct hif_softc *scn; 3473 struct CE_handle *ce_hdl; 3474 uint32_t buf_sz; 3475 struct HIF_CE_state *hif_state; 3476 qdf_nbuf_t netbuf; 3477 qdf_dma_addr_t CE_data; 3478 void *per_CE_context; 3479 3480 buf_sz = pipe_info->buf_sz; 3481 /* Unused Copy Engine */ 3482 if (buf_sz == 0) 3483 return; 3484 3485 3486 hif_state = pipe_info->HIF_CE_state; 3487 if (!hif_state->started) 3488 return; 3489 3490 scn = HIF_GET_SOFTC(hif_state); 3491 ce_hdl = pipe_info->ce_hdl; 3492 3493 if (!scn->qdf_dev) 3494 return; 3495 while (ce_revoke_recv_next 3496 (ce_hdl, &per_CE_context, (void **)&netbuf, 3497 &CE_data) == QDF_STATUS_SUCCESS) { 3498 if (netbuf) { 3499 qdf_nbuf_unmap_single(scn->qdf_dev, netbuf, 3500 QDF_DMA_FROM_DEVICE); 3501 qdf_nbuf_free(netbuf); 3502 } 3503 } 3504 } 3505 3506 static void hif_send_buffer_cleanup_on_pipe(struct HIF_CE_pipe_info *pipe_info) 3507 { 3508 struct CE_handle *ce_hdl; 3509 struct HIF_CE_state *hif_state; 3510 struct hif_softc *scn; 3511 qdf_nbuf_t netbuf; 3512 void *per_CE_context; 3513 qdf_dma_addr_t CE_data; 3514 unsigned int nbytes; 3515 unsigned int id; 3516 uint32_t buf_sz; 3517 uint32_t toeplitz_hash_result; 3518 3519 buf_sz = pipe_info->buf_sz; 3520 if (buf_sz == 0) { 3521 /* Unused Copy Engine */ 3522 return; 3523 } 3524 3525 hif_state = pipe_info->HIF_CE_state; 3526 if (!hif_state->started) { 3527 return; 3528 } 3529 3530 scn = HIF_GET_SOFTC(hif_state); 3531 3532 ce_hdl = pipe_info->ce_hdl; 3533 3534 while (ce_cancel_send_next 3535 (ce_hdl, &per_CE_context, 3536 (void **)&netbuf, &CE_data, &nbytes, 3537 &id, &toeplitz_hash_result) == QDF_STATUS_SUCCESS) { 3538 if (netbuf != CE_SENDLIST_ITEM_CTXT) { 3539 /* 3540 * Packets enqueued by htt_h2t_ver_req_msg() and 3541 * htt_h2t_rx_ring_cfg_msg_ll() have already been 3542 * freed in htt_htc_misc_pkt_pool_free() in 3543 * wlantl_close(), so do not free them here again 3544 * by checking whether it's the endpoint 3545 * which they are queued in. 3546 */ 3547 if (id == scn->htc_htt_tx_endpoint) 3548 return; 3549 /* Indicate the completion to higher 3550 * layer to free the buffer 3551 */ 3552 if (pipe_info->pipe_callbacks.txCompletionHandler) 3553 pipe_info->pipe_callbacks. 3554 txCompletionHandler(pipe_info-> 3555 pipe_callbacks.Context, 3556 netbuf, id, toeplitz_hash_result); 3557 } 3558 } 3559 } 3560 3561 /* 3562 * Cleanup residual buffers for device shutdown: 3563 * buffers that were enqueued for receive 3564 * buffers that were to be sent 3565 * Note: Buffers that had completed but which were 3566 * not yet processed are on a completion queue. They 3567 * are handled when the completion thread shuts down. 3568 */ 3569 static void hif_buffer_cleanup(struct HIF_CE_state *hif_state) 3570 { 3571 int pipe_num; 3572 struct hif_softc *scn = HIF_GET_SOFTC(hif_state); 3573 struct CE_state *ce_state; 3574 3575 for (pipe_num = 0; pipe_num < scn->ce_count; pipe_num++) { 3576 struct HIF_CE_pipe_info *pipe_info; 3577 3578 ce_state = scn->ce_id_to_state[pipe_num]; 3579 if (hif_is_nss_wifi_enabled(scn) && ce_state && 3580 ((ce_state->htt_tx_data) || 3581 (ce_state->htt_rx_data))) { 3582 continue; 3583 } 3584 3585 pipe_info = &hif_state->pipe_info[pipe_num]; 3586 hif_recv_buffer_cleanup_on_pipe(pipe_info); 3587 hif_send_buffer_cleanup_on_pipe(pipe_info); 3588 } 3589 } 3590 3591 void hif_flush_surprise_remove(struct hif_opaque_softc *hif_ctx) 3592 { 3593 struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); 3594 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 3595 3596 hif_buffer_cleanup(hif_state); 3597 } 3598 3599 static void hif_destroy_oom_work(struct hif_softc *scn) 3600 { 3601 struct CE_state *ce_state; 3602 int ce_id; 3603 3604 for (ce_id = 0; ce_id < scn->ce_count; ce_id++) { 3605 ce_state = scn->ce_id_to_state[ce_id]; 3606 if (ce_state) 3607 qdf_destroy_work(scn->qdf_dev, 3608 &ce_state->oom_allocation_work); 3609 } 3610 } 3611 3612 void hif_ce_stop(struct hif_softc *scn) 3613 { 3614 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 3615 int pipe_num; 3616 3617 /* 3618 * before cleaning up any memory, ensure irq & 3619 * bottom half contexts will not be re-entered 3620 */ 3621 hif_disable_isr(&scn->osc); 3622 hif_destroy_oom_work(scn); 3623 scn->hif_init_done = false; 3624 3625 /* 3626 * At this point, asynchronous threads are stopped, 3627 * The Target should not DMA nor interrupt, Host code may 3628 * not initiate anything more. So we just need to clean 3629 * up Host-side state. 3630 */ 3631 3632 if (scn->athdiag_procfs_inited) { 3633 athdiag_procfs_remove(); 3634 scn->athdiag_procfs_inited = false; 3635 } 3636 3637 hif_buffer_cleanup(hif_state); 3638 3639 for (pipe_num = 0; pipe_num < scn->ce_count; pipe_num++) { 3640 struct HIF_CE_pipe_info *pipe_info; 3641 struct CE_attr attr; 3642 struct CE_handle *ce_diag = hif_state->ce_diag; 3643 3644 pipe_info = &hif_state->pipe_info[pipe_num]; 3645 if (pipe_info->ce_hdl) { 3646 if (pipe_info->ce_hdl != ce_diag && 3647 hif_state->started) { 3648 attr = hif_state->host_ce_config[pipe_num]; 3649 if (attr.src_nentries) 3650 qdf_spinlock_destroy(&pipe_info-> 3651 completion_freeq_lock); 3652 } 3653 ce_fini(pipe_info->ce_hdl); 3654 pipe_info->ce_hdl = NULL; 3655 pipe_info->buf_sz = 0; 3656 qdf_spinlock_destroy(&pipe_info->recv_bufs_needed_lock); 3657 } 3658 } 3659 3660 if (hif_state->sleep_timer_init) { 3661 qdf_timer_stop(&hif_state->sleep_timer); 3662 qdf_timer_free(&hif_state->sleep_timer); 3663 hif_state->sleep_timer_init = false; 3664 } 3665 3666 hif_state->started = false; 3667 } 3668 3669 static void hif_get_shadow_reg_cfg(struct hif_softc *scn, 3670 struct shadow_reg_cfg 3671 **target_shadow_reg_cfg_ret, 3672 uint32_t *shadow_cfg_sz_ret) 3673 { 3674 if (target_shadow_reg_cfg_ret) 3675 *target_shadow_reg_cfg_ret = target_shadow_reg_cfg; 3676 if (shadow_cfg_sz_ret) 3677 *shadow_cfg_sz_ret = shadow_cfg_sz; 3678 } 3679 3680 /** 3681 * hif_get_target_ce_config() - get copy engine configuration 3682 * @scn: HIF context 3683 * @target_ce_config_ret: basic copy engine configuration 3684 * @target_ce_config_sz_ret: size of the basic configuration in bytes 3685 * @target_service_to_ce_map_ret: service mapping for the copy engines 3686 * @target_service_to_ce_map_sz_ret: size of the mapping in bytes 3687 * @target_shadow_reg_cfg_ret: shadow register configuration 3688 * @shadow_cfg_sz_ret: size of the shadow register configuration in bytes 3689 * 3690 * providing accessor to these values outside of this file. 3691 * currently these are stored in static pointers to const sections. 3692 * there are multiple configurations that are selected from at compile time. 3693 * Runtime selection would need to consider mode, target type and bus type. 3694 * 3695 * Return: return by parameter. 3696 */ 3697 void hif_get_target_ce_config(struct hif_softc *scn, 3698 struct CE_pipe_config **target_ce_config_ret, 3699 uint32_t *target_ce_config_sz_ret, 3700 struct service_to_pipe **target_service_to_ce_map_ret, 3701 uint32_t *target_service_to_ce_map_sz_ret, 3702 struct shadow_reg_cfg **target_shadow_reg_cfg_ret, 3703 uint32_t *shadow_cfg_sz_ret) 3704 { 3705 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 3706 3707 *target_ce_config_ret = hif_state->target_ce_config; 3708 *target_ce_config_sz_ret = hif_state->target_ce_config_sz; 3709 3710 hif_select_service_to_pipe_map(scn, target_service_to_ce_map_ret, 3711 target_service_to_ce_map_sz_ret); 3712 hif_get_shadow_reg_cfg(scn, target_shadow_reg_cfg_ret, 3713 shadow_cfg_sz_ret); 3714 } 3715 3716 #ifdef CONFIG_SHADOW_V3 3717 static void hif_print_hal_shadow_register_cfg(struct pld_wlan_enable_cfg *cfg) 3718 { 3719 int i; 3720 3721 hif_err("v3: num_config %d", cfg->num_shadow_reg_v3_cfg); 3722 3723 for (i = 0; i < cfg->num_shadow_reg_v3_cfg; i++) { 3724 hif_err("i %d, val %x", i, cfg->shadow_reg_v3_cfg[i].addr); 3725 } 3726 } 3727 3728 #elif defined(CONFIG_SHADOW_V2) 3729 static void hif_print_hal_shadow_register_cfg(struct pld_wlan_enable_cfg *cfg) 3730 { 3731 int i; 3732 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 3733 "%s: num_config %d", __func__, cfg->num_shadow_reg_v2_cfg); 3734 3735 for (i = 0; i < cfg->num_shadow_reg_v2_cfg; i++) { 3736 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_INFO, 3737 "%s: i %d, val %x", __func__, i, 3738 cfg->shadow_reg_v2_cfg[i].addr); 3739 } 3740 } 3741 3742 #else 3743 static void hif_print_hal_shadow_register_cfg(struct pld_wlan_enable_cfg *cfg) 3744 { 3745 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 3746 "%s: CONFIG_SHADOW V2/V3 not defined", __func__); 3747 } 3748 #endif 3749 3750 #ifdef ADRASTEA_RRI_ON_DDR 3751 /** 3752 * hif_get_src_ring_read_index(): Called to get the SRRI 3753 * 3754 * @scn: hif_softc pointer 3755 * @CE_ctrl_addr: base address of the CE whose RRI is to be read 3756 * 3757 * This function returns the SRRI to the caller. For CEs that 3758 * dont have interrupts enabled, we look at the DDR based SRRI 3759 * 3760 * Return: SRRI 3761 */ 3762 inline unsigned int hif_get_src_ring_read_index(struct hif_softc *scn, 3763 uint32_t CE_ctrl_addr) 3764 { 3765 struct CE_attr attr; 3766 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 3767 3768 attr = hif_state->host_ce_config[COPY_ENGINE_ID(CE_ctrl_addr)]; 3769 if (attr.flags & CE_ATTR_DISABLE_INTR) { 3770 return CE_SRC_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr); 3771 } else { 3772 if (TARGET_REGISTER_ACCESS_ALLOWED(scn)) 3773 return A_TARGET_READ(scn, 3774 (CE_ctrl_addr) + CURRENT_SRRI_ADDRESS); 3775 else 3776 return CE_SRC_RING_READ_IDX_GET_FROM_DDR(scn, 3777 CE_ctrl_addr); 3778 } 3779 } 3780 3781 /** 3782 * hif_get_dst_ring_read_index(): Called to get the DRRI 3783 * 3784 * @scn: hif_softc pointer 3785 * @CE_ctrl_addr: base address of the CE whose RRI is to be read 3786 * 3787 * This function returns the DRRI to the caller. For CEs that 3788 * dont have interrupts enabled, we look at the DDR based DRRI 3789 * 3790 * Return: DRRI 3791 */ 3792 inline unsigned int hif_get_dst_ring_read_index(struct hif_softc *scn, 3793 uint32_t CE_ctrl_addr) 3794 { 3795 struct CE_attr attr; 3796 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 3797 3798 attr = hif_state->host_ce_config[COPY_ENGINE_ID(CE_ctrl_addr)]; 3799 3800 if (attr.flags & CE_ATTR_DISABLE_INTR) { 3801 return CE_DEST_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr); 3802 } else { 3803 if (TARGET_REGISTER_ACCESS_ALLOWED(scn)) 3804 return A_TARGET_READ(scn, 3805 (CE_ctrl_addr) + CURRENT_DRRI_ADDRESS); 3806 else 3807 return CE_DEST_RING_READ_IDX_GET_FROM_DDR(scn, 3808 CE_ctrl_addr); 3809 } 3810 } 3811 3812 /** 3813 * hif_alloc_rri_on_ddr() - Allocate memory for rri on ddr 3814 * @scn: hif_softc pointer 3815 * 3816 * Return: qdf status 3817 */ 3818 static inline QDF_STATUS hif_alloc_rri_on_ddr(struct hif_softc *scn) 3819 { 3820 qdf_dma_addr_t paddr_rri_on_ddr = 0; 3821 3822 scn->vaddr_rri_on_ddr = 3823 (uint32_t *)qdf_mem_alloc_consistent(scn->qdf_dev, 3824 scn->qdf_dev->dev, (CE_COUNT * sizeof(uint32_t)), 3825 &paddr_rri_on_ddr); 3826 3827 if (!scn->vaddr_rri_on_ddr) { 3828 hif_err("dmaable page alloc fail"); 3829 return QDF_STATUS_E_NOMEM; 3830 } 3831 3832 scn->paddr_rri_on_ddr = paddr_rri_on_ddr; 3833 3834 qdf_mem_zero(scn->vaddr_rri_on_ddr, CE_COUNT * sizeof(uint32_t)); 3835 3836 return QDF_STATUS_SUCCESS; 3837 } 3838 #endif 3839 3840 #if (!defined(QCN7605_SUPPORT)) && defined(ADRASTEA_RRI_ON_DDR) 3841 /** 3842 * hif_config_rri_on_ddr(): Configure the RRI on DDR mechanism 3843 * 3844 * @scn: hif_softc pointer 3845 * 3846 * This function allocates non cached memory on ddr and sends 3847 * the physical address of this memory to the CE hardware. The 3848 * hardware updates the RRI on this particular location. 3849 * 3850 * Return: None 3851 */ 3852 static inline void hif_config_rri_on_ddr(struct hif_softc *scn) 3853 { 3854 unsigned int i; 3855 uint32_t high_paddr, low_paddr; 3856 3857 if (hif_alloc_rri_on_ddr(scn) != QDF_STATUS_SUCCESS) 3858 return; 3859 3860 low_paddr = BITS0_TO_31(scn->paddr_rri_on_ddr); 3861 high_paddr = BITS32_TO_35(scn->paddr_rri_on_ddr); 3862 3863 hif_debug("using srri and drri from DDR"); 3864 3865 WRITE_CE_DDR_ADDRESS_FOR_RRI_LOW(scn, low_paddr); 3866 WRITE_CE_DDR_ADDRESS_FOR_RRI_HIGH(scn, high_paddr); 3867 3868 for (i = 0; i < CE_COUNT; i++) 3869 CE_IDX_UPD_EN_SET(scn, CE_BASE_ADDRESS(i)); 3870 } 3871 #else 3872 /** 3873 * hif_config_rri_on_ddr(): Configure the RRI on DDR mechanism 3874 * 3875 * @scn: hif_softc pointer 3876 * 3877 * This is a dummy implementation for platforms that don't 3878 * support this functionality. 3879 * 3880 * Return: None 3881 */ 3882 static inline void hif_config_rri_on_ddr(struct hif_softc *scn) 3883 { 3884 } 3885 #endif 3886 3887 /** 3888 * hif_update_rri_over_ddr_config() - update rri_over_ddr config for 3889 * QMI command 3890 * @scn: hif context 3891 * @cfg: wlan enable config 3892 * 3893 * In case of Genoa, rri_over_ddr memory configuration is passed 3894 * to firmware through QMI configure command. 3895 */ 3896 #if defined(QCN7605_SUPPORT) && defined(ADRASTEA_RRI_ON_DDR) 3897 static void hif_update_rri_over_ddr_config(struct hif_softc *scn, 3898 struct pld_wlan_enable_cfg *cfg) 3899 { 3900 if (hif_alloc_rri_on_ddr(scn) != QDF_STATUS_SUCCESS) 3901 return; 3902 3903 cfg->rri_over_ddr_cfg_valid = true; 3904 cfg->rri_over_ddr_cfg.base_addr_low = 3905 BITS0_TO_31(scn->paddr_rri_on_ddr); 3906 cfg->rri_over_ddr_cfg.base_addr_high = 3907 BITS32_TO_35(scn->paddr_rri_on_ddr); 3908 } 3909 #else 3910 static void hif_update_rri_over_ddr_config(struct hif_softc *scn, 3911 struct pld_wlan_enable_cfg *cfg) 3912 { 3913 } 3914 #endif 3915 3916 /** 3917 * hif_wlan_enable(): call the platform driver to enable wlan 3918 * @scn: HIF Context 3919 * 3920 * This function passes the con_mode and CE configuration to 3921 * platform driver to enable wlan. 3922 * 3923 * Return: linux error code 3924 */ 3925 int hif_wlan_enable(struct hif_softc *scn) 3926 { 3927 struct hif_opaque_softc *hif_hdl = GET_HIF_OPAQUE_HDL(scn); 3928 struct hif_target_info *tgt_info = hif_get_target_info_handle(hif_hdl); 3929 struct pld_wlan_enable_cfg cfg = { 0 }; 3930 enum pld_driver_mode mode; 3931 uint32_t con_mode = hif_get_conparam(scn); 3932 3933 hif_get_target_ce_config(scn, 3934 (struct CE_pipe_config **)&cfg.ce_tgt_cfg, 3935 &cfg.num_ce_tgt_cfg, 3936 (struct service_to_pipe **)&cfg.ce_svc_cfg, 3937 &cfg.num_ce_svc_pipe_cfg, 3938 (struct shadow_reg_cfg **)&cfg.shadow_reg_cfg, 3939 &cfg.num_shadow_reg_cfg); 3940 3941 /* translate from structure size to array size */ 3942 cfg.num_ce_tgt_cfg /= sizeof(struct CE_pipe_config); 3943 cfg.num_ce_svc_pipe_cfg /= sizeof(struct service_to_pipe); 3944 cfg.num_shadow_reg_cfg /= sizeof(struct shadow_reg_cfg); 3945 3946 switch (tgt_info->target_type) { 3947 case TARGET_TYPE_KIWI: 3948 case TARGET_TYPE_MANGO: 3949 hif_prepare_hal_shadow_reg_cfg_v3(scn, &cfg); 3950 break; 3951 default: 3952 hif_prepare_hal_shadow_register_cfg(scn, 3953 &cfg.shadow_reg_v2_cfg, 3954 &cfg.num_shadow_reg_v2_cfg); 3955 break; 3956 } 3957 3958 hif_print_hal_shadow_register_cfg(&cfg); 3959 3960 hif_update_rri_over_ddr_config(scn, &cfg); 3961 3962 if (QDF_GLOBAL_FTM_MODE == con_mode) 3963 mode = PLD_FTM; 3964 else if (QDF_GLOBAL_COLDBOOT_CALIB_MODE == con_mode) 3965 mode = PLD_COLDBOOT_CALIBRATION; 3966 else if (QDF_GLOBAL_FTM_COLDBOOT_CALIB_MODE == con_mode) 3967 mode = PLD_FTM_COLDBOOT_CALIBRATION; 3968 else if (QDF_IS_EPPING_ENABLED(con_mode)) 3969 mode = PLD_EPPING; 3970 else 3971 mode = PLD_MISSION; 3972 3973 if (BYPASS_QMI) 3974 return 0; 3975 else 3976 return pld_wlan_enable(scn->qdf_dev->dev, &cfg, mode); 3977 } 3978 3979 #ifdef WLAN_FEATURE_EPPING 3980 3981 #define CE_EPPING_USES_IRQ true 3982 3983 void hif_ce_prepare_epping_config(struct hif_softc *scn, 3984 struct HIF_CE_state *hif_state) 3985 { 3986 if (CE_EPPING_USES_IRQ) 3987 hif_state->host_ce_config = host_ce_config_wlan_epping_irq; 3988 else 3989 hif_state->host_ce_config = host_ce_config_wlan_epping_poll; 3990 hif_state->target_ce_config = target_ce_config_wlan_epping; 3991 hif_state->target_ce_config_sz = sizeof(target_ce_config_wlan_epping); 3992 target_shadow_reg_cfg = target_shadow_reg_cfg_epping; 3993 shadow_cfg_sz = sizeof(target_shadow_reg_cfg_epping); 3994 scn->ce_count = EPPING_HOST_CE_COUNT; 3995 } 3996 #endif 3997 3998 #ifdef QCN7605_SUPPORT 3999 static inline 4000 void hif_set_ce_config_qcn7605(struct hif_softc *scn, 4001 struct HIF_CE_state *hif_state) 4002 { 4003 hif_state->host_ce_config = host_ce_config_wlan_qcn7605; 4004 hif_state->target_ce_config = target_ce_config_wlan_qcn7605; 4005 hif_state->target_ce_config_sz = 4006 sizeof(target_ce_config_wlan_qcn7605); 4007 target_shadow_reg_cfg = target_shadow_reg_cfg_map_qcn7605; 4008 shadow_cfg_sz = sizeof(target_shadow_reg_cfg_map_qcn7605); 4009 scn->ce_count = QCN7605_CE_COUNT; 4010 } 4011 #else 4012 static inline 4013 void hif_set_ce_config_qcn7605(struct hif_softc *scn, 4014 struct HIF_CE_state *hif_state) 4015 { 4016 hif_err("QCN7605 not supported"); 4017 } 4018 #endif 4019 4020 #ifdef CE_SVC_CMN_INIT 4021 #ifdef QCA_WIFI_SUPPORT_SRNG 4022 static inline void hif_ce_service_init(void) 4023 { 4024 ce_service_srng_init(); 4025 } 4026 #else 4027 static inline void hif_ce_service_init(void) 4028 { 4029 ce_service_legacy_init(); 4030 } 4031 #endif 4032 #else 4033 static inline void hif_ce_service_init(void) 4034 { 4035 } 4036 #endif 4037 4038 #ifdef FEATURE_DIRECT_LINK 4039 /** 4040 * hif_ce_select_config_kiwi() - Select the host and target CE 4041 * configuration for Kiwi 4042 * @hif_state: HIF CE context 4043 * 4044 * Return: None 4045 */ 4046 static inline 4047 void hif_ce_select_config_kiwi(struct HIF_CE_state *hif_state) 4048 { 4049 struct hif_softc *hif_ctx = HIF_GET_SOFTC(hif_state); 4050 4051 if (pld_is_direct_link_supported(hif_ctx->qdf_dev->dev)) { 4052 hif_state->host_ce_config = 4053 host_ce_config_wlan_kiwi_direct_link; 4054 hif_state->target_ce_config = 4055 target_ce_config_wlan_kiwi_direct_link; 4056 hif_state->target_ce_config_sz = 4057 sizeof(target_ce_config_wlan_kiwi_direct_link); 4058 } else { 4059 hif_state->host_ce_config = host_ce_config_wlan_kiwi; 4060 hif_state->target_ce_config = target_ce_config_wlan_kiwi; 4061 hif_state->target_ce_config_sz = 4062 sizeof(target_ce_config_wlan_kiwi); 4063 } 4064 } 4065 #else 4066 static inline 4067 void hif_ce_select_config_kiwi(struct HIF_CE_state *hif_state) 4068 { 4069 hif_state->host_ce_config = host_ce_config_wlan_kiwi; 4070 hif_state->target_ce_config = target_ce_config_wlan_kiwi; 4071 hif_state->target_ce_config_sz = sizeof(target_ce_config_wlan_kiwi); 4072 } 4073 #endif 4074 4075 /** 4076 * hif_ce_prepare_config() - load the correct static tables. 4077 * @scn: hif context 4078 * 4079 * Epping uses different static attribute tables than mission mode. 4080 */ 4081 void hif_ce_prepare_config(struct hif_softc *scn) 4082 { 4083 uint32_t mode = hif_get_conparam(scn); 4084 struct hif_opaque_softc *hif_hdl = GET_HIF_OPAQUE_HDL(scn); 4085 struct hif_target_info *tgt_info = hif_get_target_info_handle(hif_hdl); 4086 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 4087 int ret; 4088 int msi_data_count = 0; 4089 int msi_data_start = 0; 4090 int msi_irq_start = 0; 4091 4092 hif_ce_service_init(); 4093 hif_state->ce_services = ce_services_attach(scn); 4094 4095 ret = pld_get_user_msi_assignment(scn->qdf_dev->dev, "CE", 4096 &msi_data_count, &msi_data_start, 4097 &msi_irq_start); 4098 4099 scn->ce_count = HOST_CE_COUNT; 4100 scn->int_assignment = &ce_int_context[msi_data_count]; 4101 scn->free_irq_done = false; 4102 /* if epping is enabled we need to use the epping configuration. */ 4103 if (QDF_IS_EPPING_ENABLED(mode)) { 4104 hif_ce_prepare_epping_config(scn, hif_state); 4105 return; 4106 } 4107 4108 switch (tgt_info->target_type) { 4109 default: 4110 hif_state->host_ce_config = host_ce_config_wlan; 4111 hif_state->target_ce_config = target_ce_config_wlan; 4112 hif_state->target_ce_config_sz = sizeof(target_ce_config_wlan); 4113 break; 4114 case TARGET_TYPE_QCN7605: 4115 hif_set_ce_config_qcn7605(scn, hif_state); 4116 break; 4117 case TARGET_TYPE_AR900B: 4118 case TARGET_TYPE_QCA9984: 4119 case TARGET_TYPE_QCA9888: 4120 if (hif_is_attribute_set(scn, HIF_LOWDESC_CE_NO_PKTLOG_CFG)) { 4121 hif_state->host_ce_config = 4122 host_lowdesc_ce_cfg_wlan_ar900b_nopktlog; 4123 } else if (hif_is_attribute_set(scn, HIF_LOWDESC_CE_CFG)) { 4124 hif_state->host_ce_config = 4125 host_lowdesc_ce_cfg_wlan_ar900b; 4126 } else { 4127 hif_state->host_ce_config = host_ce_config_wlan_ar900b; 4128 } 4129 4130 hif_state->target_ce_config = target_ce_config_wlan_ar900b; 4131 hif_state->target_ce_config_sz = 4132 sizeof(target_ce_config_wlan_ar900b); 4133 4134 break; 4135 4136 case TARGET_TYPE_AR9888: 4137 case TARGET_TYPE_AR9888V2: 4138 if (hif_is_attribute_set(scn, HIF_LOWDESC_CE_CFG)) { 4139 hif_state->host_ce_config = host_lowdesc_ce_cfg_wlan_ar9888; 4140 } else { 4141 hif_state->host_ce_config = host_ce_config_wlan_ar9888; 4142 } 4143 4144 hif_state->target_ce_config = target_ce_config_wlan_ar9888; 4145 hif_state->target_ce_config_sz = 4146 sizeof(target_ce_config_wlan_ar9888); 4147 4148 break; 4149 4150 case TARGET_TYPE_QCA8074: 4151 case TARGET_TYPE_QCA8074V2: 4152 case TARGET_TYPE_QCA6018: 4153 if (scn->bus_type == QDF_BUS_TYPE_PCI) { 4154 hif_state->host_ce_config = 4155 host_ce_config_wlan_qca8074_pci; 4156 hif_state->target_ce_config = 4157 target_ce_config_wlan_qca8074_pci; 4158 hif_state->target_ce_config_sz = 4159 sizeof(target_ce_config_wlan_qca8074_pci); 4160 } else { 4161 hif_state->host_ce_config = host_ce_config_wlan_qca8074; 4162 hif_state->target_ce_config = 4163 target_ce_config_wlan_qca8074; 4164 hif_state->target_ce_config_sz = 4165 sizeof(target_ce_config_wlan_qca8074); 4166 } 4167 break; 4168 case TARGET_TYPE_QCA6290: 4169 hif_state->host_ce_config = host_ce_config_wlan_qca6290; 4170 hif_state->target_ce_config = target_ce_config_wlan_qca6290; 4171 hif_state->target_ce_config_sz = 4172 sizeof(target_ce_config_wlan_qca6290); 4173 4174 scn->ce_count = QCA_6290_CE_COUNT; 4175 break; 4176 case TARGET_TYPE_QCN9000: 4177 hif_state->host_ce_config = host_ce_config_wlan_qcn9000; 4178 hif_state->target_ce_config = target_ce_config_wlan_qcn9000; 4179 hif_state->target_ce_config_sz = 4180 sizeof(target_ce_config_wlan_qcn9000); 4181 scn->ce_count = QCN_9000_CE_COUNT; 4182 scn->ini_cfg.disable_wake_irq = 1; 4183 break; 4184 case TARGET_TYPE_QCN9224: 4185 hif_set_ce_config_qcn9224(scn, hif_state); 4186 break; 4187 case TARGET_TYPE_QCA5332: 4188 hif_state->host_ce_config = host_ce_config_wlan_qca5332; 4189 hif_state->target_ce_config = target_ce_config_wlan_qca5332; 4190 hif_state->target_ce_config_sz = 4191 sizeof(target_ce_config_wlan_qca5332); 4192 scn->ce_count = QCA_5332_CE_COUNT; 4193 break; 4194 case TARGET_TYPE_QCN6122: 4195 hif_state->host_ce_config = host_ce_config_wlan_qcn6122; 4196 hif_state->target_ce_config = target_ce_config_wlan_qcn6122; 4197 hif_state->target_ce_config_sz = 4198 sizeof(target_ce_config_wlan_qcn6122); 4199 scn->ce_count = QCN_6122_CE_COUNT; 4200 scn->ini_cfg.disable_wake_irq = 1; 4201 break; 4202 case TARGET_TYPE_QCN9160: 4203 hif_state->host_ce_config = host_ce_config_wlan_qcn9160; 4204 hif_state->target_ce_config = target_ce_config_wlan_qcn9160; 4205 hif_state->target_ce_config_sz = 4206 sizeof(target_ce_config_wlan_qcn9160); 4207 scn->ce_count = QCN_9160_CE_COUNT; 4208 scn->ini_cfg.disable_wake_irq = 1; 4209 break; 4210 case TARGET_TYPE_QCA5018: 4211 hif_state->host_ce_config = host_ce_config_wlan_qca5018; 4212 hif_state->target_ce_config = target_ce_config_wlan_qca5018; 4213 hif_state->target_ce_config_sz = 4214 sizeof(target_ce_config_wlan_qca5018); 4215 scn->ce_count = QCA_5018_CE_COUNT; 4216 break; 4217 case TARGET_TYPE_QCA9574: 4218 hif_state->host_ce_config = host_ce_config_wlan_qca9574; 4219 hif_state->target_ce_config = target_ce_config_wlan_qca9574; 4220 hif_state->target_ce_config_sz = 4221 sizeof(target_ce_config_wlan_qca9574); 4222 break; 4223 case TARGET_TYPE_QCA6390: 4224 hif_state->host_ce_config = host_ce_config_wlan_qca6390; 4225 hif_state->target_ce_config = target_ce_config_wlan_qca6390; 4226 hif_state->target_ce_config_sz = 4227 sizeof(target_ce_config_wlan_qca6390); 4228 4229 scn->ce_count = QCA_6390_CE_COUNT; 4230 break; 4231 case TARGET_TYPE_QCA6490: 4232 hif_state->host_ce_config = host_ce_config_wlan_qca6490; 4233 hif_state->target_ce_config = target_ce_config_wlan_qca6490; 4234 hif_state->target_ce_config_sz = 4235 sizeof(target_ce_config_wlan_qca6490); 4236 4237 scn->ce_count = QCA_6490_CE_COUNT; 4238 break; 4239 case TARGET_TYPE_QCA6750: 4240 hif_state->host_ce_config = host_ce_config_wlan_qca6750; 4241 hif_state->target_ce_config = target_ce_config_wlan_qca6750; 4242 hif_state->target_ce_config_sz = 4243 sizeof(target_ce_config_wlan_qca6750); 4244 4245 scn->ce_count = QCA_6750_CE_COUNT; 4246 break; 4247 case TARGET_TYPE_KIWI: 4248 case TARGET_TYPE_MANGO: 4249 hif_ce_select_config_kiwi(hif_state); 4250 scn->ce_count = KIWI_CE_COUNT; 4251 break; 4252 case TARGET_TYPE_ADRASTEA: 4253 if (hif_is_attribute_set(scn, HIF_LOWDESC_CE_NO_PKTLOG_CFG)) { 4254 hif_state->host_ce_config = 4255 host_lowdesc_ce_config_wlan_adrastea_nopktlog; 4256 hif_state->target_ce_config = 4257 target_lowdesc_ce_config_wlan_adrastea_nopktlog; 4258 hif_state->target_ce_config_sz = 4259 sizeof(target_lowdesc_ce_config_wlan_adrastea_nopktlog); 4260 } else { 4261 hif_state->host_ce_config = 4262 host_ce_config_wlan_adrastea; 4263 hif_state->target_ce_config = 4264 target_ce_config_wlan_adrastea; 4265 hif_state->target_ce_config_sz = 4266 sizeof(target_ce_config_wlan_adrastea); 4267 } 4268 break; 4269 4270 } 4271 QDF_BUG(scn->ce_count <= CE_COUNT_MAX); 4272 } 4273 4274 /** 4275 * hif_ce_open() - do ce specific allocations 4276 * @hif_sc: pointer to hif context 4277 * 4278 * return: 0 for success or QDF_STATUS_E_NOMEM 4279 */ 4280 QDF_STATUS hif_ce_open(struct hif_softc *hif_sc) 4281 { 4282 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(hif_sc); 4283 4284 qdf_spinlock_create(&hif_state->irq_reg_lock); 4285 qdf_spinlock_create(&hif_state->keep_awake_lock); 4286 return QDF_STATUS_SUCCESS; 4287 } 4288 4289 /** 4290 * hif_ce_close() - do ce specific free 4291 * @hif_sc: pointer to hif context 4292 */ 4293 void hif_ce_close(struct hif_softc *hif_sc) 4294 { 4295 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(hif_sc); 4296 4297 qdf_spinlock_destroy(&hif_state->irq_reg_lock); 4298 qdf_spinlock_destroy(&hif_state->keep_awake_lock); 4299 } 4300 4301 /** 4302 * hif_unconfig_ce() - ensure resources from hif_config_ce are freed 4303 * @hif_sc: hif context 4304 * 4305 * uses state variables to support cleaning up when hif_config_ce fails. 4306 */ 4307 void hif_unconfig_ce(struct hif_softc *hif_sc) 4308 { 4309 int pipe_num; 4310 struct HIF_CE_pipe_info *pipe_info; 4311 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(hif_sc); 4312 struct hif_opaque_softc *hif_hdl = GET_HIF_OPAQUE_HDL(hif_sc); 4313 4314 for (pipe_num = 0; pipe_num < hif_sc->ce_count; pipe_num++) { 4315 pipe_info = &hif_state->pipe_info[pipe_num]; 4316 if (pipe_info->ce_hdl) { 4317 ce_unregister_irq(hif_state, (1 << pipe_num)); 4318 } 4319 } 4320 deinit_tasklet_workers(hif_hdl); 4321 for (pipe_num = 0; pipe_num < hif_sc->ce_count; pipe_num++) { 4322 pipe_info = &hif_state->pipe_info[pipe_num]; 4323 if (pipe_info->ce_hdl) { 4324 ce_fini(pipe_info->ce_hdl); 4325 pipe_info->ce_hdl = NULL; 4326 pipe_info->buf_sz = 0; 4327 qdf_spinlock_destroy(&pipe_info->recv_bufs_needed_lock); 4328 } 4329 } 4330 if (hif_sc->athdiag_procfs_inited) { 4331 athdiag_procfs_remove(); 4332 hif_sc->athdiag_procfs_inited = false; 4333 } 4334 } 4335 4336 #ifdef CONFIG_BYPASS_QMI 4337 #ifdef QCN7605_SUPPORT 4338 /** 4339 * hif_post_static_buf_to_target() - post static buffer to WLAN FW 4340 * @scn: pointer to HIF structure 4341 * 4342 * WLAN FW needs 2MB memory from DDR when QMI is disabled. 4343 * 4344 * Return: void 4345 */ 4346 static void hif_post_static_buf_to_target(struct hif_softc *scn) 4347 { 4348 phys_addr_t target_pa; 4349 struct ce_info *ce_info_ptr; 4350 uint32_t msi_data_start; 4351 uint32_t msi_data_count; 4352 uint32_t msi_irq_start; 4353 uint32_t i = 0; 4354 int ret; 4355 4356 scn->vaddr_qmi_bypass = 4357 (uint32_t *)qdf_mem_alloc_consistent(scn->qdf_dev, 4358 scn->qdf_dev->dev, 4359 FW_SHARED_MEM, 4360 &target_pa); 4361 if (!scn->vaddr_qmi_bypass) { 4362 hif_err("Memory allocation failed could not post target buf"); 4363 return; 4364 } 4365 4366 scn->paddr_qmi_bypass = target_pa; 4367 4368 ce_info_ptr = (struct ce_info *)scn->vaddr_qmi_bypass; 4369 4370 if (scn->vaddr_rri_on_ddr) { 4371 ce_info_ptr->rri_over_ddr_low_paddr = 4372 BITS0_TO_31(scn->paddr_rri_on_ddr); 4373 ce_info_ptr->rri_over_ddr_high_paddr = 4374 BITS32_TO_35(scn->paddr_rri_on_ddr); 4375 } 4376 4377 ret = pld_get_user_msi_assignment(scn->qdf_dev->dev, "CE", 4378 &msi_data_count, &msi_data_start, 4379 &msi_irq_start); 4380 if (ret) { 4381 hif_err("Failed to get CE msi config"); 4382 return; 4383 } 4384 4385 for (i = 0; i < CE_COUNT_MAX; i++) { 4386 ce_info_ptr->cfg[i].ce_id = i; 4387 ce_info_ptr->cfg[i].msi_vector = 4388 (i % msi_data_count) + msi_irq_start; 4389 } 4390 4391 hif_write32_mb(scn, scn->mem + BYPASS_QMI_TEMP_REGISTER, target_pa); 4392 hif_info("target va %pK target pa %pa", scn->vaddr_qmi_bypass, 4393 &target_pa); 4394 } 4395 4396 /** 4397 * hif_cleanup_static_buf_to_target() - clean up static buffer to WLAN FW 4398 * @scn: pointer to HIF structure 4399 * 4400 * 4401 * Return: void 4402 */ 4403 void hif_cleanup_static_buf_to_target(struct hif_softc *scn) 4404 { 4405 void *target_va = scn->vaddr_qmi_bypass; 4406 phys_addr_t target_pa = scn->paddr_qmi_bypass; 4407 4408 qdf_mem_free_consistent(scn->qdf_dev, scn->qdf_dev->dev, 4409 FW_SHARED_MEM, target_va, 4410 target_pa, 0); 4411 hif_write32_mb(scn, scn->mem + BYPASS_QMI_TEMP_REGISTER, 0); 4412 } 4413 #else 4414 /** 4415 * hif_post_static_buf_to_target() - post static buffer to WLAN FW 4416 * @scn: pointer to HIF structure 4417 * 4418 * WLAN FW needs 2MB memory from DDR when QMI is disabled. 4419 * 4420 * Return: void 4421 */ 4422 static void hif_post_static_buf_to_target(struct hif_softc *scn) 4423 { 4424 qdf_dma_addr_t target_pa; 4425 4426 scn->vaddr_qmi_bypass = 4427 (uint32_t *)qdf_mem_alloc_consistent(scn->qdf_dev, 4428 scn->qdf_dev->dev, 4429 FW_SHARED_MEM, 4430 &target_pa); 4431 if (!scn->vaddr_qmi_bypass) { 4432 hif_err("Memory allocation failed could not post target buf"); 4433 return; 4434 } 4435 4436 scn->paddr_qmi_bypass = target_pa; 4437 hif_write32_mb(scn, scn->mem + BYPASS_QMI_TEMP_REGISTER, target_pa); 4438 } 4439 4440 /** 4441 * hif_cleanup_static_buf_to_target() - clean up static buffer to WLAN FW 4442 * @scn: pointer to HIF structure 4443 * 4444 * 4445 * Return: void 4446 */ 4447 void hif_cleanup_static_buf_to_target(struct hif_softc *scn) 4448 { 4449 void *target_va = scn->vaddr_qmi_bypass; 4450 phys_addr_t target_pa = scn->paddr_qmi_bypass; 4451 4452 qdf_mem_free_consistent(scn->qdf_dev, scn->qdf_dev->dev, 4453 FW_SHARED_MEM, target_va, 4454 target_pa, 0); 4455 hif_write32_mb(snc, scn->mem + BYPASS_QMI_TEMP_REGISTER, 0); 4456 } 4457 #endif 4458 4459 #else 4460 static inline void hif_post_static_buf_to_target(struct hif_softc *scn) 4461 { 4462 } 4463 4464 void hif_cleanup_static_buf_to_target(struct hif_softc *scn) 4465 { 4466 } 4467 #endif 4468 4469 static int hif_srng_sleep_state_adjust(struct hif_softc *scn, bool sleep_ok, 4470 bool wait_for_it) 4471 { 4472 /* todo */ 4473 return 0; 4474 } 4475 4476 int hif_config_ce_by_id(struct hif_softc *scn, int pipe_num) 4477 { 4478 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 4479 struct hif_opaque_softc *hif_hdl = GET_HIF_OPAQUE_HDL(scn); 4480 struct HIF_CE_pipe_info *pipe_info; 4481 struct CE_state *ce_state = NULL; 4482 struct CE_attr *attr; 4483 int rv = 0; 4484 4485 if (pipe_num >= CE_COUNT_MAX) 4486 return -EINVAL; 4487 4488 pipe_info = &hif_state->pipe_info[pipe_num]; 4489 pipe_info->pipe_num = pipe_num; 4490 pipe_info->HIF_CE_state = hif_state; 4491 attr = &hif_state->host_ce_config[pipe_num]; 4492 ce_state = scn->ce_id_to_state[pipe_num]; 4493 4494 if (ce_state) { 4495 /* Do not reinitialize the CE if its done already */ 4496 rv = QDF_STATUS_E_BUSY; 4497 goto err; 4498 } 4499 4500 pipe_info->ce_hdl = ce_init(scn, pipe_num, attr); 4501 ce_state = scn->ce_id_to_state[pipe_num]; 4502 if (!ce_state) { 4503 A_TARGET_ACCESS_UNLIKELY(scn); 4504 rv = QDF_STATUS_E_FAILURE; 4505 goto err; 4506 } 4507 qdf_spinlock_create(&pipe_info->recv_bufs_needed_lock); 4508 QDF_ASSERT(pipe_info->ce_hdl); 4509 if (!pipe_info->ce_hdl) { 4510 rv = QDF_STATUS_E_FAILURE; 4511 A_TARGET_ACCESS_UNLIKELY(scn); 4512 goto err; 4513 } 4514 4515 ce_state->lro_data = qdf_lro_init(); 4516 4517 if (attr->flags & CE_ATTR_DIAG) { 4518 /* Reserve the ultimate CE for 4519 * Diagnostic Window support 4520 */ 4521 hif_state->ce_diag = pipe_info->ce_hdl; 4522 goto skip; 4523 } 4524 4525 if (hif_is_nss_wifi_enabled(scn) && ce_state && 4526 (ce_state->htt_rx_data)) { 4527 goto skip; 4528 } 4529 4530 pipe_info->buf_sz = (qdf_size_t)(attr->src_sz_max); 4531 if (attr->dest_nentries > 0) { 4532 atomic_set(&pipe_info->recv_bufs_needed, 4533 init_buffer_count(attr->dest_nentries - 1)); 4534 /*SRNG based CE has one entry less */ 4535 if (ce_srng_based(scn)) 4536 atomic_dec(&pipe_info->recv_bufs_needed); 4537 } else { 4538 atomic_set(&pipe_info->recv_bufs_needed, 0); 4539 } 4540 ce_tasklet_init(hif_state, (1 << pipe_num)); 4541 ce_register_irq(hif_state, (1 << pipe_num)); 4542 4543 init_tasklet_worker_by_ceid(hif_hdl, pipe_num); 4544 skip: 4545 return 0; 4546 err: 4547 return rv; 4548 } 4549 4550 #if defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF) 4551 static inline void hif_gen_ce_id_history_idx_mapping(struct hif_softc *scn) 4552 { 4553 struct ce_desc_hist *ce_hist = &scn->hif_ce_desc_hist; 4554 uint8_t ce_id, hist_idx = 0; 4555 4556 for (ce_id = 0; ce_id < scn->ce_count; ce_id++) { 4557 if (IS_CE_DEBUG_ONLY_FOR_CRIT_CE & (1 << ce_id)) 4558 ce_hist->ce_id_hist_map[ce_id] = hist_idx++; 4559 else 4560 ce_hist->ce_id_hist_map[ce_id] = -1; 4561 } 4562 } 4563 #else 4564 static inline void hif_gen_ce_id_history_idx_mapping(struct hif_softc *scn) 4565 { 4566 } 4567 #endif 4568 4569 /** 4570 * hif_config_ce() - configure copy engines 4571 * @scn: hif context 4572 * 4573 * Prepares fw, copy engine hardware and host sw according 4574 * to the attributes selected by hif_ce_prepare_config. 4575 * 4576 * also calls athdiag_procfs_init 4577 * 4578 * return: 0 for success nonzero for failure. 4579 */ 4580 int hif_config_ce(struct hif_softc *scn) 4581 { 4582 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 4583 struct HIF_CE_pipe_info *pipe_info; 4584 int pipe_num; 4585 4586 #ifdef ADRASTEA_SHADOW_REGISTERS 4587 int i; 4588 #endif 4589 QDF_STATUS rv = QDF_STATUS_SUCCESS; 4590 4591 scn->notice_send = true; 4592 scn->ce_service_max_rx_ind_flush = MSG_FLUSH_NUM; 4593 4594 hif_post_static_buf_to_target(scn); 4595 4596 hif_state->fw_indicator_address = FW_INDICATOR_ADDRESS; 4597 4598 hif_config_rri_on_ddr(scn); 4599 4600 if (ce_srng_based(scn)) 4601 scn->bus_ops.hif_target_sleep_state_adjust = 4602 &hif_srng_sleep_state_adjust; 4603 4604 /* Initialise the CE debug history sysfs interface inputs ce_id and 4605 * index. Disable data storing 4606 */ 4607 reset_ce_debug_history(scn); 4608 hif_gen_ce_id_history_idx_mapping(scn); 4609 4610 for (pipe_num = 0; pipe_num < scn->ce_count; pipe_num++) { 4611 struct CE_attr *attr; 4612 4613 pipe_info = &hif_state->pipe_info[pipe_num]; 4614 attr = &hif_state->host_ce_config[pipe_num]; 4615 4616 if (attr->flags & CE_ATTR_INIT_ON_DEMAND) 4617 continue; 4618 4619 if (hif_config_ce_by_id(scn, pipe_num)) 4620 goto err; 4621 } 4622 4623 if (athdiag_procfs_init(scn) != 0) { 4624 A_TARGET_ACCESS_UNLIKELY(scn); 4625 goto err; 4626 } 4627 scn->athdiag_procfs_inited = true; 4628 4629 hif_debug("ce_init done"); 4630 hif_debug("%s: X, ret = %d", __func__, rv); 4631 4632 #ifdef ADRASTEA_SHADOW_REGISTERS 4633 hif_debug("Using Shadow Registers instead of CE Registers"); 4634 for (i = 0; i < NUM_SHADOW_REGISTERS; i++) { 4635 hif_debug("Shadow Register%d is mapped to address %x", 4636 i, 4637 (A_TARGET_READ(scn, (SHADOW_ADDRESS(i))) << 2)); 4638 } 4639 #endif 4640 4641 return rv != QDF_STATUS_SUCCESS; 4642 err: 4643 /* Failure, so clean up */ 4644 hif_unconfig_ce(scn); 4645 hif_info("X, ret = %d", rv); 4646 return QDF_STATUS_SUCCESS != QDF_STATUS_E_FAILURE; 4647 } 4648 4649 /** 4650 * hif_config_ce_pktlog() - configure copy engines 4651 * @hif_hdl: hif context 4652 * 4653 * Prepares fw, copy engine hardware and host sw according 4654 * to the attributes selected by hif_ce_prepare_config. 4655 * 4656 * also calls athdiag_procfs_init 4657 * 4658 * return: 0 for success nonzero for failure. 4659 */ 4660 int hif_config_ce_pktlog(struct hif_opaque_softc *hif_hdl) 4661 { 4662 struct hif_softc *scn = HIF_GET_SOFTC(hif_hdl); 4663 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 4664 int pipe_num; 4665 QDF_STATUS qdf_status = QDF_STATUS_E_FAILURE; 4666 struct HIF_CE_pipe_info *pipe_info; 4667 4668 if (!scn) 4669 goto err; 4670 4671 if (scn->pktlog_init) 4672 return QDF_STATUS_SUCCESS; 4673 4674 pipe_num = hif_get_pktlog_ce_num(scn); 4675 if (pipe_num < 0) { 4676 qdf_status = QDF_STATUS_E_FAILURE; 4677 goto err; 4678 } 4679 4680 pipe_info = &hif_state->pipe_info[pipe_num]; 4681 4682 qdf_status = hif_config_ce_by_id(scn, pipe_num); 4683 /* CE Already initialized. Do not try to reinitialized again */ 4684 if (qdf_status == QDF_STATUS_E_BUSY) 4685 return QDF_STATUS_SUCCESS; 4686 4687 qdf_status = hif_config_irq_by_ceid(scn, pipe_num); 4688 if (qdf_status < 0) 4689 goto err; 4690 4691 qdf_status = hif_completion_thread_startup_by_ceid(hif_state, pipe_num); 4692 if (!QDF_IS_STATUS_SUCCESS(qdf_status)) { 4693 hif_err("%s:failed to start hif thread", __func__); 4694 goto err; 4695 } 4696 4697 /* Post buffers for pktlog copy engine. */ 4698 qdf_status = hif_post_recv_buffers_for_pipe(pipe_info); 4699 if (!QDF_IS_STATUS_SUCCESS(qdf_status)) { 4700 /* cleanup is done in hif_ce_disable */ 4701 hif_err("%s:failed to post buffers", __func__); 4702 return qdf_status; 4703 } 4704 scn->pktlog_init = true; 4705 return qdf_status != QDF_STATUS_SUCCESS; 4706 4707 err: 4708 hif_debug("%s: X, ret = %d", __func__, qdf_status); 4709 return QDF_STATUS_SUCCESS != QDF_STATUS_E_FAILURE; 4710 } 4711 4712 #ifdef IPA_OFFLOAD 4713 /** 4714 * hif_ce_ipa_get_ce_resource() - get uc resource on hif 4715 * @scn: bus context 4716 * @ce_sr: copyengine source ring base physical address 4717 * @ce_sr_ring_size: copyengine source ring size 4718 * @ce_reg_paddr: copyengine register physical address 4719 * 4720 * IPA micro controller data path offload feature enabled, 4721 * HIF should release copy engine related resource information to IPA UC 4722 * IPA UC will access hardware resource with released information 4723 * 4724 * Return: None 4725 */ 4726 void hif_ce_ipa_get_ce_resource(struct hif_softc *scn, 4727 qdf_shared_mem_t **ce_sr, 4728 uint32_t *ce_sr_ring_size, 4729 qdf_dma_addr_t *ce_reg_paddr) 4730 { 4731 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 4732 struct HIF_CE_pipe_info *pipe_info = 4733 &(hif_state->pipe_info[HIF_PCI_IPA_UC_ASSIGNED_CE]); 4734 struct CE_handle *ce_hdl = pipe_info->ce_hdl; 4735 4736 ce_ipa_get_resource(ce_hdl, ce_sr, ce_sr_ring_size, 4737 ce_reg_paddr); 4738 } 4739 #endif /* IPA_OFFLOAD */ 4740 4741 4742 #ifdef ADRASTEA_SHADOW_REGISTERS 4743 4744 /* 4745 * Current shadow register config 4746 * 4747 * ----------------------------------------------------------- 4748 * Shadow Register | CE | src/dst write index 4749 * ----------------------------------------------------------- 4750 * 0 | 0 | src 4751 * 1 No Config - Doesn't point to anything 4752 * 2 No Config - Doesn't point to anything 4753 * 3 | 3 | src 4754 * 4 | 4 | src 4755 * 5 | 5 | src 4756 * 6 No Config - Doesn't point to anything 4757 * 7 | 7 | src 4758 * 8 No Config - Doesn't point to anything 4759 * 9 No Config - Doesn't point to anything 4760 * 10 No Config - Doesn't point to anything 4761 * 11 No Config - Doesn't point to anything 4762 * ----------------------------------------------------------- 4763 * 12 No Config - Doesn't point to anything 4764 * 13 | 1 | dst 4765 * 14 | 2 | dst 4766 * 15 No Config - Doesn't point to anything 4767 * 16 No Config - Doesn't point to anything 4768 * 17 No Config - Doesn't point to anything 4769 * 18 No Config - Doesn't point to anything 4770 * 19 | 7 | dst 4771 * 20 | 8 | dst 4772 * 21 No Config - Doesn't point to anything 4773 * 22 No Config - Doesn't point to anything 4774 * 23 No Config - Doesn't point to anything 4775 * ----------------------------------------------------------- 4776 * 4777 * 4778 * ToDo - Move shadow register config to following in the future 4779 * This helps free up a block of shadow registers towards the end. 4780 * Can be used for other purposes 4781 * 4782 * ----------------------------------------------------------- 4783 * Shadow Register | CE | src/dst write index 4784 * ----------------------------------------------------------- 4785 * 0 | 0 | src 4786 * 1 | 3 | src 4787 * 2 | 4 | src 4788 * 3 | 5 | src 4789 * 4 | 7 | src 4790 * ----------------------------------------------------------- 4791 * 5 | 1 | dst 4792 * 6 | 2 | dst 4793 * 7 | 7 | dst 4794 * 8 | 8 | dst 4795 * ----------------------------------------------------------- 4796 * 9 No Config - Doesn't point to anything 4797 * 12 No Config - Doesn't point to anything 4798 * 13 No Config - Doesn't point to anything 4799 * 14 No Config - Doesn't point to anything 4800 * 15 No Config - Doesn't point to anything 4801 * 16 No Config - Doesn't point to anything 4802 * 17 No Config - Doesn't point to anything 4803 * 18 No Config - Doesn't point to anything 4804 * 19 No Config - Doesn't point to anything 4805 * 20 No Config - Doesn't point to anything 4806 * 21 No Config - Doesn't point to anything 4807 * 22 No Config - Doesn't point to anything 4808 * 23 No Config - Doesn't point to anything 4809 * ----------------------------------------------------------- 4810 */ 4811 #ifndef QCN7605_SUPPORT 4812 u32 shadow_sr_wr_ind_addr(struct hif_softc *scn, u32 ctrl_addr) 4813 { 4814 u32 addr = 0; 4815 u32 ce = COPY_ENGINE_ID(ctrl_addr); 4816 4817 switch (ce) { 4818 case 0: 4819 addr = SHADOW_VALUE0; 4820 break; 4821 case 3: 4822 addr = SHADOW_VALUE3; 4823 break; 4824 case 4: 4825 addr = SHADOW_VALUE4; 4826 break; 4827 case 5: 4828 addr = SHADOW_VALUE5; 4829 break; 4830 case 7: 4831 addr = SHADOW_VALUE7; 4832 break; 4833 default: 4834 hif_err("Invalid CE ctrl_addr (CE=%d)", ce); 4835 QDF_ASSERT(0); 4836 } 4837 return addr; 4838 4839 } 4840 4841 u32 shadow_dst_wr_ind_addr(struct hif_softc *scn, u32 ctrl_addr) 4842 { 4843 u32 addr = 0; 4844 u32 ce = COPY_ENGINE_ID(ctrl_addr); 4845 4846 switch (ce) { 4847 case 1: 4848 addr = SHADOW_VALUE13; 4849 break; 4850 case 2: 4851 addr = SHADOW_VALUE14; 4852 break; 4853 case 5: 4854 addr = SHADOW_VALUE17; 4855 break; 4856 case 7: 4857 addr = SHADOW_VALUE19; 4858 break; 4859 case 8: 4860 addr = SHADOW_VALUE20; 4861 break; 4862 case 9: 4863 addr = SHADOW_VALUE21; 4864 break; 4865 case 10: 4866 addr = SHADOW_VALUE22; 4867 break; 4868 case 11: 4869 addr = SHADOW_VALUE23; 4870 break; 4871 default: 4872 hif_err("Invalid CE ctrl_addr (CE=%d)", ce); 4873 QDF_ASSERT(0); 4874 } 4875 4876 return addr; 4877 4878 } 4879 #else 4880 u32 shadow_sr_wr_ind_addr(struct hif_softc *scn, u32 ctrl_addr) 4881 { 4882 u32 addr = 0; 4883 u32 ce = COPY_ENGINE_ID(ctrl_addr); 4884 4885 switch (ce) { 4886 case 0: 4887 addr = SHADOW_VALUE0; 4888 break; 4889 case 3: 4890 addr = SHADOW_VALUE3; 4891 break; 4892 case 4: 4893 addr = SHADOW_VALUE4; 4894 break; 4895 case 5: 4896 addr = SHADOW_VALUE5; 4897 break; 4898 default: 4899 hif_err("Invalid CE ctrl_addr (CE=%d)", ce); 4900 QDF_ASSERT(0); 4901 } 4902 return addr; 4903 } 4904 4905 u32 shadow_dst_wr_ind_addr(struct hif_softc *scn, u32 ctrl_addr) 4906 { 4907 u32 addr = 0; 4908 u32 ce = COPY_ENGINE_ID(ctrl_addr); 4909 4910 switch (ce) { 4911 case 1: 4912 addr = SHADOW_VALUE13; 4913 break; 4914 case 2: 4915 addr = SHADOW_VALUE14; 4916 break; 4917 case 3: 4918 addr = SHADOW_VALUE15; 4919 break; 4920 case 5: 4921 addr = SHADOW_VALUE17; 4922 break; 4923 case 7: 4924 addr = SHADOW_VALUE19; 4925 break; 4926 case 8: 4927 addr = SHADOW_VALUE20; 4928 break; 4929 case 9: 4930 addr = SHADOW_VALUE21; 4931 break; 4932 case 10: 4933 addr = SHADOW_VALUE22; 4934 break; 4935 case 11: 4936 addr = SHADOW_VALUE23; 4937 break; 4938 default: 4939 hif_err("Invalid CE ctrl_addr (CE=%d)", ce); 4940 QDF_ASSERT(0); 4941 } 4942 4943 return addr; 4944 } 4945 #endif 4946 #endif 4947 4948 #if defined(FEATURE_LRO) 4949 void *hif_ce_get_lro_ctx(struct hif_opaque_softc *hif_hdl, int ctx_id) 4950 { 4951 struct CE_state *ce_state; 4952 struct hif_softc *scn = HIF_GET_SOFTC(hif_hdl); 4953 4954 ce_state = scn->ce_id_to_state[ctx_id]; 4955 4956 return ce_state->lro_data; 4957 } 4958 #endif 4959 4960 /** 4961 * hif_map_service_to_pipe() - returns the ce ids pertaining to 4962 * this service 4963 * @hif_hdl: hif_softc pointer. 4964 * @svc_id: Service ID for which the mapping is needed. 4965 * @ul_pipe: address of the container in which ul pipe is returned. 4966 * @dl_pipe: address of the container in which dl pipe is returned. 4967 * @ul_is_polled: address of the container in which a bool 4968 * indicating if the UL CE for this service 4969 * is polled is returned. 4970 * @dl_is_polled: address of the container in which a bool 4971 * indicating if the DL CE for this service 4972 * is polled is returned. 4973 * 4974 * Return: Indicates whether the service has been found in the table. 4975 * Upon return, ul_is_polled is updated only if ul_pipe is updated. 4976 * There will be warning logs if either leg has not been updated 4977 * because it missed the entry in the table (but this is not an err). 4978 */ 4979 int hif_map_service_to_pipe(struct hif_opaque_softc *hif_hdl, uint16_t svc_id, 4980 uint8_t *ul_pipe, uint8_t *dl_pipe, int *ul_is_polled, 4981 int *dl_is_polled) 4982 { 4983 int status = -EINVAL; 4984 unsigned int i; 4985 struct service_to_pipe element; 4986 struct service_to_pipe *tgt_svc_map_to_use; 4987 uint32_t sz_tgt_svc_map_to_use; 4988 struct hif_softc *scn = HIF_GET_SOFTC(hif_hdl); 4989 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 4990 bool dl_updated = false; 4991 bool ul_updated = false; 4992 4993 hif_select_service_to_pipe_map(scn, &tgt_svc_map_to_use, 4994 &sz_tgt_svc_map_to_use); 4995 4996 *dl_is_polled = 0; /* polling for received messages not supported */ 4997 4998 for (i = 0; i < (sz_tgt_svc_map_to_use/sizeof(element)); i++) { 4999 5000 memcpy(&element, &tgt_svc_map_to_use[i], sizeof(element)); 5001 if (element.service_id == svc_id) { 5002 if (element.pipedir == PIPEDIR_OUT) { 5003 *ul_pipe = element.pipenum; 5004 *ul_is_polled = 5005 (hif_state->host_ce_config[*ul_pipe].flags & 5006 CE_ATTR_DISABLE_INTR) != 0; 5007 ul_updated = true; 5008 } else if (element.pipedir == PIPEDIR_IN) { 5009 *dl_pipe = element.pipenum; 5010 dl_updated = true; 5011 } 5012 status = 0; 5013 } 5014 } 5015 if (ul_updated == false) 5016 hif_debug("ul pipe is NOT updated for service %d", svc_id); 5017 if (dl_updated == false) 5018 hif_debug("dl pipe is NOT updated for service %d", svc_id); 5019 5020 return status; 5021 } 5022 5023 #ifdef SHADOW_REG_DEBUG 5024 inline uint32_t DEBUG_CE_SRC_RING_READ_IDX_GET(struct hif_softc *scn, 5025 uint32_t CE_ctrl_addr) 5026 { 5027 uint32_t read_from_hw, srri_from_ddr = 0; 5028 5029 read_from_hw = A_TARGET_READ(scn, CE_ctrl_addr + CURRENT_SRRI_ADDRESS); 5030 5031 srri_from_ddr = SRRI_FROM_DDR_ADDR(VADDR_FOR_CE(scn, CE_ctrl_addr)); 5032 5033 if (read_from_hw != srri_from_ddr) { 5034 hif_err("read from ddr = %d actual read from register = %d, CE_MISC_INT_STATUS_GET = 0x%x", 5035 srri_from_ddr, read_from_hw, 5036 CE_MISC_INT_STATUS_GET(scn, CE_ctrl_addr)); 5037 QDF_ASSERT(0); 5038 } 5039 return srri_from_ddr; 5040 } 5041 5042 5043 inline uint32_t DEBUG_CE_DEST_RING_READ_IDX_GET(struct hif_softc *scn, 5044 uint32_t CE_ctrl_addr) 5045 { 5046 uint32_t read_from_hw, drri_from_ddr = 0; 5047 5048 read_from_hw = A_TARGET_READ(scn, CE_ctrl_addr + CURRENT_DRRI_ADDRESS); 5049 5050 drri_from_ddr = DRRI_FROM_DDR_ADDR(VADDR_FOR_CE(scn, CE_ctrl_addr)); 5051 5052 if (read_from_hw != drri_from_ddr) { 5053 hif_err("read from ddr = %d actual read from register = %d, CE_MISC_INT_STATUS_GET = 0x%x", 5054 drri_from_ddr, read_from_hw, 5055 CE_MISC_INT_STATUS_GET(scn, CE_ctrl_addr)); 5056 QDF_ASSERT(0); 5057 } 5058 return drri_from_ddr; 5059 } 5060 5061 #endif 5062 5063 /** 5064 * hif_dump_ce_registers() - dump ce registers 5065 * @scn: hif_opaque_softc pointer. 5066 * 5067 * Output the copy engine registers 5068 * 5069 * Return: 0 for success or error code 5070 */ 5071 int hif_dump_ce_registers(struct hif_softc *scn) 5072 { 5073 struct hif_opaque_softc *hif_hdl = GET_HIF_OPAQUE_HDL(scn); 5074 uint32_t ce_reg_address = CE0_BASE_ADDRESS; 5075 uint32_t ce_reg_values[CE_USEFUL_SIZE >> 2]; 5076 uint32_t ce_reg_word_size = CE_USEFUL_SIZE >> 2; 5077 uint16_t i; 5078 QDF_STATUS status; 5079 5080 for (i = 0; i < scn->ce_count; i++, ce_reg_address += CE_OFFSET) { 5081 if (!scn->ce_id_to_state[i]) { 5082 hif_debug("CE%d not used", i); 5083 continue; 5084 } 5085 5086 status = hif_diag_read_mem(hif_hdl, ce_reg_address, 5087 (uint8_t *) &ce_reg_values[0], 5088 ce_reg_word_size * sizeof(uint32_t)); 5089 5090 if (status != QDF_STATUS_SUCCESS) { 5091 hif_err("Dumping CE register failed!"); 5092 return -EACCES; 5093 } 5094 hif_debug("CE%d=>", i); 5095 qdf_trace_hex_dump(QDF_MODULE_ID_HIF, QDF_TRACE_LEVEL_DEBUG, 5096 (uint8_t *) &ce_reg_values[0], 5097 ce_reg_word_size * sizeof(uint32_t)); 5098 qdf_print("ADDR:[0x%08X], SR_WR_INDEX:%d", (ce_reg_address 5099 + SR_WR_INDEX_ADDRESS), 5100 ce_reg_values[SR_WR_INDEX_ADDRESS/4]); 5101 qdf_print("ADDR:[0x%08X], CURRENT_SRRI:%d", (ce_reg_address 5102 + CURRENT_SRRI_ADDRESS), 5103 ce_reg_values[CURRENT_SRRI_ADDRESS/4]); 5104 qdf_print("ADDR:[0x%08X], DST_WR_INDEX:%d", (ce_reg_address 5105 + DST_WR_INDEX_ADDRESS), 5106 ce_reg_values[DST_WR_INDEX_ADDRESS/4]); 5107 qdf_print("ADDR:[0x%08X], CURRENT_DRRI:%d", (ce_reg_address 5108 + CURRENT_DRRI_ADDRESS), 5109 ce_reg_values[CURRENT_DRRI_ADDRESS/4]); 5110 qdf_print("---"); 5111 } 5112 return 0; 5113 } 5114 qdf_export_symbol(hif_dump_ce_registers); 5115 #ifdef QCA_NSS_WIFI_OFFLOAD_SUPPORT 5116 struct hif_pipe_addl_info *hif_get_addl_pipe_info(struct hif_opaque_softc *osc, 5117 struct hif_pipe_addl_info *hif_info, uint32_t pipe) 5118 { 5119 struct hif_softc *scn = HIF_GET_SOFTC(osc); 5120 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn); 5121 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(osc); 5122 struct HIF_CE_pipe_info *pipe_info = &(hif_state->pipe_info[pipe]); 5123 struct CE_handle *ce_hdl = pipe_info->ce_hdl; 5124 struct CE_state *ce_state = (struct CE_state *)ce_hdl; 5125 struct CE_ring_state *src_ring = ce_state->src_ring; 5126 struct CE_ring_state *dest_ring = ce_state->dest_ring; 5127 5128 if (src_ring) { 5129 hif_info->ul_pipe.nentries = src_ring->nentries; 5130 hif_info->ul_pipe.nentries_mask = src_ring->nentries_mask; 5131 hif_info->ul_pipe.sw_index = src_ring->sw_index; 5132 hif_info->ul_pipe.write_index = src_ring->write_index; 5133 hif_info->ul_pipe.hw_index = src_ring->hw_index; 5134 hif_info->ul_pipe.base_addr_CE_space = 5135 src_ring->base_addr_CE_space; 5136 hif_info->ul_pipe.base_addr_owner_space = 5137 src_ring->base_addr_owner_space; 5138 } 5139 5140 5141 if (dest_ring) { 5142 hif_info->dl_pipe.nentries = dest_ring->nentries; 5143 hif_info->dl_pipe.nentries_mask = dest_ring->nentries_mask; 5144 hif_info->dl_pipe.sw_index = dest_ring->sw_index; 5145 hif_info->dl_pipe.write_index = dest_ring->write_index; 5146 hif_info->dl_pipe.hw_index = dest_ring->hw_index; 5147 hif_info->dl_pipe.base_addr_CE_space = 5148 dest_ring->base_addr_CE_space; 5149 hif_info->dl_pipe.base_addr_owner_space = 5150 dest_ring->base_addr_owner_space; 5151 } 5152 5153 hif_info->pci_mem = pci_resource_start(sc->pdev, 0); 5154 hif_info->ctrl_addr = ce_state->ctrl_addr; 5155 5156 return hif_info; 5157 } 5158 qdf_export_symbol(hif_get_addl_pipe_info); 5159 5160 uint32_t hif_set_nss_wifiol_mode(struct hif_opaque_softc *osc, uint32_t mode) 5161 { 5162 struct hif_softc *scn = HIF_GET_SOFTC(osc); 5163 5164 scn->nss_wifi_ol_mode = mode; 5165 return 0; 5166 } 5167 qdf_export_symbol(hif_set_nss_wifiol_mode); 5168 #endif 5169 5170 void hif_set_attribute(struct hif_opaque_softc *osc, uint8_t hif_attrib) 5171 { 5172 struct hif_softc *scn = HIF_GET_SOFTC(osc); 5173 scn->hif_attribute = hif_attrib; 5174 } 5175 5176 5177 /* disable interrupts (only applicable for legacy copy engine currently */ 5178 void hif_disable_interrupt(struct hif_opaque_softc *osc, uint32_t pipe_num) 5179 { 5180 struct hif_softc *scn = HIF_GET_SOFTC(osc); 5181 struct CE_state *CE_state = scn->ce_id_to_state[pipe_num]; 5182 uint32_t ctrl_addr = CE_state->ctrl_addr; 5183 5184 Q_TARGET_ACCESS_BEGIN(scn); 5185 CE_COPY_COMPLETE_INTR_DISABLE(scn, ctrl_addr); 5186 Q_TARGET_ACCESS_END(scn); 5187 } 5188 qdf_export_symbol(hif_disable_interrupt); 5189 5190 /** 5191 * hif_fw_event_handler() - hif fw event handler 5192 * @hif_state: pointer to hif ce state structure 5193 * 5194 * Process fw events and raise HTC callback to process fw events. 5195 * 5196 * Return: none 5197 */ 5198 static inline void hif_fw_event_handler(struct HIF_CE_state *hif_state) 5199 { 5200 struct hif_msg_callbacks *msg_callbacks = 5201 &hif_state->msg_callbacks_current; 5202 5203 if (!msg_callbacks->fwEventHandler) 5204 return; 5205 5206 msg_callbacks->fwEventHandler(msg_callbacks->Context, 5207 QDF_STATUS_E_FAILURE); 5208 } 5209 5210 #ifndef QCA_WIFI_3_0 5211 /** 5212 * hif_fw_interrupt_handler() - FW interrupt handler 5213 * @irq: irq number 5214 * @arg: the user pointer 5215 * 5216 * Called from the PCI interrupt handler when a 5217 * firmware-generated interrupt to the Host. 5218 * 5219 * only registered for legacy ce devices 5220 * 5221 * Return: status of handled irq 5222 */ 5223 irqreturn_t hif_fw_interrupt_handler(int irq, void *arg) 5224 { 5225 struct hif_softc *scn = arg; 5226 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 5227 uint32_t fw_indicator_address, fw_indicator; 5228 5229 if (Q_TARGET_ACCESS_BEGIN(scn) < 0) 5230 return ATH_ISR_NOSCHED; 5231 5232 fw_indicator_address = hif_state->fw_indicator_address; 5233 /* For sudden unplug this will return ~0 */ 5234 fw_indicator = A_TARGET_READ(scn, fw_indicator_address); 5235 5236 if ((fw_indicator != ~0) && (fw_indicator & FW_IND_EVENT_PENDING)) { 5237 /* ACK: clear Target-side pending event */ 5238 A_TARGET_WRITE(scn, fw_indicator_address, 5239 fw_indicator & ~FW_IND_EVENT_PENDING); 5240 if (Q_TARGET_ACCESS_END(scn) < 0) 5241 return ATH_ISR_SCHED; 5242 5243 if (hif_state->started) { 5244 hif_fw_event_handler(hif_state); 5245 } else { 5246 /* 5247 * Probable Target failure before we're prepared 5248 * to handle it. Generally unexpected. 5249 * fw_indicator used as bitmap, and defined as below: 5250 * FW_IND_EVENT_PENDING 0x1 5251 * FW_IND_INITIALIZED 0x2 5252 * FW_IND_NEEDRECOVER 0x4 5253 */ 5254 AR_DEBUG_PRINTF(ATH_DEBUG_ERR, 5255 ("%s: Early firmware event indicated 0x%x\n", 5256 __func__, fw_indicator)); 5257 } 5258 } else { 5259 if (Q_TARGET_ACCESS_END(scn) < 0) 5260 return ATH_ISR_SCHED; 5261 } 5262 5263 return ATH_ISR_SCHED; 5264 } 5265 #else 5266 irqreturn_t hif_fw_interrupt_handler(int irq, void *arg) 5267 { 5268 return ATH_ISR_SCHED; 5269 } 5270 #endif /* #ifdef QCA_WIFI_3_0 */ 5271 5272 5273 /** 5274 * hif_wlan_disable(): call the platform driver to disable wlan 5275 * @scn: HIF Context 5276 * 5277 * This function passes the con_mode to platform driver to disable 5278 * wlan. 5279 * 5280 * Return: void 5281 */ 5282 void hif_wlan_disable(struct hif_softc *scn) 5283 { 5284 enum pld_driver_mode mode; 5285 uint32_t con_mode = hif_get_conparam(scn); 5286 5287 if (scn->target_status == TARGET_STATUS_RESET) 5288 return; 5289 5290 if (QDF_GLOBAL_FTM_MODE == con_mode) 5291 mode = PLD_FTM; 5292 else if (QDF_IS_EPPING_ENABLED(con_mode)) 5293 mode = PLD_EPPING; 5294 else 5295 mode = PLD_MISSION; 5296 5297 pld_wlan_disable(scn->qdf_dev->dev, mode); 5298 } 5299 5300 int hif_get_wake_ce_id(struct hif_softc *scn, uint8_t *ce_id) 5301 { 5302 int status; 5303 uint8_t ul_pipe, dl_pipe; 5304 int ul_is_polled, dl_is_polled; 5305 5306 /* DL pipe for HTC_CTRL_RSVD_SVC should map to the wake CE */ 5307 status = hif_map_service_to_pipe(GET_HIF_OPAQUE_HDL(scn), 5308 HTC_CTRL_RSVD_SVC, 5309 &ul_pipe, &dl_pipe, 5310 &ul_is_polled, &dl_is_polled); 5311 if (status) { 5312 hif_err("Failed to map pipe: %d", status); 5313 return status; 5314 } 5315 5316 *ce_id = dl_pipe; 5317 5318 return 0; 5319 } 5320 5321 int hif_get_fw_diag_ce_id(struct hif_softc *scn, uint8_t *ce_id) 5322 { 5323 int status; 5324 uint8_t ul_pipe, dl_pipe; 5325 int ul_is_polled, dl_is_polled; 5326 5327 /* DL pipe for WMI_CONTROL_DIAG_SVC should map to the FW DIAG CE_ID */ 5328 status = hif_map_service_to_pipe(GET_HIF_OPAQUE_HDL(scn), 5329 WMI_CONTROL_DIAG_SVC, 5330 &ul_pipe, &dl_pipe, 5331 &ul_is_polled, &dl_is_polled); 5332 if (status) { 5333 hif_err("Failed to map pipe: %d", status); 5334 return status; 5335 } 5336 5337 *ce_id = dl_pipe; 5338 5339 return 0; 5340 } 5341 5342 #ifdef HIF_CE_LOG_INFO 5343 /** 5344 * ce_get_index_info(): Get CE index info 5345 * @scn: HIF Context 5346 * @ce_state: CE opaque handle 5347 * @info: CE info 5348 * 5349 * Return: 0 for success and non zero for failure 5350 */ 5351 static 5352 int ce_get_index_info(struct hif_softc *scn, void *ce_state, 5353 struct ce_index *info) 5354 { 5355 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 5356 5357 return hif_state->ce_services->ce_get_index_info(scn, ce_state, info); 5358 } 5359 5360 void hif_log_ce_info(struct hif_softc *scn, uint8_t *data, 5361 unsigned int *offset) 5362 { 5363 struct hang_event_info info = {0}; 5364 static uint32_t tracked_ce = BIT(CE_ID_1) | BIT(CE_ID_2) | 5365 BIT(CE_ID_3) | BIT(CE_ID_4) | BIT(CE_ID_9) | BIT(CE_ID_10); 5366 uint8_t curr_index = 0; 5367 uint8_t i; 5368 uint16_t size; 5369 5370 info.active_tasklet_count = qdf_atomic_read(&scn->active_tasklet_cnt); 5371 info.active_grp_tasklet_cnt = 5372 qdf_atomic_read(&scn->active_grp_tasklet_cnt); 5373 5374 for (i = 0; i < scn->ce_count; i++) { 5375 if (!(tracked_ce & BIT(i)) || !scn->ce_id_to_state[i]) 5376 continue; 5377 5378 if (ce_get_index_info(scn, scn->ce_id_to_state[i], 5379 &info.ce_info[curr_index])) 5380 continue; 5381 5382 curr_index++; 5383 } 5384 5385 info.ce_count = curr_index; 5386 size = sizeof(info) - 5387 (CE_COUNT_MAX - info.ce_count) * sizeof(struct ce_index); 5388 5389 if (*offset + size > QDF_WLAN_HANG_FW_OFFSET) 5390 return; 5391 5392 QDF_HANG_EVT_SET_HDR(&info.tlv_header, HANG_EVT_TAG_CE_INFO, 5393 size - QDF_HANG_EVENT_TLV_HDR_SIZE); 5394 5395 qdf_mem_copy(data + *offset, &info, size); 5396 *offset = *offset + size; 5397 } 5398 5399 #ifdef FEATURE_DIRECT_LINK 5400 QDF_STATUS 5401 hif_set_irq_config_by_ceid(struct hif_opaque_softc *scn, uint8_t ce_id, 5402 uint64_t addr, uint32_t data) 5403 { 5404 struct hif_softc *hif_ctx = HIF_GET_SOFTC(scn); 5405 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 5406 5407 if (hif_state->ce_services->ce_set_irq_config_by_ceid) 5408 return hif_state->ce_services->ce_set_irq_config_by_ceid( 5409 hif_ctx, 5410 ce_id, 5411 addr, 5412 data); 5413 5414 return QDF_STATUS_E_NOSUPPORT; 5415 } 5416 5417 uint16_t hif_get_direct_link_ce_dest_srng_buffers(struct hif_opaque_softc *scn, 5418 uint64_t **dma_addr, 5419 uint32_t *buf_size) 5420 { 5421 struct hif_softc *hif_ctx = HIF_GET_SOFTC(scn); 5422 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 5423 struct ce_ops *ce_services = hif_state->ce_services; 5424 5425 if (ce_services->ce_get_direct_link_dest_buffers) 5426 return ce_services->ce_get_direct_link_dest_buffers(hif_ctx, 5427 dma_addr, 5428 buf_size); 5429 5430 return 0; 5431 } 5432 5433 QDF_STATUS 5434 hif_get_direct_link_ce_srng_info(struct hif_opaque_softc *scn, 5435 struct hif_direct_link_ce_info *info, 5436 uint8_t max_ce_info_len) 5437 { 5438 struct hif_softc *hif_ctx = HIF_GET_SOFTC(scn); 5439 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 5440 struct ce_ops *ce_services = hif_state->ce_services; 5441 5442 if (ce_services->ce_get_direct_link_ring_info) 5443 return ce_services->ce_get_direct_link_ring_info(hif_ctx, 5444 info, 5445 max_ce_info_len); 5446 5447 return QDF_STATUS_E_NOSUPPORT; 5448 } 5449 #endif 5450 #endif 5451