1 /* 2 * Copyright (c) 2013-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include "targcfg.h" 21 #include "qdf_lock.h" 22 #include "qdf_status.h" 23 #include "qdf_status.h" 24 #include <qdf_atomic.h> /* qdf_atomic_read */ 25 #include <targaddrs.h> 26 #include "hif_io32.h" 27 #include <hif.h> 28 #include <target_type.h> 29 #include "regtable.h" 30 #define ATH_MODULE_NAME hif 31 #include <a_debug.h> 32 #include "hif_main.h" 33 #include "ce_api.h" 34 #include "qdf_trace.h" 35 #include "pld_common.h" 36 #include "hif_debug.h" 37 #include "ce_internal.h" 38 #include "ce_reg.h" 39 #include "ce_assignment.h" 40 #include "ce_tasklet.h" 41 #include "qdf_module.h" 42 43 #define CE_POLL_TIMEOUT 10 /* ms */ 44 45 #define AGC_DUMP 1 46 #define CHANINFO_DUMP 2 47 #define BB_WATCHDOG_DUMP 3 48 #ifdef CONFIG_ATH_PCIE_ACCESS_DEBUG 49 #define PCIE_ACCESS_DUMP 4 50 #endif 51 #include "mp_dev.h" 52 #ifdef HIF_CE_LOG_INFO 53 #include "qdf_hang_event_notifier.h" 54 #endif 55 56 #if (defined(QCA_WIFI_QCA8074) || defined(QCA_WIFI_QCA6290) || \ 57 defined(QCA_WIFI_QCA6018) || defined(QCA_WIFI_QCA5018) || \ 58 defined(QCA_WIFI_KIWI) || defined(QCA_WIFI_QCA5332) || \ 59 defined(QCA_WIFI_QCA9574)) && !defined(QCA_WIFI_SUPPORT_SRNG) 60 #define QCA_WIFI_SUPPORT_SRNG 61 #endif 62 63 #ifdef QCA_WIFI_SUPPORT_SRNG 64 #include <hal_api.h> 65 #endif 66 67 /* Forward references */ 68 QDF_STATUS hif_post_recv_buffers_for_pipe(struct HIF_CE_pipe_info *pipe_info); 69 70 /* 71 * Fix EV118783, poll to check whether a BMI response comes 72 * other than waiting for the interruption which may be lost. 73 */ 74 /* #define BMI_RSP_POLLING */ 75 #define BMI_RSP_TO_MILLISEC 1000 76 77 #ifdef CONFIG_BYPASS_QMI 78 #define BYPASS_QMI 1 79 #else 80 #define BYPASS_QMI 0 81 #endif 82 83 #ifdef ENABLE_10_4_FW_HDR 84 #if (ENABLE_10_4_FW_HDR == 1) 85 #define WDI_IPA_SERVICE_GROUP 5 86 #define WDI_IPA_TX_SVC MAKE_SERVICE_ID(WDI_IPA_SERVICE_GROUP, 0) 87 #define HTT_DATA2_MSG_SVC MAKE_SERVICE_ID(HTT_SERVICE_GROUP, 1) 88 #define HTT_DATA3_MSG_SVC MAKE_SERVICE_ID(HTT_SERVICE_GROUP, 2) 89 #endif /* ENABLE_10_4_FW_HDR == 1 */ 90 #endif /* ENABLE_10_4_FW_HDR */ 91 92 static void hif_config_rri_on_ddr(struct hif_softc *scn); 93 94 /** 95 * hif_target_access_log_dump() - dump access log 96 * 97 * dump access log 98 * 99 * Return: n/a 100 */ 101 #ifdef CONFIG_ATH_PCIE_ACCESS_DEBUG 102 static void hif_target_access_log_dump(void) 103 { 104 hif_target_dump_access_log(); 105 } 106 #endif 107 108 /* 109 * This structure contains the interrupt index for each Copy engine 110 * for various number of MSIs available in the system. 111 */ 112 static struct ce_int_assignment ce_int_context[NUM_CE_CONTEXT] = { 113 /* Default configuration */ 114 {{ CE_INTERRUPT_IDX(0), 115 CE_INTERRUPT_IDX(1), 116 CE_INTERRUPT_IDX(2), 117 CE_INTERRUPT_IDX(3), 118 CE_INTERRUPT_IDX(4), 119 CE_INTERRUPT_IDX(5), 120 CE_INTERRUPT_IDX(6), 121 CE_INTERRUPT_IDX(7), 122 CE_INTERRUPT_IDX(8), 123 CE_INTERRUPT_IDX(9), 124 CE_INTERRUPT_IDX(10), 125 CE_INTERRUPT_IDX(11), 126 #ifdef QCA_WIFI_QCN9224 127 CE_INTERRUPT_IDX(12), 128 CE_INTERRUPT_IDX(13), 129 CE_INTERRUPT_IDX(14), 130 CE_INTERRUPT_IDX(15), 131 #endif 132 } }, 133 /* Interrupt assignment for 1 MSI combination */ 134 {{ CE_INTERRUPT_IDX(0), 135 CE_INTERRUPT_IDX(0), 136 CE_INTERRUPT_IDX(0), 137 CE_INTERRUPT_IDX(0), 138 CE_INTERRUPT_IDX(0), 139 CE_INTERRUPT_IDX(0), 140 CE_INTERRUPT_IDX(0), 141 CE_INTERRUPT_IDX(0), 142 CE_INTERRUPT_IDX(0), 143 CE_INTERRUPT_IDX(0), 144 CE_INTERRUPT_IDX(0), 145 CE_INTERRUPT_IDX(0), 146 #ifdef QCA_WIFI_QCN9224 147 CE_INTERRUPT_IDX(0), 148 CE_INTERRUPT_IDX(0), 149 CE_INTERRUPT_IDX(0), 150 CE_INTERRUPT_IDX(0), 151 #endif 152 } }, 153 /* Interrupt assignment for 2 MSI combination */ 154 {{ CE_INTERRUPT_IDX(0), 155 CE_INTERRUPT_IDX(1), 156 CE_INTERRUPT_IDX(0), 157 CE_INTERRUPT_IDX(1), 158 CE_INTERRUPT_IDX(0), 159 CE_INTERRUPT_IDX(1), 160 CE_INTERRUPT_IDX(0), 161 CE_INTERRUPT_IDX(0), 162 CE_INTERRUPT_IDX(0), 163 CE_INTERRUPT_IDX(0), 164 CE_INTERRUPT_IDX(0), 165 CE_INTERRUPT_IDX(0), 166 #ifdef QCA_WIFI_QCN9224 167 CE_INTERRUPT_IDX(0), 168 CE_INTERRUPT_IDX(0), 169 CE_INTERRUPT_IDX(0), 170 CE_INTERRUPT_IDX(0), 171 #endif 172 } }, 173 /* Interrupt assignment for 3 MSI combination */ 174 {{ CE_INTERRUPT_IDX(0), 175 CE_INTERRUPT_IDX(1), 176 CE_INTERRUPT_IDX(2), 177 CE_INTERRUPT_IDX(1), 178 CE_INTERRUPT_IDX(0), 179 CE_INTERRUPT_IDX(1), 180 CE_INTERRUPT_IDX(0), 181 CE_INTERRUPT_IDX(0), 182 CE_INTERRUPT_IDX(0), 183 CE_INTERRUPT_IDX(0), 184 CE_INTERRUPT_IDX(0), 185 CE_INTERRUPT_IDX(0), 186 #ifdef QCA_WIFI_QCN9224 187 CE_INTERRUPT_IDX(0), 188 CE_INTERRUPT_IDX(0), 189 CE_INTERRUPT_IDX(0), 190 CE_INTERRUPT_IDX(0), 191 #endif 192 } }, 193 /* Interrupt assignment for 4 MSI combination */ 194 {{ CE_INTERRUPT_IDX(0), 195 CE_INTERRUPT_IDX(1), 196 CE_INTERRUPT_IDX(2), 197 CE_INTERRUPT_IDX(3), 198 CE_INTERRUPT_IDX(0), 199 CE_INTERRUPT_IDX(1), 200 CE_INTERRUPT_IDX(0), 201 CE_INTERRUPT_IDX(0), 202 CE_INTERRUPT_IDX(0), 203 CE_INTERRUPT_IDX(0), 204 CE_INTERRUPT_IDX(0), 205 CE_INTERRUPT_IDX(0), 206 #ifdef QCA_WIFI_QCN9224 207 CE_INTERRUPT_IDX(0), 208 CE_INTERRUPT_IDX(0), 209 CE_INTERRUPT_IDX(0), 210 CE_INTERRUPT_IDX(0), 211 #endif 212 } }, 213 /* Interrupt assignment for 5 MSI combination */ 214 {{ CE_INTERRUPT_IDX(0), 215 CE_INTERRUPT_IDX(1), 216 CE_INTERRUPT_IDX(2), 217 CE_INTERRUPT_IDX(3), 218 CE_INTERRUPT_IDX(0), 219 CE_INTERRUPT_IDX(4), 220 CE_INTERRUPT_IDX(0), 221 CE_INTERRUPT_IDX(0), 222 CE_INTERRUPT_IDX(0), 223 CE_INTERRUPT_IDX(0), 224 CE_INTERRUPT_IDX(0), 225 CE_INTERRUPT_IDX(0), 226 #ifdef QCA_WIFI_QCN9224 227 CE_INTERRUPT_IDX(0), 228 CE_INTERRUPT_IDX(0), 229 CE_INTERRUPT_IDX(0), 230 CE_INTERRUPT_IDX(0), 231 #endif 232 } }, 233 /* Interrupt assignment for 6 MSI combination */ 234 {{ CE_INTERRUPT_IDX(0), 235 CE_INTERRUPT_IDX(1), 236 CE_INTERRUPT_IDX(2), 237 CE_INTERRUPT_IDX(3), 238 CE_INTERRUPT_IDX(4), 239 CE_INTERRUPT_IDX(5), 240 CE_INTERRUPT_IDX(0), 241 CE_INTERRUPT_IDX(0), 242 CE_INTERRUPT_IDX(0), 243 CE_INTERRUPT_IDX(0), 244 CE_INTERRUPT_IDX(0), 245 CE_INTERRUPT_IDX(0), 246 #ifdef QCA_WIFI_QCN9224 247 CE_INTERRUPT_IDX(0), 248 CE_INTERRUPT_IDX(0), 249 CE_INTERRUPT_IDX(0), 250 CE_INTERRUPT_IDX(0), 251 #endif 252 } }, 253 /* Interrupt assignment for 7 MSI combination */ 254 {{ CE_INTERRUPT_IDX(0), 255 CE_INTERRUPT_IDX(1), 256 CE_INTERRUPT_IDX(2), 257 CE_INTERRUPT_IDX(3), 258 CE_INTERRUPT_IDX(4), 259 CE_INTERRUPT_IDX(5), 260 CE_INTERRUPT_IDX(6), 261 CE_INTERRUPT_IDX(0), 262 CE_INTERRUPT_IDX(0), 263 CE_INTERRUPT_IDX(0), 264 CE_INTERRUPT_IDX(0), 265 CE_INTERRUPT_IDX(0), 266 #ifdef QCA_WIFI_QCN9224 267 CE_INTERRUPT_IDX(0), 268 CE_INTERRUPT_IDX(0), 269 CE_INTERRUPT_IDX(0), 270 CE_INTERRUPT_IDX(0), 271 #endif 272 } }, 273 /* Interrupt assignment for 8 MSI combination */ 274 {{ CE_INTERRUPT_IDX(0), 275 CE_INTERRUPT_IDX(1), 276 CE_INTERRUPT_IDX(2), 277 CE_INTERRUPT_IDX(3), 278 CE_INTERRUPT_IDX(4), 279 CE_INTERRUPT_IDX(5), 280 CE_INTERRUPT_IDX(6), 281 CE_INTERRUPT_IDX(7), 282 CE_INTERRUPT_IDX(0), 283 CE_INTERRUPT_IDX(0), 284 CE_INTERRUPT_IDX(0), 285 CE_INTERRUPT_IDX(0), 286 #ifdef QCA_WIFI_QCN9224 287 CE_INTERRUPT_IDX(0), 288 CE_INTERRUPT_IDX(0), 289 CE_INTERRUPT_IDX(0), 290 CE_INTERRUPT_IDX(0), 291 #endif 292 } }, 293 /* Interrupt assignment for 9 MSI combination */ 294 {{ CE_INTERRUPT_IDX(0), 295 CE_INTERRUPT_IDX(1), 296 CE_INTERRUPT_IDX(2), 297 CE_INTERRUPT_IDX(3), 298 CE_INTERRUPT_IDX(4), 299 CE_INTERRUPT_IDX(5), 300 CE_INTERRUPT_IDX(6), 301 CE_INTERRUPT_IDX(7), 302 CE_INTERRUPT_IDX(8), 303 CE_INTERRUPT_IDX(0), 304 CE_INTERRUPT_IDX(0), 305 CE_INTERRUPT_IDX(0), 306 #ifdef QCA_WIFI_QCN9224 307 CE_INTERRUPT_IDX(0), 308 CE_INTERRUPT_IDX(0), 309 CE_INTERRUPT_IDX(0), 310 CE_INTERRUPT_IDX(0), 311 #endif 312 } }, 313 /* Interrupt assignment for 10 MSI combination */ 314 {{ CE_INTERRUPT_IDX(0), 315 CE_INTERRUPT_IDX(1), 316 CE_INTERRUPT_IDX(2), 317 CE_INTERRUPT_IDX(3), 318 CE_INTERRUPT_IDX(4), 319 CE_INTERRUPT_IDX(5), 320 CE_INTERRUPT_IDX(6), 321 CE_INTERRUPT_IDX(7), 322 CE_INTERRUPT_IDX(8), 323 CE_INTERRUPT_IDX(9), 324 CE_INTERRUPT_IDX(0), 325 CE_INTERRUPT_IDX(0), 326 #ifdef QCA_WIFI_QCN9224 327 CE_INTERRUPT_IDX(0), 328 CE_INTERRUPT_IDX(0), 329 CE_INTERRUPT_IDX(0), 330 CE_INTERRUPT_IDX(0), 331 #endif 332 } }, 333 /* Interrupt assignment for 11 MSI combination */ 334 {{ CE_INTERRUPT_IDX(0), 335 CE_INTERRUPT_IDX(1), 336 CE_INTERRUPT_IDX(2), 337 CE_INTERRUPT_IDX(3), 338 CE_INTERRUPT_IDX(4), 339 CE_INTERRUPT_IDX(5), 340 CE_INTERRUPT_IDX(6), 341 CE_INTERRUPT_IDX(7), 342 CE_INTERRUPT_IDX(8), 343 CE_INTERRUPT_IDX(9), 344 CE_INTERRUPT_IDX(10), 345 CE_INTERRUPT_IDX(0), 346 #ifdef QCA_WIFI_QCN9224 347 CE_INTERRUPT_IDX(0), 348 CE_INTERRUPT_IDX(0), 349 CE_INTERRUPT_IDX(0), 350 CE_INTERRUPT_IDX(0), 351 #endif 352 } }, 353 /* Interrupt assignment for 12 MSI combination */ 354 {{ CE_INTERRUPT_IDX(0), 355 CE_INTERRUPT_IDX(1), 356 CE_INTERRUPT_IDX(2), 357 CE_INTERRUPT_IDX(3), 358 CE_INTERRUPT_IDX(4), 359 CE_INTERRUPT_IDX(5), 360 CE_INTERRUPT_IDX(6), 361 CE_INTERRUPT_IDX(7), 362 CE_INTERRUPT_IDX(8), 363 CE_INTERRUPT_IDX(9), 364 CE_INTERRUPT_IDX(10), 365 CE_INTERRUPT_IDX(11), 366 #ifdef QCA_WIFI_QCN9224 367 CE_INTERRUPT_IDX(0), 368 CE_INTERRUPT_IDX(0), 369 CE_INTERRUPT_IDX(0), 370 CE_INTERRUPT_IDX(0), 371 #endif 372 } }, 373 #ifdef QCA_WIFI_QCN9224 374 /* Interrupt assignment for 13 MSI combination */ 375 {{ CE_INTERRUPT_IDX(0), 376 CE_INTERRUPT_IDX(1), 377 CE_INTERRUPT_IDX(2), 378 CE_INTERRUPT_IDX(3), 379 CE_INTERRUPT_IDX(4), 380 CE_INTERRUPT_IDX(5), 381 CE_INTERRUPT_IDX(6), 382 CE_INTERRUPT_IDX(7), 383 CE_INTERRUPT_IDX(8), 384 CE_INTERRUPT_IDX(9), 385 CE_INTERRUPT_IDX(10), 386 CE_INTERRUPT_IDX(11), 387 CE_INTERRUPT_IDX(12), 388 CE_INTERRUPT_IDX(0), 389 CE_INTERRUPT_IDX(0), 390 CE_INTERRUPT_IDX(0), 391 } }, 392 /* Interrupt assignment for 14 MSI combination */ 393 {{ CE_INTERRUPT_IDX(0), 394 CE_INTERRUPT_IDX(1), 395 CE_INTERRUPT_IDX(2), 396 CE_INTERRUPT_IDX(3), 397 CE_INTERRUPT_IDX(4), 398 CE_INTERRUPT_IDX(5), 399 CE_INTERRUPT_IDX(6), 400 CE_INTERRUPT_IDX(7), 401 CE_INTERRUPT_IDX(8), 402 CE_INTERRUPT_IDX(9), 403 CE_INTERRUPT_IDX(10), 404 CE_INTERRUPT_IDX(11), 405 CE_INTERRUPT_IDX(12), 406 CE_INTERRUPT_IDX(13), 407 CE_INTERRUPT_IDX(0), 408 CE_INTERRUPT_IDX(0), 409 } }, 410 /* Interrupt assignment for 15 MSI combination */ 411 {{ CE_INTERRUPT_IDX(0), 412 CE_INTERRUPT_IDX(1), 413 CE_INTERRUPT_IDX(2), 414 CE_INTERRUPT_IDX(3), 415 CE_INTERRUPT_IDX(4), 416 CE_INTERRUPT_IDX(5), 417 CE_INTERRUPT_IDX(6), 418 CE_INTERRUPT_IDX(7), 419 CE_INTERRUPT_IDX(8), 420 CE_INTERRUPT_IDX(9), 421 CE_INTERRUPT_IDX(10), 422 CE_INTERRUPT_IDX(11), 423 CE_INTERRUPT_IDX(12), 424 CE_INTERRUPT_IDX(13), 425 CE_INTERRUPT_IDX(14), 426 CE_INTERRUPT_IDX(0), 427 } }, 428 /* Interrupt assignment for 16 MSI combination */ 429 {{ CE_INTERRUPT_IDX(0), 430 CE_INTERRUPT_IDX(1), 431 CE_INTERRUPT_IDX(2), 432 CE_INTERRUPT_IDX(3), 433 CE_INTERRUPT_IDX(4), 434 CE_INTERRUPT_IDX(5), 435 CE_INTERRUPT_IDX(6), 436 CE_INTERRUPT_IDX(7), 437 CE_INTERRUPT_IDX(8), 438 CE_INTERRUPT_IDX(9), 439 CE_INTERRUPT_IDX(10), 440 CE_INTERRUPT_IDX(11), 441 CE_INTERRUPT_IDX(12), 442 CE_INTERRUPT_IDX(13), 443 CE_INTERRUPT_IDX(14), 444 CE_INTERRUPT_IDX(15), 445 } }, 446 #endif 447 }; 448 449 450 void hif_trigger_dump(struct hif_opaque_softc *hif_ctx, 451 uint8_t cmd_id, bool start) 452 { 453 struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); 454 455 switch (cmd_id) { 456 case AGC_DUMP: 457 if (start) 458 priv_start_agc(scn); 459 else 460 priv_dump_agc(scn); 461 break; 462 case CHANINFO_DUMP: 463 if (start) 464 priv_start_cap_chaninfo(scn); 465 else 466 priv_dump_chaninfo(scn); 467 break; 468 case BB_WATCHDOG_DUMP: 469 priv_dump_bbwatchdog(scn); 470 break; 471 #ifdef CONFIG_ATH_PCIE_ACCESS_DEBUG 472 case PCIE_ACCESS_DUMP: 473 hif_target_access_log_dump(); 474 break; 475 #endif 476 default: 477 hif_err("Invalid htc dump command: %d", cmd_id); 478 break; 479 } 480 } 481 482 static void ce_poll_timeout(void *arg) 483 { 484 struct CE_state *CE_state = (struct CE_state *)arg; 485 486 if (CE_state->timer_inited) { 487 ce_per_engine_service(CE_state->scn, CE_state->id); 488 qdf_timer_mod(&CE_state->poll_timer, CE_POLL_TIMEOUT); 489 } 490 } 491 492 static unsigned int roundup_pwr2(unsigned int n) 493 { 494 int i; 495 unsigned int test_pwr2; 496 497 if (!(n & (n - 1))) 498 return n; /* already a power of 2 */ 499 500 test_pwr2 = 4; 501 for (i = 0; i < 29; i++) { 502 if (test_pwr2 > n) 503 return test_pwr2; 504 test_pwr2 = test_pwr2 << 1; 505 } 506 507 QDF_ASSERT(0); /* n too large */ 508 return 0; 509 } 510 511 #define ADRASTEA_SRC_WR_INDEX_OFFSET 0x3C 512 #define ADRASTEA_DST_WR_INDEX_OFFSET 0x40 513 514 static struct shadow_reg_cfg target_shadow_reg_cfg_map[] = { 515 { 0, ADRASTEA_SRC_WR_INDEX_OFFSET}, 516 { 3, ADRASTEA_SRC_WR_INDEX_OFFSET}, 517 { 4, ADRASTEA_SRC_WR_INDEX_OFFSET}, 518 { 5, ADRASTEA_SRC_WR_INDEX_OFFSET}, 519 { 7, ADRASTEA_SRC_WR_INDEX_OFFSET}, 520 { 1, ADRASTEA_DST_WR_INDEX_OFFSET}, 521 { 2, ADRASTEA_DST_WR_INDEX_OFFSET}, 522 { 7, ADRASTEA_DST_WR_INDEX_OFFSET}, 523 { 8, ADRASTEA_DST_WR_INDEX_OFFSET}, 524 #ifdef QCA_WIFI_3_0_ADRASTEA 525 { 9, ADRASTEA_DST_WR_INDEX_OFFSET}, 526 { 10, ADRASTEA_DST_WR_INDEX_OFFSET}, 527 { 11, ADRASTEA_DST_WR_INDEX_OFFSET}, 528 #endif 529 }; 530 531 #ifdef QCN7605_SUPPORT 532 static struct shadow_reg_cfg target_shadow_reg_cfg_map_qcn7605[] = { 533 { 0, ADRASTEA_SRC_WR_INDEX_OFFSET}, 534 { 4, ADRASTEA_SRC_WR_INDEX_OFFSET}, 535 { 5, ADRASTEA_SRC_WR_INDEX_OFFSET}, 536 { 3, ADRASTEA_DST_WR_INDEX_OFFSET}, 537 { 1, ADRASTEA_DST_WR_INDEX_OFFSET}, 538 { 2, ADRASTEA_DST_WR_INDEX_OFFSET}, 539 { 7, ADRASTEA_DST_WR_INDEX_OFFSET}, 540 { 8, ADRASTEA_DST_WR_INDEX_OFFSET}, 541 }; 542 #endif 543 544 #ifdef WLAN_FEATURE_EPPING 545 static struct shadow_reg_cfg target_shadow_reg_cfg_epping[] = { 546 { 0, ADRASTEA_SRC_WR_INDEX_OFFSET}, 547 { 3, ADRASTEA_SRC_WR_INDEX_OFFSET}, 548 { 4, ADRASTEA_SRC_WR_INDEX_OFFSET}, 549 { 7, ADRASTEA_SRC_WR_INDEX_OFFSET}, 550 { 1, ADRASTEA_DST_WR_INDEX_OFFSET}, 551 { 2, ADRASTEA_DST_WR_INDEX_OFFSET}, 552 { 5, ADRASTEA_DST_WR_INDEX_OFFSET}, 553 { 7, ADRASTEA_DST_WR_INDEX_OFFSET}, 554 { 8, ADRASTEA_DST_WR_INDEX_OFFSET}, 555 }; 556 #endif 557 558 /* CE_PCI TABLE */ 559 /* 560 * NOTE: the table below is out of date, though still a useful reference. 561 * Refer to target_service_to_ce_map and hif_map_service_to_pipe for the actual 562 * mapping of HTC services to HIF pipes. 563 */ 564 /* 565 * This authoritative table defines Copy Engine configuration and the mapping 566 * of services/endpoints to CEs. A subset of this information is passed to 567 * the Target during startup as a prerequisite to entering BMI phase. 568 * See: 569 * target_service_to_ce_map - Target-side mapping 570 * hif_map_service_to_pipe - Host-side mapping 571 * target_ce_config - Target-side configuration 572 * host_ce_config - Host-side configuration 573 ============================================================================ 574 Purpose | Service / Endpoint | CE | Dire | Xfer | Xfer 575 | | | ctio | Size | Frequency 576 | | | n | | 577 ============================================================================ 578 tx | HTT_DATA (downlink) | CE 0 | h->t | medium - | very frequent 579 descriptor | | | | O(100B) | and regular 580 download | | | | | 581 ---------------------------------------------------------------------------- 582 rx | HTT_DATA (uplink) | CE 1 | t->h | small - | frequent and 583 indication | | | | O(10B) | regular 584 upload | | | | | 585 ---------------------------------------------------------------------------- 586 MSDU | DATA_BK (uplink) | CE 2 | t->h | large - | rare 587 upload | | | | O(1000B) | (frequent 588 e.g. noise | | | | | during IP1.0 589 packets | | | | | testing) 590 ---------------------------------------------------------------------------- 591 MSDU | DATA_BK (downlink) | CE 3 | h->t | large - | very rare 592 download | | | | O(1000B) | (frequent 593 e.g. | | | | | during IP1.0 594 misdirecte | | | | | testing) 595 d EAPOL | | | | | 596 packets | | | | | 597 ---------------------------------------------------------------------------- 598 n/a | DATA_BE, DATA_VI | CE 2 | t->h | | never(?) 599 | DATA_VO (uplink) | | | | 600 ---------------------------------------------------------------------------- 601 n/a | DATA_BE, DATA_VI | CE 3 | h->t | | never(?) 602 | DATA_VO (downlink) | | | | 603 ---------------------------------------------------------------------------- 604 WMI events | WMI_CONTROL (uplink) | CE 4 | t->h | medium - | infrequent 605 | | | | O(100B) | 606 ---------------------------------------------------------------------------- 607 WMI | WMI_CONTROL | CE 5 | h->t | medium - | infrequent 608 messages | (downlink) | | | O(100B) | 609 | | | | | 610 ---------------------------------------------------------------------------- 611 n/a | HTC_CTRL_RSVD, | CE 1 | t->h | | never(?) 612 | HTC_RAW_STREAMS | | | | 613 | (uplink) | | | | 614 ---------------------------------------------------------------------------- 615 n/a | HTC_CTRL_RSVD, | CE 0 | h->t | | never(?) 616 | HTC_RAW_STREAMS | | | | 617 | (downlink) | | | | 618 ---------------------------------------------------------------------------- 619 diag | none (raw CE) | CE 7 | t<>h | 4 | Diag Window 620 | | | | | infrequent 621 ============================================================================ 622 */ 623 624 /* 625 * Map from service/endpoint to Copy Engine. 626 * This table is derived from the CE_PCI TABLE, above. 627 * It is passed to the Target at startup for use by firmware. 628 */ 629 static struct service_to_pipe target_service_to_ce_map_wlan[] = { 630 { 631 WMI_DATA_VO_SVC, 632 PIPEDIR_OUT, /* out = UL = host -> target */ 633 3, 634 }, 635 { 636 WMI_DATA_VO_SVC, 637 PIPEDIR_IN, /* in = DL = target -> host */ 638 2, 639 }, 640 { 641 WMI_DATA_BK_SVC, 642 PIPEDIR_OUT, /* out = UL = host -> target */ 643 3, 644 }, 645 { 646 WMI_DATA_BK_SVC, 647 PIPEDIR_IN, /* in = DL = target -> host */ 648 2, 649 }, 650 { 651 WMI_DATA_BE_SVC, 652 PIPEDIR_OUT, /* out = UL = host -> target */ 653 3, 654 }, 655 { 656 WMI_DATA_BE_SVC, 657 PIPEDIR_IN, /* in = DL = target -> host */ 658 2, 659 }, 660 { 661 WMI_DATA_VI_SVC, 662 PIPEDIR_OUT, /* out = UL = host -> target */ 663 3, 664 }, 665 { 666 WMI_DATA_VI_SVC, 667 PIPEDIR_IN, /* in = DL = target -> host */ 668 2, 669 }, 670 { 671 WMI_CONTROL_SVC, 672 PIPEDIR_OUT, /* out = UL = host -> target */ 673 3, 674 }, 675 { 676 WMI_CONTROL_SVC, 677 PIPEDIR_IN, /* in = DL = target -> host */ 678 2, 679 }, 680 { 681 HTC_CTRL_RSVD_SVC, 682 PIPEDIR_OUT, /* out = UL = host -> target */ 683 0, /* could be moved to 3 (share with WMI) */ 684 }, 685 { 686 HTC_CTRL_RSVD_SVC, 687 PIPEDIR_IN, /* in = DL = target -> host */ 688 2, 689 }, 690 { 691 HTC_RAW_STREAMS_SVC, /* not currently used */ 692 PIPEDIR_OUT, /* out = UL = host -> target */ 693 0, 694 }, 695 { 696 HTC_RAW_STREAMS_SVC, /* not currently used */ 697 PIPEDIR_IN, /* in = DL = target -> host */ 698 2, 699 }, 700 { 701 HTT_DATA_MSG_SVC, 702 PIPEDIR_OUT, /* out = UL = host -> target */ 703 4, 704 }, 705 { 706 HTT_DATA_MSG_SVC, 707 PIPEDIR_IN, /* in = DL = target -> host */ 708 1, 709 }, 710 { 711 WDI_IPA_TX_SVC, 712 PIPEDIR_OUT, /* in = DL = target -> host */ 713 5, 714 }, 715 #if defined(QCA_WIFI_3_0_ADRASTEA) 716 { 717 HTT_DATA2_MSG_SVC, 718 PIPEDIR_IN, /* in = DL = target -> host */ 719 9, 720 }, 721 { 722 HTT_DATA3_MSG_SVC, 723 PIPEDIR_IN, /* in = DL = target -> host */ 724 10, 725 }, 726 { 727 PACKET_LOG_SVC, 728 PIPEDIR_IN, /* in = DL = target -> host */ 729 11, 730 }, 731 #endif 732 /* (Additions here) */ 733 734 { /* Must be last */ 735 0, 736 0, 737 0, 738 }, 739 }; 740 741 /* PIPEDIR_OUT = HOST to Target */ 742 /* PIPEDIR_IN = TARGET to HOST */ 743 #if (defined(QCA_WIFI_QCA8074)) 744 static struct service_to_pipe target_service_to_ce_map_qca8074[] = { 745 { WMI_DATA_VO_SVC, PIPEDIR_OUT, 3, }, 746 { WMI_DATA_VO_SVC, PIPEDIR_IN, 2, }, 747 { WMI_DATA_BK_SVC, PIPEDIR_OUT, 3, }, 748 { WMI_DATA_BK_SVC, PIPEDIR_IN, 2, }, 749 { WMI_DATA_BE_SVC, PIPEDIR_OUT, 3, }, 750 { WMI_DATA_BE_SVC, PIPEDIR_IN, 2, }, 751 { WMI_DATA_VI_SVC, PIPEDIR_OUT, 3, }, 752 { WMI_DATA_VI_SVC, PIPEDIR_IN, 2, }, 753 { WMI_CONTROL_SVC, PIPEDIR_OUT, 3, }, 754 { WMI_CONTROL_SVC, PIPEDIR_IN, 2, }, 755 { WMI_CONTROL_SVC_WMAC1, PIPEDIR_OUT, 7}, 756 { WMI_CONTROL_SVC_WMAC1, PIPEDIR_IN, 2}, 757 { HTC_CTRL_RSVD_SVC, PIPEDIR_OUT, 0, }, 758 { HTC_CTRL_RSVD_SVC, PIPEDIR_IN, 1, }, 759 { HTC_RAW_STREAMS_SVC, PIPEDIR_OUT, 0}, 760 { HTC_RAW_STREAMS_SVC, PIPEDIR_IN, 1 }, 761 { HTT_DATA_MSG_SVC, PIPEDIR_OUT, 4, }, 762 { HTT_DATA_MSG_SVC, PIPEDIR_IN, 1, }, 763 { PACKET_LOG_SVC, PIPEDIR_IN, 5, }, 764 /* (Additions here) */ 765 { 0, 0, 0, }, 766 }; 767 #else 768 static struct service_to_pipe target_service_to_ce_map_qca8074[] = { 769 }; 770 #endif 771 772 #if (defined(QCA_WIFI_QCA9574)) 773 static struct service_to_pipe target_service_to_ce_map_qca9574[] = { 774 { WMI_DATA_VO_SVC, PIPEDIR_OUT, 3, }, 775 { WMI_DATA_VO_SVC, PIPEDIR_IN, 2, }, 776 { WMI_DATA_BK_SVC, PIPEDIR_OUT, 3, }, 777 { WMI_DATA_BK_SVC, PIPEDIR_IN, 2, }, 778 { WMI_DATA_BE_SVC, PIPEDIR_OUT, 3, }, 779 { WMI_DATA_BE_SVC, PIPEDIR_IN, 2, }, 780 { WMI_DATA_VI_SVC, PIPEDIR_OUT, 3, }, 781 { WMI_DATA_VI_SVC, PIPEDIR_IN, 2, }, 782 { WMI_CONTROL_SVC, PIPEDIR_OUT, 3, }, 783 { WMI_CONTROL_SVC, PIPEDIR_IN, 2, }, 784 { WMI_CONTROL_SVC_WMAC1, PIPEDIR_OUT, 7}, 785 { WMI_CONTROL_SVC_WMAC1, PIPEDIR_IN, 2}, 786 { HTC_CTRL_RSVD_SVC, PIPEDIR_OUT, 0, }, 787 { HTC_CTRL_RSVD_SVC, PIPEDIR_IN, 1, }, 788 { HTC_RAW_STREAMS_SVC, PIPEDIR_OUT, 0}, 789 { HTC_RAW_STREAMS_SVC, PIPEDIR_IN, 1 }, 790 { HTT_DATA_MSG_SVC, PIPEDIR_OUT, 4, }, 791 { HTT_DATA_MSG_SVC, PIPEDIR_IN, 1, }, 792 { PACKET_LOG_SVC, PIPEDIR_IN, 5, }, 793 /* (Additions here) */ 794 { 0, 0, 0, }, 795 }; 796 #else 797 static struct service_to_pipe target_service_to_ce_map_qca9574[] = { 798 }; 799 #endif 800 801 #if (defined(QCA_WIFI_QCA8074V2)) 802 static struct service_to_pipe target_service_to_ce_map_qca8074_v2[] = { 803 { WMI_DATA_VO_SVC, PIPEDIR_OUT, 3, }, 804 { WMI_DATA_VO_SVC, PIPEDIR_IN, 2, }, 805 { WMI_DATA_BK_SVC, PIPEDIR_OUT, 3, }, 806 { WMI_DATA_BK_SVC, PIPEDIR_IN, 2, }, 807 { WMI_DATA_BE_SVC, PIPEDIR_OUT, 3, }, 808 { WMI_DATA_BE_SVC, PIPEDIR_IN, 2, }, 809 { WMI_DATA_VI_SVC, PIPEDIR_OUT, 3, }, 810 { WMI_DATA_VI_SVC, PIPEDIR_IN, 2, }, 811 { WMI_CONTROL_SVC, PIPEDIR_OUT, 3, }, 812 { WMI_CONTROL_SVC, PIPEDIR_IN, 2, }, 813 { WMI_CONTROL_SVC_WMAC1, PIPEDIR_OUT, 7}, 814 { WMI_CONTROL_SVC_WMAC1, PIPEDIR_IN, 2}, 815 { WMI_CONTROL_SVC_WMAC2, PIPEDIR_OUT, 9}, 816 { WMI_CONTROL_SVC_WMAC2, PIPEDIR_IN, 2}, 817 { HTC_CTRL_RSVD_SVC, PIPEDIR_OUT, 0, }, 818 { HTC_CTRL_RSVD_SVC, PIPEDIR_IN, 1, }, 819 { HTC_RAW_STREAMS_SVC, PIPEDIR_OUT, 0}, 820 { HTC_RAW_STREAMS_SVC, PIPEDIR_IN, 1 }, 821 { HTT_DATA_MSG_SVC, PIPEDIR_OUT, 4, }, 822 { HTT_DATA_MSG_SVC, PIPEDIR_IN, 1, }, 823 { PACKET_LOG_SVC, PIPEDIR_IN, 5, }, 824 /* (Additions here) */ 825 { 0, 0, 0, }, 826 }; 827 #else 828 static struct service_to_pipe target_service_to_ce_map_qca8074_v2[] = { 829 }; 830 #endif 831 832 #if (defined(QCA_WIFI_QCA6018)) 833 static struct service_to_pipe target_service_to_ce_map_qca6018[] = { 834 { WMI_DATA_VO_SVC, PIPEDIR_OUT, 3, }, 835 { WMI_DATA_VO_SVC, PIPEDIR_IN, 2, }, 836 { WMI_DATA_BK_SVC, PIPEDIR_OUT, 3, }, 837 { WMI_DATA_BK_SVC, PIPEDIR_IN, 2, }, 838 { WMI_DATA_BE_SVC, PIPEDIR_OUT, 3, }, 839 { WMI_DATA_BE_SVC, PIPEDIR_IN, 2, }, 840 { WMI_DATA_VI_SVC, PIPEDIR_OUT, 3, }, 841 { WMI_DATA_VI_SVC, PIPEDIR_IN, 2, }, 842 { WMI_CONTROL_SVC, PIPEDIR_OUT, 3, }, 843 { WMI_CONTROL_SVC, PIPEDIR_IN, 2, }, 844 { WMI_CONTROL_SVC_WMAC1, PIPEDIR_OUT, 7}, 845 { WMI_CONTROL_SVC_WMAC1, PIPEDIR_IN, 2}, 846 { HTC_CTRL_RSVD_SVC, PIPEDIR_OUT, 0, }, 847 { HTC_CTRL_RSVD_SVC, PIPEDIR_IN, 1, }, 848 { HTC_RAW_STREAMS_SVC, PIPEDIR_OUT, 0}, 849 { HTC_RAW_STREAMS_SVC, PIPEDIR_IN, 1 }, 850 { HTT_DATA_MSG_SVC, PIPEDIR_OUT, 4, }, 851 { HTT_DATA_MSG_SVC, PIPEDIR_IN, 1, }, 852 { PACKET_LOG_SVC, PIPEDIR_IN, 5, }, 853 /* (Additions here) */ 854 { 0, 0, 0, }, 855 }; 856 #else 857 static struct service_to_pipe target_service_to_ce_map_qca6018[] = { 858 }; 859 #endif 860 861 #if (defined(QCA_WIFI_QCN9000)) 862 static struct service_to_pipe target_service_to_ce_map_qcn9000[] = { 863 { WMI_DATA_VO_SVC, PIPEDIR_OUT, 3, }, 864 { WMI_DATA_VO_SVC, PIPEDIR_IN, 2, }, 865 { WMI_DATA_BK_SVC, PIPEDIR_OUT, 3, }, 866 { WMI_DATA_BK_SVC, PIPEDIR_IN, 2, }, 867 { WMI_DATA_BE_SVC, PIPEDIR_OUT, 3, }, 868 { WMI_DATA_BE_SVC, PIPEDIR_IN, 2, }, 869 { WMI_DATA_VI_SVC, PIPEDIR_OUT, 3, }, 870 { WMI_DATA_VI_SVC, PIPEDIR_IN, 2, }, 871 { WMI_CONTROL_SVC, PIPEDIR_OUT, 3, }, 872 { WMI_CONTROL_SVC, PIPEDIR_IN, 2, }, 873 { HTC_CTRL_RSVD_SVC, PIPEDIR_OUT, 0, }, 874 { HTC_CTRL_RSVD_SVC, PIPEDIR_IN, 1, }, 875 { HTC_RAW_STREAMS_SVC, PIPEDIR_OUT, 0}, 876 { HTC_RAW_STREAMS_SVC, PIPEDIR_IN, 1 }, 877 { HTT_DATA_MSG_SVC, PIPEDIR_OUT, 4, }, 878 { HTT_DATA_MSG_SVC, PIPEDIR_IN, 1, }, 879 { PACKET_LOG_SVC, PIPEDIR_IN, 5, }, 880 /* (Additions here) */ 881 { 0, 0, 0, }, 882 }; 883 #else 884 static struct service_to_pipe target_service_to_ce_map_qcn9000[] = { 885 }; 886 #endif 887 888 #if (defined(QCA_WIFI_QCA5332)) 889 static struct service_to_pipe target_service_to_ce_map_qca5332[] = { 890 { WMI_DATA_VO_SVC, PIPEDIR_OUT, 3, }, 891 { WMI_DATA_VO_SVC, PIPEDIR_IN, 2, }, 892 { WMI_DATA_BK_SVC, PIPEDIR_OUT, 3, }, 893 { WMI_DATA_BK_SVC, PIPEDIR_IN, 2, }, 894 { WMI_DATA_BE_SVC, PIPEDIR_OUT, 3, }, 895 { WMI_DATA_BE_SVC, PIPEDIR_IN, 2, }, 896 { WMI_DATA_VI_SVC, PIPEDIR_OUT, 3, }, 897 { WMI_DATA_VI_SVC, PIPEDIR_IN, 2, }, 898 { WMI_CONTROL_SVC, PIPEDIR_OUT, 3, }, 899 { WMI_CONTROL_SVC, PIPEDIR_IN, 2, }, 900 { HTC_CTRL_RSVD_SVC, PIPEDIR_OUT, 0, }, 901 { HTC_CTRL_RSVD_SVC, PIPEDIR_IN, 1, }, 902 { HTC_RAW_STREAMS_SVC, PIPEDIR_OUT, 0}, 903 { HTC_RAW_STREAMS_SVC, PIPEDIR_IN, 1 }, 904 { HTT_DATA_MSG_SVC, PIPEDIR_OUT, 4, }, 905 { HTT_DATA_MSG_SVC, PIPEDIR_IN, 1, }, 906 { PACKET_LOG_SVC, PIPEDIR_IN, 5, }, 907 { WMI_CONTROL_DIAG_SVC, PIPEDIR_IN, 9, }, 908 /* (Additions here) */ 909 { 0, 0, 0, }, 910 }; 911 #else 912 static struct service_to_pipe target_service_to_ce_map_qca5332[] = { 913 }; 914 #endif 915 916 #if (defined(QCA_WIFI_QCN9224)) 917 static struct service_to_pipe target_service_to_ce_map_qcn9224[] = { 918 { WMI_DATA_VO_SVC, PIPEDIR_OUT, 3, }, 919 { WMI_DATA_VO_SVC, PIPEDIR_IN, 2, }, 920 { WMI_DATA_BK_SVC, PIPEDIR_OUT, 3, }, 921 { WMI_DATA_BK_SVC, PIPEDIR_IN, 2, }, 922 { WMI_DATA_BE_SVC, PIPEDIR_OUT, 3, }, 923 { WMI_DATA_BE_SVC, PIPEDIR_IN, 2, }, 924 { WMI_DATA_VI_SVC, PIPEDIR_OUT, 3, }, 925 { WMI_DATA_VI_SVC, PIPEDIR_IN, 2, }, 926 { WMI_CONTROL_SVC, PIPEDIR_OUT, 3, }, 927 { WMI_CONTROL_SVC, PIPEDIR_IN, 2, }, 928 { HTC_CTRL_RSVD_SVC, PIPEDIR_OUT, 0, }, 929 { HTC_CTRL_RSVD_SVC, PIPEDIR_IN, 1, }, 930 { HTC_RAW_STREAMS_SVC, PIPEDIR_OUT, 0}, 931 { HTC_RAW_STREAMS_SVC, PIPEDIR_IN, 1 }, 932 { HTT_DATA_MSG_SVC, PIPEDIR_OUT, 4, }, 933 { HTT_DATA_MSG_SVC, PIPEDIR_IN, 1, }, 934 { WMI_CONTROL_SVC_WMAC1, PIPEDIR_OUT, 7, }, 935 { WMI_CONTROL_SVC_WMAC1, PIPEDIR_IN, 2, }, 936 { PACKET_LOG_SVC, PIPEDIR_IN, 5, }, 937 { WMI_CONTROL_DIAG_SVC, PIPEDIR_IN, 14, }, 938 { WMI_CONTROL_DBR_SVC, PIPEDIR_IN, 14, }, 939 /* (Additions here) */ 940 { 0, 0, 0, }, 941 }; 942 #endif 943 944 #if (defined(QCA_WIFI_QCA5018)) 945 static struct service_to_pipe target_service_to_ce_map_qca5018[] = { 946 { WMI_DATA_VO_SVC, PIPEDIR_OUT, 3, }, 947 { WMI_DATA_VO_SVC, PIPEDIR_IN, 2, }, 948 { WMI_DATA_BK_SVC, PIPEDIR_OUT, 3, }, 949 { WMI_DATA_BK_SVC, PIPEDIR_IN, 2, }, 950 { WMI_DATA_BE_SVC, PIPEDIR_OUT, 3, }, 951 { WMI_DATA_BE_SVC, PIPEDIR_IN, 2, }, 952 { WMI_DATA_VI_SVC, PIPEDIR_OUT, 3, }, 953 { WMI_DATA_VI_SVC, PIPEDIR_IN, 2, }, 954 { WMI_CONTROL_SVC, PIPEDIR_OUT, 3, }, 955 { WMI_CONTROL_SVC, PIPEDIR_IN, 2, }, 956 { HTC_CTRL_RSVD_SVC, PIPEDIR_OUT, 0, }, 957 { HTC_CTRL_RSVD_SVC, PIPEDIR_IN, 1, }, 958 { HTC_RAW_STREAMS_SVC, PIPEDIR_OUT, 0}, 959 { HTC_RAW_STREAMS_SVC, PIPEDIR_IN, 1 }, 960 { HTT_DATA_MSG_SVC, PIPEDIR_OUT, 4, }, 961 { HTT_DATA_MSG_SVC, PIPEDIR_IN, 1, }, 962 { PACKET_LOG_SVC, PIPEDIR_IN, 5, }, 963 /* (Additions here) */ 964 { 0, 0, 0, }, 965 }; 966 #else 967 static struct service_to_pipe target_service_to_ce_map_qca5018[] = { 968 }; 969 #endif 970 971 /* PIPEDIR_OUT = HOST to Target */ 972 /* PIPEDIR_IN = TARGET to HOST */ 973 #ifdef QCN7605_SUPPORT 974 static struct service_to_pipe target_service_to_ce_map_qcn7605[] = { 975 { WMI_DATA_VO_SVC, PIPEDIR_OUT, 0, }, 976 { WMI_DATA_VO_SVC, PIPEDIR_IN, 2, }, 977 { WMI_DATA_BK_SVC, PIPEDIR_OUT, 0, }, 978 { WMI_DATA_BK_SVC, PIPEDIR_IN, 2, }, 979 { WMI_DATA_BE_SVC, PIPEDIR_OUT, 0, }, 980 { WMI_DATA_BE_SVC, PIPEDIR_IN, 2, }, 981 { WMI_DATA_VI_SVC, PIPEDIR_OUT, 0, }, 982 { WMI_DATA_VI_SVC, PIPEDIR_IN, 2, }, 983 { WMI_CONTROL_SVC, PIPEDIR_OUT, 0, }, 984 { WMI_CONTROL_SVC, PIPEDIR_IN, 2, }, 985 { HTC_CTRL_RSVD_SVC, PIPEDIR_OUT, 0, }, 986 { HTC_CTRL_RSVD_SVC, PIPEDIR_IN, 2, }, 987 { HTC_RAW_STREAMS_SVC, PIPEDIR_OUT, 0, }, 988 { HTC_RAW_STREAMS_SVC, PIPEDIR_IN, 2, }, 989 { HTT_DATA_MSG_SVC, PIPEDIR_OUT, 4, }, 990 { HTT_DATA_MSG_SVC, PIPEDIR_IN, 1, }, 991 { HTT_DATA2_MSG_SVC, PIPEDIR_IN, 3, }, 992 #ifdef IPA_OFFLOAD 993 { WDI_IPA_TX_SVC, PIPEDIR_OUT, 5, }, 994 #else 995 { HTT_DATA3_MSG_SVC, PIPEDIR_IN, 8, }, 996 #endif 997 { PACKET_LOG_SVC, PIPEDIR_IN, 7, }, 998 /* (Additions here) */ 999 { 0, 0, 0, }, 1000 }; 1001 #endif 1002 1003 #if (defined(QCA_WIFI_QCA6290)) 1004 #ifdef QCA_6290_AP_MODE 1005 static struct service_to_pipe target_service_to_ce_map_qca6290[] = { 1006 { WMI_DATA_VO_SVC, PIPEDIR_OUT, 3, }, 1007 { WMI_DATA_VO_SVC, PIPEDIR_IN , 2, }, 1008 { WMI_DATA_BK_SVC, PIPEDIR_OUT, 3, }, 1009 { WMI_DATA_BK_SVC, PIPEDIR_IN , 2, }, 1010 { WMI_DATA_BE_SVC, PIPEDIR_OUT, 3, }, 1011 { WMI_DATA_BE_SVC, PIPEDIR_IN , 2, }, 1012 { WMI_DATA_VI_SVC, PIPEDIR_OUT, 3, }, 1013 { WMI_DATA_VI_SVC, PIPEDIR_IN , 2, }, 1014 { WMI_CONTROL_SVC, PIPEDIR_OUT, 3, }, 1015 { WMI_CONTROL_SVC, PIPEDIR_IN , 2, }, 1016 { HTC_CTRL_RSVD_SVC, PIPEDIR_OUT, 0, }, 1017 { HTC_CTRL_RSVD_SVC, PIPEDIR_IN , 2, }, 1018 { HTT_DATA_MSG_SVC, PIPEDIR_OUT, 4, }, 1019 { HTT_DATA_MSG_SVC, PIPEDIR_IN , 1, }, 1020 { WMI_CONTROL_SVC_WMAC1, PIPEDIR_OUT, 7}, 1021 { WMI_CONTROL_SVC_WMAC1, PIPEDIR_IN, 2}, 1022 { PACKET_LOG_SVC, PIPEDIR_IN, 5, }, 1023 /* (Additions here) */ 1024 { 0, 0, 0, }, 1025 }; 1026 #else 1027 static struct service_to_pipe target_service_to_ce_map_qca6290[] = { 1028 { WMI_DATA_VO_SVC, PIPEDIR_OUT, 3, }, 1029 { WMI_DATA_VO_SVC, PIPEDIR_IN, 2, }, 1030 { WMI_DATA_BK_SVC, PIPEDIR_OUT, 3, }, 1031 { WMI_DATA_BK_SVC, PIPEDIR_IN, 2, }, 1032 { WMI_DATA_BE_SVC, PIPEDIR_OUT, 3, }, 1033 { WMI_DATA_BE_SVC, PIPEDIR_IN, 2, }, 1034 { WMI_DATA_VI_SVC, PIPEDIR_OUT, 3, }, 1035 { WMI_DATA_VI_SVC, PIPEDIR_IN, 2, }, 1036 { WMI_CONTROL_SVC, PIPEDIR_OUT, 3, }, 1037 { WMI_CONTROL_SVC, PIPEDIR_IN, 2, }, 1038 { HTC_CTRL_RSVD_SVC, PIPEDIR_OUT, 0, }, 1039 { HTC_CTRL_RSVD_SVC, PIPEDIR_IN, 2, }, 1040 { HTT_DATA_MSG_SVC, PIPEDIR_OUT, 4, }, 1041 { HTT_DATA_MSG_SVC, PIPEDIR_IN, 1, }, 1042 /* (Additions here) */ 1043 { 0, 0, 0, }, 1044 }; 1045 #endif 1046 #else 1047 static struct service_to_pipe target_service_to_ce_map_qca6290[] = { 1048 }; 1049 #endif 1050 1051 #if (defined(QCA_WIFI_QCA6390)) 1052 static struct service_to_pipe target_service_to_ce_map_qca6390[] = { 1053 { WMI_DATA_VO_SVC, PIPEDIR_OUT, 3, }, 1054 { WMI_DATA_VO_SVC, PIPEDIR_IN, 2, }, 1055 { WMI_DATA_BK_SVC, PIPEDIR_OUT, 3, }, 1056 { WMI_DATA_BK_SVC, PIPEDIR_IN, 2, }, 1057 { WMI_DATA_BE_SVC, PIPEDIR_OUT, 3, }, 1058 { WMI_DATA_BE_SVC, PIPEDIR_IN, 2, }, 1059 { WMI_DATA_VI_SVC, PIPEDIR_OUT, 3, }, 1060 { WMI_DATA_VI_SVC, PIPEDIR_IN, 2, }, 1061 { WMI_CONTROL_SVC, PIPEDIR_OUT, 3, }, 1062 { WMI_CONTROL_SVC, PIPEDIR_IN, 2, }, 1063 { HTC_CTRL_RSVD_SVC, PIPEDIR_OUT, 0, }, 1064 { HTC_CTRL_RSVD_SVC, PIPEDIR_IN, 2, }, 1065 { HTT_DATA_MSG_SVC, PIPEDIR_OUT, 4, }, 1066 { HTT_DATA_MSG_SVC, PIPEDIR_IN, 1, }, 1067 { PACKET_LOG_SVC, PIPEDIR_IN, 5, }, 1068 /* (Additions here) */ 1069 { 0, 0, 0, }, 1070 }; 1071 #else 1072 static struct service_to_pipe target_service_to_ce_map_qca6390[] = { 1073 }; 1074 #endif 1075 1076 static struct service_to_pipe target_service_to_ce_map_qca6490[] = { 1077 { WMI_DATA_VO_SVC, PIPEDIR_OUT, 3, }, 1078 { WMI_DATA_VO_SVC, PIPEDIR_IN, 2, }, 1079 { WMI_DATA_BK_SVC, PIPEDIR_OUT, 3, }, 1080 { WMI_DATA_BK_SVC, PIPEDIR_IN, 2, }, 1081 { WMI_DATA_BE_SVC, PIPEDIR_OUT, 3, }, 1082 { WMI_DATA_BE_SVC, PIPEDIR_IN, 2, }, 1083 { WMI_DATA_VI_SVC, PIPEDIR_OUT, 3, }, 1084 { WMI_DATA_VI_SVC, PIPEDIR_IN, 2, }, 1085 { WMI_CONTROL_SVC, PIPEDIR_OUT, 3, }, 1086 { WMI_CONTROL_SVC, PIPEDIR_IN, 2, }, 1087 { HTC_CTRL_RSVD_SVC, PIPEDIR_OUT, 0, }, 1088 { HTC_CTRL_RSVD_SVC, PIPEDIR_IN, 2, }, 1089 { HTT_DATA_MSG_SVC, PIPEDIR_OUT, 4, }, 1090 { HTT_DATA_MSG_SVC, PIPEDIR_IN, 1, }, 1091 { PACKET_LOG_SVC, PIPEDIR_IN, 5, }, 1092 /* (Additions here) */ 1093 { 0, 0, 0, }, 1094 }; 1095 1096 #if (defined(QCA_WIFI_QCA6750)) 1097 static struct service_to_pipe target_service_to_ce_map_qca6750[] = { 1098 { WMI_DATA_VO_SVC, PIPEDIR_OUT, 3, }, 1099 { WMI_DATA_VO_SVC, PIPEDIR_IN, 2, }, 1100 { WMI_DATA_BK_SVC, PIPEDIR_OUT, 3, }, 1101 { WMI_DATA_BK_SVC, PIPEDIR_IN, 2, }, 1102 { WMI_DATA_BE_SVC, PIPEDIR_OUT, 3, }, 1103 { WMI_DATA_BE_SVC, PIPEDIR_IN, 2, }, 1104 { WMI_DATA_VI_SVC, PIPEDIR_OUT, 3, }, 1105 { WMI_DATA_VI_SVC, PIPEDIR_IN, 2, }, 1106 { WMI_CONTROL_SVC, PIPEDIR_OUT, 3, }, 1107 { WMI_CONTROL_SVC, PIPEDIR_IN, 2, }, 1108 { HTC_CTRL_RSVD_SVC, PIPEDIR_OUT, 0, }, 1109 { HTC_CTRL_RSVD_SVC, PIPEDIR_IN, 2, }, 1110 { HTT_DATA_MSG_SVC, PIPEDIR_OUT, 4, }, 1111 { HTT_DATA_MSG_SVC, PIPEDIR_IN, 1, }, 1112 { PACKET_LOG_SVC, PIPEDIR_IN, 5, }, 1113 #ifdef WLAN_FEATURE_WMI_DIAG_OVER_CE7 1114 { WMI_CONTROL_DIAG_SVC, PIPEDIR_IN, 7, }, 1115 #endif 1116 /* (Additions here) */ 1117 { 0, 0, 0, }, 1118 }; 1119 #else 1120 static struct service_to_pipe target_service_to_ce_map_qca6750[] = { 1121 }; 1122 #endif 1123 1124 #if (defined(QCA_WIFI_KIWI)) 1125 static struct service_to_pipe target_service_to_ce_map_kiwi[] = { 1126 { WMI_DATA_VO_SVC, PIPEDIR_OUT, 3, }, 1127 { WMI_DATA_VO_SVC, PIPEDIR_IN, 2, }, 1128 { WMI_DATA_BK_SVC, PIPEDIR_OUT, 3, }, 1129 { WMI_DATA_BK_SVC, PIPEDIR_IN, 2, }, 1130 { WMI_DATA_BE_SVC, PIPEDIR_OUT, 3, }, 1131 { WMI_DATA_BE_SVC, PIPEDIR_IN, 2, }, 1132 { WMI_DATA_VI_SVC, PIPEDIR_OUT, 3, }, 1133 { WMI_DATA_VI_SVC, PIPEDIR_IN, 2, }, 1134 { WMI_CONTROL_SVC, PIPEDIR_OUT, 3, }, 1135 { WMI_CONTROL_SVC, PIPEDIR_IN, 2, }, 1136 #ifdef FEATURE_XPAN 1137 { HTC_CTRL_RSVD_SVC, PIPEDIR_OUT, 4, }, 1138 #else 1139 { HTC_CTRL_RSVD_SVC, PIPEDIR_OUT, 0, }, 1140 #endif 1141 { HTC_CTRL_RSVD_SVC, PIPEDIR_IN, 2, }, 1142 { HTT_DATA_MSG_SVC, PIPEDIR_OUT, 4, }, 1143 { HTT_DATA_MSG_SVC, PIPEDIR_IN, 1, }, 1144 #ifdef WLAN_FEATURE_WMI_DIAG_OVER_CE7 1145 { WMI_CONTROL_DIAG_SVC, PIPEDIR_IN, 7, }, 1146 #endif 1147 #ifdef FEATURE_XPAN 1148 { LPASS_DATA_MSG_SVC, PIPEDIR_OUT, 0, }, 1149 { LPASS_DATA_MSG_SVC, PIPEDIR_IN, 5, }, 1150 #endif 1151 /* (Additions here) */ 1152 { 0, 0, 0, }, 1153 }; 1154 #else 1155 static struct service_to_pipe target_service_to_ce_map_kiwi[] = { 1156 }; 1157 #endif 1158 1159 static struct service_to_pipe target_service_to_ce_map_ar900b[] = { 1160 { 1161 WMI_DATA_VO_SVC, 1162 PIPEDIR_OUT, /* out = UL = host -> target */ 1163 3, 1164 }, 1165 { 1166 WMI_DATA_VO_SVC, 1167 PIPEDIR_IN, /* in = DL = target -> host */ 1168 2, 1169 }, 1170 { 1171 WMI_DATA_BK_SVC, 1172 PIPEDIR_OUT, /* out = UL = host -> target */ 1173 3, 1174 }, 1175 { 1176 WMI_DATA_BK_SVC, 1177 PIPEDIR_IN, /* in = DL = target -> host */ 1178 2, 1179 }, 1180 { 1181 WMI_DATA_BE_SVC, 1182 PIPEDIR_OUT, /* out = UL = host -> target */ 1183 3, 1184 }, 1185 { 1186 WMI_DATA_BE_SVC, 1187 PIPEDIR_IN, /* in = DL = target -> host */ 1188 2, 1189 }, 1190 { 1191 WMI_DATA_VI_SVC, 1192 PIPEDIR_OUT, /* out = UL = host -> target */ 1193 3, 1194 }, 1195 { 1196 WMI_DATA_VI_SVC, 1197 PIPEDIR_IN, /* in = DL = target -> host */ 1198 2, 1199 }, 1200 { 1201 WMI_CONTROL_SVC, 1202 PIPEDIR_OUT, /* out = UL = host -> target */ 1203 3, 1204 }, 1205 { 1206 WMI_CONTROL_SVC, 1207 PIPEDIR_IN, /* in = DL = target -> host */ 1208 2, 1209 }, 1210 { 1211 HTC_CTRL_RSVD_SVC, 1212 PIPEDIR_OUT, /* out = UL = host -> target */ 1213 0, /* could be moved to 3 (share with WMI) */ 1214 }, 1215 { 1216 HTC_CTRL_RSVD_SVC, 1217 PIPEDIR_IN, /* in = DL = target -> host */ 1218 1, 1219 }, 1220 { 1221 HTC_RAW_STREAMS_SVC, /* not currently used */ 1222 PIPEDIR_OUT, /* out = UL = host -> target */ 1223 0, 1224 }, 1225 { 1226 HTC_RAW_STREAMS_SVC, /* not currently used */ 1227 PIPEDIR_IN, /* in = DL = target -> host */ 1228 1, 1229 }, 1230 { 1231 HTT_DATA_MSG_SVC, 1232 PIPEDIR_OUT, /* out = UL = host -> target */ 1233 4, 1234 }, 1235 #ifdef WLAN_FEATURE_FASTPATH 1236 { 1237 HTT_DATA_MSG_SVC, 1238 PIPEDIR_IN, /* in = DL = target -> host */ 1239 5, 1240 }, 1241 #else /* WLAN_FEATURE_FASTPATH */ 1242 { 1243 HTT_DATA_MSG_SVC, 1244 PIPEDIR_IN, /* in = DL = target -> host */ 1245 1, 1246 }, 1247 #endif /* WLAN_FEATURE_FASTPATH */ 1248 1249 /* (Additions here) */ 1250 1251 { /* Must be last */ 1252 0, 1253 0, 1254 0, 1255 }, 1256 }; 1257 1258 static struct shadow_reg_cfg *target_shadow_reg_cfg = target_shadow_reg_cfg_map; 1259 static int shadow_cfg_sz = sizeof(target_shadow_reg_cfg_map); 1260 1261 #ifdef WLAN_FEATURE_EPPING 1262 static struct service_to_pipe target_service_to_ce_map_wlan_epping[] = { 1263 {WMI_DATA_VO_SVC, PIPEDIR_OUT, 3,}, /* out = UL = host -> target */ 1264 {WMI_DATA_VO_SVC, PIPEDIR_IN, 2,}, /* in = DL = target -> host */ 1265 {WMI_DATA_BK_SVC, PIPEDIR_OUT, 4,}, /* out = UL = host -> target */ 1266 {WMI_DATA_BK_SVC, PIPEDIR_IN, 1,}, /* in = DL = target -> host */ 1267 {WMI_DATA_BE_SVC, PIPEDIR_OUT, 3,}, /* out = UL = host -> target */ 1268 {WMI_DATA_BE_SVC, PIPEDIR_IN, 2,}, /* in = DL = target -> host */ 1269 {WMI_DATA_VI_SVC, PIPEDIR_OUT, 3,}, /* out = UL = host -> target */ 1270 {WMI_DATA_VI_SVC, PIPEDIR_IN, 2,}, /* in = DL = target -> host */ 1271 {WMI_CONTROL_SVC, PIPEDIR_OUT, 3,}, /* out = UL = host -> target */ 1272 {WMI_CONTROL_SVC, PIPEDIR_IN, 2,}, /* in = DL = target -> host */ 1273 {HTC_CTRL_RSVD_SVC, PIPEDIR_OUT, 0,}, /* out = UL = host -> target */ 1274 {HTC_CTRL_RSVD_SVC, PIPEDIR_IN, 2,}, /* in = DL = target -> host */ 1275 {HTC_RAW_STREAMS_SVC, PIPEDIR_OUT, 0,}, /* out = UL = host -> target */ 1276 {HTC_RAW_STREAMS_SVC, PIPEDIR_IN, 2,}, /* in = DL = target -> host */ 1277 {HTT_DATA_MSG_SVC, PIPEDIR_OUT, 4,}, /* out = UL = host -> target */ 1278 {HTT_DATA_MSG_SVC, PIPEDIR_IN, 1,}, /* in = DL = target -> host */ 1279 {0, 0, 0,}, /* Must be last */ 1280 }; 1281 1282 void hif_select_epping_service_to_pipe_map(struct service_to_pipe 1283 **tgt_svc_map_to_use, 1284 uint32_t *sz_tgt_svc_map_to_use) 1285 { 1286 *tgt_svc_map_to_use = target_service_to_ce_map_wlan_epping; 1287 *sz_tgt_svc_map_to_use = 1288 sizeof(target_service_to_ce_map_wlan_epping); 1289 } 1290 #endif 1291 1292 #ifdef QCN7605_SUPPORT 1293 static inline 1294 void hif_select_ce_map_qcn7605(struct service_to_pipe **tgt_svc_map_to_use, 1295 uint32_t *sz_tgt_svc_map_to_use) 1296 { 1297 *tgt_svc_map_to_use = target_service_to_ce_map_qcn7605; 1298 *sz_tgt_svc_map_to_use = sizeof(target_service_to_ce_map_qcn7605); 1299 } 1300 #else 1301 static inline 1302 void hif_select_ce_map_qcn7605(struct service_to_pipe **tgt_svc_map_to_use, 1303 uint32_t *sz_tgt_svc_map_to_use) 1304 { 1305 hif_err("QCN7605 not supported"); 1306 } 1307 #endif 1308 1309 #ifdef QCA_WIFI_QCN9224 1310 static 1311 void hif_set_ce_config_qcn9224(struct hif_softc *scn, 1312 struct HIF_CE_state *hif_state) 1313 { 1314 hif_state->host_ce_config = host_ce_config_wlan_qcn9224; 1315 hif_state->target_ce_config = target_ce_config_wlan_qcn9224; 1316 hif_state->target_ce_config_sz = 1317 sizeof(target_ce_config_wlan_qcn9224); 1318 scn->ce_count = QCN_9224_CE_COUNT; 1319 scn->disable_wake_irq = 1; 1320 } 1321 1322 static 1323 void hif_select_ce_map_qcn9224(struct service_to_pipe **tgt_svc_map_to_use, 1324 uint32_t *sz_tgt_svc_map_to_use) 1325 { 1326 *tgt_svc_map_to_use = target_service_to_ce_map_qcn9224; 1327 *sz_tgt_svc_map_to_use = sizeof(target_service_to_ce_map_qcn9224); 1328 } 1329 #else 1330 static inline 1331 void hif_set_ce_config_qcn9224(struct hif_softc *scn, 1332 struct HIF_CE_state *hif_state) 1333 { 1334 hif_err("QCN9224 not supported"); 1335 } 1336 1337 static inline 1338 void hif_select_ce_map_qcn9224(struct service_to_pipe **tgt_svc_map_to_use, 1339 uint32_t *sz_tgt_svc_map_to_use) 1340 { 1341 hif_err("QCN9224 not supported"); 1342 } 1343 #endif 1344 1345 static void hif_select_service_to_pipe_map(struct hif_softc *scn, 1346 struct service_to_pipe **tgt_svc_map_to_use, 1347 uint32_t *sz_tgt_svc_map_to_use) 1348 { 1349 uint32_t mode = hif_get_conparam(scn); 1350 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 1351 struct hif_target_info *tgt_info = &scn->target_info; 1352 1353 if (QDF_IS_EPPING_ENABLED(mode)) { 1354 hif_select_epping_service_to_pipe_map(tgt_svc_map_to_use, 1355 sz_tgt_svc_map_to_use); 1356 } else { 1357 switch (tgt_info->target_type) { 1358 default: 1359 *tgt_svc_map_to_use = target_service_to_ce_map_wlan; 1360 *sz_tgt_svc_map_to_use = 1361 sizeof(target_service_to_ce_map_wlan); 1362 break; 1363 case TARGET_TYPE_QCN7605: 1364 hif_select_ce_map_qcn7605(tgt_svc_map_to_use, 1365 sz_tgt_svc_map_to_use); 1366 break; 1367 case TARGET_TYPE_AR900B: 1368 case TARGET_TYPE_QCA9984: 1369 case TARGET_TYPE_QCA9888: 1370 case TARGET_TYPE_AR9888: 1371 case TARGET_TYPE_AR9888V2: 1372 *tgt_svc_map_to_use = target_service_to_ce_map_ar900b; 1373 *sz_tgt_svc_map_to_use = 1374 sizeof(target_service_to_ce_map_ar900b); 1375 break; 1376 case TARGET_TYPE_QCA6290: 1377 *tgt_svc_map_to_use = target_service_to_ce_map_qca6290; 1378 *sz_tgt_svc_map_to_use = 1379 sizeof(target_service_to_ce_map_qca6290); 1380 break; 1381 case TARGET_TYPE_QCA6390: 1382 *tgt_svc_map_to_use = target_service_to_ce_map_qca6390; 1383 *sz_tgt_svc_map_to_use = 1384 sizeof(target_service_to_ce_map_qca6390); 1385 break; 1386 case TARGET_TYPE_QCA6490: 1387 *tgt_svc_map_to_use = target_service_to_ce_map_qca6490; 1388 *sz_tgt_svc_map_to_use = 1389 sizeof(target_service_to_ce_map_qca6490); 1390 break; 1391 case TARGET_TYPE_QCA6750: 1392 *tgt_svc_map_to_use = target_service_to_ce_map_qca6750; 1393 *sz_tgt_svc_map_to_use = 1394 sizeof(target_service_to_ce_map_qca6750); 1395 break; 1396 case TARGET_TYPE_KIWI: 1397 case TARGET_TYPE_MANGO: 1398 *tgt_svc_map_to_use = target_service_to_ce_map_kiwi; 1399 *sz_tgt_svc_map_to_use = 1400 sizeof(target_service_to_ce_map_kiwi); 1401 break; 1402 case TARGET_TYPE_QCA8074: 1403 *tgt_svc_map_to_use = target_service_to_ce_map_qca8074; 1404 *sz_tgt_svc_map_to_use = 1405 sizeof(target_service_to_ce_map_qca8074); 1406 break; 1407 case TARGET_TYPE_QCA8074V2: 1408 *tgt_svc_map_to_use = 1409 target_service_to_ce_map_qca8074_v2; 1410 *sz_tgt_svc_map_to_use = 1411 sizeof(target_service_to_ce_map_qca8074_v2); 1412 break; 1413 case TARGET_TYPE_QCA9574: 1414 *tgt_svc_map_to_use = 1415 target_service_to_ce_map_qca9574; 1416 *sz_tgt_svc_map_to_use = 1417 sizeof(target_service_to_ce_map_qca9574); 1418 break; 1419 case TARGET_TYPE_QCA6018: 1420 *tgt_svc_map_to_use = 1421 target_service_to_ce_map_qca6018; 1422 *sz_tgt_svc_map_to_use = 1423 sizeof(target_service_to_ce_map_qca6018); 1424 break; 1425 case TARGET_TYPE_QCN9000: 1426 *tgt_svc_map_to_use = 1427 target_service_to_ce_map_qcn9000; 1428 *sz_tgt_svc_map_to_use = 1429 sizeof(target_service_to_ce_map_qcn9000); 1430 break; 1431 case TARGET_TYPE_QCN9224: 1432 hif_select_ce_map_qcn9224(tgt_svc_map_to_use, 1433 sz_tgt_svc_map_to_use); 1434 break; 1435 case TARGET_TYPE_QCA5332: 1436 *tgt_svc_map_to_use = target_service_to_ce_map_qca5332; 1437 *sz_tgt_svc_map_to_use = 1438 sizeof(target_service_to_ce_map_qca5332); 1439 break; 1440 case TARGET_TYPE_QCA5018: 1441 case TARGET_TYPE_QCN6122: 1442 *tgt_svc_map_to_use = 1443 target_service_to_ce_map_qca5018; 1444 *sz_tgt_svc_map_to_use = 1445 sizeof(target_service_to_ce_map_qca5018); 1446 break; 1447 } 1448 } 1449 hif_state->tgt_svc_map = *tgt_svc_map_to_use; 1450 hif_state->sz_tgt_svc_map = *sz_tgt_svc_map_to_use / 1451 sizeof(struct service_to_pipe); 1452 } 1453 1454 /** 1455 * ce_mark_datapath() - marks the ce_state->htt_rx_data accordingly 1456 * @ce_state : pointer to the state context of the CE 1457 * 1458 * Description: 1459 * Sets htt_rx_data attribute of the state structure if the 1460 * CE serves one of the HTT DATA services. 1461 * 1462 * Return: 1463 * false (attribute set to false) 1464 * true (attribute set to true); 1465 */ 1466 static bool ce_mark_datapath(struct CE_state *ce_state) 1467 { 1468 struct service_to_pipe *svc_map; 1469 uint32_t map_sz, map_len; 1470 int i; 1471 bool rc = false; 1472 1473 if (ce_state) { 1474 hif_select_service_to_pipe_map(ce_state->scn, &svc_map, 1475 &map_sz); 1476 1477 map_len = map_sz / sizeof(struct service_to_pipe); 1478 for (i = 0; i < map_len; i++) { 1479 if ((svc_map[i].pipenum == ce_state->id) && 1480 ((svc_map[i].service_id == HTT_DATA_MSG_SVC) || 1481 (svc_map[i].service_id == HTT_DATA2_MSG_SVC) || 1482 (svc_map[i].service_id == HTT_DATA3_MSG_SVC))) { 1483 /* HTT CEs are unidirectional */ 1484 if (svc_map[i].pipedir == PIPEDIR_IN) 1485 ce_state->htt_rx_data = true; 1486 else 1487 ce_state->htt_tx_data = true; 1488 rc = true; 1489 } 1490 } 1491 } 1492 return rc; 1493 } 1494 1495 /** 1496 * hif_get_max_wmi_ep() - Get max WMI EPs configured in target svc map 1497 * @hif_ctx: hif opaque handle 1498 * 1499 * Description: 1500 * Gets number of WMI EPs configured in target svc map. Since EP map 1501 * include IN and OUT direction pipes, count only OUT pipes to get EPs 1502 * configured for WMI service. 1503 * 1504 * Return: 1505 * uint8_t: count for WMI eps in target svc map 1506 */ 1507 uint8_t hif_get_max_wmi_ep(struct hif_opaque_softc *hif_ctx) 1508 { 1509 struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); 1510 struct service_to_pipe *svc_map; 1511 uint32_t map_sz, map_len; 1512 int i; 1513 uint8_t wmi_ep_count = 0; 1514 1515 hif_select_service_to_pipe_map(scn, &svc_map, 1516 &map_sz); 1517 map_len = map_sz / sizeof(struct service_to_pipe); 1518 1519 for (i = 0; i < map_len; i++) { 1520 /* Count number of WMI EPs based on out direction */ 1521 if ((svc_map[i].pipedir == PIPEDIR_OUT) && 1522 ((svc_map[i].service_id == WMI_CONTROL_SVC) || 1523 (svc_map[i].service_id == WMI_CONTROL_SVC_WMAC1) || 1524 (svc_map[i].service_id == WMI_CONTROL_SVC_WMAC2))) { 1525 wmi_ep_count++; 1526 } 1527 } 1528 1529 return wmi_ep_count; 1530 } 1531 1532 /** 1533 * ce_ring_test_initial_indexes() - tests the initial ce ring indexes 1534 * @ce_id: ce in question 1535 * @ring: ring state being examined 1536 * @type: "src_ring" or "dest_ring" string for identifying the ring 1537 * 1538 * Warns on non-zero index values. 1539 * Causes a kernel panic if the ring is not empty durring initialization. 1540 */ 1541 static void ce_ring_test_initial_indexes(int ce_id, struct CE_ring_state *ring, 1542 char *type) 1543 { 1544 if (ring->write_index != 0 || ring->sw_index != 0) 1545 hif_err("ce %d, %s, initial sw_index = %d, initial write_index =%d", 1546 ce_id, type, ring->sw_index, ring->write_index); 1547 if (ring->write_index != ring->sw_index) 1548 QDF_BUG(0); 1549 } 1550 1551 #ifdef IPA_OFFLOAD 1552 /** 1553 * ce_alloc_desc_ring() - Allocate copyengine descriptor ring 1554 * @scn: softc instance 1555 * @ce_id: ce in question 1556 * @base_addr: pointer to copyengine ring base address 1557 * @ce_ring: copyengine instance 1558 * @nentries: number of entries should be allocated 1559 * @desc_size: ce desc size 1560 * 1561 * Return: QDF_STATUS_SUCCESS - for success 1562 */ 1563 static QDF_STATUS ce_alloc_desc_ring(struct hif_softc *scn, unsigned int CE_id, 1564 qdf_dma_addr_t *base_addr, 1565 struct CE_ring_state *ce_ring, 1566 unsigned int nentries, uint32_t desc_size) 1567 { 1568 if ((CE_id == HIF_PCI_IPA_UC_ASSIGNED_CE) && 1569 !ce_srng_based(scn)) { 1570 if (!scn->ipa_ce_ring) { 1571 scn->ipa_ce_ring = qdf_mem_shared_mem_alloc( 1572 scn->qdf_dev, 1573 nentries * desc_size + CE_DESC_RING_ALIGN); 1574 if (!scn->ipa_ce_ring) { 1575 hif_err( 1576 "Failed to allocate memory for IPA ce ring"); 1577 return QDF_STATUS_E_NOMEM; 1578 } 1579 } 1580 *base_addr = qdf_mem_get_dma_addr(scn->qdf_dev, 1581 &scn->ipa_ce_ring->mem_info); 1582 ce_ring->base_addr_owner_space_unaligned = 1583 scn->ipa_ce_ring->vaddr; 1584 } else { 1585 ce_ring->base_addr_owner_space_unaligned = 1586 hif_mem_alloc_consistent_unaligned 1587 (scn, 1588 (nentries * desc_size + 1589 CE_DESC_RING_ALIGN), 1590 base_addr, 1591 ce_ring->hal_ring_type, 1592 &ce_ring->is_ring_prealloc); 1593 1594 if (!ce_ring->base_addr_owner_space_unaligned) { 1595 hif_err("Failed to allocate DMA memory for ce ring id: %u", 1596 CE_id); 1597 return QDF_STATUS_E_NOMEM; 1598 } 1599 } 1600 return QDF_STATUS_SUCCESS; 1601 } 1602 1603 /** 1604 * ce_free_desc_ring() - Frees copyengine descriptor ring 1605 * @scn: softc instance 1606 * @ce_id: ce in question 1607 * @ce_ring: copyengine instance 1608 * @desc_size: ce desc size 1609 * 1610 * Return: None 1611 */ 1612 static void ce_free_desc_ring(struct hif_softc *scn, unsigned int CE_id, 1613 struct CE_ring_state *ce_ring, uint32_t desc_size) 1614 { 1615 if ((CE_id == HIF_PCI_IPA_UC_ASSIGNED_CE) && 1616 !ce_srng_based(scn)) { 1617 if (scn->ipa_ce_ring) { 1618 qdf_mem_shared_mem_free(scn->qdf_dev, 1619 scn->ipa_ce_ring); 1620 scn->ipa_ce_ring = NULL; 1621 } 1622 ce_ring->base_addr_owner_space_unaligned = NULL; 1623 } else { 1624 hif_mem_free_consistent_unaligned 1625 (scn, 1626 ce_ring->nentries * desc_size + CE_DESC_RING_ALIGN, 1627 ce_ring->base_addr_owner_space_unaligned, 1628 ce_ring->base_addr_CE_space, 0, 1629 ce_ring->is_ring_prealloc); 1630 ce_ring->base_addr_owner_space_unaligned = NULL; 1631 } 1632 } 1633 #else 1634 static QDF_STATUS ce_alloc_desc_ring(struct hif_softc *scn, unsigned int CE_id, 1635 qdf_dma_addr_t *base_addr, 1636 struct CE_ring_state *ce_ring, 1637 unsigned int nentries, uint32_t desc_size) 1638 { 1639 ce_ring->base_addr_owner_space_unaligned = 1640 hif_mem_alloc_consistent_unaligned 1641 (scn, 1642 (nentries * desc_size + 1643 CE_DESC_RING_ALIGN), 1644 base_addr, 1645 ce_ring->hal_ring_type, 1646 &ce_ring->is_ring_prealloc); 1647 1648 if (!ce_ring->base_addr_owner_space_unaligned) { 1649 hif_err("Failed to allocate DMA memory for ce ring id: %u", 1650 CE_id); 1651 return QDF_STATUS_E_NOMEM; 1652 } 1653 return QDF_STATUS_SUCCESS; 1654 } 1655 1656 static void ce_free_desc_ring(struct hif_softc *scn, unsigned int CE_id, 1657 struct CE_ring_state *ce_ring, uint32_t desc_size) 1658 { 1659 hif_mem_free_consistent_unaligned 1660 (scn, 1661 ce_ring->nentries * desc_size + CE_DESC_RING_ALIGN, 1662 ce_ring->base_addr_owner_space_unaligned, 1663 ce_ring->base_addr_CE_space, 0, 1664 ce_ring->is_ring_prealloc); 1665 ce_ring->base_addr_owner_space_unaligned = NULL; 1666 } 1667 #endif /* IPA_OFFLOAD */ 1668 1669 /* 1670 * TODO: Need to explore the possibility of having this as part of a 1671 * target context instead of a global array. 1672 */ 1673 static struct ce_ops* (*ce_attach_register[CE_MAX_TARGET_TYPE])(void); 1674 1675 void ce_service_register_module(enum ce_target_type target_type, 1676 struct ce_ops* (*ce_attach)(void)) 1677 { 1678 if (target_type < CE_MAX_TARGET_TYPE) 1679 ce_attach_register[target_type] = ce_attach; 1680 } 1681 1682 qdf_export_symbol(ce_service_register_module); 1683 1684 /** 1685 * ce_srng_based() - Does this target use srng 1686 * @ce_state : pointer to the state context of the CE 1687 * 1688 * Description: 1689 * returns true if the target is SRNG based 1690 * 1691 * Return: 1692 * false (attribute set to false) 1693 * true (attribute set to true); 1694 */ 1695 bool ce_srng_based(struct hif_softc *scn) 1696 { 1697 struct hif_opaque_softc *hif_hdl = GET_HIF_OPAQUE_HDL(scn); 1698 struct hif_target_info *tgt_info = hif_get_target_info_handle(hif_hdl); 1699 1700 switch (tgt_info->target_type) { 1701 case TARGET_TYPE_QCA8074: 1702 case TARGET_TYPE_QCA8074V2: 1703 case TARGET_TYPE_QCA6290: 1704 case TARGET_TYPE_QCA6390: 1705 case TARGET_TYPE_QCA6490: 1706 case TARGET_TYPE_QCA6750: 1707 case TARGET_TYPE_QCA6018: 1708 case TARGET_TYPE_QCN9000: 1709 case TARGET_TYPE_QCN6122: 1710 case TARGET_TYPE_QCA5018: 1711 case TARGET_TYPE_KIWI: 1712 case TARGET_TYPE_MANGO: 1713 case TARGET_TYPE_QCN9224: 1714 case TARGET_TYPE_QCA9574: 1715 case TARGET_TYPE_QCA5332: 1716 return true; 1717 default: 1718 return false; 1719 } 1720 return false; 1721 } 1722 qdf_export_symbol(ce_srng_based); 1723 1724 #ifdef QCA_WIFI_SUPPORT_SRNG 1725 static struct ce_ops *ce_services_attach(struct hif_softc *scn) 1726 { 1727 struct ce_ops *ops = NULL; 1728 1729 if (ce_srng_based(scn)) { 1730 if (ce_attach_register[CE_SVC_SRNG]) 1731 ops = ce_attach_register[CE_SVC_SRNG](); 1732 } else if (ce_attach_register[CE_SVC_LEGACY]) { 1733 ops = ce_attach_register[CE_SVC_LEGACY](); 1734 } 1735 1736 return ops; 1737 } 1738 1739 1740 #else /* QCA_LITHIUM */ 1741 static struct ce_ops *ce_services_attach(struct hif_softc *scn) 1742 { 1743 if (ce_attach_register[CE_SVC_LEGACY]) 1744 return ce_attach_register[CE_SVC_LEGACY](); 1745 1746 return NULL; 1747 } 1748 #endif /* QCA_LITHIUM */ 1749 1750 static void hif_prepare_hal_shadow_register_cfg(struct hif_softc *scn, 1751 struct pld_shadow_reg_v2_cfg **shadow_config, 1752 int *num_shadow_registers_configured) { 1753 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 1754 1755 hif_state->ce_services->ce_prepare_shadow_register_v2_cfg( 1756 scn, shadow_config, num_shadow_registers_configured); 1757 1758 return; 1759 } 1760 1761 #ifdef CONFIG_SHADOW_V3 1762 static inline void 1763 hif_prepare_hal_shadow_reg_cfg_v3(struct hif_softc *scn, 1764 struct pld_wlan_enable_cfg *cfg) 1765 { 1766 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 1767 1768 if (!hif_state->ce_services->ce_prepare_shadow_register_v3_cfg) 1769 return; 1770 1771 hif_state->ce_services->ce_prepare_shadow_register_v3_cfg( 1772 scn, &cfg->shadow_reg_v3_cfg, 1773 &cfg->num_shadow_reg_v3_cfg); 1774 } 1775 #else 1776 static inline void 1777 hif_prepare_hal_shadow_reg_cfg_v3(struct hif_softc *scn, 1778 struct pld_wlan_enable_cfg *cfg) 1779 { 1780 } 1781 #endif 1782 1783 static inline uint32_t ce_get_desc_size(struct hif_softc *scn, 1784 uint8_t ring_type) 1785 { 1786 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 1787 1788 return hif_state->ce_services->ce_get_desc_size(ring_type); 1789 } 1790 1791 #ifdef QCA_WIFI_SUPPORT_SRNG 1792 static inline int32_t ce_ring_type_to_hal_ring_type(uint32_t ce_ring_type) 1793 { 1794 switch (ce_ring_type) { 1795 case CE_RING_SRC: 1796 return CE_SRC; 1797 case CE_RING_DEST: 1798 return CE_DST; 1799 case CE_RING_STATUS: 1800 return CE_DST_STATUS; 1801 default: 1802 return -EINVAL; 1803 } 1804 } 1805 #else 1806 static int32_t ce_ring_type_to_hal_ring_type(uint32_t ce_ring_type) 1807 { 1808 return 0; 1809 } 1810 #endif 1811 static struct CE_ring_state *ce_alloc_ring_state(struct CE_state *CE_state, 1812 uint8_t ring_type, uint32_t nentries) 1813 { 1814 uint32_t ce_nbytes; 1815 char *ptr; 1816 qdf_dma_addr_t base_addr; 1817 struct CE_ring_state *ce_ring; 1818 uint32_t desc_size; 1819 struct hif_softc *scn = CE_state->scn; 1820 1821 ce_nbytes = sizeof(struct CE_ring_state) 1822 + (nentries * sizeof(void *)); 1823 ptr = qdf_mem_malloc(ce_nbytes); 1824 if (!ptr) 1825 return NULL; 1826 1827 ce_ring = (struct CE_ring_state *)ptr; 1828 ptr += sizeof(struct CE_ring_state); 1829 ce_ring->nentries = nentries; 1830 ce_ring->nentries_mask = nentries - 1; 1831 1832 ce_ring->low_water_mark_nentries = 0; 1833 ce_ring->high_water_mark_nentries = nentries; 1834 ce_ring->per_transfer_context = (void **)ptr; 1835 ce_ring->hal_ring_type = ce_ring_type_to_hal_ring_type(ring_type); 1836 1837 desc_size = ce_get_desc_size(scn, ring_type); 1838 1839 /* Legacy platforms that do not support cache 1840 * coherent DMA are unsupported 1841 */ 1842 if (ce_alloc_desc_ring(scn, CE_state->id, &base_addr, 1843 ce_ring, nentries, 1844 desc_size) != 1845 QDF_STATUS_SUCCESS) { 1846 hif_err("ring has no DMA mem"); 1847 qdf_mem_free(ce_ring); 1848 return NULL; 1849 } 1850 ce_ring->base_addr_CE_space_unaligned = base_addr; 1851 1852 /* Correctly initialize memory to 0 to 1853 * prevent garbage data crashing system 1854 * when download firmware 1855 */ 1856 qdf_mem_zero(ce_ring->base_addr_owner_space_unaligned, 1857 nentries * desc_size + 1858 CE_DESC_RING_ALIGN); 1859 1860 if (ce_ring->base_addr_CE_space_unaligned & (CE_DESC_RING_ALIGN - 1)) { 1861 1862 ce_ring->base_addr_CE_space = 1863 (ce_ring->base_addr_CE_space_unaligned + 1864 CE_DESC_RING_ALIGN - 1) & ~(CE_DESC_RING_ALIGN - 1); 1865 1866 ce_ring->base_addr_owner_space = (void *) 1867 (((size_t) ce_ring->base_addr_owner_space_unaligned + 1868 CE_DESC_RING_ALIGN - 1) & ~(CE_DESC_RING_ALIGN - 1)); 1869 } else { 1870 ce_ring->base_addr_CE_space = 1871 ce_ring->base_addr_CE_space_unaligned; 1872 ce_ring->base_addr_owner_space = 1873 ce_ring->base_addr_owner_space_unaligned; 1874 } 1875 1876 return ce_ring; 1877 } 1878 1879 static int ce_ring_setup(struct hif_softc *scn, uint8_t ring_type, 1880 uint32_t ce_id, struct CE_ring_state *ring, 1881 struct CE_attr *attr) 1882 { 1883 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 1884 1885 return hif_state->ce_services->ce_ring_setup(scn, ring_type, ce_id, 1886 ring, attr); 1887 } 1888 1889 static void ce_srng_cleanup(struct hif_softc *scn, struct CE_state *CE_state, 1890 uint8_t ring_type) 1891 { 1892 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 1893 1894 if (hif_state->ce_services->ce_srng_cleanup) 1895 hif_state->ce_services->ce_srng_cleanup(scn, 1896 CE_state, ring_type); 1897 } 1898 1899 int hif_ce_bus_early_suspend(struct hif_softc *scn) 1900 { 1901 uint8_t ul_pipe, dl_pipe; 1902 int ce_id, status, ul_is_polled, dl_is_polled; 1903 struct CE_state *ce_state; 1904 1905 status = hif_map_service_to_pipe(&scn->osc, WMI_CONTROL_SVC, 1906 &ul_pipe, &dl_pipe, 1907 &ul_is_polled, &dl_is_polled); 1908 if (status) { 1909 hif_err("pipe_mapping failure"); 1910 return status; 1911 } 1912 1913 for (ce_id = 0; ce_id < scn->ce_count; ce_id++) { 1914 if (ce_id == ul_pipe) 1915 continue; 1916 if (ce_id == dl_pipe) 1917 continue; 1918 1919 ce_state = scn->ce_id_to_state[ce_id]; 1920 qdf_spin_lock_bh(&ce_state->ce_index_lock); 1921 if (ce_state->state == CE_RUNNING) 1922 ce_state->state = CE_PAUSED; 1923 qdf_spin_unlock_bh(&ce_state->ce_index_lock); 1924 } 1925 1926 return status; 1927 } 1928 1929 int hif_ce_bus_late_resume(struct hif_softc *scn) 1930 { 1931 int ce_id; 1932 struct CE_state *ce_state; 1933 int write_index = 0; 1934 bool index_updated; 1935 1936 for (ce_id = 0; ce_id < scn->ce_count; ce_id++) { 1937 ce_state = scn->ce_id_to_state[ce_id]; 1938 qdf_spin_lock_bh(&ce_state->ce_index_lock); 1939 if (ce_state->state == CE_PENDING) { 1940 write_index = ce_state->src_ring->write_index; 1941 CE_SRC_RING_WRITE_IDX_SET(scn, ce_state->ctrl_addr, 1942 write_index); 1943 ce_state->state = CE_RUNNING; 1944 index_updated = true; 1945 } else { 1946 index_updated = false; 1947 } 1948 1949 if (ce_state->state == CE_PAUSED) 1950 ce_state->state = CE_RUNNING; 1951 qdf_spin_unlock_bh(&ce_state->ce_index_lock); 1952 1953 if (index_updated) 1954 hif_record_ce_desc_event(scn, ce_id, 1955 RESUME_WRITE_INDEX_UPDATE, 1956 NULL, NULL, write_index, 0); 1957 } 1958 1959 return 0; 1960 } 1961 1962 /** 1963 * ce_oom_recovery() - try to recover rx ce from oom condition 1964 * @context: CE_state of the CE with oom rx ring 1965 * 1966 * the executing work Will continue to be rescheduled until 1967 * at least 1 descriptor is successfully posted to the rx ring. 1968 * 1969 * return: none 1970 */ 1971 static void ce_oom_recovery(void *context) 1972 { 1973 struct CE_state *ce_state = context; 1974 struct hif_softc *scn = ce_state->scn; 1975 struct HIF_CE_state *ce_softc = HIF_GET_CE_STATE(scn); 1976 struct HIF_CE_pipe_info *pipe_info = 1977 &ce_softc->pipe_info[ce_state->id]; 1978 1979 hif_post_recv_buffers_for_pipe(pipe_info); 1980 } 1981 1982 #ifdef HIF_CE_DEBUG_DATA_BUF 1983 /** 1984 * alloc_mem_ce_debug_hist_data() - Allocate mem for the data pointed by 1985 * the CE descriptors. 1986 * Allocate HIF_CE_HISTORY_MAX records by CE_DEBUG_MAX_DATA_BUF_SIZE 1987 * @scn: hif scn handle 1988 * ce_id: Copy Engine Id 1989 * 1990 * Return: QDF_STATUS 1991 */ 1992 QDF_STATUS alloc_mem_ce_debug_hist_data(struct hif_softc *scn, uint32_t ce_id) 1993 { 1994 struct hif_ce_desc_event *event = NULL; 1995 struct hif_ce_desc_event *hist_ev = NULL; 1996 uint32_t index = 0; 1997 1998 hist_ev = 1999 (struct hif_ce_desc_event *)scn->hif_ce_desc_hist.hist_ev[ce_id]; 2000 2001 if (!hist_ev) 2002 return QDF_STATUS_E_NOMEM; 2003 2004 scn->hif_ce_desc_hist.data_enable[ce_id] = true; 2005 for (index = 0; index < HIF_CE_HISTORY_MAX; index++) { 2006 event = &hist_ev[index]; 2007 event->data = 2008 (uint8_t *)qdf_mem_malloc(CE_DEBUG_MAX_DATA_BUF_SIZE); 2009 if (!event->data) { 2010 hif_err_rl("ce debug data alloc failed"); 2011 scn->hif_ce_desc_hist.data_enable[ce_id] = false; 2012 return QDF_STATUS_E_NOMEM; 2013 } 2014 } 2015 return QDF_STATUS_SUCCESS; 2016 } 2017 2018 /** 2019 * free_mem_ce_debug_hist_data() - Free mem of the data pointed by 2020 * the CE descriptors. 2021 * @scn: hif scn handle 2022 * ce_id: Copy Engine Id 2023 * 2024 * Return: 2025 */ 2026 void free_mem_ce_debug_hist_data(struct hif_softc *scn, uint32_t ce_id) 2027 { 2028 struct hif_ce_desc_event *event = NULL; 2029 struct hif_ce_desc_event *hist_ev = NULL; 2030 uint32_t index = 0; 2031 2032 hist_ev = 2033 (struct hif_ce_desc_event *)scn->hif_ce_desc_hist.hist_ev[ce_id]; 2034 2035 if (!hist_ev) 2036 return; 2037 2038 for (index = 0; index < HIF_CE_HISTORY_MAX; index++) { 2039 event = &hist_ev[index]; 2040 if (event->data) 2041 qdf_mem_free(event->data); 2042 event->data = NULL; 2043 event = NULL; 2044 } 2045 2046 } 2047 #endif /* HIF_CE_DEBUG_DATA_BUF */ 2048 2049 #ifndef HIF_CE_DEBUG_DATA_DYNAMIC_BUF 2050 #if defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF) 2051 2052 /* define below variables for crashscope parse */ 2053 struct hif_ce_desc_event *hif_ce_desc_history[CE_COUNT_MAX]; 2054 uint32_t hif_ce_history_max = HIF_CE_HISTORY_MAX; 2055 2056 /** 2057 * for debug build, it will enable ce history for all ce, but for 2058 * perf build(if CONFIG_SLUB_DEBUG_ON is N), it only enable for 2059 * ce2(wmi event) & ce3(wmi cmd) history. 2060 */ 2061 #if defined(CONFIG_SLUB_DEBUG_ON) 2062 #define CE_DESC_HISTORY_BUFF_CNT CE_COUNT_MAX 2063 #define IS_CE_DEBUG_ONLY_FOR_CRIT_CE 0 2064 #else 2065 /* CE2, CE3, CE7 */ 2066 #define CE_DESC_HISTORY_BUFF_CNT 3 2067 #define IS_CE_DEBUG_ONLY_FOR_CRIT_CE (BIT(2) | BIT(3) | BIT(7)) 2068 #endif 2069 struct hif_ce_desc_event 2070 hif_ce_desc_history_buff[CE_DESC_HISTORY_BUFF_CNT][HIF_CE_HISTORY_MAX]; 2071 2072 static struct hif_ce_desc_event * 2073 hif_ce_debug_history_buf_get(struct hif_softc *scn, unsigned int ce_id) 2074 { 2075 struct ce_desc_hist *ce_hist = &scn->hif_ce_desc_hist; 2076 2077 hif_debug("get ce debug buffer ce_id %u, only_ce2/ce3=0x%x, idx=%u", 2078 ce_id, IS_CE_DEBUG_ONLY_FOR_CRIT_CE, 2079 ce_hist->ce_id_hist_map[ce_id]); 2080 if (IS_CE_DEBUG_ONLY_FOR_CRIT_CE && 2081 (ce_id == CE_ID_2 || ce_id == CE_ID_3 || ce_id == CE_ID_7)) { 2082 uint8_t idx = ce_hist->ce_id_hist_map[ce_id]; 2083 2084 hif_ce_desc_history[ce_id] = hif_ce_desc_history_buff[idx]; 2085 } else { 2086 hif_ce_desc_history[ce_id] = 2087 hif_ce_desc_history_buff[ce_id]; 2088 } 2089 2090 return hif_ce_desc_history[ce_id]; 2091 } 2092 2093 /** 2094 * alloc_mem_ce_debug_history() - Allocate CE descriptor history 2095 * @scn: hif scn handle 2096 * @ce_id: Copy Engine Id 2097 * @src_nentries: source ce ring entries 2098 * Return: QDF_STATUS 2099 */ 2100 static QDF_STATUS 2101 alloc_mem_ce_debug_history(struct hif_softc *scn, unsigned int ce_id, 2102 uint32_t src_nentries) 2103 { 2104 struct ce_desc_hist *ce_hist = &scn->hif_ce_desc_hist; 2105 QDF_STATUS status = QDF_STATUS_SUCCESS; 2106 2107 /* For perf build, return directly for non ce2/ce3 */ 2108 if (IS_CE_DEBUG_ONLY_FOR_CRIT_CE && 2109 ce_id != CE_ID_2 && 2110 ce_id != CE_ID_3 && 2111 ce_id != CE_ID_7) { 2112 ce_hist->enable[ce_id] = false; 2113 ce_hist->data_enable[ce_id] = false; 2114 return QDF_STATUS_SUCCESS; 2115 } 2116 2117 ce_hist->hist_ev[ce_id] = hif_ce_debug_history_buf_get(scn, ce_id); 2118 ce_hist->enable[ce_id] = true; 2119 2120 if (src_nentries) { 2121 status = alloc_mem_ce_debug_hist_data(scn, ce_id); 2122 if (status != QDF_STATUS_SUCCESS) { 2123 ce_hist->enable[ce_id] = false; 2124 ce_hist->hist_ev[ce_id] = NULL; 2125 return status; 2126 } 2127 } else { 2128 ce_hist->data_enable[ce_id] = false; 2129 } 2130 2131 return QDF_STATUS_SUCCESS; 2132 } 2133 2134 /** 2135 * free_mem_ce_debug_history() - Free CE descriptor history 2136 * @scn: hif scn handle 2137 * @ce_id: Copy Engine Id 2138 * 2139 * Return: None 2140 */ 2141 static void free_mem_ce_debug_history(struct hif_softc *scn, unsigned int ce_id) 2142 { 2143 struct ce_desc_hist *ce_hist = &scn->hif_ce_desc_hist; 2144 2145 if (!ce_hist->enable[ce_id]) 2146 return; 2147 2148 ce_hist->enable[ce_id] = false; 2149 if (ce_hist->data_enable[ce_id]) { 2150 ce_hist->data_enable[ce_id] = false; 2151 free_mem_ce_debug_hist_data(scn, ce_id); 2152 } 2153 ce_hist->hist_ev[ce_id] = NULL; 2154 } 2155 #else 2156 static inline QDF_STATUS 2157 alloc_mem_ce_debug_history(struct hif_softc *scn, unsigned int CE_id, 2158 uint32_t src_nentries) 2159 { 2160 return QDF_STATUS_SUCCESS; 2161 } 2162 2163 static inline void 2164 free_mem_ce_debug_history(struct hif_softc *scn, unsigned int CE_id) { } 2165 #endif /* (HIF_CONFIG_SLUB_DEBUG_ON) || (HIF_CE_DEBUG_DATA_BUF) */ 2166 #else 2167 #if defined(HIF_CE_DEBUG_DATA_BUF) 2168 2169 static QDF_STATUS 2170 alloc_mem_ce_debug_history(struct hif_softc *scn, unsigned int CE_id, 2171 uint32_t src_nentries) 2172 { 2173 scn->hif_ce_desc_hist.hist_ev[CE_id] = (struct hif_ce_desc_event *) 2174 qdf_mem_malloc(HIF_CE_HISTORY_MAX * sizeof(struct hif_ce_desc_event)); 2175 2176 if (!scn->hif_ce_desc_hist.hist_ev[CE_id]) { 2177 scn->hif_ce_desc_hist.enable[CE_id] = 0; 2178 return QDF_STATUS_E_NOMEM; 2179 } else { 2180 scn->hif_ce_desc_hist.enable[CE_id] = 1; 2181 return QDF_STATUS_SUCCESS; 2182 } 2183 } 2184 2185 static void free_mem_ce_debug_history(struct hif_softc *scn, unsigned int CE_id) 2186 { 2187 struct ce_desc_hist *ce_hist = &scn->hif_ce_desc_hist; 2188 struct hif_ce_desc_event *hist_ev = ce_hist->hist_ev[CE_id]; 2189 2190 if (!hist_ev) 2191 return; 2192 2193 if (ce_hist->data_enable[CE_id]) { 2194 ce_hist->data_enable[CE_id] = false; 2195 free_mem_ce_debug_hist_data(scn, CE_id); 2196 } 2197 2198 ce_hist->enable[CE_id] = false; 2199 qdf_mem_free(ce_hist->hist_ev[CE_id]); 2200 ce_hist->hist_ev[CE_id] = NULL; 2201 } 2202 2203 #else 2204 2205 static inline QDF_STATUS 2206 alloc_mem_ce_debug_history(struct hif_softc *scn, unsigned int CE_id, 2207 uint32_t src_nentries) 2208 { 2209 return QDF_STATUS_SUCCESS; 2210 } 2211 2212 static inline void 2213 free_mem_ce_debug_history(struct hif_softc *scn, unsigned int CE_id) { } 2214 #endif /* HIF_CE_DEBUG_DATA_BUF */ 2215 #endif /* HIF_CE_DEBUG_DATA_DYNAMIC_BUF */ 2216 2217 #if defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF) 2218 /** 2219 * reset_ce_debug_history() - reset the index and ce id used for dumping the 2220 * CE records on the console using sysfs. 2221 * @scn: hif scn handle 2222 * 2223 * Return: 2224 */ 2225 static inline void reset_ce_debug_history(struct hif_softc *scn) 2226 { 2227 struct ce_desc_hist *ce_hist = &scn->hif_ce_desc_hist; 2228 /* Initialise the CE debug history sysfs interface inputs ce_id and 2229 * index. Disable data storing 2230 */ 2231 ce_hist->hist_index = 0; 2232 ce_hist->hist_id = 0; 2233 } 2234 #else /* defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF) */ 2235 static inline void reset_ce_debug_history(struct hif_softc *scn) { } 2236 #endif /*defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF) */ 2237 2238 void ce_enable_polling(void *cestate) 2239 { 2240 struct CE_state *CE_state = (struct CE_state *)cestate; 2241 2242 if (CE_state && CE_state->attr_flags & CE_ATTR_ENABLE_POLL) 2243 CE_state->timer_inited = true; 2244 } 2245 2246 void ce_disable_polling(void *cestate) 2247 { 2248 struct CE_state *CE_state = (struct CE_state *)cestate; 2249 2250 if (CE_state && CE_state->attr_flags & CE_ATTR_ENABLE_POLL) 2251 CE_state->timer_inited = false; 2252 } 2253 2254 /* 2255 * Initialize a Copy Engine based on caller-supplied attributes. 2256 * This may be called once to initialize both source and destination 2257 * rings or it may be called twice for separate source and destination 2258 * initialization. It may be that only one side or the other is 2259 * initialized by software/firmware. 2260 * 2261 * This should be called durring the initialization sequence before 2262 * interupts are enabled, so we don't have to worry about thread safety. 2263 */ 2264 struct CE_handle *ce_init(struct hif_softc *scn, 2265 unsigned int CE_id, struct CE_attr *attr) 2266 { 2267 struct CE_state *CE_state; 2268 uint32_t ctrl_addr; 2269 unsigned int nentries; 2270 bool malloc_CE_state = false; 2271 bool malloc_src_ring = false; 2272 int status; 2273 QDF_STATUS mem_status = QDF_STATUS_SUCCESS; 2274 2275 QDF_ASSERT(CE_id < scn->ce_count); 2276 ctrl_addr = CE_BASE_ADDRESS(CE_id); 2277 CE_state = scn->ce_id_to_state[CE_id]; 2278 2279 if (!CE_state) { 2280 CE_state = 2281 (struct CE_state *)qdf_mem_malloc(sizeof(*CE_state)); 2282 if (!CE_state) 2283 return NULL; 2284 2285 malloc_CE_state = true; 2286 qdf_spinlock_create(&CE_state->ce_index_lock); 2287 2288 CE_state->id = CE_id; 2289 CE_state->ctrl_addr = ctrl_addr; 2290 CE_state->state = CE_RUNNING; 2291 CE_state->attr_flags = attr->flags; 2292 } 2293 CE_state->scn = scn; 2294 CE_state->service = ce_engine_service_reg; 2295 2296 qdf_atomic_init(&CE_state->rx_pending); 2297 if (!attr) { 2298 /* Already initialized; caller wants the handle */ 2299 return (struct CE_handle *)CE_state; 2300 } 2301 2302 if (CE_state->src_sz_max) 2303 QDF_ASSERT(CE_state->src_sz_max == attr->src_sz_max); 2304 else 2305 CE_state->src_sz_max = attr->src_sz_max; 2306 2307 ce_init_ce_desc_event_log(scn, CE_id, 2308 attr->src_nentries + attr->dest_nentries); 2309 2310 /* source ring setup */ 2311 nentries = attr->src_nentries; 2312 if (nentries) { 2313 struct CE_ring_state *src_ring; 2314 2315 nentries = roundup_pwr2(nentries); 2316 if (CE_state->src_ring) { 2317 QDF_ASSERT(CE_state->src_ring->nentries == nentries); 2318 } else { 2319 src_ring = CE_state->src_ring = 2320 ce_alloc_ring_state(CE_state, 2321 CE_RING_SRC, 2322 nentries); 2323 if (!src_ring) { 2324 /* cannot allocate src ring. If the 2325 * CE_state is allocated locally free 2326 * CE_State and return error. 2327 */ 2328 hif_err("src ring has no mem"); 2329 if (malloc_CE_state) { 2330 /* allocated CE_state locally */ 2331 qdf_mem_free(CE_state); 2332 malloc_CE_state = false; 2333 } 2334 return NULL; 2335 } 2336 /* we can allocate src ring. Mark that the src ring is 2337 * allocated locally 2338 */ 2339 malloc_src_ring = true; 2340 2341 /* 2342 * Also allocate a shadow src ring in 2343 * regular mem to use for faster access. 2344 */ 2345 src_ring->shadow_base_unaligned = 2346 qdf_mem_malloc(nentries * 2347 sizeof(struct CE_src_desc) + 2348 CE_DESC_RING_ALIGN); 2349 if (!src_ring->shadow_base_unaligned) 2350 goto error_no_dma_mem; 2351 2352 src_ring->shadow_base = (struct CE_src_desc *) 2353 (((size_t) src_ring->shadow_base_unaligned + 2354 CE_DESC_RING_ALIGN - 1) & 2355 ~(CE_DESC_RING_ALIGN - 1)); 2356 2357 status = ce_ring_setup(scn, CE_RING_SRC, CE_id, 2358 src_ring, attr); 2359 if (status < 0) 2360 goto error_target_access; 2361 2362 ce_ring_test_initial_indexes(CE_id, src_ring, 2363 "src_ring"); 2364 } 2365 } 2366 2367 /* destination ring setup */ 2368 nentries = attr->dest_nentries; 2369 if (nentries) { 2370 struct CE_ring_state *dest_ring; 2371 2372 nentries = roundup_pwr2(nentries); 2373 if (CE_state->dest_ring) { 2374 QDF_ASSERT(CE_state->dest_ring->nentries == nentries); 2375 } else { 2376 dest_ring = CE_state->dest_ring = 2377 ce_alloc_ring_state(CE_state, 2378 CE_RING_DEST, 2379 nentries); 2380 if (!dest_ring) { 2381 /* cannot allocate dst ring. If the CE_state 2382 * or src ring is allocated locally free 2383 * CE_State and src ring and return error. 2384 */ 2385 hif_err("dest ring has no mem"); 2386 goto error_no_dma_mem; 2387 } 2388 2389 status = ce_ring_setup(scn, CE_RING_DEST, CE_id, 2390 dest_ring, attr); 2391 if (status < 0) 2392 goto error_target_access; 2393 2394 ce_ring_test_initial_indexes(CE_id, dest_ring, 2395 "dest_ring"); 2396 2397 /* For srng based target, init status ring here */ 2398 if (ce_srng_based(CE_state->scn)) { 2399 CE_state->status_ring = 2400 ce_alloc_ring_state(CE_state, 2401 CE_RING_STATUS, 2402 nentries); 2403 if (!CE_state->status_ring) { 2404 /*Allocation failed. Cleanup*/ 2405 qdf_mem_free(CE_state->dest_ring); 2406 if (malloc_src_ring) { 2407 qdf_mem_free 2408 (CE_state->src_ring); 2409 CE_state->src_ring = NULL; 2410 malloc_src_ring = false; 2411 } 2412 if (malloc_CE_state) { 2413 /* allocated CE_state locally */ 2414 scn->ce_id_to_state[CE_id] = 2415 NULL; 2416 qdf_mem_free(CE_state); 2417 malloc_CE_state = false; 2418 } 2419 2420 return NULL; 2421 } 2422 2423 status = ce_ring_setup(scn, CE_RING_STATUS, 2424 CE_id, CE_state->status_ring, 2425 attr); 2426 if (status < 0) 2427 goto error_target_access; 2428 2429 } 2430 2431 /* epping */ 2432 /* poll timer */ 2433 if (CE_state->attr_flags & CE_ATTR_ENABLE_POLL) { 2434 qdf_timer_init(scn->qdf_dev, 2435 &CE_state->poll_timer, 2436 ce_poll_timeout, 2437 CE_state, 2438 QDF_TIMER_TYPE_WAKE_APPS); 2439 ce_enable_polling(CE_state); 2440 qdf_timer_mod(&CE_state->poll_timer, 2441 CE_POLL_TIMEOUT); 2442 } 2443 } 2444 } 2445 2446 if (!ce_srng_based(scn)) { 2447 /* Enable CE error interrupts */ 2448 if (Q_TARGET_ACCESS_BEGIN(scn) < 0) 2449 goto error_target_access; 2450 CE_ERROR_INTR_ENABLE(scn, ctrl_addr); 2451 if (Q_TARGET_ACCESS_END(scn) < 0) 2452 goto error_target_access; 2453 } 2454 2455 qdf_create_work(scn->qdf_dev, &CE_state->oom_allocation_work, 2456 ce_oom_recovery, CE_state); 2457 2458 /* update the htt_data attribute */ 2459 ce_mark_datapath(CE_state); 2460 scn->ce_id_to_state[CE_id] = CE_state; 2461 2462 mem_status = alloc_mem_ce_debug_history(scn, CE_id, attr->src_nentries); 2463 if (mem_status != QDF_STATUS_SUCCESS) 2464 goto error_target_access; 2465 2466 return (struct CE_handle *)CE_state; 2467 2468 error_target_access: 2469 error_no_dma_mem: 2470 ce_fini((struct CE_handle *)CE_state); 2471 return NULL; 2472 } 2473 2474 /** 2475 * hif_is_polled_mode_enabled - API to query if polling is enabled on all CEs 2476 * @hif_ctx: HIF Context 2477 * 2478 * API to check if polling is enabled on all CEs. Returns true when polling 2479 * is enabled on all CEs. 2480 * 2481 * Return: bool 2482 */ 2483 bool hif_is_polled_mode_enabled(struct hif_opaque_softc *hif_ctx) 2484 { 2485 struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); 2486 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 2487 struct CE_attr *attr; 2488 int id; 2489 2490 for (id = 0; id < scn->ce_count; id++) { 2491 attr = &hif_state->host_ce_config[id]; 2492 if (attr && (attr->dest_nentries) && 2493 !(attr->flags & CE_ATTR_ENABLE_POLL)) 2494 return false; 2495 } 2496 return true; 2497 } 2498 qdf_export_symbol(hif_is_polled_mode_enabled); 2499 2500 static int hif_get_pktlog_ce_num(struct hif_softc *scn) 2501 { 2502 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 2503 int id; 2504 2505 for (id = 0; id < hif_state->sz_tgt_svc_map; id++) { 2506 if (hif_state->tgt_svc_map[id].service_id == PACKET_LOG_SVC) 2507 return hif_state->tgt_svc_map[id].pipenum; 2508 } 2509 return -EINVAL; 2510 } 2511 2512 #ifdef WLAN_FEATURE_FASTPATH 2513 /** 2514 * hif_enable_fastpath() Update that we have enabled fastpath mode 2515 * @hif_ctx: HIF context 2516 * 2517 * For use in data path 2518 * 2519 * Retrun: void 2520 */ 2521 void hif_enable_fastpath(struct hif_opaque_softc *hif_ctx) 2522 { 2523 struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); 2524 2525 if (ce_srng_based(scn)) { 2526 hif_warn("srng rings do not support fastpath"); 2527 return; 2528 } 2529 hif_debug("Enabling fastpath mode"); 2530 scn->fastpath_mode_on = true; 2531 } 2532 2533 /** 2534 * hif_is_fastpath_mode_enabled - API to query if fasthpath mode is enabled 2535 * @hif_ctx: HIF Context 2536 * 2537 * For use in data path to skip HTC 2538 * 2539 * Return: bool 2540 */ 2541 bool hif_is_fastpath_mode_enabled(struct hif_opaque_softc *hif_ctx) 2542 { 2543 struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); 2544 2545 return scn->fastpath_mode_on; 2546 } 2547 2548 /** 2549 * hif_get_ce_handle - API to get CE handle for FastPath mode 2550 * @hif_ctx: HIF Context 2551 * @id: CopyEngine Id 2552 * 2553 * API to return CE handle for fastpath mode 2554 * 2555 * Return: void 2556 */ 2557 void *hif_get_ce_handle(struct hif_opaque_softc *hif_ctx, int id) 2558 { 2559 struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); 2560 2561 return scn->ce_id_to_state[id]; 2562 } 2563 qdf_export_symbol(hif_get_ce_handle); 2564 2565 /** 2566 * ce_h2t_tx_ce_cleanup() Place holder function for H2T CE cleanup. 2567 * No processing is required inside this function. 2568 * @ce_hdl: Cope engine handle 2569 * Using an assert, this function makes sure that, 2570 * the TX CE has been processed completely. 2571 * 2572 * This is called while dismantling CE structures. No other thread 2573 * should be using these structures while dismantling is occurring 2574 * therfore no locking is needed. 2575 * 2576 * Return: none 2577 */ 2578 void ce_h2t_tx_ce_cleanup(struct CE_handle *ce_hdl) 2579 { 2580 struct CE_state *ce_state = (struct CE_state *)ce_hdl; 2581 struct CE_ring_state *src_ring = ce_state->src_ring; 2582 struct hif_softc *sc = ce_state->scn; 2583 uint32_t sw_index, write_index; 2584 2585 if (hif_is_nss_wifi_enabled(sc)) 2586 return; 2587 2588 if (sc->fastpath_mode_on && ce_state->htt_tx_data) { 2589 hif_debug("Fastpath mode ON, Cleaning up HTT Tx CE"); 2590 sw_index = src_ring->sw_index; 2591 write_index = src_ring->sw_index; 2592 2593 /* At this point Tx CE should be clean */ 2594 qdf_assert_always(sw_index == write_index); 2595 } 2596 } 2597 2598 /** 2599 * ce_t2h_msg_ce_cleanup() - Cleanup buffers on the t2h datapath msg queue. 2600 * @ce_hdl: Handle to CE 2601 * 2602 * These buffers are never allocated on the fly, but 2603 * are allocated only once during HIF start and freed 2604 * only once during HIF stop. 2605 * NOTE: 2606 * The assumption here is there is no in-flight DMA in progress 2607 * currently, so that buffers can be freed up safely. 2608 * 2609 * Return: NONE 2610 */ 2611 void ce_t2h_msg_ce_cleanup(struct CE_handle *ce_hdl) 2612 { 2613 struct CE_state *ce_state = (struct CE_state *)ce_hdl; 2614 struct CE_ring_state *dst_ring = ce_state->dest_ring; 2615 qdf_nbuf_t nbuf; 2616 int i; 2617 2618 if (ce_state->scn->fastpath_mode_on == false) 2619 return; 2620 2621 if (!ce_state->htt_rx_data) 2622 return; 2623 2624 /* 2625 * when fastpath_mode is on and for datapath CEs. Unlike other CE's, 2626 * this CE is completely full: does not leave one blank space, to 2627 * distinguish between empty queue & full queue. So free all the 2628 * entries. 2629 */ 2630 for (i = 0; i < dst_ring->nentries; i++) { 2631 nbuf = dst_ring->per_transfer_context[i]; 2632 2633 /* 2634 * The reasons for doing this check are: 2635 * 1) Protect against calling cleanup before allocating buffers 2636 * 2) In a corner case, FASTPATH_mode_on may be set, but we 2637 * could have a partially filled ring, because of a memory 2638 * allocation failure in the middle of allocating ring. 2639 * This check accounts for that case, checking 2640 * fastpath_mode_on flag or started flag would not have 2641 * covered that case. This is not in performance path, 2642 * so OK to do this. 2643 */ 2644 if (nbuf) { 2645 qdf_nbuf_unmap_single(ce_state->scn->qdf_dev, nbuf, 2646 QDF_DMA_FROM_DEVICE); 2647 qdf_nbuf_free(nbuf); 2648 } 2649 } 2650 } 2651 2652 /** 2653 * hif_update_fastpath_recv_bufs_cnt() - Increments the Rx buf count by 1 2654 * @scn: HIF handle 2655 * 2656 * Datapath Rx CEs are special case, where we reuse all the message buffers. 2657 * Hence we have to post all the entries in the pipe, even, in the beginning 2658 * unlike for other CE pipes where one less than dest_nentries are filled in 2659 * the beginning. 2660 * 2661 * Return: None 2662 */ 2663 static void hif_update_fastpath_recv_bufs_cnt(struct hif_softc *scn) 2664 { 2665 int pipe_num; 2666 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 2667 2668 if (scn->fastpath_mode_on == false) 2669 return; 2670 2671 for (pipe_num = 0; pipe_num < scn->ce_count; pipe_num++) { 2672 struct HIF_CE_pipe_info *pipe_info = 2673 &hif_state->pipe_info[pipe_num]; 2674 struct CE_state *ce_state = 2675 scn->ce_id_to_state[pipe_info->pipe_num]; 2676 2677 if (ce_state->htt_rx_data) 2678 atomic_inc(&pipe_info->recv_bufs_needed); 2679 } 2680 } 2681 #else 2682 static inline void hif_update_fastpath_recv_bufs_cnt(struct hif_softc *scn) 2683 { 2684 } 2685 2686 static inline bool ce_is_fastpath_enabled(struct hif_softc *scn) 2687 { 2688 return false; 2689 } 2690 #endif /* WLAN_FEATURE_FASTPATH */ 2691 2692 void ce_fini(struct CE_handle *copyeng) 2693 { 2694 struct CE_state *CE_state = (struct CE_state *)copyeng; 2695 unsigned int CE_id = CE_state->id; 2696 struct hif_softc *scn = CE_state->scn; 2697 uint32_t desc_size; 2698 2699 bool inited = CE_state->timer_inited; 2700 CE_state->state = CE_UNUSED; 2701 scn->ce_id_to_state[CE_id] = NULL; 2702 /* Set the flag to false first to stop processing in ce_poll_timeout */ 2703 ce_disable_polling(CE_state); 2704 2705 qdf_lro_deinit(CE_state->lro_data); 2706 2707 if (CE_state->src_ring) { 2708 /* Cleanup the datapath Tx ring */ 2709 ce_h2t_tx_ce_cleanup(copyeng); 2710 2711 desc_size = ce_get_desc_size(scn, CE_RING_SRC); 2712 if (CE_state->src_ring->shadow_base_unaligned) 2713 qdf_mem_free(CE_state->src_ring->shadow_base_unaligned); 2714 if (CE_state->src_ring->base_addr_owner_space_unaligned) 2715 ce_free_desc_ring(scn, CE_state->id, 2716 CE_state->src_ring, 2717 desc_size); 2718 ce_srng_cleanup(scn, CE_state, CE_RING_SRC); 2719 qdf_mem_free(CE_state->src_ring); 2720 } 2721 if (CE_state->dest_ring) { 2722 /* Cleanup the datapath Rx ring */ 2723 ce_t2h_msg_ce_cleanup(copyeng); 2724 2725 desc_size = ce_get_desc_size(scn, CE_RING_DEST); 2726 if (CE_state->dest_ring->base_addr_owner_space_unaligned) 2727 ce_free_desc_ring(scn, CE_state->id, 2728 CE_state->dest_ring, 2729 desc_size); 2730 ce_srng_cleanup(scn, CE_state, CE_RING_DEST); 2731 qdf_mem_free(CE_state->dest_ring); 2732 2733 /* epping */ 2734 if (inited) { 2735 qdf_timer_free(&CE_state->poll_timer); 2736 } 2737 } 2738 if ((ce_srng_based(CE_state->scn)) && (CE_state->status_ring)) { 2739 /* Cleanup the datapath Tx ring */ 2740 ce_h2t_tx_ce_cleanup(copyeng); 2741 2742 if (CE_state->status_ring->shadow_base_unaligned) 2743 qdf_mem_free( 2744 CE_state->status_ring->shadow_base_unaligned); 2745 2746 desc_size = ce_get_desc_size(scn, CE_RING_STATUS); 2747 if (CE_state->status_ring->base_addr_owner_space_unaligned) 2748 ce_free_desc_ring(scn, CE_state->id, 2749 CE_state->status_ring, 2750 desc_size); 2751 ce_srng_cleanup(scn, CE_state, CE_RING_STATUS); 2752 qdf_mem_free(CE_state->status_ring); 2753 } 2754 2755 free_mem_ce_debug_history(scn, CE_id); 2756 reset_ce_debug_history(scn); 2757 ce_deinit_ce_desc_event_log(scn, CE_id); 2758 2759 qdf_spinlock_destroy(&CE_state->ce_index_lock); 2760 qdf_mem_free(CE_state); 2761 } 2762 2763 void hif_detach_htc(struct hif_opaque_softc *hif_ctx) 2764 { 2765 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(hif_ctx); 2766 2767 qdf_mem_zero(&hif_state->msg_callbacks_pending, 2768 sizeof(hif_state->msg_callbacks_pending)); 2769 qdf_mem_zero(&hif_state->msg_callbacks_current, 2770 sizeof(hif_state->msg_callbacks_current)); 2771 } 2772 2773 /* Send the first nbytes bytes of the buffer */ 2774 QDF_STATUS 2775 hif_send_head(struct hif_opaque_softc *hif_ctx, 2776 uint8_t pipe, unsigned int transfer_id, unsigned int nbytes, 2777 qdf_nbuf_t nbuf, unsigned int data_attr) 2778 { 2779 struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); 2780 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(hif_ctx); 2781 struct HIF_CE_pipe_info *pipe_info = &(hif_state->pipe_info[pipe]); 2782 struct CE_handle *ce_hdl = pipe_info->ce_hdl; 2783 int bytes = nbytes, nfrags = 0; 2784 struct ce_sendlist sendlist; 2785 int i = 0; 2786 QDF_STATUS status; 2787 unsigned int mux_id = 0; 2788 2789 if (nbytes > qdf_nbuf_len(nbuf)) { 2790 hif_err("nbytes: %d nbuf_len: %d", nbytes, 2791 (uint32_t)qdf_nbuf_len(nbuf)); 2792 QDF_ASSERT(0); 2793 } 2794 2795 transfer_id = 2796 (mux_id & MUX_ID_MASK) | 2797 (transfer_id & TRANSACTION_ID_MASK); 2798 data_attr &= DESC_DATA_FLAG_MASK; 2799 /* 2800 * The common case involves sending multiple fragments within a 2801 * single download (the tx descriptor and the tx frame header). 2802 * So, optimize for the case of multiple fragments by not even 2803 * checking whether it's necessary to use a sendlist. 2804 * The overhead of using a sendlist for a single buffer download 2805 * is not a big deal, since it happens rarely (for WMI messages). 2806 */ 2807 ce_sendlist_init(&sendlist); 2808 do { 2809 qdf_dma_addr_t frag_paddr; 2810 int frag_bytes; 2811 2812 frag_paddr = qdf_nbuf_get_frag_paddr(nbuf, nfrags); 2813 frag_bytes = qdf_nbuf_get_frag_len(nbuf, nfrags); 2814 /* 2815 * Clear the packet offset for all but the first CE desc. 2816 */ 2817 if (i++ > 0) 2818 data_attr &= ~QDF_CE_TX_PKT_OFFSET_BIT_M; 2819 2820 status = ce_sendlist_buf_add(&sendlist, frag_paddr, 2821 frag_bytes > 2822 bytes ? bytes : frag_bytes, 2823 qdf_nbuf_get_frag_is_wordstream 2824 (nbuf, 2825 nfrags) ? 0 : 2826 CE_SEND_FLAG_SWAP_DISABLE, 2827 data_attr); 2828 if (status != QDF_STATUS_SUCCESS) { 2829 hif_err("frag_num: %d larger than limit (status=%d)", 2830 nfrags, status); 2831 return status; 2832 } 2833 bytes -= frag_bytes; 2834 nfrags++; 2835 } while (bytes > 0); 2836 2837 /* Make sure we have resources to handle this request */ 2838 qdf_spin_lock_bh(&pipe_info->completion_freeq_lock); 2839 if (pipe_info->num_sends_allowed < nfrags) { 2840 qdf_spin_unlock_bh(&pipe_info->completion_freeq_lock); 2841 ce_pkt_error_count_incr(hif_state, HIF_PIPE_NO_RESOURCE); 2842 return QDF_STATUS_E_RESOURCES; 2843 } 2844 pipe_info->num_sends_allowed -= nfrags; 2845 qdf_spin_unlock_bh(&pipe_info->completion_freeq_lock); 2846 2847 if (qdf_unlikely(!ce_hdl)) { 2848 hif_err("CE handle is null"); 2849 return A_ERROR; 2850 } 2851 2852 QDF_NBUF_UPDATE_TX_PKT_COUNT(nbuf, QDF_NBUF_TX_PKT_HIF); 2853 DPTRACE(qdf_dp_trace(nbuf, QDF_DP_TRACE_HIF_PACKET_PTR_RECORD, 2854 QDF_TRACE_DEFAULT_PDEV_ID, qdf_nbuf_data_addr(nbuf), 2855 sizeof(qdf_nbuf_data(nbuf)), QDF_TX)); 2856 status = ce_sendlist_send(ce_hdl, nbuf, &sendlist, transfer_id); 2857 QDF_ASSERT(status == QDF_STATUS_SUCCESS); 2858 2859 return status; 2860 } 2861 2862 void hif_send_complete_check(struct hif_opaque_softc *hif_ctx, uint8_t pipe, 2863 int force) 2864 { 2865 struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); 2866 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(hif_ctx); 2867 2868 if (!force) { 2869 int resources; 2870 /* 2871 * Decide whether to actually poll for completions, or just 2872 * wait for a later chance. If there seem to be plenty of 2873 * resources left, then just wait, since checking involves 2874 * reading a CE register, which is a relatively expensive 2875 * operation. 2876 */ 2877 resources = hif_get_free_queue_number(hif_ctx, pipe); 2878 /* 2879 * If at least 50% of the total resources are still available, 2880 * don't bother checking again yet. 2881 */ 2882 if (resources > (hif_state->host_ce_config[pipe].src_nentries >> 2883 1)) 2884 return; 2885 } 2886 #ifdef ATH_11AC_TXCOMPACT 2887 ce_per_engine_servicereap(scn, pipe); 2888 #else 2889 ce_per_engine_service(scn, pipe); 2890 #endif 2891 } 2892 2893 #if defined(CE_TASKLET_SCHEDULE_ON_FULL) && defined(CE_TASKLET_DEBUG_ENABLE) 2894 #define CE_RING_FULL_THRESHOLD_TIME 3000000 2895 #define CE_RING_FULL_THRESHOLD 1024 2896 /* Ths function is called from htc_send path. If there is no resourse to send 2897 * packet via HTC, then check if interrupts are not processed from that 2898 * CE for last 3 seconds. If so, schedule a tasklet to reap available entries. 2899 * Also if Queue has reached 1024 entries within 3 seconds, then also schedule 2900 * tasklet. 2901 */ 2902 void hif_schedule_ce_tasklet(struct hif_opaque_softc *hif_ctx, uint8_t pipe) 2903 { 2904 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(hif_ctx); 2905 uint64_t diff_time = qdf_get_log_timestamp_usecs() - 2906 hif_state->stats.tasklet_sched_entry_ts[pipe]; 2907 2908 hif_state->stats.ce_ring_full_count[pipe]++; 2909 2910 if (diff_time >= CE_RING_FULL_THRESHOLD_TIME || 2911 hif_state->stats.ce_ring_full_count[pipe] >= 2912 CE_RING_FULL_THRESHOLD) { 2913 hif_state->stats.ce_ring_full_count[pipe] = 0; 2914 hif_state->stats.ce_manual_tasklet_schedule_count[pipe]++; 2915 hif_state->stats.ce_last_manual_tasklet_schedule_ts[pipe] = 2916 qdf_get_log_timestamp_usecs(); 2917 ce_dispatch_interrupt(pipe, &hif_state->tasklets[pipe]); 2918 } 2919 } 2920 #else 2921 void hif_schedule_ce_tasklet(struct hif_opaque_softc *hif_ctx, uint8_t pipe) 2922 { 2923 } 2924 #endif 2925 2926 uint16_t 2927 hif_get_free_queue_number(struct hif_opaque_softc *hif_ctx, uint8_t pipe) 2928 { 2929 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(hif_ctx); 2930 struct HIF_CE_pipe_info *pipe_info = &(hif_state->pipe_info[pipe]); 2931 uint16_t rv; 2932 2933 qdf_spin_lock_bh(&pipe_info->completion_freeq_lock); 2934 rv = pipe_info->num_sends_allowed; 2935 qdf_spin_unlock_bh(&pipe_info->completion_freeq_lock); 2936 return rv; 2937 } 2938 2939 /* Called by lower (CE) layer when a send to Target completes. */ 2940 static void 2941 hif_pci_ce_send_done(struct CE_handle *copyeng, void *ce_context, 2942 void *transfer_context, qdf_dma_addr_t CE_data, 2943 unsigned int nbytes, unsigned int transfer_id, 2944 unsigned int sw_index, unsigned int hw_index, 2945 unsigned int toeplitz_hash_result) 2946 { 2947 struct HIF_CE_pipe_info *pipe_info = 2948 (struct HIF_CE_pipe_info *)ce_context; 2949 unsigned int sw_idx = sw_index, hw_idx = hw_index; 2950 struct hif_msg_callbacks *msg_callbacks = 2951 &pipe_info->pipe_callbacks; 2952 2953 do { 2954 /* 2955 * The upper layer callback will be triggered 2956 * when last fragment is complteted. 2957 */ 2958 if (transfer_context != CE_SENDLIST_ITEM_CTXT) 2959 msg_callbacks->txCompletionHandler( 2960 msg_callbacks->Context, 2961 transfer_context, transfer_id, 2962 toeplitz_hash_result); 2963 2964 qdf_spin_lock_bh(&pipe_info->completion_freeq_lock); 2965 pipe_info->num_sends_allowed++; 2966 qdf_spin_unlock_bh(&pipe_info->completion_freeq_lock); 2967 } while (ce_completed_send_next(copyeng, 2968 &ce_context, &transfer_context, 2969 &CE_data, &nbytes, &transfer_id, 2970 &sw_idx, &hw_idx, 2971 &toeplitz_hash_result) == QDF_STATUS_SUCCESS); 2972 } 2973 2974 /** 2975 * hif_ce_do_recv(): send message from copy engine to upper layers 2976 * @msg_callbacks: structure containing callback and callback context 2977 * @netbuff: skb containing message 2978 * @nbytes: number of bytes in the message 2979 * @pipe_info: used for the pipe_number info 2980 * 2981 * Checks the packet length, configures the length in the netbuff, 2982 * and calls the upper layer callback. 2983 * 2984 * return: None 2985 */ 2986 static inline void hif_ce_do_recv(struct hif_msg_callbacks *msg_callbacks, 2987 qdf_nbuf_t netbuf, int nbytes, 2988 struct HIF_CE_pipe_info *pipe_info) { 2989 if (nbytes <= pipe_info->buf_sz) { 2990 qdf_nbuf_set_pktlen(netbuf, nbytes); 2991 msg_callbacks-> 2992 rxCompletionHandler(msg_callbacks->Context, 2993 netbuf, pipe_info->pipe_num); 2994 } else { 2995 hif_err("Invalid Rx msg buf: %pK nbytes: %d", netbuf, nbytes); 2996 qdf_nbuf_free(netbuf); 2997 } 2998 } 2999 3000 /* Called by lower (CE) layer when data is received from the Target. */ 3001 static void 3002 hif_pci_ce_recv_data(struct CE_handle *copyeng, void *ce_context, 3003 void *transfer_context, qdf_dma_addr_t CE_data, 3004 unsigned int nbytes, unsigned int transfer_id, 3005 unsigned int flags) 3006 { 3007 struct HIF_CE_pipe_info *pipe_info = 3008 (struct HIF_CE_pipe_info *)ce_context; 3009 struct HIF_CE_state *hif_state = pipe_info->HIF_CE_state; 3010 struct CE_state *ce_state = (struct CE_state *) copyeng; 3011 struct hif_softc *scn = HIF_GET_SOFTC(hif_state); 3012 struct hif_msg_callbacks *msg_callbacks = &pipe_info->pipe_callbacks; 3013 3014 do { 3015 hif_rtpm_mark_last_busy(HIF_RTPM_ID_CE); 3016 qdf_nbuf_unmap_single(scn->qdf_dev, 3017 (qdf_nbuf_t) transfer_context, 3018 QDF_DMA_FROM_DEVICE); 3019 3020 atomic_inc(&pipe_info->recv_bufs_needed); 3021 hif_post_recv_buffers_for_pipe(pipe_info); 3022 if (scn->target_status == TARGET_STATUS_RESET) 3023 qdf_nbuf_free(transfer_context); 3024 else 3025 hif_ce_do_recv(msg_callbacks, transfer_context, 3026 nbytes, pipe_info); 3027 3028 /* Set up force_break flag if num of receices reaches 3029 * MAX_NUM_OF_RECEIVES 3030 */ 3031 ce_state->receive_count++; 3032 if (qdf_unlikely(hif_ce_service_should_yield(scn, ce_state))) { 3033 ce_state->force_break = 1; 3034 break; 3035 } 3036 } while (ce_completed_recv_next(copyeng, &ce_context, &transfer_context, 3037 &CE_data, &nbytes, &transfer_id, 3038 &flags) == QDF_STATUS_SUCCESS); 3039 3040 } 3041 3042 /* TBDXXX: Set CE High Watermark; invoke txResourceAvailHandler in response */ 3043 3044 void 3045 hif_post_init(struct hif_opaque_softc *hif_ctx, void *unused, 3046 struct hif_msg_callbacks *callbacks) 3047 { 3048 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(hif_ctx); 3049 3050 #ifdef CONFIG_ATH_PCIE_ACCESS_DEBUG 3051 spin_lock_init(&pcie_access_log_lock); 3052 #endif 3053 /* Save callbacks for later installation */ 3054 qdf_mem_copy(&hif_state->msg_callbacks_pending, callbacks, 3055 sizeof(hif_state->msg_callbacks_pending)); 3056 3057 } 3058 3059 static int hif_completion_thread_startup_by_ceid(struct HIF_CE_state *hif_state, 3060 int pipe_num) 3061 { 3062 struct CE_attr attr; 3063 struct hif_softc *scn = HIF_GET_SOFTC(hif_state); 3064 struct hif_msg_callbacks *hif_msg_callbacks = 3065 &hif_state->msg_callbacks_current; 3066 struct HIF_CE_pipe_info *pipe_info; 3067 struct CE_state *ce_state; 3068 3069 if (pipe_num >= CE_COUNT_MAX) 3070 return -EINVAL; 3071 3072 pipe_info = &hif_state->pipe_info[pipe_num]; 3073 ce_state = scn->ce_id_to_state[pipe_num]; 3074 3075 if (!hif_msg_callbacks || 3076 !hif_msg_callbacks->rxCompletionHandler || 3077 !hif_msg_callbacks->txCompletionHandler) { 3078 hif_err("%s: no completion handler registered", __func__); 3079 return -EFAULT; 3080 } 3081 3082 attr = hif_state->host_ce_config[pipe_num]; 3083 if (attr.src_nentries) { 3084 /* pipe used to send to target */ 3085 hif_debug("%s: pipe_num:%d pipe_info:0x%pK\n", 3086 __func__, pipe_num, pipe_info); 3087 ce_send_cb_register(pipe_info->ce_hdl, 3088 hif_pci_ce_send_done, pipe_info, 3089 attr.flags & CE_ATTR_DISABLE_INTR); 3090 pipe_info->num_sends_allowed = attr.src_nentries - 1; 3091 } 3092 if (attr.dest_nentries) { 3093 hif_debug("%s: pipe_num:%d pipe_info:0x%pK\n", 3094 __func__, pipe_num, pipe_info); 3095 /* pipe used to receive from target */ 3096 ce_recv_cb_register(pipe_info->ce_hdl, 3097 hif_pci_ce_recv_data, pipe_info, 3098 attr.flags & CE_ATTR_DISABLE_INTR); 3099 } 3100 3101 if (attr.src_nentries) 3102 qdf_spinlock_create(&pipe_info->completion_freeq_lock); 3103 3104 if (!(ce_state->attr_flags & CE_ATTR_INIT_ON_DEMAND)) 3105 qdf_mem_copy(&pipe_info->pipe_callbacks, hif_msg_callbacks, 3106 sizeof(pipe_info->pipe_callbacks)); 3107 3108 return 0; 3109 } 3110 3111 static int hif_completion_thread_startup(struct HIF_CE_state *hif_state) 3112 { 3113 struct CE_handle *ce_diag = hif_state->ce_diag; 3114 int pipe_num, ret; 3115 struct hif_softc *scn = HIF_GET_SOFTC(hif_state); 3116 3117 /* daemonize("hif_compl_thread"); */ 3118 3119 if (scn->ce_count == 0) { 3120 hif_err("ce_count is 0"); 3121 return -EINVAL; 3122 } 3123 3124 3125 A_TARGET_ACCESS_LIKELY(scn); 3126 for (pipe_num = 0; pipe_num < scn->ce_count; pipe_num++) { 3127 struct HIF_CE_pipe_info *pipe_info; 3128 3129 pipe_info = &hif_state->pipe_info[pipe_num]; 3130 if (pipe_info->ce_hdl == ce_diag) 3131 continue; /* Handle Diagnostic CE specially */ 3132 3133 ret = hif_completion_thread_startup_by_ceid(hif_state, 3134 pipe_num); 3135 if (ret < 0) 3136 return ret; 3137 3138 } 3139 3140 A_TARGET_ACCESS_UNLIKELY(scn); 3141 return 0; 3142 } 3143 3144 /* 3145 * Install pending msg callbacks. 3146 * 3147 * TBDXXX: This hack is needed because upper layers install msg callbacks 3148 * for use with HTC before BMI is done; yet this HIF implementation 3149 * needs to continue to use BMI msg callbacks. Really, upper layers 3150 * should not register HTC callbacks until AFTER BMI phase. 3151 */ 3152 static void hif_msg_callbacks_install(struct hif_softc *scn) 3153 { 3154 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 3155 3156 qdf_mem_copy(&hif_state->msg_callbacks_current, 3157 &hif_state->msg_callbacks_pending, 3158 sizeof(hif_state->msg_callbacks_pending)); 3159 } 3160 3161 void hif_get_default_pipe(struct hif_opaque_softc *hif_hdl, uint8_t *ULPipe, 3162 uint8_t *DLPipe) 3163 { 3164 int ul_is_polled, dl_is_polled; 3165 3166 (void)hif_map_service_to_pipe(hif_hdl, HTC_CTRL_RSVD_SVC, 3167 ULPipe, DLPipe, &ul_is_polled, &dl_is_polled); 3168 } 3169 3170 /** 3171 * hif_dump_pipe_debug_count() - Log error count 3172 * @scn: hif_softc pointer. 3173 * 3174 * Output the pipe error counts of each pipe to log file 3175 * 3176 * Return: N/A 3177 */ 3178 void hif_dump_pipe_debug_count(struct hif_softc *scn) 3179 { 3180 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 3181 int pipe_num; 3182 3183 if (!hif_state) { 3184 hif_err("hif_state is NULL"); 3185 return; 3186 } 3187 for (pipe_num = 0; pipe_num < scn->ce_count; pipe_num++) { 3188 struct HIF_CE_pipe_info *pipe_info; 3189 3190 pipe_info = &hif_state->pipe_info[pipe_num]; 3191 3192 if (pipe_info->nbuf_alloc_err_count > 0 || 3193 pipe_info->nbuf_dma_err_count > 0 || 3194 pipe_info->nbuf_ce_enqueue_err_count) 3195 hif_err( 3196 "pipe_id = %d, recv_bufs_needed = %d, nbuf_alloc_err_count = %u, nbuf_dma_err_count = %u, nbuf_ce_enqueue_err_count = %u", 3197 pipe_info->pipe_num, 3198 atomic_read(&pipe_info->recv_bufs_needed), 3199 pipe_info->nbuf_alloc_err_count, 3200 pipe_info->nbuf_dma_err_count, 3201 pipe_info->nbuf_ce_enqueue_err_count); 3202 } 3203 } 3204 3205 static void hif_post_recv_buffers_failure(struct HIF_CE_pipe_info *pipe_info, 3206 void *nbuf, uint32_t *error_cnt, 3207 enum hif_ce_event_type failure_type, 3208 const char *failure_type_string) 3209 { 3210 int bufs_needed_tmp = atomic_inc_return(&pipe_info->recv_bufs_needed); 3211 struct CE_state *CE_state = (struct CE_state *)pipe_info->ce_hdl; 3212 struct hif_softc *scn = HIF_GET_SOFTC(pipe_info->HIF_CE_state); 3213 int ce_id = CE_state->id; 3214 uint32_t error_cnt_tmp; 3215 3216 qdf_spin_lock_bh(&pipe_info->recv_bufs_needed_lock); 3217 error_cnt_tmp = ++(*error_cnt); 3218 qdf_spin_unlock_bh(&pipe_info->recv_bufs_needed_lock); 3219 hif_debug("pipe_num: %d, needed: %d, err_cnt: %u, fail_type: %s", 3220 pipe_info->pipe_num, bufs_needed_tmp, error_cnt_tmp, 3221 failure_type_string); 3222 hif_record_ce_desc_event(scn, ce_id, failure_type, 3223 NULL, nbuf, bufs_needed_tmp, 0); 3224 /* if we fail to allocate the last buffer for an rx pipe, 3225 * there is no trigger to refill the ce and we will 3226 * eventually crash 3227 */ 3228 if (bufs_needed_tmp == CE_state->dest_ring->nentries - 1 || 3229 (ce_srng_based(scn) && 3230 bufs_needed_tmp == CE_state->dest_ring->nentries - 2)) 3231 qdf_sched_work(scn->qdf_dev, &CE_state->oom_allocation_work); 3232 3233 } 3234 3235 3236 3237 3238 QDF_STATUS hif_post_recv_buffers_for_pipe(struct HIF_CE_pipe_info *pipe_info) 3239 { 3240 struct CE_handle *ce_hdl; 3241 qdf_size_t buf_sz; 3242 struct hif_softc *scn = HIF_GET_SOFTC(pipe_info->HIF_CE_state); 3243 QDF_STATUS status; 3244 uint32_t bufs_posted = 0; 3245 unsigned int ce_id; 3246 3247 buf_sz = pipe_info->buf_sz; 3248 if (buf_sz == 0) { 3249 /* Unused Copy Engine */ 3250 return QDF_STATUS_SUCCESS; 3251 } 3252 3253 ce_hdl = pipe_info->ce_hdl; 3254 ce_id = ((struct CE_state *)ce_hdl)->id; 3255 3256 qdf_spin_lock_bh(&pipe_info->recv_bufs_needed_lock); 3257 while (atomic_read(&pipe_info->recv_bufs_needed) > 0) { 3258 qdf_dma_addr_t CE_data; /* CE space buffer address */ 3259 qdf_nbuf_t nbuf; 3260 3261 atomic_dec(&pipe_info->recv_bufs_needed); 3262 qdf_spin_unlock_bh(&pipe_info->recv_bufs_needed_lock); 3263 3264 hif_record_ce_desc_event(scn, ce_id, 3265 HIF_RX_DESC_PRE_NBUF_ALLOC, NULL, NULL, 3266 0, 0); 3267 nbuf = qdf_nbuf_alloc(scn->qdf_dev, buf_sz, 0, 4, false); 3268 if (!nbuf) { 3269 hif_post_recv_buffers_failure(pipe_info, nbuf, 3270 &pipe_info->nbuf_alloc_err_count, 3271 HIF_RX_NBUF_ALLOC_FAILURE, 3272 "HIF_RX_NBUF_ALLOC_FAILURE"); 3273 return QDF_STATUS_E_NOMEM; 3274 } 3275 3276 hif_record_ce_desc_event(scn, ce_id, 3277 HIF_RX_DESC_PRE_NBUF_MAP, NULL, nbuf, 3278 0, 0); 3279 /* 3280 * qdf_nbuf_peek_header(nbuf, &data, &unused); 3281 * CE_data = dma_map_single(dev, data, buf_sz, ); 3282 * DMA_FROM_DEVICE); 3283 */ 3284 status = qdf_nbuf_map_single(scn->qdf_dev, nbuf, 3285 QDF_DMA_FROM_DEVICE); 3286 3287 if (qdf_unlikely(status != QDF_STATUS_SUCCESS)) { 3288 hif_post_recv_buffers_failure(pipe_info, nbuf, 3289 &pipe_info->nbuf_dma_err_count, 3290 HIF_RX_NBUF_MAP_FAILURE, 3291 "HIF_RX_NBUF_MAP_FAILURE"); 3292 qdf_nbuf_free(nbuf); 3293 return status; 3294 } 3295 3296 CE_data = qdf_nbuf_get_frag_paddr(nbuf, 0); 3297 hif_record_ce_desc_event(scn, ce_id, 3298 HIF_RX_DESC_POST_NBUF_MAP, NULL, nbuf, 3299 0, 0); 3300 qdf_mem_dma_sync_single_for_device(scn->qdf_dev, CE_data, 3301 buf_sz, DMA_FROM_DEVICE); 3302 status = ce_recv_buf_enqueue(ce_hdl, (void *)nbuf, CE_data); 3303 if (qdf_unlikely(status != QDF_STATUS_SUCCESS)) { 3304 hif_post_recv_buffers_failure(pipe_info, nbuf, 3305 &pipe_info->nbuf_ce_enqueue_err_count, 3306 HIF_RX_NBUF_ENQUEUE_FAILURE, 3307 "HIF_RX_NBUF_ENQUEUE_FAILURE"); 3308 3309 qdf_nbuf_unmap_single(scn->qdf_dev, nbuf, 3310 QDF_DMA_FROM_DEVICE); 3311 qdf_nbuf_free(nbuf); 3312 return status; 3313 } 3314 3315 qdf_spin_lock_bh(&pipe_info->recv_bufs_needed_lock); 3316 bufs_posted++; 3317 } 3318 pipe_info->nbuf_alloc_err_count = 3319 (pipe_info->nbuf_alloc_err_count > bufs_posted) ? 3320 pipe_info->nbuf_alloc_err_count - bufs_posted : 0; 3321 pipe_info->nbuf_dma_err_count = 3322 (pipe_info->nbuf_dma_err_count > bufs_posted) ? 3323 pipe_info->nbuf_dma_err_count - bufs_posted : 0; 3324 pipe_info->nbuf_ce_enqueue_err_count = 3325 (pipe_info->nbuf_ce_enqueue_err_count > bufs_posted) ? 3326 pipe_info->nbuf_ce_enqueue_err_count - bufs_posted : 0; 3327 3328 qdf_spin_unlock_bh(&pipe_info->recv_bufs_needed_lock); 3329 3330 return QDF_STATUS_SUCCESS; 3331 } 3332 3333 /* 3334 * Try to post all desired receive buffers for all pipes. 3335 * Returns 0 for non fastpath rx copy engine as 3336 * oom_allocation_work will be scheduled to recover any 3337 * failures, non-zero if unable to completely replenish 3338 * receive buffers for fastpath rx Copy engine. 3339 */ 3340 static QDF_STATUS hif_post_recv_buffers(struct hif_softc *scn) 3341 { 3342 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 3343 int pipe_num; 3344 struct CE_state *ce_state = NULL; 3345 QDF_STATUS qdf_status; 3346 3347 A_TARGET_ACCESS_LIKELY(scn); 3348 for (pipe_num = 0; pipe_num < scn->ce_count; pipe_num++) { 3349 struct HIF_CE_pipe_info *pipe_info; 3350 3351 ce_state = scn->ce_id_to_state[pipe_num]; 3352 pipe_info = &hif_state->pipe_info[pipe_num]; 3353 3354 if (!ce_state) 3355 continue; 3356 3357 /* Do not init dynamic CEs, during initial load */ 3358 if (ce_state->attr_flags & CE_ATTR_INIT_ON_DEMAND) 3359 continue; 3360 3361 if (hif_is_nss_wifi_enabled(scn) && 3362 ce_state && (ce_state->htt_rx_data)) 3363 continue; 3364 3365 qdf_status = hif_post_recv_buffers_for_pipe(pipe_info); 3366 if (!QDF_IS_STATUS_SUCCESS(qdf_status) && ce_state && 3367 ce_state->htt_rx_data && 3368 scn->fastpath_mode_on) { 3369 A_TARGET_ACCESS_UNLIKELY(scn); 3370 return qdf_status; 3371 } 3372 } 3373 3374 A_TARGET_ACCESS_UNLIKELY(scn); 3375 3376 return QDF_STATUS_SUCCESS; 3377 } 3378 3379 QDF_STATUS hif_start(struct hif_opaque_softc *hif_ctx) 3380 { 3381 struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); 3382 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 3383 QDF_STATUS qdf_status = QDF_STATUS_SUCCESS; 3384 3385 hif_update_fastpath_recv_bufs_cnt(scn); 3386 3387 hif_msg_callbacks_install(scn); 3388 3389 if (hif_completion_thread_startup(hif_state)) 3390 return QDF_STATUS_E_FAILURE; 3391 3392 /* enable buffer cleanup */ 3393 hif_state->started = true; 3394 3395 /* Post buffers once to start things off. */ 3396 qdf_status = hif_post_recv_buffers(scn); 3397 if (!QDF_IS_STATUS_SUCCESS(qdf_status)) { 3398 /* cleanup is done in hif_ce_disable */ 3399 hif_err("Failed to post buffers"); 3400 return qdf_status; 3401 } 3402 3403 return qdf_status; 3404 } 3405 3406 static void hif_recv_buffer_cleanup_on_pipe(struct HIF_CE_pipe_info *pipe_info) 3407 { 3408 struct hif_softc *scn; 3409 struct CE_handle *ce_hdl; 3410 uint32_t buf_sz; 3411 struct HIF_CE_state *hif_state; 3412 qdf_nbuf_t netbuf; 3413 qdf_dma_addr_t CE_data; 3414 void *per_CE_context; 3415 3416 buf_sz = pipe_info->buf_sz; 3417 /* Unused Copy Engine */ 3418 if (buf_sz == 0) 3419 return; 3420 3421 3422 hif_state = pipe_info->HIF_CE_state; 3423 if (!hif_state->started) 3424 return; 3425 3426 scn = HIF_GET_SOFTC(hif_state); 3427 ce_hdl = pipe_info->ce_hdl; 3428 3429 if (!scn->qdf_dev) 3430 return; 3431 while (ce_revoke_recv_next 3432 (ce_hdl, &per_CE_context, (void **)&netbuf, 3433 &CE_data) == QDF_STATUS_SUCCESS) { 3434 if (netbuf) { 3435 qdf_nbuf_unmap_single(scn->qdf_dev, netbuf, 3436 QDF_DMA_FROM_DEVICE); 3437 qdf_nbuf_free(netbuf); 3438 } 3439 } 3440 } 3441 3442 static void hif_send_buffer_cleanup_on_pipe(struct HIF_CE_pipe_info *pipe_info) 3443 { 3444 struct CE_handle *ce_hdl; 3445 struct HIF_CE_state *hif_state; 3446 struct hif_softc *scn; 3447 qdf_nbuf_t netbuf; 3448 void *per_CE_context; 3449 qdf_dma_addr_t CE_data; 3450 unsigned int nbytes; 3451 unsigned int id; 3452 uint32_t buf_sz; 3453 uint32_t toeplitz_hash_result; 3454 3455 buf_sz = pipe_info->buf_sz; 3456 if (buf_sz == 0) { 3457 /* Unused Copy Engine */ 3458 return; 3459 } 3460 3461 hif_state = pipe_info->HIF_CE_state; 3462 if (!hif_state->started) { 3463 return; 3464 } 3465 3466 scn = HIF_GET_SOFTC(hif_state); 3467 3468 ce_hdl = pipe_info->ce_hdl; 3469 3470 while (ce_cancel_send_next 3471 (ce_hdl, &per_CE_context, 3472 (void **)&netbuf, &CE_data, &nbytes, 3473 &id, &toeplitz_hash_result) == QDF_STATUS_SUCCESS) { 3474 if (netbuf != CE_SENDLIST_ITEM_CTXT) { 3475 /* 3476 * Packets enqueued by htt_h2t_ver_req_msg() and 3477 * htt_h2t_rx_ring_cfg_msg_ll() have already been 3478 * freed in htt_htc_misc_pkt_pool_free() in 3479 * wlantl_close(), so do not free them here again 3480 * by checking whether it's the endpoint 3481 * which they are queued in. 3482 */ 3483 if (id == scn->htc_htt_tx_endpoint) 3484 return; 3485 /* Indicate the completion to higher 3486 * layer to free the buffer 3487 */ 3488 if (pipe_info->pipe_callbacks.txCompletionHandler) 3489 pipe_info->pipe_callbacks. 3490 txCompletionHandler(pipe_info-> 3491 pipe_callbacks.Context, 3492 netbuf, id, toeplitz_hash_result); 3493 } 3494 } 3495 } 3496 3497 /* 3498 * Cleanup residual buffers for device shutdown: 3499 * buffers that were enqueued for receive 3500 * buffers that were to be sent 3501 * Note: Buffers that had completed but which were 3502 * not yet processed are on a completion queue. They 3503 * are handled when the completion thread shuts down. 3504 */ 3505 static void hif_buffer_cleanup(struct HIF_CE_state *hif_state) 3506 { 3507 int pipe_num; 3508 struct hif_softc *scn = HIF_GET_SOFTC(hif_state); 3509 struct CE_state *ce_state; 3510 3511 for (pipe_num = 0; pipe_num < scn->ce_count; pipe_num++) { 3512 struct HIF_CE_pipe_info *pipe_info; 3513 3514 ce_state = scn->ce_id_to_state[pipe_num]; 3515 if (hif_is_nss_wifi_enabled(scn) && ce_state && 3516 ((ce_state->htt_tx_data) || 3517 (ce_state->htt_rx_data))) { 3518 continue; 3519 } 3520 3521 pipe_info = &hif_state->pipe_info[pipe_num]; 3522 hif_recv_buffer_cleanup_on_pipe(pipe_info); 3523 hif_send_buffer_cleanup_on_pipe(pipe_info); 3524 } 3525 } 3526 3527 void hif_flush_surprise_remove(struct hif_opaque_softc *hif_ctx) 3528 { 3529 struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); 3530 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 3531 3532 hif_buffer_cleanup(hif_state); 3533 } 3534 3535 static void hif_destroy_oom_work(struct hif_softc *scn) 3536 { 3537 struct CE_state *ce_state; 3538 int ce_id; 3539 3540 for (ce_id = 0; ce_id < scn->ce_count; ce_id++) { 3541 ce_state = scn->ce_id_to_state[ce_id]; 3542 if (ce_state) 3543 qdf_destroy_work(scn->qdf_dev, 3544 &ce_state->oom_allocation_work); 3545 } 3546 } 3547 3548 void hif_ce_stop(struct hif_softc *scn) 3549 { 3550 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 3551 int pipe_num; 3552 3553 /* 3554 * before cleaning up any memory, ensure irq & 3555 * bottom half contexts will not be re-entered 3556 */ 3557 hif_disable_isr(&scn->osc); 3558 hif_destroy_oom_work(scn); 3559 scn->hif_init_done = false; 3560 3561 /* 3562 * At this point, asynchronous threads are stopped, 3563 * The Target should not DMA nor interrupt, Host code may 3564 * not initiate anything more. So we just need to clean 3565 * up Host-side state. 3566 */ 3567 3568 if (scn->athdiag_procfs_inited) { 3569 athdiag_procfs_remove(); 3570 scn->athdiag_procfs_inited = false; 3571 } 3572 3573 hif_buffer_cleanup(hif_state); 3574 3575 for (pipe_num = 0; pipe_num < scn->ce_count; pipe_num++) { 3576 struct HIF_CE_pipe_info *pipe_info; 3577 struct CE_attr attr; 3578 struct CE_handle *ce_diag = hif_state->ce_diag; 3579 3580 pipe_info = &hif_state->pipe_info[pipe_num]; 3581 if (pipe_info->ce_hdl) { 3582 if (pipe_info->ce_hdl != ce_diag && 3583 hif_state->started) { 3584 attr = hif_state->host_ce_config[pipe_num]; 3585 if (attr.src_nentries) 3586 qdf_spinlock_destroy(&pipe_info-> 3587 completion_freeq_lock); 3588 } 3589 ce_fini(pipe_info->ce_hdl); 3590 pipe_info->ce_hdl = NULL; 3591 pipe_info->buf_sz = 0; 3592 qdf_spinlock_destroy(&pipe_info->recv_bufs_needed_lock); 3593 } 3594 } 3595 3596 if (hif_state->sleep_timer_init) { 3597 qdf_timer_stop(&hif_state->sleep_timer); 3598 qdf_timer_free(&hif_state->sleep_timer); 3599 hif_state->sleep_timer_init = false; 3600 } 3601 3602 hif_state->started = false; 3603 } 3604 3605 static void hif_get_shadow_reg_cfg(struct hif_softc *scn, 3606 struct shadow_reg_cfg 3607 **target_shadow_reg_cfg_ret, 3608 uint32_t *shadow_cfg_sz_ret) 3609 { 3610 if (target_shadow_reg_cfg_ret) 3611 *target_shadow_reg_cfg_ret = target_shadow_reg_cfg; 3612 if (shadow_cfg_sz_ret) 3613 *shadow_cfg_sz_ret = shadow_cfg_sz; 3614 } 3615 3616 /** 3617 * hif_get_target_ce_config() - get copy engine configuration 3618 * @target_ce_config_ret: basic copy engine configuration 3619 * @target_ce_config_sz_ret: size of the basic configuration in bytes 3620 * @target_service_to_ce_map_ret: service mapping for the copy engines 3621 * @target_service_to_ce_map_sz_ret: size of the mapping in bytes 3622 * @target_shadow_reg_cfg_ret: shadow register configuration 3623 * @shadow_cfg_sz_ret: size of the shadow register configuration in bytes 3624 * 3625 * providing accessor to these values outside of this file. 3626 * currently these are stored in static pointers to const sections. 3627 * there are multiple configurations that are selected from at compile time. 3628 * Runtime selection would need to consider mode, target type and bus type. 3629 * 3630 * Return: return by parameter. 3631 */ 3632 void hif_get_target_ce_config(struct hif_softc *scn, 3633 struct CE_pipe_config **target_ce_config_ret, 3634 uint32_t *target_ce_config_sz_ret, 3635 struct service_to_pipe **target_service_to_ce_map_ret, 3636 uint32_t *target_service_to_ce_map_sz_ret, 3637 struct shadow_reg_cfg **target_shadow_reg_cfg_ret, 3638 uint32_t *shadow_cfg_sz_ret) 3639 { 3640 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 3641 3642 *target_ce_config_ret = hif_state->target_ce_config; 3643 *target_ce_config_sz_ret = hif_state->target_ce_config_sz; 3644 3645 hif_select_service_to_pipe_map(scn, target_service_to_ce_map_ret, 3646 target_service_to_ce_map_sz_ret); 3647 hif_get_shadow_reg_cfg(scn, target_shadow_reg_cfg_ret, 3648 shadow_cfg_sz_ret); 3649 } 3650 3651 #ifdef CONFIG_SHADOW_V3 3652 static void hif_print_hal_shadow_register_cfg(struct pld_wlan_enable_cfg *cfg) 3653 { 3654 int i; 3655 3656 hif_err("v3: num_config %d", cfg->num_shadow_reg_v3_cfg); 3657 3658 for (i = 0; i < cfg->num_shadow_reg_v3_cfg; i++) { 3659 hif_err("i %d, val %x", i, cfg->shadow_reg_v3_cfg[i].addr); 3660 } 3661 } 3662 3663 #elif defined(CONFIG_SHADOW_V2) 3664 static void hif_print_hal_shadow_register_cfg(struct pld_wlan_enable_cfg *cfg) 3665 { 3666 int i; 3667 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 3668 "%s: num_config %d", __func__, cfg->num_shadow_reg_v2_cfg); 3669 3670 for (i = 0; i < cfg->num_shadow_reg_v2_cfg; i++) { 3671 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_INFO, 3672 "%s: i %d, val %x", __func__, i, 3673 cfg->shadow_reg_v2_cfg[i].addr); 3674 } 3675 } 3676 3677 #else 3678 static void hif_print_hal_shadow_register_cfg(struct pld_wlan_enable_cfg *cfg) 3679 { 3680 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 3681 "%s: CONFIG_SHADOW V2/V3 not defined", __func__); 3682 } 3683 #endif 3684 3685 #ifdef ADRASTEA_RRI_ON_DDR 3686 /** 3687 * hif_get_src_ring_read_index(): Called to get the SRRI 3688 * 3689 * @scn: hif_softc pointer 3690 * @CE_ctrl_addr: base address of the CE whose RRI is to be read 3691 * 3692 * This function returns the SRRI to the caller. For CEs that 3693 * dont have interrupts enabled, we look at the DDR based SRRI 3694 * 3695 * Return: SRRI 3696 */ 3697 inline unsigned int hif_get_src_ring_read_index(struct hif_softc *scn, 3698 uint32_t CE_ctrl_addr) 3699 { 3700 struct CE_attr attr; 3701 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 3702 3703 attr = hif_state->host_ce_config[COPY_ENGINE_ID(CE_ctrl_addr)]; 3704 if (attr.flags & CE_ATTR_DISABLE_INTR) { 3705 return CE_SRC_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr); 3706 } else { 3707 if (TARGET_REGISTER_ACCESS_ALLOWED(scn)) 3708 return A_TARGET_READ(scn, 3709 (CE_ctrl_addr) + CURRENT_SRRI_ADDRESS); 3710 else 3711 return CE_SRC_RING_READ_IDX_GET_FROM_DDR(scn, 3712 CE_ctrl_addr); 3713 } 3714 } 3715 3716 /** 3717 * hif_get_dst_ring_read_index(): Called to get the DRRI 3718 * 3719 * @scn: hif_softc pointer 3720 * @CE_ctrl_addr: base address of the CE whose RRI is to be read 3721 * 3722 * This function returns the DRRI to the caller. For CEs that 3723 * dont have interrupts enabled, we look at the DDR based DRRI 3724 * 3725 * Return: DRRI 3726 */ 3727 inline unsigned int hif_get_dst_ring_read_index(struct hif_softc *scn, 3728 uint32_t CE_ctrl_addr) 3729 { 3730 struct CE_attr attr; 3731 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 3732 3733 attr = hif_state->host_ce_config[COPY_ENGINE_ID(CE_ctrl_addr)]; 3734 3735 if (attr.flags & CE_ATTR_DISABLE_INTR) { 3736 return CE_DEST_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr); 3737 } else { 3738 if (TARGET_REGISTER_ACCESS_ALLOWED(scn)) 3739 return A_TARGET_READ(scn, 3740 (CE_ctrl_addr) + CURRENT_DRRI_ADDRESS); 3741 else 3742 return CE_DEST_RING_READ_IDX_GET_FROM_DDR(scn, 3743 CE_ctrl_addr); 3744 } 3745 } 3746 3747 /** 3748 * hif_alloc_rri_on_ddr() - Allocate memory for rri on ddr 3749 * @scn: hif_softc pointer 3750 * 3751 * Return: qdf status 3752 */ 3753 static inline QDF_STATUS hif_alloc_rri_on_ddr(struct hif_softc *scn) 3754 { 3755 qdf_dma_addr_t paddr_rri_on_ddr = 0; 3756 3757 scn->vaddr_rri_on_ddr = 3758 (uint32_t *)qdf_mem_alloc_consistent(scn->qdf_dev, 3759 scn->qdf_dev->dev, (CE_COUNT * sizeof(uint32_t)), 3760 &paddr_rri_on_ddr); 3761 3762 if (!scn->vaddr_rri_on_ddr) { 3763 hif_err("dmaable page alloc fail"); 3764 return QDF_STATUS_E_NOMEM; 3765 } 3766 3767 scn->paddr_rri_on_ddr = paddr_rri_on_ddr; 3768 3769 qdf_mem_zero(scn->vaddr_rri_on_ddr, CE_COUNT * sizeof(uint32_t)); 3770 3771 return QDF_STATUS_SUCCESS; 3772 } 3773 #endif 3774 3775 #if (!defined(QCN7605_SUPPORT)) && defined(ADRASTEA_RRI_ON_DDR) 3776 /** 3777 * hif_config_rri_on_ddr(): Configure the RRI on DDR mechanism 3778 * 3779 * @scn: hif_softc pointer 3780 * 3781 * This function allocates non cached memory on ddr and sends 3782 * the physical address of this memory to the CE hardware. The 3783 * hardware updates the RRI on this particular location. 3784 * 3785 * Return: None 3786 */ 3787 static inline void hif_config_rri_on_ddr(struct hif_softc *scn) 3788 { 3789 unsigned int i; 3790 uint32_t high_paddr, low_paddr; 3791 3792 if (hif_alloc_rri_on_ddr(scn) != QDF_STATUS_SUCCESS) 3793 return; 3794 3795 low_paddr = BITS0_TO_31(scn->paddr_rri_on_ddr); 3796 high_paddr = BITS32_TO_35(scn->paddr_rri_on_ddr); 3797 3798 hif_debug("using srri and drri from DDR"); 3799 3800 WRITE_CE_DDR_ADDRESS_FOR_RRI_LOW(scn, low_paddr); 3801 WRITE_CE_DDR_ADDRESS_FOR_RRI_HIGH(scn, high_paddr); 3802 3803 for (i = 0; i < CE_COUNT; i++) 3804 CE_IDX_UPD_EN_SET(scn, CE_BASE_ADDRESS(i)); 3805 } 3806 #else 3807 /** 3808 * hif_config_rri_on_ddr(): Configure the RRI on DDR mechanism 3809 * 3810 * @scn: hif_softc pointer 3811 * 3812 * This is a dummy implementation for platforms that don't 3813 * support this functionality. 3814 * 3815 * Return: None 3816 */ 3817 static inline void hif_config_rri_on_ddr(struct hif_softc *scn) 3818 { 3819 } 3820 #endif 3821 3822 /** 3823 * hif_update_rri_over_ddr_config() - update rri_over_ddr config for 3824 * QMI command 3825 * @scn: hif context 3826 * @cfg: wlan enable config 3827 * 3828 * In case of Genoa, rri_over_ddr memory configuration is passed 3829 * to firmware through QMI configure command. 3830 */ 3831 #if defined(QCN7605_SUPPORT) && defined(ADRASTEA_RRI_ON_DDR) 3832 static void hif_update_rri_over_ddr_config(struct hif_softc *scn, 3833 struct pld_wlan_enable_cfg *cfg) 3834 { 3835 if (hif_alloc_rri_on_ddr(scn) != QDF_STATUS_SUCCESS) 3836 return; 3837 3838 cfg->rri_over_ddr_cfg_valid = true; 3839 cfg->rri_over_ddr_cfg.base_addr_low = 3840 BITS0_TO_31(scn->paddr_rri_on_ddr); 3841 cfg->rri_over_ddr_cfg.base_addr_high = 3842 BITS32_TO_35(scn->paddr_rri_on_ddr); 3843 } 3844 #else 3845 static void hif_update_rri_over_ddr_config(struct hif_softc *scn, 3846 struct pld_wlan_enable_cfg *cfg) 3847 { 3848 } 3849 #endif 3850 3851 /** 3852 * hif_wlan_enable(): call the platform driver to enable wlan 3853 * @scn: HIF Context 3854 * 3855 * This function passes the con_mode and CE configuration to 3856 * platform driver to enable wlan. 3857 * 3858 * Return: linux error code 3859 */ 3860 int hif_wlan_enable(struct hif_softc *scn) 3861 { 3862 struct hif_opaque_softc *hif_hdl = GET_HIF_OPAQUE_HDL(scn); 3863 struct hif_target_info *tgt_info = hif_get_target_info_handle(hif_hdl); 3864 struct pld_wlan_enable_cfg cfg = { 0 }; 3865 enum pld_driver_mode mode; 3866 uint32_t con_mode = hif_get_conparam(scn); 3867 3868 hif_get_target_ce_config(scn, 3869 (struct CE_pipe_config **)&cfg.ce_tgt_cfg, 3870 &cfg.num_ce_tgt_cfg, 3871 (struct service_to_pipe **)&cfg.ce_svc_cfg, 3872 &cfg.num_ce_svc_pipe_cfg, 3873 (struct shadow_reg_cfg **)&cfg.shadow_reg_cfg, 3874 &cfg.num_shadow_reg_cfg); 3875 3876 /* translate from structure size to array size */ 3877 cfg.num_ce_tgt_cfg /= sizeof(struct CE_pipe_config); 3878 cfg.num_ce_svc_pipe_cfg /= sizeof(struct service_to_pipe); 3879 cfg.num_shadow_reg_cfg /= sizeof(struct shadow_reg_cfg); 3880 3881 switch (tgt_info->target_type) { 3882 case TARGET_TYPE_KIWI: 3883 case TARGET_TYPE_MANGO: 3884 hif_prepare_hal_shadow_reg_cfg_v3(scn, &cfg); 3885 break; 3886 default: 3887 hif_prepare_hal_shadow_register_cfg(scn, 3888 &cfg.shadow_reg_v2_cfg, 3889 &cfg.num_shadow_reg_v2_cfg); 3890 break; 3891 } 3892 3893 hif_print_hal_shadow_register_cfg(&cfg); 3894 3895 hif_update_rri_over_ddr_config(scn, &cfg); 3896 3897 if (QDF_GLOBAL_FTM_MODE == con_mode) 3898 mode = PLD_FTM; 3899 else if (QDF_GLOBAL_COLDBOOT_CALIB_MODE == con_mode) 3900 mode = PLD_COLDBOOT_CALIBRATION; 3901 else if (QDF_GLOBAL_FTM_COLDBOOT_CALIB_MODE == con_mode) 3902 mode = PLD_FTM_COLDBOOT_CALIBRATION; 3903 else if (QDF_IS_EPPING_ENABLED(con_mode)) 3904 mode = PLD_EPPING; 3905 else 3906 mode = PLD_MISSION; 3907 3908 if (BYPASS_QMI) 3909 return 0; 3910 else 3911 return pld_wlan_enable(scn->qdf_dev->dev, &cfg, mode); 3912 } 3913 3914 #ifdef WLAN_FEATURE_EPPING 3915 3916 #define CE_EPPING_USES_IRQ true 3917 3918 void hif_ce_prepare_epping_config(struct hif_softc *scn, 3919 struct HIF_CE_state *hif_state) 3920 { 3921 if (CE_EPPING_USES_IRQ) 3922 hif_state->host_ce_config = host_ce_config_wlan_epping_irq; 3923 else 3924 hif_state->host_ce_config = host_ce_config_wlan_epping_poll; 3925 hif_state->target_ce_config = target_ce_config_wlan_epping; 3926 hif_state->target_ce_config_sz = sizeof(target_ce_config_wlan_epping); 3927 target_shadow_reg_cfg = target_shadow_reg_cfg_epping; 3928 shadow_cfg_sz = sizeof(target_shadow_reg_cfg_epping); 3929 scn->ce_count = EPPING_HOST_CE_COUNT; 3930 } 3931 #endif 3932 3933 #ifdef QCN7605_SUPPORT 3934 static inline 3935 void hif_set_ce_config_qcn7605(struct hif_softc *scn, 3936 struct HIF_CE_state *hif_state) 3937 { 3938 hif_state->host_ce_config = host_ce_config_wlan_qcn7605; 3939 hif_state->target_ce_config = target_ce_config_wlan_qcn7605; 3940 hif_state->target_ce_config_sz = 3941 sizeof(target_ce_config_wlan_qcn7605); 3942 target_shadow_reg_cfg = target_shadow_reg_cfg_map_qcn7605; 3943 shadow_cfg_sz = sizeof(target_shadow_reg_cfg_map_qcn7605); 3944 scn->ce_count = QCN7605_CE_COUNT; 3945 } 3946 #else 3947 static inline 3948 void hif_set_ce_config_qcn7605(struct hif_softc *scn, 3949 struct HIF_CE_state *hif_state) 3950 { 3951 hif_err("QCN7605 not supported"); 3952 } 3953 #endif 3954 3955 #ifdef CE_SVC_CMN_INIT 3956 #ifdef QCA_WIFI_SUPPORT_SRNG 3957 static inline void hif_ce_service_init(void) 3958 { 3959 ce_service_srng_init(); 3960 } 3961 #else 3962 static inline void hif_ce_service_init(void) 3963 { 3964 ce_service_legacy_init(); 3965 } 3966 #endif 3967 #else 3968 static inline void hif_ce_service_init(void) 3969 { 3970 } 3971 #endif 3972 3973 3974 /** 3975 * hif_ce_prepare_config() - load the correct static tables. 3976 * @scn: hif context 3977 * 3978 * Epping uses different static attribute tables than mission mode. 3979 */ 3980 void hif_ce_prepare_config(struct hif_softc *scn) 3981 { 3982 uint32_t mode = hif_get_conparam(scn); 3983 struct hif_opaque_softc *hif_hdl = GET_HIF_OPAQUE_HDL(scn); 3984 struct hif_target_info *tgt_info = hif_get_target_info_handle(hif_hdl); 3985 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 3986 int ret; 3987 int msi_data_count = 0; 3988 int msi_data_start = 0; 3989 int msi_irq_start = 0; 3990 3991 hif_ce_service_init(); 3992 hif_state->ce_services = ce_services_attach(scn); 3993 3994 ret = pld_get_user_msi_assignment(scn->qdf_dev->dev, "CE", 3995 &msi_data_count, &msi_data_start, 3996 &msi_irq_start); 3997 3998 scn->ce_count = HOST_CE_COUNT; 3999 scn->int_assignment = &ce_int_context[msi_data_count]; 4000 scn->free_irq_done = false; 4001 /* if epping is enabled we need to use the epping configuration. */ 4002 if (QDF_IS_EPPING_ENABLED(mode)) { 4003 hif_ce_prepare_epping_config(scn, hif_state); 4004 return; 4005 } 4006 4007 switch (tgt_info->target_type) { 4008 default: 4009 hif_state->host_ce_config = host_ce_config_wlan; 4010 hif_state->target_ce_config = target_ce_config_wlan; 4011 hif_state->target_ce_config_sz = sizeof(target_ce_config_wlan); 4012 break; 4013 case TARGET_TYPE_QCN7605: 4014 hif_set_ce_config_qcn7605(scn, hif_state); 4015 break; 4016 case TARGET_TYPE_AR900B: 4017 case TARGET_TYPE_QCA9984: 4018 case TARGET_TYPE_QCA9888: 4019 if (hif_is_attribute_set(scn, HIF_LOWDESC_CE_NO_PKTLOG_CFG)) { 4020 hif_state->host_ce_config = 4021 host_lowdesc_ce_cfg_wlan_ar900b_nopktlog; 4022 } else if (hif_is_attribute_set(scn, HIF_LOWDESC_CE_CFG)) { 4023 hif_state->host_ce_config = 4024 host_lowdesc_ce_cfg_wlan_ar900b; 4025 } else { 4026 hif_state->host_ce_config = host_ce_config_wlan_ar900b; 4027 } 4028 4029 hif_state->target_ce_config = target_ce_config_wlan_ar900b; 4030 hif_state->target_ce_config_sz = 4031 sizeof(target_ce_config_wlan_ar900b); 4032 4033 break; 4034 4035 case TARGET_TYPE_AR9888: 4036 case TARGET_TYPE_AR9888V2: 4037 if (hif_is_attribute_set(scn, HIF_LOWDESC_CE_CFG)) { 4038 hif_state->host_ce_config = host_lowdesc_ce_cfg_wlan_ar9888; 4039 } else { 4040 hif_state->host_ce_config = host_ce_config_wlan_ar9888; 4041 } 4042 4043 hif_state->target_ce_config = target_ce_config_wlan_ar9888; 4044 hif_state->target_ce_config_sz = 4045 sizeof(target_ce_config_wlan_ar9888); 4046 4047 break; 4048 4049 case TARGET_TYPE_QCA8074: 4050 case TARGET_TYPE_QCA8074V2: 4051 case TARGET_TYPE_QCA6018: 4052 if (scn->bus_type == QDF_BUS_TYPE_PCI) { 4053 hif_state->host_ce_config = 4054 host_ce_config_wlan_qca8074_pci; 4055 hif_state->target_ce_config = 4056 target_ce_config_wlan_qca8074_pci; 4057 hif_state->target_ce_config_sz = 4058 sizeof(target_ce_config_wlan_qca8074_pci); 4059 } else { 4060 hif_state->host_ce_config = host_ce_config_wlan_qca8074; 4061 hif_state->target_ce_config = 4062 target_ce_config_wlan_qca8074; 4063 hif_state->target_ce_config_sz = 4064 sizeof(target_ce_config_wlan_qca8074); 4065 } 4066 break; 4067 case TARGET_TYPE_QCA6290: 4068 hif_state->host_ce_config = host_ce_config_wlan_qca6290; 4069 hif_state->target_ce_config = target_ce_config_wlan_qca6290; 4070 hif_state->target_ce_config_sz = 4071 sizeof(target_ce_config_wlan_qca6290); 4072 4073 scn->ce_count = QCA_6290_CE_COUNT; 4074 break; 4075 case TARGET_TYPE_QCN9000: 4076 hif_state->host_ce_config = host_ce_config_wlan_qcn9000; 4077 hif_state->target_ce_config = target_ce_config_wlan_qcn9000; 4078 hif_state->target_ce_config_sz = 4079 sizeof(target_ce_config_wlan_qcn9000); 4080 scn->ce_count = QCN_9000_CE_COUNT; 4081 scn->disable_wake_irq = 1; 4082 break; 4083 case TARGET_TYPE_QCN9224: 4084 hif_set_ce_config_qcn9224(scn, hif_state); 4085 break; 4086 case TARGET_TYPE_QCA5332: 4087 hif_state->host_ce_config = host_ce_config_wlan_qca5332; 4088 hif_state->target_ce_config = target_ce_config_wlan_qca5332; 4089 hif_state->target_ce_config_sz = 4090 sizeof(target_ce_config_wlan_qca5332); 4091 scn->ce_count = QCA_5332_CE_COUNT; 4092 break; 4093 case TARGET_TYPE_QCN6122: 4094 hif_state->host_ce_config = host_ce_config_wlan_qcn6122; 4095 hif_state->target_ce_config = target_ce_config_wlan_qcn6122; 4096 hif_state->target_ce_config_sz = 4097 sizeof(target_ce_config_wlan_qcn6122); 4098 scn->ce_count = QCN_6122_CE_COUNT; 4099 scn->disable_wake_irq = 1; 4100 break; 4101 case TARGET_TYPE_QCA5018: 4102 hif_state->host_ce_config = host_ce_config_wlan_qca5018; 4103 hif_state->target_ce_config = target_ce_config_wlan_qca5018; 4104 hif_state->target_ce_config_sz = 4105 sizeof(target_ce_config_wlan_qca5018); 4106 scn->ce_count = QCA_5018_CE_COUNT; 4107 break; 4108 case TARGET_TYPE_QCA9574: 4109 hif_state->host_ce_config = host_ce_config_wlan_qca9574; 4110 hif_state->target_ce_config = target_ce_config_wlan_qca9574; 4111 hif_state->target_ce_config_sz = 4112 sizeof(target_ce_config_wlan_qca9574); 4113 break; 4114 case TARGET_TYPE_QCA6390: 4115 hif_state->host_ce_config = host_ce_config_wlan_qca6390; 4116 hif_state->target_ce_config = target_ce_config_wlan_qca6390; 4117 hif_state->target_ce_config_sz = 4118 sizeof(target_ce_config_wlan_qca6390); 4119 4120 scn->ce_count = QCA_6390_CE_COUNT; 4121 break; 4122 case TARGET_TYPE_QCA6490: 4123 hif_state->host_ce_config = host_ce_config_wlan_qca6490; 4124 hif_state->target_ce_config = target_ce_config_wlan_qca6490; 4125 hif_state->target_ce_config_sz = 4126 sizeof(target_ce_config_wlan_qca6490); 4127 4128 scn->ce_count = QCA_6490_CE_COUNT; 4129 break; 4130 case TARGET_TYPE_QCA6750: 4131 hif_state->host_ce_config = host_ce_config_wlan_qca6750; 4132 hif_state->target_ce_config = target_ce_config_wlan_qca6750; 4133 hif_state->target_ce_config_sz = 4134 sizeof(target_ce_config_wlan_qca6750); 4135 4136 scn->ce_count = QCA_6750_CE_COUNT; 4137 break; 4138 case TARGET_TYPE_KIWI: 4139 case TARGET_TYPE_MANGO: 4140 hif_state->host_ce_config = host_ce_config_wlan_kiwi; 4141 hif_state->target_ce_config = target_ce_config_wlan_kiwi; 4142 hif_state->target_ce_config_sz = 4143 sizeof(target_ce_config_wlan_kiwi); 4144 scn->ce_count = KIWI_CE_COUNT; 4145 break; 4146 case TARGET_TYPE_ADRASTEA: 4147 if (hif_is_attribute_set(scn, HIF_LOWDESC_CE_NO_PKTLOG_CFG)) { 4148 hif_state->host_ce_config = 4149 host_lowdesc_ce_config_wlan_adrastea_nopktlog; 4150 hif_state->target_ce_config = 4151 target_lowdesc_ce_config_wlan_adrastea_nopktlog; 4152 hif_state->target_ce_config_sz = 4153 sizeof(target_lowdesc_ce_config_wlan_adrastea_nopktlog); 4154 } else { 4155 hif_state->host_ce_config = 4156 host_ce_config_wlan_adrastea; 4157 hif_state->target_ce_config = 4158 target_ce_config_wlan_adrastea; 4159 hif_state->target_ce_config_sz = 4160 sizeof(target_ce_config_wlan_adrastea); 4161 } 4162 break; 4163 4164 } 4165 QDF_BUG(scn->ce_count <= CE_COUNT_MAX); 4166 } 4167 4168 /** 4169 * hif_ce_open() - do ce specific allocations 4170 * @hif_sc: pointer to hif context 4171 * 4172 * return: 0 for success or QDF_STATUS_E_NOMEM 4173 */ 4174 QDF_STATUS hif_ce_open(struct hif_softc *hif_sc) 4175 { 4176 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(hif_sc); 4177 4178 qdf_spinlock_create(&hif_state->irq_reg_lock); 4179 qdf_spinlock_create(&hif_state->keep_awake_lock); 4180 return QDF_STATUS_SUCCESS; 4181 } 4182 4183 /** 4184 * hif_ce_close() - do ce specific free 4185 * @hif_sc: pointer to hif context 4186 */ 4187 void hif_ce_close(struct hif_softc *hif_sc) 4188 { 4189 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(hif_sc); 4190 4191 qdf_spinlock_destroy(&hif_state->irq_reg_lock); 4192 qdf_spinlock_destroy(&hif_state->keep_awake_lock); 4193 } 4194 4195 /** 4196 * hif_unconfig_ce() - ensure resources from hif_config_ce are freed 4197 * @hif_sc: hif context 4198 * 4199 * uses state variables to support cleaning up when hif_config_ce fails. 4200 */ 4201 void hif_unconfig_ce(struct hif_softc *hif_sc) 4202 { 4203 int pipe_num; 4204 struct HIF_CE_pipe_info *pipe_info; 4205 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(hif_sc); 4206 struct hif_opaque_softc *hif_hdl = GET_HIF_OPAQUE_HDL(hif_sc); 4207 4208 for (pipe_num = 0; pipe_num < hif_sc->ce_count; pipe_num++) { 4209 pipe_info = &hif_state->pipe_info[pipe_num]; 4210 if (pipe_info->ce_hdl) { 4211 ce_unregister_irq(hif_state, (1 << pipe_num)); 4212 } 4213 } 4214 deinit_tasklet_workers(hif_hdl); 4215 for (pipe_num = 0; pipe_num < hif_sc->ce_count; pipe_num++) { 4216 pipe_info = &hif_state->pipe_info[pipe_num]; 4217 if (pipe_info->ce_hdl) { 4218 ce_fini(pipe_info->ce_hdl); 4219 pipe_info->ce_hdl = NULL; 4220 pipe_info->buf_sz = 0; 4221 qdf_spinlock_destroy(&pipe_info->recv_bufs_needed_lock); 4222 } 4223 } 4224 if (hif_sc->athdiag_procfs_inited) { 4225 athdiag_procfs_remove(); 4226 hif_sc->athdiag_procfs_inited = false; 4227 } 4228 } 4229 4230 #ifdef CONFIG_BYPASS_QMI 4231 #ifdef QCN7605_SUPPORT 4232 /** 4233 * hif_post_static_buf_to_target() - post static buffer to WLAN FW 4234 * @scn: pointer to HIF structure 4235 * 4236 * WLAN FW needs 2MB memory from DDR when QMI is disabled. 4237 * 4238 * Return: void 4239 */ 4240 static void hif_post_static_buf_to_target(struct hif_softc *scn) 4241 { 4242 phys_addr_t target_pa; 4243 struct ce_info *ce_info_ptr; 4244 uint32_t msi_data_start; 4245 uint32_t msi_data_count; 4246 uint32_t msi_irq_start; 4247 uint32_t i = 0; 4248 int ret; 4249 4250 scn->vaddr_qmi_bypass = 4251 (uint32_t *)qdf_mem_alloc_consistent(scn->qdf_dev, 4252 scn->qdf_dev->dev, 4253 FW_SHARED_MEM, 4254 &target_pa); 4255 if (!scn->vaddr_qmi_bypass) { 4256 hif_err("Memory allocation failed could not post target buf"); 4257 return; 4258 } 4259 4260 scn->paddr_qmi_bypass = target_pa; 4261 4262 ce_info_ptr = (struct ce_info *)scn->vaddr_qmi_bypass; 4263 4264 if (scn->vaddr_rri_on_ddr) { 4265 ce_info_ptr->rri_over_ddr_low_paddr = 4266 BITS0_TO_31(scn->paddr_rri_on_ddr); 4267 ce_info_ptr->rri_over_ddr_high_paddr = 4268 BITS32_TO_35(scn->paddr_rri_on_ddr); 4269 } 4270 4271 ret = pld_get_user_msi_assignment(scn->qdf_dev->dev, "CE", 4272 &msi_data_count, &msi_data_start, 4273 &msi_irq_start); 4274 if (ret) { 4275 hif_err("Failed to get CE msi config"); 4276 return; 4277 } 4278 4279 for (i = 0; i < CE_COUNT_MAX; i++) { 4280 ce_info_ptr->cfg[i].ce_id = i; 4281 ce_info_ptr->cfg[i].msi_vector = 4282 (i % msi_data_count) + msi_irq_start; 4283 } 4284 4285 hif_write32_mb(scn, scn->mem + BYPASS_QMI_TEMP_REGISTER, target_pa); 4286 hif_info("target va %pK target pa %pa", scn->vaddr_qmi_bypass, 4287 &target_pa); 4288 } 4289 4290 /** 4291 * hif_cleanup_static_buf_to_target() - clean up static buffer to WLAN FW 4292 * @scn: pointer to HIF structure 4293 * 4294 * 4295 * Return: void 4296 */ 4297 void hif_cleanup_static_buf_to_target(struct hif_softc *scn) 4298 { 4299 void *target_va = scn->vaddr_qmi_bypass; 4300 phys_addr_t target_pa = scn->paddr_qmi_bypass; 4301 4302 qdf_mem_free_consistent(scn->qdf_dev, scn->qdf_dev->dev, 4303 FW_SHARED_MEM, target_va, 4304 target_pa, 0); 4305 hif_write32_mb(scn, scn->mem + BYPASS_QMI_TEMP_REGISTER, 0); 4306 } 4307 #else 4308 /** 4309 * hif_post_static_buf_to_target() - post static buffer to WLAN FW 4310 * @scn: pointer to HIF structure 4311 * 4312 * WLAN FW needs 2MB memory from DDR when QMI is disabled. 4313 * 4314 * Return: void 4315 */ 4316 static void hif_post_static_buf_to_target(struct hif_softc *scn) 4317 { 4318 qdf_dma_addr_t target_pa; 4319 4320 scn->vaddr_qmi_bypass = 4321 (uint32_t *)qdf_mem_alloc_consistent(scn->qdf_dev, 4322 scn->qdf_dev->dev, 4323 FW_SHARED_MEM, 4324 &target_pa); 4325 if (!scn->vaddr_qmi_bypass) { 4326 hif_err("Memory allocation failed could not post target buf"); 4327 return; 4328 } 4329 4330 scn->paddr_qmi_bypass = target_pa; 4331 hif_write32_mb(scn, scn->mem + BYPASS_QMI_TEMP_REGISTER, target_pa); 4332 } 4333 4334 /** 4335 * hif_cleanup_static_buf_to_target() - clean up static buffer to WLAN FW 4336 * @scn: pointer to HIF structure 4337 * 4338 * 4339 * Return: void 4340 */ 4341 void hif_cleanup_static_buf_to_target(struct hif_softc *scn) 4342 { 4343 void *target_va = scn->vaddr_qmi_bypass; 4344 phys_addr_t target_pa = scn->paddr_qmi_bypass; 4345 4346 qdf_mem_free_consistent(scn->qdf_dev, scn->qdf_dev->dev, 4347 FW_SHARED_MEM, target_va, 4348 target_pa, 0); 4349 hif_write32_mb(snc, scn->mem + BYPASS_QMI_TEMP_REGISTER, 0); 4350 } 4351 #endif 4352 4353 #else 4354 static inline void hif_post_static_buf_to_target(struct hif_softc *scn) 4355 { 4356 } 4357 4358 void hif_cleanup_static_buf_to_target(struct hif_softc *scn) 4359 { 4360 } 4361 #endif 4362 4363 static int hif_srng_sleep_state_adjust(struct hif_softc *scn, bool sleep_ok, 4364 bool wait_for_it) 4365 { 4366 /* todo */ 4367 return 0; 4368 } 4369 4370 int hif_config_ce_by_id(struct hif_softc *scn, int pipe_num) 4371 { 4372 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 4373 struct hif_opaque_softc *hif_hdl = GET_HIF_OPAQUE_HDL(scn); 4374 struct HIF_CE_pipe_info *pipe_info; 4375 struct CE_state *ce_state = NULL; 4376 struct CE_attr *attr; 4377 int rv = 0; 4378 4379 if (pipe_num >= CE_COUNT_MAX) 4380 return -EINVAL; 4381 4382 pipe_info = &hif_state->pipe_info[pipe_num]; 4383 pipe_info->pipe_num = pipe_num; 4384 pipe_info->HIF_CE_state = hif_state; 4385 attr = &hif_state->host_ce_config[pipe_num]; 4386 ce_state = scn->ce_id_to_state[pipe_num]; 4387 4388 if (ce_state) { 4389 /* Do not reinitialize the CE if its done already */ 4390 rv = QDF_STATUS_E_BUSY; 4391 goto err; 4392 } 4393 4394 pipe_info->ce_hdl = ce_init(scn, pipe_num, attr); 4395 ce_state = scn->ce_id_to_state[pipe_num]; 4396 if (!ce_state) { 4397 A_TARGET_ACCESS_UNLIKELY(scn); 4398 rv = QDF_STATUS_E_FAILURE; 4399 goto err; 4400 } 4401 qdf_spinlock_create(&pipe_info->recv_bufs_needed_lock); 4402 QDF_ASSERT(pipe_info->ce_hdl); 4403 if (!pipe_info->ce_hdl) { 4404 rv = QDF_STATUS_E_FAILURE; 4405 A_TARGET_ACCESS_UNLIKELY(scn); 4406 goto err; 4407 } 4408 4409 ce_state->lro_data = qdf_lro_init(); 4410 4411 if (attr->flags & CE_ATTR_DIAG) { 4412 /* Reserve the ultimate CE for 4413 * Diagnostic Window support 4414 */ 4415 hif_state->ce_diag = pipe_info->ce_hdl; 4416 goto skip; 4417 } 4418 4419 if (hif_is_nss_wifi_enabled(scn) && ce_state && 4420 (ce_state->htt_rx_data)) { 4421 goto skip; 4422 } 4423 4424 pipe_info->buf_sz = (qdf_size_t)(attr->src_sz_max); 4425 if (attr->dest_nentries > 0) { 4426 atomic_set(&pipe_info->recv_bufs_needed, 4427 init_buffer_count(attr->dest_nentries - 1)); 4428 /*SRNG based CE has one entry less */ 4429 if (ce_srng_based(scn)) 4430 atomic_dec(&pipe_info->recv_bufs_needed); 4431 } else { 4432 atomic_set(&pipe_info->recv_bufs_needed, 0); 4433 } 4434 ce_tasklet_init(hif_state, (1 << pipe_num)); 4435 ce_register_irq(hif_state, (1 << pipe_num)); 4436 4437 init_tasklet_worker_by_ceid(hif_hdl, pipe_num); 4438 skip: 4439 return 0; 4440 err: 4441 return rv; 4442 } 4443 4444 #if defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF) 4445 static inline void hif_gen_ce_id_history_idx_mapping(struct hif_softc *scn) 4446 { 4447 struct ce_desc_hist *ce_hist = &scn->hif_ce_desc_hist; 4448 uint8_t ce_id, hist_idx = 0; 4449 4450 for (ce_id = 0; ce_id < scn->ce_count; ce_id++) { 4451 if (IS_CE_DEBUG_ONLY_FOR_CRIT_CE & (1 << ce_id)) 4452 ce_hist->ce_id_hist_map[ce_id] = hist_idx++; 4453 else 4454 ce_hist->ce_id_hist_map[ce_id] = -1; 4455 } 4456 } 4457 #else 4458 static inline void hif_gen_ce_id_history_idx_mapping(struct hif_softc *scn) 4459 { 4460 } 4461 #endif 4462 4463 /** 4464 * hif_config_ce() - configure copy engines 4465 * @scn: hif context 4466 * 4467 * Prepares fw, copy engine hardware and host sw according 4468 * to the attributes selected by hif_ce_prepare_config. 4469 * 4470 * also calls athdiag_procfs_init 4471 * 4472 * return: 0 for success nonzero for failure. 4473 */ 4474 int hif_config_ce(struct hif_softc *scn) 4475 { 4476 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 4477 struct HIF_CE_pipe_info *pipe_info; 4478 int pipe_num; 4479 4480 #ifdef ADRASTEA_SHADOW_REGISTERS 4481 int i; 4482 #endif 4483 QDF_STATUS rv = QDF_STATUS_SUCCESS; 4484 4485 scn->notice_send = true; 4486 scn->ce_service_max_rx_ind_flush = MSG_FLUSH_NUM; 4487 4488 hif_post_static_buf_to_target(scn); 4489 4490 hif_state->fw_indicator_address = FW_INDICATOR_ADDRESS; 4491 4492 hif_config_rri_on_ddr(scn); 4493 4494 if (ce_srng_based(scn)) 4495 scn->bus_ops.hif_target_sleep_state_adjust = 4496 &hif_srng_sleep_state_adjust; 4497 4498 /* Initialise the CE debug history sysfs interface inputs ce_id and 4499 * index. Disable data storing 4500 */ 4501 reset_ce_debug_history(scn); 4502 hif_gen_ce_id_history_idx_mapping(scn); 4503 4504 for (pipe_num = 0; pipe_num < scn->ce_count; pipe_num++) { 4505 struct CE_attr *attr; 4506 4507 pipe_info = &hif_state->pipe_info[pipe_num]; 4508 attr = &hif_state->host_ce_config[pipe_num]; 4509 4510 if (attr->flags & CE_ATTR_INIT_ON_DEMAND) 4511 continue; 4512 4513 if (hif_config_ce_by_id(scn, pipe_num)) 4514 goto err; 4515 } 4516 4517 if (athdiag_procfs_init(scn) != 0) { 4518 A_TARGET_ACCESS_UNLIKELY(scn); 4519 goto err; 4520 } 4521 scn->athdiag_procfs_inited = true; 4522 4523 hif_debug("ce_init done"); 4524 hif_debug("%s: X, ret = %d", __func__, rv); 4525 4526 #ifdef ADRASTEA_SHADOW_REGISTERS 4527 hif_debug("Using Shadow Registers instead of CE Registers"); 4528 for (i = 0; i < NUM_SHADOW_REGISTERS; i++) { 4529 hif_debug("Shadow Register%d is mapped to address %x", 4530 i, 4531 (A_TARGET_READ(scn, (SHADOW_ADDRESS(i))) << 2)); 4532 } 4533 #endif 4534 4535 return rv != QDF_STATUS_SUCCESS; 4536 err: 4537 /* Failure, so clean up */ 4538 hif_unconfig_ce(scn); 4539 hif_info("X, ret = %d", rv); 4540 return QDF_STATUS_SUCCESS != QDF_STATUS_E_FAILURE; 4541 } 4542 4543 /** 4544 * hif_config_ce_pktlog() - configure copy engines 4545 * @scn: hif context 4546 * 4547 * Prepares fw, copy engine hardware and host sw according 4548 * to the attributes selected by hif_ce_prepare_config. 4549 * 4550 * also calls athdiag_procfs_init 4551 * 4552 * return: 0 for success nonzero for failure. 4553 */ 4554 int hif_config_ce_pktlog(struct hif_opaque_softc *hif_hdl) 4555 { 4556 struct hif_softc *scn = HIF_GET_SOFTC(hif_hdl); 4557 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 4558 int pipe_num; 4559 QDF_STATUS qdf_status = QDF_STATUS_E_FAILURE; 4560 struct HIF_CE_pipe_info *pipe_info; 4561 4562 if (!scn) 4563 goto err; 4564 4565 if (scn->pktlog_init) 4566 return QDF_STATUS_SUCCESS; 4567 4568 pipe_num = hif_get_pktlog_ce_num(scn); 4569 if (pipe_num < 0) { 4570 qdf_status = QDF_STATUS_E_FAILURE; 4571 goto err; 4572 } 4573 4574 pipe_info = &hif_state->pipe_info[pipe_num]; 4575 4576 qdf_status = hif_config_ce_by_id(scn, pipe_num); 4577 /* CE Already initialized. Do not try to reinitialized again */ 4578 if (qdf_status == QDF_STATUS_E_BUSY) 4579 return QDF_STATUS_SUCCESS; 4580 4581 qdf_status = hif_config_irq_by_ceid(scn, pipe_num); 4582 if (qdf_status < 0) 4583 goto err; 4584 4585 qdf_status = hif_completion_thread_startup_by_ceid(hif_state, pipe_num); 4586 if (!QDF_IS_STATUS_SUCCESS(qdf_status)) { 4587 hif_err("%s:failed to start hif thread", __func__); 4588 goto err; 4589 } 4590 4591 /* Post buffers for pktlog copy engine. */ 4592 qdf_status = hif_post_recv_buffers_for_pipe(pipe_info); 4593 if (!QDF_IS_STATUS_SUCCESS(qdf_status)) { 4594 /* cleanup is done in hif_ce_disable */ 4595 hif_err("%s:failed to post buffers", __func__); 4596 return qdf_status; 4597 } 4598 scn->pktlog_init = true; 4599 return qdf_status != QDF_STATUS_SUCCESS; 4600 4601 err: 4602 hif_debug("%s: X, ret = %d", __func__, qdf_status); 4603 return QDF_STATUS_SUCCESS != QDF_STATUS_E_FAILURE; 4604 } 4605 4606 #ifdef IPA_OFFLOAD 4607 /** 4608 * hif_ce_ipa_get_ce_resource() - get uc resource on hif 4609 * @scn: bus context 4610 * @ce_sr_base_paddr: copyengine source ring base physical address 4611 * @ce_sr_ring_size: copyengine source ring size 4612 * @ce_reg_paddr: copyengine register physical address 4613 * 4614 * IPA micro controller data path offload feature enabled, 4615 * HIF should release copy engine related resource information to IPA UC 4616 * IPA UC will access hardware resource with released information 4617 * 4618 * Return: None 4619 */ 4620 void hif_ce_ipa_get_ce_resource(struct hif_softc *scn, 4621 qdf_shared_mem_t **ce_sr, 4622 uint32_t *ce_sr_ring_size, 4623 qdf_dma_addr_t *ce_reg_paddr) 4624 { 4625 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 4626 struct HIF_CE_pipe_info *pipe_info = 4627 &(hif_state->pipe_info[HIF_PCI_IPA_UC_ASSIGNED_CE]); 4628 struct CE_handle *ce_hdl = pipe_info->ce_hdl; 4629 4630 ce_ipa_get_resource(ce_hdl, ce_sr, ce_sr_ring_size, 4631 ce_reg_paddr); 4632 } 4633 #endif /* IPA_OFFLOAD */ 4634 4635 4636 #ifdef ADRASTEA_SHADOW_REGISTERS 4637 4638 /* 4639 * Current shadow register config 4640 * 4641 * ----------------------------------------------------------- 4642 * Shadow Register | CE | src/dst write index 4643 * ----------------------------------------------------------- 4644 * 0 | 0 | src 4645 * 1 No Config - Doesn't point to anything 4646 * 2 No Config - Doesn't point to anything 4647 * 3 | 3 | src 4648 * 4 | 4 | src 4649 * 5 | 5 | src 4650 * 6 No Config - Doesn't point to anything 4651 * 7 | 7 | src 4652 * 8 No Config - Doesn't point to anything 4653 * 9 No Config - Doesn't point to anything 4654 * 10 No Config - Doesn't point to anything 4655 * 11 No Config - Doesn't point to anything 4656 * ----------------------------------------------------------- 4657 * 12 No Config - Doesn't point to anything 4658 * 13 | 1 | dst 4659 * 14 | 2 | dst 4660 * 15 No Config - Doesn't point to anything 4661 * 16 No Config - Doesn't point to anything 4662 * 17 No Config - Doesn't point to anything 4663 * 18 No Config - Doesn't point to anything 4664 * 19 | 7 | dst 4665 * 20 | 8 | dst 4666 * 21 No Config - Doesn't point to anything 4667 * 22 No Config - Doesn't point to anything 4668 * 23 No Config - Doesn't point to anything 4669 * ----------------------------------------------------------- 4670 * 4671 * 4672 * ToDo - Move shadow register config to following in the future 4673 * This helps free up a block of shadow registers towards the end. 4674 * Can be used for other purposes 4675 * 4676 * ----------------------------------------------------------- 4677 * Shadow Register | CE | src/dst write index 4678 * ----------------------------------------------------------- 4679 * 0 | 0 | src 4680 * 1 | 3 | src 4681 * 2 | 4 | src 4682 * 3 | 5 | src 4683 * 4 | 7 | src 4684 * ----------------------------------------------------------- 4685 * 5 | 1 | dst 4686 * 6 | 2 | dst 4687 * 7 | 7 | dst 4688 * 8 | 8 | dst 4689 * ----------------------------------------------------------- 4690 * 9 No Config - Doesn't point to anything 4691 * 12 No Config - Doesn't point to anything 4692 * 13 No Config - Doesn't point to anything 4693 * 14 No Config - Doesn't point to anything 4694 * 15 No Config - Doesn't point to anything 4695 * 16 No Config - Doesn't point to anything 4696 * 17 No Config - Doesn't point to anything 4697 * 18 No Config - Doesn't point to anything 4698 * 19 No Config - Doesn't point to anything 4699 * 20 No Config - Doesn't point to anything 4700 * 21 No Config - Doesn't point to anything 4701 * 22 No Config - Doesn't point to anything 4702 * 23 No Config - Doesn't point to anything 4703 * ----------------------------------------------------------- 4704 */ 4705 #ifndef QCN7605_SUPPORT 4706 u32 shadow_sr_wr_ind_addr(struct hif_softc *scn, u32 ctrl_addr) 4707 { 4708 u32 addr = 0; 4709 u32 ce = COPY_ENGINE_ID(ctrl_addr); 4710 4711 switch (ce) { 4712 case 0: 4713 addr = SHADOW_VALUE0; 4714 break; 4715 case 3: 4716 addr = SHADOW_VALUE3; 4717 break; 4718 case 4: 4719 addr = SHADOW_VALUE4; 4720 break; 4721 case 5: 4722 addr = SHADOW_VALUE5; 4723 break; 4724 case 7: 4725 addr = SHADOW_VALUE7; 4726 break; 4727 default: 4728 hif_err("Invalid CE ctrl_addr (CE=%d)", ce); 4729 QDF_ASSERT(0); 4730 } 4731 return addr; 4732 4733 } 4734 4735 u32 shadow_dst_wr_ind_addr(struct hif_softc *scn, u32 ctrl_addr) 4736 { 4737 u32 addr = 0; 4738 u32 ce = COPY_ENGINE_ID(ctrl_addr); 4739 4740 switch (ce) { 4741 case 1: 4742 addr = SHADOW_VALUE13; 4743 break; 4744 case 2: 4745 addr = SHADOW_VALUE14; 4746 break; 4747 case 5: 4748 addr = SHADOW_VALUE17; 4749 break; 4750 case 7: 4751 addr = SHADOW_VALUE19; 4752 break; 4753 case 8: 4754 addr = SHADOW_VALUE20; 4755 break; 4756 case 9: 4757 addr = SHADOW_VALUE21; 4758 break; 4759 case 10: 4760 addr = SHADOW_VALUE22; 4761 break; 4762 case 11: 4763 addr = SHADOW_VALUE23; 4764 break; 4765 default: 4766 hif_err("Invalid CE ctrl_addr (CE=%d)", ce); 4767 QDF_ASSERT(0); 4768 } 4769 4770 return addr; 4771 4772 } 4773 #else 4774 u32 shadow_sr_wr_ind_addr(struct hif_softc *scn, u32 ctrl_addr) 4775 { 4776 u32 addr = 0; 4777 u32 ce = COPY_ENGINE_ID(ctrl_addr); 4778 4779 switch (ce) { 4780 case 0: 4781 addr = SHADOW_VALUE0; 4782 break; 4783 case 3: 4784 addr = SHADOW_VALUE3; 4785 break; 4786 case 4: 4787 addr = SHADOW_VALUE4; 4788 break; 4789 case 5: 4790 addr = SHADOW_VALUE5; 4791 break; 4792 default: 4793 hif_err("Invalid CE ctrl_addr (CE=%d)", ce); 4794 QDF_ASSERT(0); 4795 } 4796 return addr; 4797 } 4798 4799 u32 shadow_dst_wr_ind_addr(struct hif_softc *scn, u32 ctrl_addr) 4800 { 4801 u32 addr = 0; 4802 u32 ce = COPY_ENGINE_ID(ctrl_addr); 4803 4804 switch (ce) { 4805 case 1: 4806 addr = SHADOW_VALUE13; 4807 break; 4808 case 2: 4809 addr = SHADOW_VALUE14; 4810 break; 4811 case 3: 4812 addr = SHADOW_VALUE15; 4813 break; 4814 case 5: 4815 addr = SHADOW_VALUE17; 4816 break; 4817 case 7: 4818 addr = SHADOW_VALUE19; 4819 break; 4820 case 8: 4821 addr = SHADOW_VALUE20; 4822 break; 4823 case 9: 4824 addr = SHADOW_VALUE21; 4825 break; 4826 case 10: 4827 addr = SHADOW_VALUE22; 4828 break; 4829 case 11: 4830 addr = SHADOW_VALUE23; 4831 break; 4832 default: 4833 hif_err("Invalid CE ctrl_addr (CE=%d)", ce); 4834 QDF_ASSERT(0); 4835 } 4836 4837 return addr; 4838 } 4839 #endif 4840 #endif 4841 4842 #if defined(FEATURE_LRO) 4843 void *hif_ce_get_lro_ctx(struct hif_opaque_softc *hif_hdl, int ctx_id) 4844 { 4845 struct CE_state *ce_state; 4846 struct hif_softc *scn = HIF_GET_SOFTC(hif_hdl); 4847 4848 ce_state = scn->ce_id_to_state[ctx_id]; 4849 4850 return ce_state->lro_data; 4851 } 4852 #endif 4853 4854 /** 4855 * hif_map_service_to_pipe() - returns the ce ids pertaining to 4856 * this service 4857 * @scn: hif_softc pointer. 4858 * @svc_id: Service ID for which the mapping is needed. 4859 * @ul_pipe: address of the container in which ul pipe is returned. 4860 * @dl_pipe: address of the container in which dl pipe is returned. 4861 * @ul_is_polled: address of the container in which a bool 4862 * indicating if the UL CE for this service 4863 * is polled is returned. 4864 * @dl_is_polled: address of the container in which a bool 4865 * indicating if the DL CE for this service 4866 * is polled is returned. 4867 * 4868 * Return: Indicates whether the service has been found in the table. 4869 * Upon return, ul_is_polled is updated only if ul_pipe is updated. 4870 * There will be warning logs if either leg has not been updated 4871 * because it missed the entry in the table (but this is not an err). 4872 */ 4873 int hif_map_service_to_pipe(struct hif_opaque_softc *hif_hdl, uint16_t svc_id, 4874 uint8_t *ul_pipe, uint8_t *dl_pipe, int *ul_is_polled, 4875 int *dl_is_polled) 4876 { 4877 int status = -EINVAL; 4878 unsigned int i; 4879 struct service_to_pipe element; 4880 struct service_to_pipe *tgt_svc_map_to_use; 4881 uint32_t sz_tgt_svc_map_to_use; 4882 struct hif_softc *scn = HIF_GET_SOFTC(hif_hdl); 4883 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 4884 bool dl_updated = false; 4885 bool ul_updated = false; 4886 4887 hif_select_service_to_pipe_map(scn, &tgt_svc_map_to_use, 4888 &sz_tgt_svc_map_to_use); 4889 4890 *dl_is_polled = 0; /* polling for received messages not supported */ 4891 4892 for (i = 0; i < (sz_tgt_svc_map_to_use/sizeof(element)); i++) { 4893 4894 memcpy(&element, &tgt_svc_map_to_use[i], sizeof(element)); 4895 if (element.service_id == svc_id) { 4896 if (element.pipedir == PIPEDIR_OUT) { 4897 *ul_pipe = element.pipenum; 4898 *ul_is_polled = 4899 (hif_state->host_ce_config[*ul_pipe].flags & 4900 CE_ATTR_DISABLE_INTR) != 0; 4901 ul_updated = true; 4902 } else if (element.pipedir == PIPEDIR_IN) { 4903 *dl_pipe = element.pipenum; 4904 dl_updated = true; 4905 } 4906 status = 0; 4907 } 4908 } 4909 if (ul_updated == false) 4910 hif_debug("ul pipe is NOT updated for service %d", svc_id); 4911 if (dl_updated == false) 4912 hif_debug("dl pipe is NOT updated for service %d", svc_id); 4913 4914 return status; 4915 } 4916 4917 #ifdef SHADOW_REG_DEBUG 4918 inline uint32_t DEBUG_CE_SRC_RING_READ_IDX_GET(struct hif_softc *scn, 4919 uint32_t CE_ctrl_addr) 4920 { 4921 uint32_t read_from_hw, srri_from_ddr = 0; 4922 4923 read_from_hw = A_TARGET_READ(scn, CE_ctrl_addr + CURRENT_SRRI_ADDRESS); 4924 4925 srri_from_ddr = SRRI_FROM_DDR_ADDR(VADDR_FOR_CE(scn, CE_ctrl_addr)); 4926 4927 if (read_from_hw != srri_from_ddr) { 4928 hif_err("read from ddr = %d actual read from register = %d, CE_MISC_INT_STATUS_GET = 0x%x", 4929 srri_from_ddr, read_from_hw, 4930 CE_MISC_INT_STATUS_GET(scn, CE_ctrl_addr)); 4931 QDF_ASSERT(0); 4932 } 4933 return srri_from_ddr; 4934 } 4935 4936 4937 inline uint32_t DEBUG_CE_DEST_RING_READ_IDX_GET(struct hif_softc *scn, 4938 uint32_t CE_ctrl_addr) 4939 { 4940 uint32_t read_from_hw, drri_from_ddr = 0; 4941 4942 read_from_hw = A_TARGET_READ(scn, CE_ctrl_addr + CURRENT_DRRI_ADDRESS); 4943 4944 drri_from_ddr = DRRI_FROM_DDR_ADDR(VADDR_FOR_CE(scn, CE_ctrl_addr)); 4945 4946 if (read_from_hw != drri_from_ddr) { 4947 hif_err("read from ddr = %d actual read from register = %d, CE_MISC_INT_STATUS_GET = 0x%x", 4948 drri_from_ddr, read_from_hw, 4949 CE_MISC_INT_STATUS_GET(scn, CE_ctrl_addr)); 4950 QDF_ASSERT(0); 4951 } 4952 return drri_from_ddr; 4953 } 4954 4955 #endif 4956 4957 /** 4958 * hif_dump_ce_registers() - dump ce registers 4959 * @scn: hif_opaque_softc pointer. 4960 * 4961 * Output the copy engine registers 4962 * 4963 * Return: 0 for success or error code 4964 */ 4965 int hif_dump_ce_registers(struct hif_softc *scn) 4966 { 4967 struct hif_opaque_softc *hif_hdl = GET_HIF_OPAQUE_HDL(scn); 4968 uint32_t ce_reg_address = CE0_BASE_ADDRESS; 4969 uint32_t ce_reg_values[CE_USEFUL_SIZE >> 2]; 4970 uint32_t ce_reg_word_size = CE_USEFUL_SIZE >> 2; 4971 uint16_t i; 4972 QDF_STATUS status; 4973 4974 for (i = 0; i < scn->ce_count; i++, ce_reg_address += CE_OFFSET) { 4975 if (!scn->ce_id_to_state[i]) { 4976 hif_debug("CE%d not used", i); 4977 continue; 4978 } 4979 4980 status = hif_diag_read_mem(hif_hdl, ce_reg_address, 4981 (uint8_t *) &ce_reg_values[0], 4982 ce_reg_word_size * sizeof(uint32_t)); 4983 4984 if (status != QDF_STATUS_SUCCESS) { 4985 hif_err("Dumping CE register failed!"); 4986 return -EACCES; 4987 } 4988 hif_debug("CE%d=>", i); 4989 qdf_trace_hex_dump(QDF_MODULE_ID_HIF, QDF_TRACE_LEVEL_DEBUG, 4990 (uint8_t *) &ce_reg_values[0], 4991 ce_reg_word_size * sizeof(uint32_t)); 4992 qdf_print("ADDR:[0x%08X], SR_WR_INDEX:%d", (ce_reg_address 4993 + SR_WR_INDEX_ADDRESS), 4994 ce_reg_values[SR_WR_INDEX_ADDRESS/4]); 4995 qdf_print("ADDR:[0x%08X], CURRENT_SRRI:%d", (ce_reg_address 4996 + CURRENT_SRRI_ADDRESS), 4997 ce_reg_values[CURRENT_SRRI_ADDRESS/4]); 4998 qdf_print("ADDR:[0x%08X], DST_WR_INDEX:%d", (ce_reg_address 4999 + DST_WR_INDEX_ADDRESS), 5000 ce_reg_values[DST_WR_INDEX_ADDRESS/4]); 5001 qdf_print("ADDR:[0x%08X], CURRENT_DRRI:%d", (ce_reg_address 5002 + CURRENT_DRRI_ADDRESS), 5003 ce_reg_values[CURRENT_DRRI_ADDRESS/4]); 5004 qdf_print("---"); 5005 } 5006 return 0; 5007 } 5008 qdf_export_symbol(hif_dump_ce_registers); 5009 #ifdef QCA_NSS_WIFI_OFFLOAD_SUPPORT 5010 struct hif_pipe_addl_info *hif_get_addl_pipe_info(struct hif_opaque_softc *osc, 5011 struct hif_pipe_addl_info *hif_info, uint32_t pipe) 5012 { 5013 struct hif_softc *scn = HIF_GET_SOFTC(osc); 5014 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn); 5015 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(osc); 5016 struct HIF_CE_pipe_info *pipe_info = &(hif_state->pipe_info[pipe]); 5017 struct CE_handle *ce_hdl = pipe_info->ce_hdl; 5018 struct CE_state *ce_state = (struct CE_state *)ce_hdl; 5019 struct CE_ring_state *src_ring = ce_state->src_ring; 5020 struct CE_ring_state *dest_ring = ce_state->dest_ring; 5021 5022 if (src_ring) { 5023 hif_info->ul_pipe.nentries = src_ring->nentries; 5024 hif_info->ul_pipe.nentries_mask = src_ring->nentries_mask; 5025 hif_info->ul_pipe.sw_index = src_ring->sw_index; 5026 hif_info->ul_pipe.write_index = src_ring->write_index; 5027 hif_info->ul_pipe.hw_index = src_ring->hw_index; 5028 hif_info->ul_pipe.base_addr_CE_space = 5029 src_ring->base_addr_CE_space; 5030 hif_info->ul_pipe.base_addr_owner_space = 5031 src_ring->base_addr_owner_space; 5032 } 5033 5034 5035 if (dest_ring) { 5036 hif_info->dl_pipe.nentries = dest_ring->nentries; 5037 hif_info->dl_pipe.nentries_mask = dest_ring->nentries_mask; 5038 hif_info->dl_pipe.sw_index = dest_ring->sw_index; 5039 hif_info->dl_pipe.write_index = dest_ring->write_index; 5040 hif_info->dl_pipe.hw_index = dest_ring->hw_index; 5041 hif_info->dl_pipe.base_addr_CE_space = 5042 dest_ring->base_addr_CE_space; 5043 hif_info->dl_pipe.base_addr_owner_space = 5044 dest_ring->base_addr_owner_space; 5045 } 5046 5047 hif_info->pci_mem = pci_resource_start(sc->pdev, 0); 5048 hif_info->ctrl_addr = ce_state->ctrl_addr; 5049 5050 return hif_info; 5051 } 5052 qdf_export_symbol(hif_get_addl_pipe_info); 5053 5054 uint32_t hif_set_nss_wifiol_mode(struct hif_opaque_softc *osc, uint32_t mode) 5055 { 5056 struct hif_softc *scn = HIF_GET_SOFTC(osc); 5057 5058 scn->nss_wifi_ol_mode = mode; 5059 return 0; 5060 } 5061 qdf_export_symbol(hif_set_nss_wifiol_mode); 5062 #endif 5063 5064 void hif_set_attribute(struct hif_opaque_softc *osc, uint8_t hif_attrib) 5065 { 5066 struct hif_softc *scn = HIF_GET_SOFTC(osc); 5067 scn->hif_attribute = hif_attrib; 5068 } 5069 5070 5071 /* disable interrupts (only applicable for legacy copy engine currently */ 5072 void hif_disable_interrupt(struct hif_opaque_softc *osc, uint32_t pipe_num) 5073 { 5074 struct hif_softc *scn = HIF_GET_SOFTC(osc); 5075 struct CE_state *CE_state = scn->ce_id_to_state[pipe_num]; 5076 uint32_t ctrl_addr = CE_state->ctrl_addr; 5077 5078 Q_TARGET_ACCESS_BEGIN(scn); 5079 CE_COPY_COMPLETE_INTR_DISABLE(scn, ctrl_addr); 5080 Q_TARGET_ACCESS_END(scn); 5081 } 5082 qdf_export_symbol(hif_disable_interrupt); 5083 5084 /** 5085 * hif_fw_event_handler() - hif fw event handler 5086 * @hif_state: pointer to hif ce state structure 5087 * 5088 * Process fw events and raise HTC callback to process fw events. 5089 * 5090 * Return: none 5091 */ 5092 static inline void hif_fw_event_handler(struct HIF_CE_state *hif_state) 5093 { 5094 struct hif_msg_callbacks *msg_callbacks = 5095 &hif_state->msg_callbacks_current; 5096 5097 if (!msg_callbacks->fwEventHandler) 5098 return; 5099 5100 msg_callbacks->fwEventHandler(msg_callbacks->Context, 5101 QDF_STATUS_E_FAILURE); 5102 } 5103 5104 #ifndef QCA_WIFI_3_0 5105 /** 5106 * hif_fw_interrupt_handler() - FW interrupt handler 5107 * @irq: irq number 5108 * @arg: the user pointer 5109 * 5110 * Called from the PCI interrupt handler when a 5111 * firmware-generated interrupt to the Host. 5112 * 5113 * only registered for legacy ce devices 5114 * 5115 * Return: status of handled irq 5116 */ 5117 irqreturn_t hif_fw_interrupt_handler(int irq, void *arg) 5118 { 5119 struct hif_softc *scn = arg; 5120 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 5121 uint32_t fw_indicator_address, fw_indicator; 5122 5123 if (Q_TARGET_ACCESS_BEGIN(scn) < 0) 5124 return ATH_ISR_NOSCHED; 5125 5126 fw_indicator_address = hif_state->fw_indicator_address; 5127 /* For sudden unplug this will return ~0 */ 5128 fw_indicator = A_TARGET_READ(scn, fw_indicator_address); 5129 5130 if ((fw_indicator != ~0) && (fw_indicator & FW_IND_EVENT_PENDING)) { 5131 /* ACK: clear Target-side pending event */ 5132 A_TARGET_WRITE(scn, fw_indicator_address, 5133 fw_indicator & ~FW_IND_EVENT_PENDING); 5134 if (Q_TARGET_ACCESS_END(scn) < 0) 5135 return ATH_ISR_SCHED; 5136 5137 if (hif_state->started) { 5138 hif_fw_event_handler(hif_state); 5139 } else { 5140 /* 5141 * Probable Target failure before we're prepared 5142 * to handle it. Generally unexpected. 5143 * fw_indicator used as bitmap, and defined as below: 5144 * FW_IND_EVENT_PENDING 0x1 5145 * FW_IND_INITIALIZED 0x2 5146 * FW_IND_NEEDRECOVER 0x4 5147 */ 5148 AR_DEBUG_PRINTF(ATH_DEBUG_ERR, 5149 ("%s: Early firmware event indicated 0x%x\n", 5150 __func__, fw_indicator)); 5151 } 5152 } else { 5153 if (Q_TARGET_ACCESS_END(scn) < 0) 5154 return ATH_ISR_SCHED; 5155 } 5156 5157 return ATH_ISR_SCHED; 5158 } 5159 #else 5160 irqreturn_t hif_fw_interrupt_handler(int irq, void *arg) 5161 { 5162 return ATH_ISR_SCHED; 5163 } 5164 #endif /* #ifdef QCA_WIFI_3_0 */ 5165 5166 5167 /** 5168 * hif_wlan_disable(): call the platform driver to disable wlan 5169 * @scn: HIF Context 5170 * 5171 * This function passes the con_mode to platform driver to disable 5172 * wlan. 5173 * 5174 * Return: void 5175 */ 5176 void hif_wlan_disable(struct hif_softc *scn) 5177 { 5178 enum pld_driver_mode mode; 5179 uint32_t con_mode = hif_get_conparam(scn); 5180 5181 if (scn->target_status == TARGET_STATUS_RESET) 5182 return; 5183 5184 if (QDF_GLOBAL_FTM_MODE == con_mode) 5185 mode = PLD_FTM; 5186 else if (QDF_IS_EPPING_ENABLED(con_mode)) 5187 mode = PLD_EPPING; 5188 else 5189 mode = PLD_MISSION; 5190 5191 pld_wlan_disable(scn->qdf_dev->dev, mode); 5192 } 5193 5194 int hif_get_wake_ce_id(struct hif_softc *scn, uint8_t *ce_id) 5195 { 5196 int status; 5197 uint8_t ul_pipe, dl_pipe; 5198 int ul_is_polled, dl_is_polled; 5199 5200 /* DL pipe for HTC_CTRL_RSVD_SVC should map to the wake CE */ 5201 status = hif_map_service_to_pipe(GET_HIF_OPAQUE_HDL(scn), 5202 HTC_CTRL_RSVD_SVC, 5203 &ul_pipe, &dl_pipe, 5204 &ul_is_polled, &dl_is_polled); 5205 if (status) { 5206 hif_err("Failed to map pipe: %d", status); 5207 return status; 5208 } 5209 5210 *ce_id = dl_pipe; 5211 5212 return 0; 5213 } 5214 5215 int hif_get_fw_diag_ce_id(struct hif_softc *scn, uint8_t *ce_id) 5216 { 5217 int status; 5218 uint8_t ul_pipe, dl_pipe; 5219 int ul_is_polled, dl_is_polled; 5220 5221 /* DL pipe for WMI_CONTROL_DIAG_SVC should map to the FW DIAG CE_ID */ 5222 status = hif_map_service_to_pipe(GET_HIF_OPAQUE_HDL(scn), 5223 WMI_CONTROL_DIAG_SVC, 5224 &ul_pipe, &dl_pipe, 5225 &ul_is_polled, &dl_is_polled); 5226 if (status) { 5227 hif_err("Failed to map pipe: %d", status); 5228 return status; 5229 } 5230 5231 *ce_id = dl_pipe; 5232 5233 return 0; 5234 } 5235 5236 #ifdef HIF_CE_LOG_INFO 5237 /** 5238 * ce_get_index_info(): Get CE index info 5239 * @scn: HIF Context 5240 * @ce_state: CE opaque handle 5241 * @info: CE info 5242 * 5243 * Return: 0 for success and non zero for failure 5244 */ 5245 static 5246 int ce_get_index_info(struct hif_softc *scn, void *ce_state, 5247 struct ce_index *info) 5248 { 5249 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 5250 5251 return hif_state->ce_services->ce_get_index_info(scn, ce_state, info); 5252 } 5253 5254 void hif_log_ce_info(struct hif_softc *scn, uint8_t *data, 5255 unsigned int *offset) 5256 { 5257 struct hang_event_info info = {0}; 5258 static uint32_t tracked_ce = BIT(CE_ID_1) | BIT(CE_ID_2) | 5259 BIT(CE_ID_3) | BIT(CE_ID_4) | BIT(CE_ID_9) | BIT(CE_ID_10); 5260 uint8_t curr_index = 0; 5261 uint8_t i; 5262 uint16_t size; 5263 5264 info.active_tasklet_count = qdf_atomic_read(&scn->active_tasklet_cnt); 5265 info.active_grp_tasklet_cnt = 5266 qdf_atomic_read(&scn->active_grp_tasklet_cnt); 5267 5268 for (i = 0; i < scn->ce_count; i++) { 5269 if (!(tracked_ce & BIT(i)) || !scn->ce_id_to_state[i]) 5270 continue; 5271 5272 if (ce_get_index_info(scn, scn->ce_id_to_state[i], 5273 &info.ce_info[curr_index])) 5274 continue; 5275 5276 curr_index++; 5277 } 5278 5279 info.ce_count = curr_index; 5280 size = sizeof(info) - 5281 (CE_COUNT_MAX - info.ce_count) * sizeof(struct ce_index); 5282 5283 if (*offset + size > QDF_WLAN_HANG_FW_OFFSET) 5284 return; 5285 5286 QDF_HANG_EVT_SET_HDR(&info.tlv_header, HANG_EVT_TAG_CE_INFO, 5287 size - QDF_HANG_EVENT_TLV_HDR_SIZE); 5288 5289 qdf_mem_copy(data + *offset, &info, size); 5290 *offset = *offset + size; 5291 } 5292 #endif 5293