1 /* 2 * Copyright (c) 2013-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include "targcfg.h" 21 #include "qdf_lock.h" 22 #include "qdf_status.h" 23 #include "qdf_status.h" 24 #include <qdf_atomic.h> /* qdf_atomic_read */ 25 #include <targaddrs.h> 26 #include "hif_io32.h" 27 #include <hif.h> 28 #include <target_type.h> 29 #include "regtable.h" 30 #define ATH_MODULE_NAME hif 31 #include <a_debug.h> 32 #include "hif_main.h" 33 #include "ce_api.h" 34 #include "qdf_trace.h" 35 #include "pld_common.h" 36 #include "hif_debug.h" 37 #include "ce_internal.h" 38 #include "ce_reg.h" 39 #include "ce_assignment.h" 40 #include "ce_tasklet.h" 41 #include "qdf_module.h" 42 #include "qdf_ssr_driver_dump.h" 43 #include <wbuff.h> 44 45 #define CE_POLL_TIMEOUT 10 /* ms */ 46 47 #define AGC_DUMP 1 48 #define CHANINFO_DUMP 2 49 #define BB_WATCHDOG_DUMP 3 50 #ifdef CONFIG_ATH_PCIE_ACCESS_DEBUG 51 #define PCIE_ACCESS_DUMP 4 52 #endif 53 #include "mp_dev.h" 54 #ifdef HIF_CE_LOG_INFO 55 #include "qdf_hang_event_notifier.h" 56 #endif 57 58 #if (defined(QCA_WIFI_QCA8074) || defined(QCA_WIFI_QCA6290) || \ 59 defined(QCA_WIFI_QCA6018) || defined(QCA_WIFI_QCA5018) || \ 60 defined(QCA_WIFI_KIWI) || defined(QCA_WIFI_QCA5332) || \ 61 defined(QCA_WIFI_QCA9574)) && !defined(QCA_WIFI_SUPPORT_SRNG) && \ 62 !defined(QCA_WIFI_WCN6450) 63 #define QCA_WIFI_SUPPORT_SRNG 64 #endif 65 66 #ifdef QCA_WIFI_SUPPORT_SRNG 67 #include <hal_api.h> 68 #endif 69 #include "qdf_ssr_driver_dump.h" 70 71 /* Forward references */ 72 QDF_STATUS hif_post_recv_buffers_for_pipe(struct HIF_CE_pipe_info *pipe_info); 73 74 /* 75 * Fix EV118783, poll to check whether a BMI response comes 76 * other than waiting for the interruption which may be lost. 77 */ 78 /* #define BMI_RSP_POLLING */ 79 #define BMI_RSP_TO_MILLISEC 1000 80 81 #ifdef CONFIG_BYPASS_QMI 82 #define BYPASS_QMI 1 83 #else 84 #define BYPASS_QMI 0 85 #endif 86 87 static void hif_config_rri_on_ddr(struct hif_softc *scn); 88 89 /** 90 * hif_target_access_log_dump() - dump access log 91 * 92 * dump access log 93 * 94 * Return: n/a 95 */ 96 #ifdef CONFIG_ATH_PCIE_ACCESS_DEBUG 97 static void hif_target_access_log_dump(void) 98 { 99 hif_target_dump_access_log(); 100 } 101 #endif 102 103 /* 104 * This structure contains the interrupt index for each Copy engine 105 * for various number of MSIs available in the system. 106 */ 107 static struct ce_int_assignment ce_int_context[NUM_CE_CONTEXT] = { 108 /* Default configuration */ 109 {{ CE_INTERRUPT_IDX(0), 110 CE_INTERRUPT_IDX(1), 111 CE_INTERRUPT_IDX(2), 112 CE_INTERRUPT_IDX(3), 113 CE_INTERRUPT_IDX(4), 114 CE_INTERRUPT_IDX(5), 115 CE_INTERRUPT_IDX(6), 116 CE_INTERRUPT_IDX(7), 117 CE_INTERRUPT_IDX(8), 118 CE_INTERRUPT_IDX(9), 119 CE_INTERRUPT_IDX(10), 120 CE_INTERRUPT_IDX(11), 121 #ifdef QCA_WIFI_QCN9224 122 CE_INTERRUPT_IDX(12), 123 CE_INTERRUPT_IDX(13), 124 CE_INTERRUPT_IDX(14), 125 CE_INTERRUPT_IDX(15), 126 #endif 127 } }, 128 /* Interrupt assignment for 1 MSI combination */ 129 {{ CE_INTERRUPT_IDX(0), 130 CE_INTERRUPT_IDX(0), 131 CE_INTERRUPT_IDX(0), 132 CE_INTERRUPT_IDX(0), 133 CE_INTERRUPT_IDX(0), 134 CE_INTERRUPT_IDX(0), 135 CE_INTERRUPT_IDX(0), 136 CE_INTERRUPT_IDX(0), 137 CE_INTERRUPT_IDX(0), 138 CE_INTERRUPT_IDX(0), 139 CE_INTERRUPT_IDX(0), 140 CE_INTERRUPT_IDX(0), 141 #ifdef QCA_WIFI_QCN9224 142 CE_INTERRUPT_IDX(0), 143 CE_INTERRUPT_IDX(0), 144 CE_INTERRUPT_IDX(0), 145 CE_INTERRUPT_IDX(0), 146 #endif 147 } }, 148 /* Interrupt assignment for 2 MSI combination */ 149 {{ CE_INTERRUPT_IDX(0), 150 CE_INTERRUPT_IDX(1), 151 CE_INTERRUPT_IDX(0), 152 CE_INTERRUPT_IDX(1), 153 CE_INTERRUPT_IDX(0), 154 CE_INTERRUPT_IDX(1), 155 CE_INTERRUPT_IDX(0), 156 CE_INTERRUPT_IDX(0), 157 CE_INTERRUPT_IDX(0), 158 CE_INTERRUPT_IDX(0), 159 CE_INTERRUPT_IDX(0), 160 CE_INTERRUPT_IDX(0), 161 #ifdef QCA_WIFI_QCN9224 162 CE_INTERRUPT_IDX(0), 163 CE_INTERRUPT_IDX(0), 164 CE_INTERRUPT_IDX(0), 165 CE_INTERRUPT_IDX(0), 166 #endif 167 } }, 168 /* Interrupt assignment for 3 MSI combination */ 169 {{ CE_INTERRUPT_IDX(0), 170 CE_INTERRUPT_IDX(1), 171 CE_INTERRUPT_IDX(2), 172 CE_INTERRUPT_IDX(1), 173 CE_INTERRUPT_IDX(0), 174 CE_INTERRUPT_IDX(1), 175 CE_INTERRUPT_IDX(0), 176 CE_INTERRUPT_IDX(0), 177 CE_INTERRUPT_IDX(0), 178 CE_INTERRUPT_IDX(0), 179 CE_INTERRUPT_IDX(0), 180 CE_INTERRUPT_IDX(0), 181 #ifdef QCA_WIFI_QCN9224 182 CE_INTERRUPT_IDX(0), 183 CE_INTERRUPT_IDX(0), 184 CE_INTERRUPT_IDX(0), 185 CE_INTERRUPT_IDX(0), 186 #endif 187 } }, 188 /* Interrupt assignment for 4 MSI combination */ 189 {{ CE_INTERRUPT_IDX(0), 190 CE_INTERRUPT_IDX(1), 191 CE_INTERRUPT_IDX(2), 192 CE_INTERRUPT_IDX(3), 193 CE_INTERRUPT_IDX(0), 194 CE_INTERRUPT_IDX(1), 195 CE_INTERRUPT_IDX(0), 196 CE_INTERRUPT_IDX(0), 197 CE_INTERRUPT_IDX(0), 198 CE_INTERRUPT_IDX(0), 199 CE_INTERRUPT_IDX(0), 200 CE_INTERRUPT_IDX(0), 201 #ifdef QCA_WIFI_QCN9224 202 CE_INTERRUPT_IDX(0), 203 CE_INTERRUPT_IDX(0), 204 CE_INTERRUPT_IDX(0), 205 CE_INTERRUPT_IDX(0), 206 #endif 207 } }, 208 /* Interrupt assignment for 5 MSI combination */ 209 {{ CE_INTERRUPT_IDX(0), 210 CE_INTERRUPT_IDX(1), 211 CE_INTERRUPT_IDX(2), 212 CE_INTERRUPT_IDX(3), 213 CE_INTERRUPT_IDX(0), 214 CE_INTERRUPT_IDX(4), 215 CE_INTERRUPT_IDX(0), 216 CE_INTERRUPT_IDX(0), 217 CE_INTERRUPT_IDX(0), 218 CE_INTERRUPT_IDX(0), 219 CE_INTERRUPT_IDX(0), 220 CE_INTERRUPT_IDX(0), 221 #ifdef QCA_WIFI_QCN9224 222 CE_INTERRUPT_IDX(0), 223 CE_INTERRUPT_IDX(0), 224 CE_INTERRUPT_IDX(0), 225 CE_INTERRUPT_IDX(0), 226 #endif 227 } }, 228 /* Interrupt assignment for 6 MSI combination */ 229 {{ CE_INTERRUPT_IDX(0), 230 CE_INTERRUPT_IDX(1), 231 CE_INTERRUPT_IDX(2), 232 CE_INTERRUPT_IDX(3), 233 CE_INTERRUPT_IDX(4), 234 CE_INTERRUPT_IDX(5), 235 CE_INTERRUPT_IDX(0), 236 CE_INTERRUPT_IDX(0), 237 CE_INTERRUPT_IDX(0), 238 CE_INTERRUPT_IDX(0), 239 CE_INTERRUPT_IDX(0), 240 CE_INTERRUPT_IDX(0), 241 #ifdef QCA_WIFI_QCN9224 242 CE_INTERRUPT_IDX(0), 243 CE_INTERRUPT_IDX(0), 244 CE_INTERRUPT_IDX(0), 245 CE_INTERRUPT_IDX(0), 246 #endif 247 } }, 248 /* Interrupt assignment for 7 MSI combination */ 249 {{ CE_INTERRUPT_IDX(0), 250 CE_INTERRUPT_IDX(1), 251 CE_INTERRUPT_IDX(2), 252 CE_INTERRUPT_IDX(3), 253 CE_INTERRUPT_IDX(4), 254 CE_INTERRUPT_IDX(5), 255 CE_INTERRUPT_IDX(6), 256 CE_INTERRUPT_IDX(0), 257 CE_INTERRUPT_IDX(0), 258 CE_INTERRUPT_IDX(0), 259 CE_INTERRUPT_IDX(0), 260 CE_INTERRUPT_IDX(0), 261 #ifdef QCA_WIFI_QCN9224 262 CE_INTERRUPT_IDX(0), 263 CE_INTERRUPT_IDX(0), 264 CE_INTERRUPT_IDX(0), 265 CE_INTERRUPT_IDX(0), 266 #endif 267 } }, 268 /* Interrupt assignment for 8 MSI combination */ 269 {{ CE_INTERRUPT_IDX(0), 270 CE_INTERRUPT_IDX(1), 271 CE_INTERRUPT_IDX(2), 272 CE_INTERRUPT_IDX(3), 273 CE_INTERRUPT_IDX(4), 274 CE_INTERRUPT_IDX(5), 275 CE_INTERRUPT_IDX(6), 276 CE_INTERRUPT_IDX(7), 277 CE_INTERRUPT_IDX(0), 278 CE_INTERRUPT_IDX(0), 279 CE_INTERRUPT_IDX(0), 280 CE_INTERRUPT_IDX(0), 281 #ifdef QCA_WIFI_QCN9224 282 CE_INTERRUPT_IDX(0), 283 CE_INTERRUPT_IDX(0), 284 CE_INTERRUPT_IDX(0), 285 CE_INTERRUPT_IDX(0), 286 #endif 287 } }, 288 /* Interrupt assignment for 9 MSI combination */ 289 {{ CE_INTERRUPT_IDX(0), 290 CE_INTERRUPT_IDX(1), 291 CE_INTERRUPT_IDX(2), 292 CE_INTERRUPT_IDX(3), 293 CE_INTERRUPT_IDX(4), 294 CE_INTERRUPT_IDX(5), 295 CE_INTERRUPT_IDX(6), 296 CE_INTERRUPT_IDX(7), 297 CE_INTERRUPT_IDX(8), 298 CE_INTERRUPT_IDX(0), 299 CE_INTERRUPT_IDX(0), 300 CE_INTERRUPT_IDX(0), 301 #ifdef QCA_WIFI_QCN9224 302 CE_INTERRUPT_IDX(0), 303 CE_INTERRUPT_IDX(0), 304 CE_INTERRUPT_IDX(0), 305 CE_INTERRUPT_IDX(0), 306 #endif 307 } }, 308 /* Interrupt assignment for 10 MSI combination */ 309 {{ CE_INTERRUPT_IDX(0), 310 CE_INTERRUPT_IDX(1), 311 CE_INTERRUPT_IDX(2), 312 CE_INTERRUPT_IDX(3), 313 CE_INTERRUPT_IDX(4), 314 CE_INTERRUPT_IDX(5), 315 CE_INTERRUPT_IDX(6), 316 CE_INTERRUPT_IDX(7), 317 CE_INTERRUPT_IDX(8), 318 CE_INTERRUPT_IDX(9), 319 CE_INTERRUPT_IDX(0), 320 CE_INTERRUPT_IDX(0), 321 #ifdef QCA_WIFI_QCN9224 322 CE_INTERRUPT_IDX(0), 323 CE_INTERRUPT_IDX(0), 324 CE_INTERRUPT_IDX(0), 325 CE_INTERRUPT_IDX(0), 326 #endif 327 } }, 328 /* Interrupt assignment for 11 MSI combination */ 329 {{ CE_INTERRUPT_IDX(0), 330 CE_INTERRUPT_IDX(1), 331 CE_INTERRUPT_IDX(2), 332 CE_INTERRUPT_IDX(3), 333 CE_INTERRUPT_IDX(4), 334 CE_INTERRUPT_IDX(5), 335 CE_INTERRUPT_IDX(6), 336 CE_INTERRUPT_IDX(7), 337 CE_INTERRUPT_IDX(8), 338 CE_INTERRUPT_IDX(9), 339 CE_INTERRUPT_IDX(10), 340 CE_INTERRUPT_IDX(0), 341 #ifdef QCA_WIFI_QCN9224 342 CE_INTERRUPT_IDX(0), 343 CE_INTERRUPT_IDX(0), 344 CE_INTERRUPT_IDX(0), 345 CE_INTERRUPT_IDX(0), 346 #endif 347 } }, 348 /* Interrupt assignment for 12 MSI combination */ 349 {{ CE_INTERRUPT_IDX(0), 350 CE_INTERRUPT_IDX(1), 351 CE_INTERRUPT_IDX(2), 352 CE_INTERRUPT_IDX(3), 353 CE_INTERRUPT_IDX(4), 354 CE_INTERRUPT_IDX(5), 355 CE_INTERRUPT_IDX(6), 356 CE_INTERRUPT_IDX(7), 357 CE_INTERRUPT_IDX(8), 358 CE_INTERRUPT_IDX(9), 359 CE_INTERRUPT_IDX(10), 360 CE_INTERRUPT_IDX(11), 361 #ifdef QCA_WIFI_QCN9224 362 CE_INTERRUPT_IDX(0), 363 CE_INTERRUPT_IDX(0), 364 CE_INTERRUPT_IDX(0), 365 CE_INTERRUPT_IDX(0), 366 #endif 367 } }, 368 #ifdef QCA_WIFI_QCN9224 369 /* Interrupt assignment for 13 MSI combination */ 370 {{ CE_INTERRUPT_IDX(0), 371 CE_INTERRUPT_IDX(1), 372 CE_INTERRUPT_IDX(2), 373 CE_INTERRUPT_IDX(3), 374 CE_INTERRUPT_IDX(4), 375 CE_INTERRUPT_IDX(5), 376 CE_INTERRUPT_IDX(6), 377 CE_INTERRUPT_IDX(7), 378 CE_INTERRUPT_IDX(8), 379 CE_INTERRUPT_IDX(9), 380 CE_INTERRUPT_IDX(10), 381 CE_INTERRUPT_IDX(11), 382 CE_INTERRUPT_IDX(12), 383 CE_INTERRUPT_IDX(0), 384 CE_INTERRUPT_IDX(0), 385 CE_INTERRUPT_IDX(0), 386 } }, 387 /* Interrupt assignment for 14 MSI combination */ 388 {{ CE_INTERRUPT_IDX(0), 389 CE_INTERRUPT_IDX(1), 390 CE_INTERRUPT_IDX(2), 391 CE_INTERRUPT_IDX(3), 392 CE_INTERRUPT_IDX(4), 393 CE_INTERRUPT_IDX(5), 394 CE_INTERRUPT_IDX(6), 395 CE_INTERRUPT_IDX(7), 396 CE_INTERRUPT_IDX(8), 397 CE_INTERRUPT_IDX(9), 398 CE_INTERRUPT_IDX(10), 399 CE_INTERRUPT_IDX(11), 400 CE_INTERRUPT_IDX(12), 401 CE_INTERRUPT_IDX(13), 402 CE_INTERRUPT_IDX(0), 403 CE_INTERRUPT_IDX(0), 404 } }, 405 /* Interrupt assignment for 15 MSI combination */ 406 {{ CE_INTERRUPT_IDX(0), 407 CE_INTERRUPT_IDX(1), 408 CE_INTERRUPT_IDX(2), 409 CE_INTERRUPT_IDX(3), 410 CE_INTERRUPT_IDX(4), 411 CE_INTERRUPT_IDX(5), 412 CE_INTERRUPT_IDX(6), 413 CE_INTERRUPT_IDX(7), 414 CE_INTERRUPT_IDX(8), 415 CE_INTERRUPT_IDX(9), 416 CE_INTERRUPT_IDX(10), 417 CE_INTERRUPT_IDX(11), 418 CE_INTERRUPT_IDX(12), 419 CE_INTERRUPT_IDX(13), 420 CE_INTERRUPT_IDX(14), 421 CE_INTERRUPT_IDX(0), 422 } }, 423 /* Interrupt assignment for 16 MSI combination */ 424 {{ CE_INTERRUPT_IDX(0), 425 CE_INTERRUPT_IDX(1), 426 CE_INTERRUPT_IDX(2), 427 CE_INTERRUPT_IDX(3), 428 CE_INTERRUPT_IDX(4), 429 CE_INTERRUPT_IDX(5), 430 CE_INTERRUPT_IDX(6), 431 CE_INTERRUPT_IDX(7), 432 CE_INTERRUPT_IDX(8), 433 CE_INTERRUPT_IDX(9), 434 CE_INTERRUPT_IDX(10), 435 CE_INTERRUPT_IDX(11), 436 CE_INTERRUPT_IDX(12), 437 CE_INTERRUPT_IDX(13), 438 CE_INTERRUPT_IDX(14), 439 CE_INTERRUPT_IDX(15), 440 } }, 441 #endif 442 }; 443 444 445 void hif_trigger_dump(struct hif_opaque_softc *hif_ctx, 446 uint8_t cmd_id, bool start) 447 { 448 struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); 449 450 switch (cmd_id) { 451 case AGC_DUMP: 452 if (start) 453 priv_start_agc(scn); 454 else 455 priv_dump_agc(scn); 456 break; 457 case CHANINFO_DUMP: 458 if (start) 459 priv_start_cap_chaninfo(scn); 460 else 461 priv_dump_chaninfo(scn); 462 break; 463 case BB_WATCHDOG_DUMP: 464 priv_dump_bbwatchdog(scn); 465 break; 466 #ifdef CONFIG_ATH_PCIE_ACCESS_DEBUG 467 case PCIE_ACCESS_DUMP: 468 hif_target_access_log_dump(); 469 break; 470 #endif 471 default: 472 hif_err("Invalid htc dump command: %d", cmd_id); 473 break; 474 } 475 } 476 477 static void ce_poll_timeout(void *arg) 478 { 479 struct CE_state *CE_state = (struct CE_state *)arg; 480 481 if (CE_state->timer_inited) { 482 ce_per_engine_service(CE_state->scn, CE_state->id); 483 qdf_timer_mod(&CE_state->poll_timer, CE_POLL_TIMEOUT); 484 } 485 } 486 487 static unsigned int roundup_pwr2(unsigned int n) 488 { 489 int i; 490 unsigned int test_pwr2; 491 492 if (!(n & (n - 1))) 493 return n; /* already a power of 2 */ 494 495 test_pwr2 = 4; 496 for (i = 0; i < 29; i++) { 497 if (test_pwr2 > n) 498 return test_pwr2; 499 test_pwr2 = test_pwr2 << 1; 500 } 501 502 QDF_ASSERT(0); /* n too large */ 503 return 0; 504 } 505 506 #define ADRASTEA_SRC_WR_INDEX_OFFSET 0x3C 507 #define ADRASTEA_DST_WR_INDEX_OFFSET 0x40 508 509 static struct shadow_reg_cfg target_shadow_reg_cfg_map[] = { 510 { 0, ADRASTEA_SRC_WR_INDEX_OFFSET}, 511 { 3, ADRASTEA_SRC_WR_INDEX_OFFSET}, 512 { 4, ADRASTEA_SRC_WR_INDEX_OFFSET}, 513 { 5, ADRASTEA_SRC_WR_INDEX_OFFSET}, 514 { 7, ADRASTEA_SRC_WR_INDEX_OFFSET}, 515 { 1, ADRASTEA_DST_WR_INDEX_OFFSET}, 516 { 2, ADRASTEA_DST_WR_INDEX_OFFSET}, 517 { 7, ADRASTEA_DST_WR_INDEX_OFFSET}, 518 { 8, ADRASTEA_DST_WR_INDEX_OFFSET}, 519 #ifdef QCA_WIFI_3_0_ADRASTEA 520 { 9, ADRASTEA_DST_WR_INDEX_OFFSET}, 521 { 10, ADRASTEA_DST_WR_INDEX_OFFSET}, 522 { 11, ADRASTEA_DST_WR_INDEX_OFFSET}, 523 #endif 524 }; 525 526 #ifdef QCN7605_SUPPORT 527 static struct shadow_reg_cfg target_shadow_reg_cfg_map_qcn7605[] = { 528 { 0, ADRASTEA_SRC_WR_INDEX_OFFSET}, 529 { 4, ADRASTEA_SRC_WR_INDEX_OFFSET}, 530 { 5, ADRASTEA_SRC_WR_INDEX_OFFSET}, 531 { 3, ADRASTEA_DST_WR_INDEX_OFFSET}, 532 { 1, ADRASTEA_DST_WR_INDEX_OFFSET}, 533 { 2, ADRASTEA_DST_WR_INDEX_OFFSET}, 534 { 7, ADRASTEA_DST_WR_INDEX_OFFSET}, 535 { 8, ADRASTEA_DST_WR_INDEX_OFFSET}, 536 }; 537 #endif 538 539 #ifdef WLAN_FEATURE_EPPING 540 static struct shadow_reg_cfg target_shadow_reg_cfg_epping[] = { 541 { 0, ADRASTEA_SRC_WR_INDEX_OFFSET}, 542 { 3, ADRASTEA_SRC_WR_INDEX_OFFSET}, 543 { 4, ADRASTEA_SRC_WR_INDEX_OFFSET}, 544 { 7, ADRASTEA_SRC_WR_INDEX_OFFSET}, 545 { 1, ADRASTEA_DST_WR_INDEX_OFFSET}, 546 { 2, ADRASTEA_DST_WR_INDEX_OFFSET}, 547 { 5, ADRASTEA_DST_WR_INDEX_OFFSET}, 548 { 7, ADRASTEA_DST_WR_INDEX_OFFSET}, 549 { 8, ADRASTEA_DST_WR_INDEX_OFFSET}, 550 }; 551 #endif 552 553 /* CE_PCI TABLE */ 554 /* 555 * NOTE: the table below is out of date, though still a useful reference. 556 * Refer to target_service_to_ce_map and hif_map_service_to_pipe for the actual 557 * mapping of HTC services to HIF pipes. 558 */ 559 /* 560 * This authoritative table defines Copy Engine configuration and the mapping 561 * of services/endpoints to CEs. A subset of this information is passed to 562 * the Target during startup as a prerequisite to entering BMI phase. 563 * See: 564 * target_service_to_ce_map - Target-side mapping 565 * hif_map_service_to_pipe - Host-side mapping 566 * target_ce_config - Target-side configuration 567 * host_ce_config - Host-side configuration 568 ============================================================================ 569 Purpose | Service / Endpoint | CE | Dire | Xfer | Xfer 570 | | | ctio | Size | Frequency 571 | | | n | | 572 ============================================================================ 573 tx | HTT_DATA (downlink) | CE 0 | h->t | medium - | very frequent 574 descriptor | | | | O(100B) | and regular 575 download | | | | | 576 ---------------------------------------------------------------------------- 577 rx | HTT_DATA (uplink) | CE 1 | t->h | small - | frequent and 578 indication | | | | O(10B) | regular 579 upload | | | | | 580 ---------------------------------------------------------------------------- 581 MSDU | DATA_BK (uplink) | CE 2 | t->h | large - | rare 582 upload | | | | O(1000B) | (frequent 583 e.g. noise | | | | | during IP1.0 584 packets | | | | | testing) 585 ---------------------------------------------------------------------------- 586 MSDU | DATA_BK (downlink) | CE 3 | h->t | large - | very rare 587 download | | | | O(1000B) | (frequent 588 e.g. | | | | | during IP1.0 589 misdirecte | | | | | testing) 590 d EAPOL | | | | | 591 packets | | | | | 592 ---------------------------------------------------------------------------- 593 n/a | DATA_BE, DATA_VI | CE 2 | t->h | | never(?) 594 | DATA_VO (uplink) | | | | 595 ---------------------------------------------------------------------------- 596 n/a | DATA_BE, DATA_VI | CE 3 | h->t | | never(?) 597 | DATA_VO (downlink) | | | | 598 ---------------------------------------------------------------------------- 599 WMI events | WMI_CONTROL (uplink) | CE 4 | t->h | medium - | infrequent 600 | | | | O(100B) | 601 ---------------------------------------------------------------------------- 602 WMI | WMI_CONTROL | CE 5 | h->t | medium - | infrequent 603 messages | (downlink) | | | O(100B) | 604 | | | | | 605 ---------------------------------------------------------------------------- 606 n/a | HTC_CTRL_RSVD, | CE 1 | t->h | | never(?) 607 | HTC_RAW_STREAMS | | | | 608 | (uplink) | | | | 609 ---------------------------------------------------------------------------- 610 n/a | HTC_CTRL_RSVD, | CE 0 | h->t | | never(?) 611 | HTC_RAW_STREAMS | | | | 612 | (downlink) | | | | 613 ---------------------------------------------------------------------------- 614 diag | none (raw CE) | CE 7 | t<>h | 4 | Diag Window 615 | | | | | infrequent 616 ============================================================================ 617 */ 618 619 /* 620 * Map from service/endpoint to Copy Engine. 621 * This table is derived from the CE_PCI TABLE, above. 622 * It is passed to the Target at startup for use by firmware. 623 */ 624 static struct service_to_pipe target_service_to_ce_map_wlan[] = { 625 { 626 WMI_DATA_VO_SVC, 627 PIPEDIR_OUT, /* out = UL = host -> target */ 628 3, 629 }, 630 { 631 WMI_DATA_VO_SVC, 632 PIPEDIR_IN, /* in = DL = target -> host */ 633 2, 634 }, 635 { 636 WMI_DATA_BK_SVC, 637 PIPEDIR_OUT, /* out = UL = host -> target */ 638 3, 639 }, 640 { 641 WMI_DATA_BK_SVC, 642 PIPEDIR_IN, /* in = DL = target -> host */ 643 2, 644 }, 645 { 646 WMI_DATA_BE_SVC, 647 PIPEDIR_OUT, /* out = UL = host -> target */ 648 3, 649 }, 650 { 651 WMI_DATA_BE_SVC, 652 PIPEDIR_IN, /* in = DL = target -> host */ 653 2, 654 }, 655 { 656 WMI_DATA_VI_SVC, 657 PIPEDIR_OUT, /* out = UL = host -> target */ 658 3, 659 }, 660 { 661 WMI_DATA_VI_SVC, 662 PIPEDIR_IN, /* in = DL = target -> host */ 663 2, 664 }, 665 { 666 WMI_CONTROL_SVC, 667 PIPEDIR_OUT, /* out = UL = host -> target */ 668 3, 669 }, 670 { 671 WMI_CONTROL_SVC, 672 PIPEDIR_IN, /* in = DL = target -> host */ 673 2, 674 }, 675 { 676 HTC_CTRL_RSVD_SVC, 677 PIPEDIR_OUT, /* out = UL = host -> target */ 678 0, /* could be moved to 3 (share with WMI) */ 679 }, 680 { 681 HTC_CTRL_RSVD_SVC, 682 PIPEDIR_IN, /* in = DL = target -> host */ 683 2, 684 }, 685 { 686 HTC_RAW_STREAMS_SVC, /* not currently used */ 687 PIPEDIR_OUT, /* out = UL = host -> target */ 688 0, 689 }, 690 { 691 HTC_RAW_STREAMS_SVC, /* not currently used */ 692 PIPEDIR_IN, /* in = DL = target -> host */ 693 2, 694 }, 695 { 696 HTT_DATA_MSG_SVC, 697 PIPEDIR_OUT, /* out = UL = host -> target */ 698 4, 699 }, 700 { 701 HTT_DATA_MSG_SVC, 702 PIPEDIR_IN, /* in = DL = target -> host */ 703 1, 704 }, 705 { 706 WDI_IPA_TX_SVC, 707 PIPEDIR_OUT, /* in = DL = target -> host */ 708 5, 709 }, 710 #if defined(QCA_WIFI_3_0_ADRASTEA) 711 { 712 HTT_DATA2_MSG_SVC, 713 PIPEDIR_IN, /* in = DL = target -> host */ 714 9, 715 }, 716 { 717 HTT_DATA3_MSG_SVC, 718 PIPEDIR_IN, /* in = DL = target -> host */ 719 10, 720 }, 721 { 722 PACKET_LOG_SVC, 723 PIPEDIR_IN, /* in = DL = target -> host */ 724 11, 725 }, 726 #endif 727 /* (Additions here) */ 728 729 { /* Must be last */ 730 0, 731 0, 732 0, 733 }, 734 }; 735 736 /* PIPEDIR_OUT = HOST to Target */ 737 /* PIPEDIR_IN = TARGET to HOST */ 738 #if (defined(QCA_WIFI_QCA8074)) 739 static struct service_to_pipe target_service_to_ce_map_qca8074[] = { 740 { WMI_DATA_VO_SVC, PIPEDIR_OUT, 3, }, 741 { WMI_DATA_VO_SVC, PIPEDIR_IN, 2, }, 742 { WMI_DATA_BK_SVC, PIPEDIR_OUT, 3, }, 743 { WMI_DATA_BK_SVC, PIPEDIR_IN, 2, }, 744 { WMI_DATA_BE_SVC, PIPEDIR_OUT, 3, }, 745 { WMI_DATA_BE_SVC, PIPEDIR_IN, 2, }, 746 { WMI_DATA_VI_SVC, PIPEDIR_OUT, 3, }, 747 { WMI_DATA_VI_SVC, PIPEDIR_IN, 2, }, 748 { WMI_CONTROL_SVC, PIPEDIR_OUT, 3, }, 749 { WMI_CONTROL_SVC, PIPEDIR_IN, 2, }, 750 { WMI_CONTROL_SVC_WMAC1, PIPEDIR_OUT, 7}, 751 { WMI_CONTROL_SVC_WMAC1, PIPEDIR_IN, 2}, 752 { HTC_CTRL_RSVD_SVC, PIPEDIR_OUT, 0, }, 753 { HTC_CTRL_RSVD_SVC, PIPEDIR_IN, 1, }, 754 { HTC_RAW_STREAMS_SVC, PIPEDIR_OUT, 0}, 755 { HTC_RAW_STREAMS_SVC, PIPEDIR_IN, 1 }, 756 { HTT_DATA_MSG_SVC, PIPEDIR_OUT, 4, }, 757 { HTT_DATA_MSG_SVC, PIPEDIR_IN, 1, }, 758 { PACKET_LOG_SVC, PIPEDIR_IN, 5, }, 759 /* (Additions here) */ 760 { 0, 0, 0, }, 761 }; 762 #else 763 static struct service_to_pipe target_service_to_ce_map_qca8074[] = { 764 }; 765 #endif 766 767 #if (defined(QCA_WIFI_QCA9574)) 768 static struct service_to_pipe target_service_to_ce_map_qca9574[] = { 769 { WMI_DATA_VO_SVC, PIPEDIR_OUT, 3, }, 770 { WMI_DATA_VO_SVC, PIPEDIR_IN, 2, }, 771 { WMI_DATA_BK_SVC, PIPEDIR_OUT, 3, }, 772 { WMI_DATA_BK_SVC, PIPEDIR_IN, 2, }, 773 { WMI_DATA_BE_SVC, PIPEDIR_OUT, 3, }, 774 { WMI_DATA_BE_SVC, PIPEDIR_IN, 2, }, 775 { WMI_DATA_VI_SVC, PIPEDIR_OUT, 3, }, 776 { WMI_DATA_VI_SVC, PIPEDIR_IN, 2, }, 777 { WMI_CONTROL_SVC, PIPEDIR_OUT, 3, }, 778 { WMI_CONTROL_SVC, PIPEDIR_IN, 2, }, 779 { WMI_CONTROL_SVC_WMAC1, PIPEDIR_OUT, 7}, 780 { WMI_CONTROL_SVC_WMAC1, PIPEDIR_IN, 2}, 781 { HTC_CTRL_RSVD_SVC, PIPEDIR_OUT, 0, }, 782 { HTC_CTRL_RSVD_SVC, PIPEDIR_IN, 1, }, 783 { HTC_RAW_STREAMS_SVC, PIPEDIR_OUT, 0}, 784 { HTC_RAW_STREAMS_SVC, PIPEDIR_IN, 1 }, 785 { HTT_DATA_MSG_SVC, PIPEDIR_OUT, 4, }, 786 { HTT_DATA_MSG_SVC, PIPEDIR_IN, 1, }, 787 { PACKET_LOG_SVC, PIPEDIR_IN, 5, }, 788 /* (Additions here) */ 789 { 0, 0, 0, }, 790 }; 791 #else 792 static struct service_to_pipe target_service_to_ce_map_qca9574[] = { 793 }; 794 #endif 795 796 #if (defined(QCA_WIFI_QCA8074V2)) 797 static struct service_to_pipe target_service_to_ce_map_qca8074_v2[] = { 798 { WMI_DATA_VO_SVC, PIPEDIR_OUT, 3, }, 799 { WMI_DATA_VO_SVC, PIPEDIR_IN, 2, }, 800 { WMI_DATA_BK_SVC, PIPEDIR_OUT, 3, }, 801 { WMI_DATA_BK_SVC, PIPEDIR_IN, 2, }, 802 { WMI_DATA_BE_SVC, PIPEDIR_OUT, 3, }, 803 { WMI_DATA_BE_SVC, PIPEDIR_IN, 2, }, 804 { WMI_DATA_VI_SVC, PIPEDIR_OUT, 3, }, 805 { WMI_DATA_VI_SVC, PIPEDIR_IN, 2, }, 806 { WMI_CONTROL_SVC, PIPEDIR_OUT, 3, }, 807 { WMI_CONTROL_SVC, PIPEDIR_IN, 2, }, 808 { WMI_CONTROL_SVC_WMAC1, PIPEDIR_OUT, 7}, 809 { WMI_CONTROL_SVC_WMAC1, PIPEDIR_IN, 2}, 810 { WMI_CONTROL_SVC_WMAC2, PIPEDIR_OUT, 9}, 811 { WMI_CONTROL_SVC_WMAC2, PIPEDIR_IN, 2}, 812 { HTC_CTRL_RSVD_SVC, PIPEDIR_OUT, 0, }, 813 { HTC_CTRL_RSVD_SVC, PIPEDIR_IN, 1, }, 814 { HTC_RAW_STREAMS_SVC, PIPEDIR_OUT, 0}, 815 { HTC_RAW_STREAMS_SVC, PIPEDIR_IN, 1 }, 816 { HTT_DATA_MSG_SVC, PIPEDIR_OUT, 4, }, 817 { HTT_DATA_MSG_SVC, PIPEDIR_IN, 1, }, 818 { PACKET_LOG_SVC, PIPEDIR_IN, 5, }, 819 /* (Additions here) */ 820 { 0, 0, 0, }, 821 }; 822 #else 823 static struct service_to_pipe target_service_to_ce_map_qca8074_v2[] = { 824 }; 825 #endif 826 827 #if (defined(QCA_WIFI_QCA6018)) 828 static struct service_to_pipe target_service_to_ce_map_qca6018[] = { 829 { WMI_DATA_VO_SVC, PIPEDIR_OUT, 3, }, 830 { WMI_DATA_VO_SVC, PIPEDIR_IN, 2, }, 831 { WMI_DATA_BK_SVC, PIPEDIR_OUT, 3, }, 832 { WMI_DATA_BK_SVC, PIPEDIR_IN, 2, }, 833 { WMI_DATA_BE_SVC, PIPEDIR_OUT, 3, }, 834 { WMI_DATA_BE_SVC, PIPEDIR_IN, 2, }, 835 { WMI_DATA_VI_SVC, PIPEDIR_OUT, 3, }, 836 { WMI_DATA_VI_SVC, PIPEDIR_IN, 2, }, 837 { WMI_CONTROL_SVC, PIPEDIR_OUT, 3, }, 838 { WMI_CONTROL_SVC, PIPEDIR_IN, 2, }, 839 { WMI_CONTROL_SVC_WMAC1, PIPEDIR_OUT, 7}, 840 { WMI_CONTROL_SVC_WMAC1, PIPEDIR_IN, 2}, 841 { HTC_CTRL_RSVD_SVC, PIPEDIR_OUT, 0, }, 842 { HTC_CTRL_RSVD_SVC, PIPEDIR_IN, 1, }, 843 { HTC_RAW_STREAMS_SVC, PIPEDIR_OUT, 0}, 844 { HTC_RAW_STREAMS_SVC, PIPEDIR_IN, 1 }, 845 { HTT_DATA_MSG_SVC, PIPEDIR_OUT, 4, }, 846 { HTT_DATA_MSG_SVC, PIPEDIR_IN, 1, }, 847 { PACKET_LOG_SVC, PIPEDIR_IN, 5, }, 848 /* (Additions here) */ 849 { 0, 0, 0, }, 850 }; 851 #else 852 static struct service_to_pipe target_service_to_ce_map_qca6018[] = { 853 }; 854 #endif 855 856 #if (defined(QCA_WIFI_QCN9000)) 857 static struct service_to_pipe target_service_to_ce_map_qcn9000[] = { 858 { WMI_DATA_VO_SVC, PIPEDIR_OUT, 3, }, 859 { WMI_DATA_VO_SVC, PIPEDIR_IN, 2, }, 860 { WMI_DATA_BK_SVC, PIPEDIR_OUT, 3, }, 861 { WMI_DATA_BK_SVC, PIPEDIR_IN, 2, }, 862 { WMI_DATA_BE_SVC, PIPEDIR_OUT, 3, }, 863 { WMI_DATA_BE_SVC, PIPEDIR_IN, 2, }, 864 { WMI_DATA_VI_SVC, PIPEDIR_OUT, 3, }, 865 { WMI_DATA_VI_SVC, PIPEDIR_IN, 2, }, 866 { WMI_CONTROL_SVC, PIPEDIR_OUT, 3, }, 867 { WMI_CONTROL_SVC, PIPEDIR_IN, 2, }, 868 { HTC_CTRL_RSVD_SVC, PIPEDIR_OUT, 0, }, 869 { HTC_CTRL_RSVD_SVC, PIPEDIR_IN, 1, }, 870 { HTC_RAW_STREAMS_SVC, PIPEDIR_OUT, 0}, 871 { HTC_RAW_STREAMS_SVC, PIPEDIR_IN, 1 }, 872 { HTT_DATA_MSG_SVC, PIPEDIR_OUT, 4, }, 873 { HTT_DATA_MSG_SVC, PIPEDIR_IN, 1, }, 874 { PACKET_LOG_SVC, PIPEDIR_IN, 5, }, 875 /* (Additions here) */ 876 { 0, 0, 0, }, 877 }; 878 #else 879 static struct service_to_pipe target_service_to_ce_map_qcn9000[] = { 880 }; 881 #endif 882 883 #if (defined(QCA_WIFI_QCA5332) || defined(QCA_WIFI_QCN6432)) 884 static struct service_to_pipe target_service_to_ce_map_qca5332[] = { 885 { WMI_DATA_VO_SVC, PIPEDIR_OUT, 3, }, 886 { WMI_DATA_VO_SVC, PIPEDIR_IN, 2, }, 887 { WMI_DATA_BK_SVC, PIPEDIR_OUT, 3, }, 888 { WMI_DATA_BK_SVC, PIPEDIR_IN, 2, }, 889 { WMI_DATA_BE_SVC, PIPEDIR_OUT, 3, }, 890 { WMI_DATA_BE_SVC, PIPEDIR_IN, 2, }, 891 { WMI_DATA_VI_SVC, PIPEDIR_OUT, 3, }, 892 { WMI_DATA_VI_SVC, PIPEDIR_IN, 2, }, 893 { WMI_CONTROL_SVC, PIPEDIR_OUT, 3, }, 894 { WMI_CONTROL_SVC, PIPEDIR_IN, 2, }, 895 { HTC_CTRL_RSVD_SVC, PIPEDIR_OUT, 0, }, 896 { HTC_CTRL_RSVD_SVC, PIPEDIR_IN, 1, }, 897 { HTC_RAW_STREAMS_SVC, PIPEDIR_OUT, 0}, 898 { HTC_RAW_STREAMS_SVC, PIPEDIR_IN, 1 }, 899 { HTT_DATA_MSG_SVC, PIPEDIR_OUT, 4, }, 900 { HTT_DATA_MSG_SVC, PIPEDIR_IN, 1, }, 901 { PACKET_LOG_SVC, PIPEDIR_IN, 5, }, 902 #ifdef WLAN_DIAG_AND_DBR_OVER_SEPARATE_CE 903 { WMI_CONTROL_DIAG_SVC, PIPEDIR_IN, 9, }, 904 { WMI_CONTROL_DBR_SVC, PIPEDIR_IN, 9, }, 905 #else 906 { WMI_CONTROL_DIAG_SVC, PIPEDIR_IN, 2, }, 907 { WMI_CONTROL_DBR_SVC, PIPEDIR_IN, 2, }, 908 #endif 909 /* (Additions here) */ 910 { 0, 0, 0, }, 911 }; 912 #else 913 static struct service_to_pipe target_service_to_ce_map_qca5332[] = { 914 }; 915 #endif 916 917 #if (defined(QCA_WIFI_QCN9224)) 918 static struct service_to_pipe target_service_to_ce_map_qcn9224[] = { 919 { WMI_DATA_VO_SVC, PIPEDIR_OUT, 3, }, 920 { WMI_DATA_VO_SVC, PIPEDIR_IN, 2, }, 921 { WMI_DATA_BK_SVC, PIPEDIR_OUT, 3, }, 922 { WMI_DATA_BK_SVC, PIPEDIR_IN, 2, }, 923 { WMI_DATA_BE_SVC, PIPEDIR_OUT, 3, }, 924 { WMI_DATA_BE_SVC, PIPEDIR_IN, 2, }, 925 { WMI_DATA_VI_SVC, PIPEDIR_OUT, 3, }, 926 { WMI_DATA_VI_SVC, PIPEDIR_IN, 2, }, 927 { WMI_CONTROL_SVC, PIPEDIR_OUT, 3, }, 928 { WMI_CONTROL_SVC, PIPEDIR_IN, 2, }, 929 { HTC_CTRL_RSVD_SVC, PIPEDIR_OUT, 0, }, 930 { HTC_CTRL_RSVD_SVC, PIPEDIR_IN, 1, }, 931 { HTC_RAW_STREAMS_SVC, PIPEDIR_OUT, 0}, 932 { HTC_RAW_STREAMS_SVC, PIPEDIR_IN, 1 }, 933 { HTT_DATA_MSG_SVC, PIPEDIR_OUT, 4, }, 934 { HTT_DATA_MSG_SVC, PIPEDIR_IN, 1, }, 935 { WMI_CONTROL_SVC_WMAC1, PIPEDIR_OUT, 7, }, 936 { WMI_CONTROL_SVC_WMAC1, PIPEDIR_IN, 2, }, 937 { PACKET_LOG_SVC, PIPEDIR_IN, 5, }, 938 #ifdef WLAN_DIAG_AND_DBR_OVER_SEPARATE_CE 939 { WMI_CONTROL_DIAG_SVC, PIPEDIR_IN, 14, }, 940 { WMI_CONTROL_DBR_SVC, PIPEDIR_IN, 14, }, 941 #else 942 { WMI_CONTROL_DIAG_SVC, PIPEDIR_IN, 2, }, 943 { WMI_CONTROL_DBR_SVC, PIPEDIR_IN, 2, }, 944 #endif 945 /* (Additions here) */ 946 { 0, 0, 0, }, 947 }; 948 #endif 949 950 #if defined(QCA_WIFI_QCA5018) || defined(QCA_WIFI_QCN9160) 951 static struct service_to_pipe target_service_to_ce_map_qca5018[] = { 952 { WMI_DATA_VO_SVC, PIPEDIR_OUT, 3, }, 953 { WMI_DATA_VO_SVC, PIPEDIR_IN, 2, }, 954 { WMI_DATA_BK_SVC, PIPEDIR_OUT, 3, }, 955 { WMI_DATA_BK_SVC, PIPEDIR_IN, 2, }, 956 { WMI_DATA_BE_SVC, PIPEDIR_OUT, 3, }, 957 { WMI_DATA_BE_SVC, PIPEDIR_IN, 2, }, 958 { WMI_DATA_VI_SVC, PIPEDIR_OUT, 3, }, 959 { WMI_DATA_VI_SVC, PIPEDIR_IN, 2, }, 960 { WMI_CONTROL_SVC, PIPEDIR_OUT, 3, }, 961 { WMI_CONTROL_SVC, PIPEDIR_IN, 2, }, 962 { HTC_CTRL_RSVD_SVC, PIPEDIR_OUT, 0, }, 963 { HTC_CTRL_RSVD_SVC, PIPEDIR_IN, 1, }, 964 { HTC_RAW_STREAMS_SVC, PIPEDIR_OUT, 0}, 965 { HTC_RAW_STREAMS_SVC, PIPEDIR_IN, 1 }, 966 { HTT_DATA_MSG_SVC, PIPEDIR_OUT, 4, }, 967 { HTT_DATA_MSG_SVC, PIPEDIR_IN, 1, }, 968 { PACKET_LOG_SVC, PIPEDIR_IN, 5, }, 969 /* (Additions here) */ 970 { 0, 0, 0, }, 971 }; 972 #else 973 static struct service_to_pipe target_service_to_ce_map_qca5018[] = { 974 }; 975 #endif 976 977 /* PIPEDIR_OUT = HOST to Target */ 978 /* PIPEDIR_IN = TARGET to HOST */ 979 #ifdef QCN7605_SUPPORT 980 static struct service_to_pipe target_service_to_ce_map_qcn7605[] = { 981 { WMI_DATA_VO_SVC, PIPEDIR_OUT, 0, }, 982 { WMI_DATA_VO_SVC, PIPEDIR_IN, 2, }, 983 { WMI_DATA_BK_SVC, PIPEDIR_OUT, 0, }, 984 { WMI_DATA_BK_SVC, PIPEDIR_IN, 2, }, 985 { WMI_DATA_BE_SVC, PIPEDIR_OUT, 0, }, 986 { WMI_DATA_BE_SVC, PIPEDIR_IN, 2, }, 987 { WMI_DATA_VI_SVC, PIPEDIR_OUT, 0, }, 988 { WMI_DATA_VI_SVC, PIPEDIR_IN, 2, }, 989 { WMI_CONTROL_SVC, PIPEDIR_OUT, 0, }, 990 { WMI_CONTROL_SVC, PIPEDIR_IN, 2, }, 991 { HTC_CTRL_RSVD_SVC, PIPEDIR_OUT, 0, }, 992 { HTC_CTRL_RSVD_SVC, PIPEDIR_IN, 2, }, 993 { HTC_RAW_STREAMS_SVC, PIPEDIR_OUT, 0, }, 994 { HTC_RAW_STREAMS_SVC, PIPEDIR_IN, 2, }, 995 { HTT_DATA_MSG_SVC, PIPEDIR_OUT, 4, }, 996 { HTT_DATA_MSG_SVC, PIPEDIR_IN, 1, }, 997 { HTT_DATA2_MSG_SVC, PIPEDIR_IN, 3, }, 998 #ifdef IPA_OFFLOAD 999 { WDI_IPA_TX_SVC, PIPEDIR_OUT, 5, }, 1000 #else 1001 { HTT_DATA3_MSG_SVC, PIPEDIR_IN, 8, }, 1002 #endif 1003 { PACKET_LOG_SVC, PIPEDIR_IN, 7, }, 1004 /* (Additions here) */ 1005 { 0, 0, 0, }, 1006 }; 1007 #endif 1008 1009 #if (defined(QCA_WIFI_QCA6290)) 1010 #ifdef QCA_6290_AP_MODE 1011 static struct service_to_pipe target_service_to_ce_map_qca6290[] = { 1012 { WMI_DATA_VO_SVC, PIPEDIR_OUT, 3, }, 1013 { WMI_DATA_VO_SVC, PIPEDIR_IN , 2, }, 1014 { WMI_DATA_BK_SVC, PIPEDIR_OUT, 3, }, 1015 { WMI_DATA_BK_SVC, PIPEDIR_IN , 2, }, 1016 { WMI_DATA_BE_SVC, PIPEDIR_OUT, 3, }, 1017 { WMI_DATA_BE_SVC, PIPEDIR_IN , 2, }, 1018 { WMI_DATA_VI_SVC, PIPEDIR_OUT, 3, }, 1019 { WMI_DATA_VI_SVC, PIPEDIR_IN , 2, }, 1020 { WMI_CONTROL_SVC, PIPEDIR_OUT, 3, }, 1021 { WMI_CONTROL_SVC, PIPEDIR_IN , 2, }, 1022 { HTC_CTRL_RSVD_SVC, PIPEDIR_OUT, 0, }, 1023 { HTC_CTRL_RSVD_SVC, PIPEDIR_IN , 2, }, 1024 { HTT_DATA_MSG_SVC, PIPEDIR_OUT, 4, }, 1025 { HTT_DATA_MSG_SVC, PIPEDIR_IN , 1, }, 1026 { WMI_CONTROL_SVC_WMAC1, PIPEDIR_OUT, 7}, 1027 { WMI_CONTROL_SVC_WMAC1, PIPEDIR_IN, 2}, 1028 { PACKET_LOG_SVC, PIPEDIR_IN, 5, }, 1029 /* (Additions here) */ 1030 { 0, 0, 0, }, 1031 }; 1032 #else 1033 static struct service_to_pipe target_service_to_ce_map_qca6290[] = { 1034 { WMI_DATA_VO_SVC, PIPEDIR_OUT, 3, }, 1035 { WMI_DATA_VO_SVC, PIPEDIR_IN, 2, }, 1036 { WMI_DATA_BK_SVC, PIPEDIR_OUT, 3, }, 1037 { WMI_DATA_BK_SVC, PIPEDIR_IN, 2, }, 1038 { WMI_DATA_BE_SVC, PIPEDIR_OUT, 3, }, 1039 { WMI_DATA_BE_SVC, PIPEDIR_IN, 2, }, 1040 { WMI_DATA_VI_SVC, PIPEDIR_OUT, 3, }, 1041 { WMI_DATA_VI_SVC, PIPEDIR_IN, 2, }, 1042 { WMI_CONTROL_SVC, PIPEDIR_OUT, 3, }, 1043 { WMI_CONTROL_SVC, PIPEDIR_IN, 2, }, 1044 { HTC_CTRL_RSVD_SVC, PIPEDIR_OUT, 0, }, 1045 { HTC_CTRL_RSVD_SVC, PIPEDIR_IN, 2, }, 1046 { HTT_DATA_MSG_SVC, PIPEDIR_OUT, 4, }, 1047 { HTT_DATA_MSG_SVC, PIPEDIR_IN, 1, }, 1048 /* (Additions here) */ 1049 { 0, 0, 0, }, 1050 }; 1051 #endif 1052 #else 1053 static struct service_to_pipe target_service_to_ce_map_qca6290[] = { 1054 }; 1055 #endif 1056 1057 #if (defined(QCA_WIFI_QCA6390)) 1058 static struct service_to_pipe target_service_to_ce_map_qca6390[] = { 1059 { WMI_DATA_VO_SVC, PIPEDIR_OUT, 3, }, 1060 { WMI_DATA_VO_SVC, PIPEDIR_IN, 2, }, 1061 { WMI_DATA_BK_SVC, PIPEDIR_OUT, 3, }, 1062 { WMI_DATA_BK_SVC, PIPEDIR_IN, 2, }, 1063 { WMI_DATA_BE_SVC, PIPEDIR_OUT, 3, }, 1064 { WMI_DATA_BE_SVC, PIPEDIR_IN, 2, }, 1065 { WMI_DATA_VI_SVC, PIPEDIR_OUT, 3, }, 1066 { WMI_DATA_VI_SVC, PIPEDIR_IN, 2, }, 1067 { WMI_CONTROL_SVC, PIPEDIR_OUT, 3, }, 1068 { WMI_CONTROL_SVC, PIPEDIR_IN, 2, }, 1069 { HTC_CTRL_RSVD_SVC, PIPEDIR_OUT, 0, }, 1070 { HTC_CTRL_RSVD_SVC, PIPEDIR_IN, 2, }, 1071 { HTT_DATA_MSG_SVC, PIPEDIR_OUT, 4, }, 1072 { HTT_DATA_MSG_SVC, PIPEDIR_IN, 1, }, 1073 { PACKET_LOG_SVC, PIPEDIR_IN, 5, }, 1074 /* (Additions here) */ 1075 { 0, 0, 0, }, 1076 }; 1077 #else 1078 static struct service_to_pipe target_service_to_ce_map_qca6390[] = { 1079 }; 1080 #endif 1081 1082 static struct service_to_pipe target_service_to_ce_map_qca6490[] = { 1083 { WMI_DATA_VO_SVC, PIPEDIR_OUT, 3, }, 1084 { WMI_DATA_VO_SVC, PIPEDIR_IN, 2, }, 1085 { WMI_DATA_BK_SVC, PIPEDIR_OUT, 3, }, 1086 { WMI_DATA_BK_SVC, PIPEDIR_IN, 2, }, 1087 { WMI_DATA_BE_SVC, PIPEDIR_OUT, 3, }, 1088 { WMI_DATA_BE_SVC, PIPEDIR_IN, 2, }, 1089 { WMI_DATA_VI_SVC, PIPEDIR_OUT, 3, }, 1090 { WMI_DATA_VI_SVC, PIPEDIR_IN, 2, }, 1091 { WMI_CONTROL_SVC, PIPEDIR_OUT, 3, }, 1092 { WMI_CONTROL_SVC, PIPEDIR_IN, 2, }, 1093 { HTC_CTRL_RSVD_SVC, PIPEDIR_OUT, 0, }, 1094 { HTC_CTRL_RSVD_SVC, PIPEDIR_IN, 2, }, 1095 { HTT_DATA_MSG_SVC, PIPEDIR_OUT, 4, }, 1096 { HTT_DATA_MSG_SVC, PIPEDIR_IN, 1, }, 1097 { PACKET_LOG_SVC, PIPEDIR_IN, 5, }, 1098 /* (Additions here) */ 1099 { 0, 0, 0, }, 1100 }; 1101 1102 #if (defined(QCA_WIFI_QCA6750)) 1103 static struct service_to_pipe target_service_to_ce_map_qca6750[] = { 1104 { WMI_DATA_VO_SVC, PIPEDIR_OUT, 3, }, 1105 { WMI_DATA_VO_SVC, PIPEDIR_IN, 2, }, 1106 { WMI_DATA_BK_SVC, PIPEDIR_OUT, 3, }, 1107 { WMI_DATA_BK_SVC, PIPEDIR_IN, 2, }, 1108 { WMI_DATA_BE_SVC, PIPEDIR_OUT, 3, }, 1109 { WMI_DATA_BE_SVC, PIPEDIR_IN, 2, }, 1110 { WMI_DATA_VI_SVC, PIPEDIR_OUT, 3, }, 1111 { WMI_DATA_VI_SVC, PIPEDIR_IN, 2, }, 1112 { WMI_CONTROL_SVC, PIPEDIR_OUT, 3, }, 1113 { WMI_CONTROL_SVC, PIPEDIR_IN, 2, }, 1114 { HTC_CTRL_RSVD_SVC, PIPEDIR_OUT, 0, }, 1115 { HTC_CTRL_RSVD_SVC, PIPEDIR_IN, 2, }, 1116 { HTT_DATA_MSG_SVC, PIPEDIR_OUT, 4, }, 1117 { HTT_DATA_MSG_SVC, PIPEDIR_IN, 1, }, 1118 { PACKET_LOG_SVC, PIPEDIR_IN, 5, }, 1119 #ifdef WLAN_FEATURE_WMI_DIAG_OVER_CE7 1120 { WMI_CONTROL_DIAG_SVC, PIPEDIR_IN, 7, }, 1121 #endif 1122 /* (Additions here) */ 1123 { 0, 0, 0, }, 1124 }; 1125 #else 1126 static struct service_to_pipe target_service_to_ce_map_qca6750[] = { 1127 }; 1128 #endif 1129 1130 #if (defined(QCA_WIFI_KIWI)) 1131 #ifdef FEATURE_DIRECT_LINK 1132 static struct service_to_pipe target_service_to_ce_map_kiwi_direct_link[] = { 1133 { WMI_DATA_VO_SVC, PIPEDIR_OUT, 3, }, 1134 { WMI_DATA_VO_SVC, PIPEDIR_IN, 2, }, 1135 { WMI_DATA_BK_SVC, PIPEDIR_OUT, 3, }, 1136 { WMI_DATA_BK_SVC, PIPEDIR_IN, 2, }, 1137 { WMI_DATA_BE_SVC, PIPEDIR_OUT, 3, }, 1138 { WMI_DATA_BE_SVC, PIPEDIR_IN, 2, }, 1139 { WMI_DATA_VI_SVC, PIPEDIR_OUT, 3, }, 1140 { WMI_DATA_VI_SVC, PIPEDIR_IN, 2, }, 1141 { WMI_CONTROL_SVC, PIPEDIR_OUT, 3, }, 1142 { WMI_CONTROL_SVC, PIPEDIR_IN, 2, }, 1143 { HTC_CTRL_RSVD_SVC, PIPEDIR_OUT, 4, }, 1144 { HTC_CTRL_RSVD_SVC, PIPEDIR_IN, 2, }, 1145 { HTT_DATA_MSG_SVC, PIPEDIR_OUT, 4, }, 1146 { HTT_DATA_MSG_SVC, PIPEDIR_IN, 1, }, 1147 #ifdef WLAN_FEATURE_WMI_DIAG_OVER_CE7 1148 { WMI_CONTROL_DIAG_SVC, PIPEDIR_IN, 7, }, 1149 #endif 1150 { LPASS_DATA_MSG_SVC, PIPEDIR_OUT, 0, }, 1151 { LPASS_DATA_MSG_SVC, PIPEDIR_IN, 5, }, 1152 /* (Additions here) */ 1153 { 0, 0, 0, }, 1154 }; 1155 #endif 1156 1157 static struct service_to_pipe target_service_to_ce_map_kiwi[] = { 1158 { WMI_DATA_VO_SVC, PIPEDIR_OUT, 3, }, 1159 { WMI_DATA_VO_SVC, PIPEDIR_IN, 2, }, 1160 { WMI_DATA_BK_SVC, PIPEDIR_OUT, 3, }, 1161 { WMI_DATA_BK_SVC, PIPEDIR_IN, 2, }, 1162 { WMI_DATA_BE_SVC, PIPEDIR_OUT, 3, }, 1163 { WMI_DATA_BE_SVC, PIPEDIR_IN, 2, }, 1164 { WMI_DATA_VI_SVC, PIPEDIR_OUT, 3, }, 1165 { WMI_DATA_VI_SVC, PIPEDIR_IN, 2, }, 1166 { WMI_CONTROL_SVC, PIPEDIR_OUT, 3, }, 1167 { WMI_CONTROL_SVC, PIPEDIR_IN, 2, }, 1168 { HTC_CTRL_RSVD_SVC, PIPEDIR_OUT, 0, }, 1169 { HTC_CTRL_RSVD_SVC, PIPEDIR_IN, 2, }, 1170 { HTT_DATA_MSG_SVC, PIPEDIR_OUT, 4, }, 1171 { HTT_DATA_MSG_SVC, PIPEDIR_IN, 1, }, 1172 #ifdef WLAN_FEATURE_WMI_DIAG_OVER_CE7 1173 { WMI_CONTROL_DIAG_SVC, PIPEDIR_IN, 7, }, 1174 #endif 1175 /* (Additions here) */ 1176 { 0, 0, 0, }, 1177 }; 1178 #else 1179 static struct service_to_pipe target_service_to_ce_map_kiwi[] = { 1180 }; 1181 #endif 1182 1183 #ifdef QCA_WIFI_WCN6450 1184 static struct service_to_pipe target_service_to_ce_map_wcn6450[] = { 1185 { WMI_DATA_VO_SVC, PIPEDIR_OUT, 3, }, 1186 { WMI_DATA_VO_SVC, PIPEDIR_IN, 2, }, 1187 { WMI_DATA_BK_SVC, PIPEDIR_OUT, 3, }, 1188 { WMI_DATA_BK_SVC, PIPEDIR_IN, 2, }, 1189 { WMI_DATA_BE_SVC, PIPEDIR_OUT, 3, }, 1190 { WMI_DATA_BE_SVC, PIPEDIR_IN, 2, }, 1191 { WMI_DATA_VI_SVC, PIPEDIR_OUT, 3, }, 1192 { WMI_DATA_VI_SVC, PIPEDIR_IN, 2, }, 1193 { WMI_CONTROL_SVC, PIPEDIR_OUT, 3, }, 1194 { WMI_CONTROL_SVC, PIPEDIR_IN, 2, }, 1195 { HTC_CTRL_RSVD_SVC, PIPEDIR_OUT, 0, }, 1196 { HTC_CTRL_RSVD_SVC, PIPEDIR_IN, 2, }, 1197 { HTT_DATA_MSG_SVC, PIPEDIR_OUT, 4, }, 1198 { HTT_DATA2_MSG_SVC, PIPEDIR_OUT, 5, }, 1199 { HTT_DATA_MSG_SVC, PIPEDIR_IN, 1, }, 1200 { HTT_DATA2_MSG_SVC, PIPEDIR_IN, 10, }, 1201 { HTT_DATA3_MSG_SVC, PIPEDIR_IN, 11, }, 1202 #ifdef WLAN_FEATURE_WMI_DIAG_OVER_CE7 1203 { WMI_CONTROL_DIAG_SVC, PIPEDIR_IN, 7, }, 1204 #endif 1205 /* (Additions here) */ 1206 { 0, 0, 0, }, 1207 }; 1208 #else 1209 static struct service_to_pipe target_service_to_ce_map_wcn6450[] = { 1210 }; 1211 #endif 1212 1213 static struct service_to_pipe target_service_to_ce_map_ar900b[] = { 1214 { 1215 WMI_DATA_VO_SVC, 1216 PIPEDIR_OUT, /* out = UL = host -> target */ 1217 3, 1218 }, 1219 { 1220 WMI_DATA_VO_SVC, 1221 PIPEDIR_IN, /* in = DL = target -> host */ 1222 2, 1223 }, 1224 { 1225 WMI_DATA_BK_SVC, 1226 PIPEDIR_OUT, /* out = UL = host -> target */ 1227 3, 1228 }, 1229 { 1230 WMI_DATA_BK_SVC, 1231 PIPEDIR_IN, /* in = DL = target -> host */ 1232 2, 1233 }, 1234 { 1235 WMI_DATA_BE_SVC, 1236 PIPEDIR_OUT, /* out = UL = host -> target */ 1237 3, 1238 }, 1239 { 1240 WMI_DATA_BE_SVC, 1241 PIPEDIR_IN, /* in = DL = target -> host */ 1242 2, 1243 }, 1244 { 1245 WMI_DATA_VI_SVC, 1246 PIPEDIR_OUT, /* out = UL = host -> target */ 1247 3, 1248 }, 1249 { 1250 WMI_DATA_VI_SVC, 1251 PIPEDIR_IN, /* in = DL = target -> host */ 1252 2, 1253 }, 1254 { 1255 WMI_CONTROL_SVC, 1256 PIPEDIR_OUT, /* out = UL = host -> target */ 1257 3, 1258 }, 1259 { 1260 WMI_CONTROL_SVC, 1261 PIPEDIR_IN, /* in = DL = target -> host */ 1262 2, 1263 }, 1264 { 1265 HTC_CTRL_RSVD_SVC, 1266 PIPEDIR_OUT, /* out = UL = host -> target */ 1267 0, /* could be moved to 3 (share with WMI) */ 1268 }, 1269 { 1270 HTC_CTRL_RSVD_SVC, 1271 PIPEDIR_IN, /* in = DL = target -> host */ 1272 1, 1273 }, 1274 { 1275 HTC_RAW_STREAMS_SVC, /* not currently used */ 1276 PIPEDIR_OUT, /* out = UL = host -> target */ 1277 0, 1278 }, 1279 { 1280 HTC_RAW_STREAMS_SVC, /* not currently used */ 1281 PIPEDIR_IN, /* in = DL = target -> host */ 1282 1, 1283 }, 1284 { 1285 HTT_DATA_MSG_SVC, 1286 PIPEDIR_OUT, /* out = UL = host -> target */ 1287 4, 1288 }, 1289 #ifdef WLAN_FEATURE_FASTPATH 1290 { 1291 HTT_DATA_MSG_SVC, 1292 PIPEDIR_IN, /* in = DL = target -> host */ 1293 5, 1294 }, 1295 #else /* WLAN_FEATURE_FASTPATH */ 1296 { 1297 HTT_DATA_MSG_SVC, 1298 PIPEDIR_IN, /* in = DL = target -> host */ 1299 1, 1300 }, 1301 #endif /* WLAN_FEATURE_FASTPATH */ 1302 1303 /* (Additions here) */ 1304 1305 { /* Must be last */ 1306 0, 1307 0, 1308 0, 1309 }, 1310 }; 1311 1312 static struct shadow_reg_cfg *target_shadow_reg_cfg = target_shadow_reg_cfg_map; 1313 static int shadow_cfg_sz = sizeof(target_shadow_reg_cfg_map); 1314 1315 #ifdef WLAN_FEATURE_EPPING 1316 static struct service_to_pipe target_service_to_ce_map_wlan_epping[] = { 1317 {WMI_DATA_VO_SVC, PIPEDIR_OUT, 3,}, /* out = UL = host -> target */ 1318 {WMI_DATA_VO_SVC, PIPEDIR_IN, 2,}, /* in = DL = target -> host */ 1319 {WMI_DATA_BK_SVC, PIPEDIR_OUT, 4,}, /* out = UL = host -> target */ 1320 {WMI_DATA_BK_SVC, PIPEDIR_IN, 1,}, /* in = DL = target -> host */ 1321 {WMI_DATA_BE_SVC, PIPEDIR_OUT, 3,}, /* out = UL = host -> target */ 1322 {WMI_DATA_BE_SVC, PIPEDIR_IN, 2,}, /* in = DL = target -> host */ 1323 {WMI_DATA_VI_SVC, PIPEDIR_OUT, 3,}, /* out = UL = host -> target */ 1324 {WMI_DATA_VI_SVC, PIPEDIR_IN, 2,}, /* in = DL = target -> host */ 1325 {WMI_CONTROL_SVC, PIPEDIR_OUT, 3,}, /* out = UL = host -> target */ 1326 {WMI_CONTROL_SVC, PIPEDIR_IN, 2,}, /* in = DL = target -> host */ 1327 {HTC_CTRL_RSVD_SVC, PIPEDIR_OUT, 0,}, /* out = UL = host -> target */ 1328 {HTC_CTRL_RSVD_SVC, PIPEDIR_IN, 2,}, /* in = DL = target -> host */ 1329 {HTC_RAW_STREAMS_SVC, PIPEDIR_OUT, 0,}, /* out = UL = host -> target */ 1330 {HTC_RAW_STREAMS_SVC, PIPEDIR_IN, 2,}, /* in = DL = target -> host */ 1331 {HTT_DATA_MSG_SVC, PIPEDIR_OUT, 4,}, /* out = UL = host -> target */ 1332 {HTT_DATA_MSG_SVC, PIPEDIR_IN, 1,}, /* in = DL = target -> host */ 1333 {0, 0, 0,}, /* Must be last */ 1334 }; 1335 1336 void hif_select_epping_service_to_pipe_map(struct service_to_pipe 1337 **tgt_svc_map_to_use, 1338 uint32_t *sz_tgt_svc_map_to_use) 1339 { 1340 *tgt_svc_map_to_use = target_service_to_ce_map_wlan_epping; 1341 *sz_tgt_svc_map_to_use = 1342 sizeof(target_service_to_ce_map_wlan_epping); 1343 } 1344 #endif 1345 1346 #ifdef QCN7605_SUPPORT 1347 static inline 1348 void hif_select_ce_map_qcn7605(struct service_to_pipe **tgt_svc_map_to_use, 1349 uint32_t *sz_tgt_svc_map_to_use) 1350 { 1351 *tgt_svc_map_to_use = target_service_to_ce_map_qcn7605; 1352 *sz_tgt_svc_map_to_use = sizeof(target_service_to_ce_map_qcn7605); 1353 } 1354 #else 1355 static inline 1356 void hif_select_ce_map_qcn7605(struct service_to_pipe **tgt_svc_map_to_use, 1357 uint32_t *sz_tgt_svc_map_to_use) 1358 { 1359 hif_err("QCN7605 not supported"); 1360 } 1361 #endif 1362 1363 #ifdef QCA_WIFI_QCN9224 1364 static 1365 void hif_set_ce_config_qcn9224(struct hif_softc *scn, 1366 struct HIF_CE_state *hif_state) 1367 { 1368 hif_state->host_ce_config = host_ce_config_wlan_qcn9224; 1369 hif_state->target_ce_config = target_ce_config_wlan_qcn9224; 1370 hif_state->target_ce_config_sz = 1371 sizeof(target_ce_config_wlan_qcn9224); 1372 scn->ce_count = QCN_9224_CE_COUNT; 1373 scn->ini_cfg.disable_wake_irq = 1; 1374 } 1375 1376 static 1377 void hif_select_ce_map_qcn9224(struct service_to_pipe **tgt_svc_map_to_use, 1378 uint32_t *sz_tgt_svc_map_to_use) 1379 { 1380 *tgt_svc_map_to_use = target_service_to_ce_map_qcn9224; 1381 *sz_tgt_svc_map_to_use = sizeof(target_service_to_ce_map_qcn9224); 1382 } 1383 #else 1384 static inline 1385 void hif_set_ce_config_qcn9224(struct hif_softc *scn, 1386 struct HIF_CE_state *hif_state) 1387 { 1388 hif_err("QCN9224 not supported"); 1389 } 1390 1391 static inline 1392 void hif_select_ce_map_qcn9224(struct service_to_pipe **tgt_svc_map_to_use, 1393 uint32_t *sz_tgt_svc_map_to_use) 1394 { 1395 hif_err("QCN9224 not supported"); 1396 } 1397 #endif 1398 1399 #ifdef FEATURE_DIRECT_LINK 1400 /** 1401 * hif_select_service_to_pipe_map_kiwi() - Select service to CE map 1402 * configuration for Kiwi 1403 * @scn: HIF context 1404 * @tgt_svc_map_to_use: returned service map 1405 * @sz_tgt_svc_map_to_use: returned length of the service map 1406 * 1407 * Return: None 1408 */ 1409 static inline void 1410 hif_select_service_to_pipe_map_kiwi(struct hif_softc *scn, 1411 struct service_to_pipe **tgt_svc_map_to_use, 1412 uint32_t *sz_tgt_svc_map_to_use) 1413 { 1414 if (pld_is_direct_link_supported(scn->qdf_dev->dev)) { 1415 *tgt_svc_map_to_use = target_service_to_ce_map_kiwi_direct_link; 1416 *sz_tgt_svc_map_to_use = 1417 sizeof(target_service_to_ce_map_kiwi_direct_link); 1418 } else { 1419 *tgt_svc_map_to_use = target_service_to_ce_map_kiwi; 1420 *sz_tgt_svc_map_to_use = sizeof(target_service_to_ce_map_kiwi); 1421 } 1422 } 1423 #else 1424 static inline void 1425 hif_select_service_to_pipe_map_kiwi(struct hif_softc *scn, 1426 struct service_to_pipe **tgt_svc_map_to_use, 1427 uint32_t *sz_tgt_svc_map_to_use) 1428 { 1429 *tgt_svc_map_to_use = target_service_to_ce_map_kiwi; 1430 *sz_tgt_svc_map_to_use = sizeof(target_service_to_ce_map_kiwi); 1431 } 1432 #endif 1433 1434 static void hif_select_service_to_pipe_map(struct hif_softc *scn, 1435 struct service_to_pipe **tgt_svc_map_to_use, 1436 uint32_t *sz_tgt_svc_map_to_use) 1437 { 1438 uint32_t mode = hif_get_conparam(scn); 1439 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 1440 struct hif_target_info *tgt_info = &scn->target_info; 1441 1442 if (QDF_IS_EPPING_ENABLED(mode)) { 1443 hif_select_epping_service_to_pipe_map(tgt_svc_map_to_use, 1444 sz_tgt_svc_map_to_use); 1445 } else { 1446 switch (tgt_info->target_type) { 1447 default: 1448 *tgt_svc_map_to_use = target_service_to_ce_map_wlan; 1449 *sz_tgt_svc_map_to_use = 1450 sizeof(target_service_to_ce_map_wlan); 1451 break; 1452 case TARGET_TYPE_QCN7605: 1453 hif_select_ce_map_qcn7605(tgt_svc_map_to_use, 1454 sz_tgt_svc_map_to_use); 1455 break; 1456 case TARGET_TYPE_AR900B: 1457 case TARGET_TYPE_QCA9984: 1458 case TARGET_TYPE_QCA9888: 1459 case TARGET_TYPE_AR9888: 1460 case TARGET_TYPE_AR9888V2: 1461 *tgt_svc_map_to_use = target_service_to_ce_map_ar900b; 1462 *sz_tgt_svc_map_to_use = 1463 sizeof(target_service_to_ce_map_ar900b); 1464 break; 1465 case TARGET_TYPE_QCA6290: 1466 *tgt_svc_map_to_use = target_service_to_ce_map_qca6290; 1467 *sz_tgt_svc_map_to_use = 1468 sizeof(target_service_to_ce_map_qca6290); 1469 break; 1470 case TARGET_TYPE_QCA6390: 1471 *tgt_svc_map_to_use = target_service_to_ce_map_qca6390; 1472 *sz_tgt_svc_map_to_use = 1473 sizeof(target_service_to_ce_map_qca6390); 1474 break; 1475 case TARGET_TYPE_QCA6490: 1476 *tgt_svc_map_to_use = target_service_to_ce_map_qca6490; 1477 *sz_tgt_svc_map_to_use = 1478 sizeof(target_service_to_ce_map_qca6490); 1479 break; 1480 case TARGET_TYPE_QCA6750: 1481 *tgt_svc_map_to_use = target_service_to_ce_map_qca6750; 1482 *sz_tgt_svc_map_to_use = 1483 sizeof(target_service_to_ce_map_qca6750); 1484 break; 1485 case TARGET_TYPE_KIWI: 1486 case TARGET_TYPE_MANGO: 1487 case TARGET_TYPE_PEACH: 1488 hif_select_service_to_pipe_map_kiwi(scn, 1489 tgt_svc_map_to_use, 1490 sz_tgt_svc_map_to_use); 1491 break; 1492 case TARGET_TYPE_WCN6450: 1493 *tgt_svc_map_to_use = target_service_to_ce_map_wcn6450; 1494 *sz_tgt_svc_map_to_use = 1495 sizeof(target_service_to_ce_map_wcn6450); 1496 break; 1497 case TARGET_TYPE_QCA8074: 1498 *tgt_svc_map_to_use = target_service_to_ce_map_qca8074; 1499 *sz_tgt_svc_map_to_use = 1500 sizeof(target_service_to_ce_map_qca8074); 1501 break; 1502 case TARGET_TYPE_QCA8074V2: 1503 *tgt_svc_map_to_use = 1504 target_service_to_ce_map_qca8074_v2; 1505 *sz_tgt_svc_map_to_use = 1506 sizeof(target_service_to_ce_map_qca8074_v2); 1507 break; 1508 case TARGET_TYPE_QCA9574: 1509 *tgt_svc_map_to_use = 1510 target_service_to_ce_map_qca9574; 1511 *sz_tgt_svc_map_to_use = 1512 sizeof(target_service_to_ce_map_qca9574); 1513 break; 1514 case TARGET_TYPE_QCA6018: 1515 *tgt_svc_map_to_use = 1516 target_service_to_ce_map_qca6018; 1517 *sz_tgt_svc_map_to_use = 1518 sizeof(target_service_to_ce_map_qca6018); 1519 break; 1520 case TARGET_TYPE_QCN9000: 1521 *tgt_svc_map_to_use = 1522 target_service_to_ce_map_qcn9000; 1523 *sz_tgt_svc_map_to_use = 1524 sizeof(target_service_to_ce_map_qcn9000); 1525 break; 1526 case TARGET_TYPE_QCN9224: 1527 hif_select_ce_map_qcn9224(tgt_svc_map_to_use, 1528 sz_tgt_svc_map_to_use); 1529 break; 1530 case TARGET_TYPE_QCA5332: 1531 case TARGET_TYPE_QCN6432: 1532 *tgt_svc_map_to_use = target_service_to_ce_map_qca5332; 1533 *sz_tgt_svc_map_to_use = 1534 sizeof(target_service_to_ce_map_qca5332); 1535 break; 1536 case TARGET_TYPE_QCA5018: 1537 case TARGET_TYPE_QCN6122: 1538 case TARGET_TYPE_QCN9160: 1539 *tgt_svc_map_to_use = 1540 target_service_to_ce_map_qca5018; 1541 *sz_tgt_svc_map_to_use = 1542 sizeof(target_service_to_ce_map_qca5018); 1543 break; 1544 } 1545 } 1546 hif_state->tgt_svc_map = *tgt_svc_map_to_use; 1547 hif_state->sz_tgt_svc_map = *sz_tgt_svc_map_to_use / 1548 sizeof(struct service_to_pipe); 1549 } 1550 1551 #ifndef QCA_WIFI_WCN6450 1552 /** 1553 * ce_mark_datapath() - marks the ce_state->htt_rx_data accordingly 1554 * @ce_state : pointer to the state context of the CE 1555 * 1556 * Description: 1557 * Sets htt_rx_data attribute of the state structure if the 1558 * CE serves one of the HTT DATA services. 1559 * 1560 * Return: 1561 * false (attribute set to false) 1562 * true (attribute set to true); 1563 */ 1564 static bool ce_mark_datapath(struct CE_state *ce_state) 1565 { 1566 struct service_to_pipe *svc_map; 1567 uint32_t map_sz, map_len; 1568 int i; 1569 bool rc = false; 1570 1571 if (ce_state) { 1572 hif_select_service_to_pipe_map(ce_state->scn, &svc_map, 1573 &map_sz); 1574 1575 map_len = map_sz / sizeof(struct service_to_pipe); 1576 for (i = 0; i < map_len; i++) { 1577 if ((svc_map[i].pipenum == ce_state->id) && 1578 ((svc_map[i].service_id == HTT_DATA_MSG_SVC) || 1579 (svc_map[i].service_id == HTT_DATA2_MSG_SVC) || 1580 (svc_map[i].service_id == HTT_DATA3_MSG_SVC))) { 1581 /* HTT CEs are unidirectional */ 1582 if (svc_map[i].pipedir == PIPEDIR_IN) 1583 ce_state->htt_rx_data = true; 1584 else 1585 ce_state->htt_tx_data = true; 1586 rc = true; 1587 } 1588 } 1589 } 1590 return rc; 1591 } 1592 1593 static void ce_update_msi_batch_intr_flags(struct CE_state *ce_state) 1594 { 1595 } 1596 1597 static inline void ce_update_wrt_idx_offset(struct hif_softc *scn, 1598 struct CE_state *ce_state, 1599 uint8_t ring_type) 1600 { 1601 } 1602 #else 1603 static bool ce_mark_datapath(struct CE_state *ce_state) 1604 { 1605 struct service_to_pipe *svc_map; 1606 uint32_t map_sz, map_len; 1607 int i; 1608 1609 if (ce_state) { 1610 hif_select_service_to_pipe_map(ce_state->scn, &svc_map, 1611 &map_sz); 1612 1613 map_len = map_sz / sizeof(struct service_to_pipe); 1614 for (i = 0; i < map_len; i++) { 1615 if ((svc_map[i].pipenum == ce_state->id) && 1616 ((svc_map[i].service_id == HTT_DATA_MSG_SVC) || 1617 (svc_map[i].service_id == HTT_DATA2_MSG_SVC) || 1618 (svc_map[i].service_id == HTT_DATA3_MSG_SVC)) && 1619 (svc_map[i].pipedir == PIPEDIR_IN)) 1620 ce_state->htt_rx_data = true; 1621 else if ((svc_map[i].pipenum == ce_state->id) && 1622 (svc_map[i].service_id == HTT_DATA2_MSG_SVC) && 1623 (svc_map[i].pipedir == PIPEDIR_OUT)) 1624 ce_state->htt_tx_data = true; 1625 } 1626 } 1627 1628 return (ce_state->htt_rx_data || ce_state->htt_tx_data); 1629 } 1630 1631 static void ce_update_msi_batch_intr_flags(struct CE_state *ce_state) 1632 { 1633 ce_state->msi_supported = true; 1634 ce_state->batch_intr_supported = true; 1635 } 1636 1637 static inline void ce_update_wrt_idx_offset(struct hif_softc *scn, 1638 struct CE_state *ce_state, 1639 uint8_t ring_type) 1640 { 1641 if (ring_type == CE_RING_SRC) 1642 ce_state->ce_wrt_idx_offset = 1643 CE_SRC_WR_IDX_OFFSET_GET(scn, ce_state->ctrl_addr); 1644 else if (ring_type == CE_RING_DEST) 1645 ce_state->ce_wrt_idx_offset = 1646 CE_DST_WR_IDX_OFFSET_GET(scn, ce_state->ctrl_addr); 1647 else 1648 QDF_BUG(0); 1649 } 1650 1651 /* 1652 * hif_ce_print_ring_stats() - Print ce ring statistics 1653 * 1654 * @hif_ctx: hif context 1655 * 1656 * Returns: None 1657 */ 1658 void hif_ce_print_ring_stats(struct hif_opaque_softc *hif_ctx) 1659 { 1660 struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); 1661 struct CE_state *ce_state; 1662 int i; 1663 1664 for (i = 0; i < scn->ce_count; i++) { 1665 ce_state = scn->ce_id_to_state[i]; 1666 if (!ce_state) 1667 continue; 1668 1669 if (ce_state->src_ring) { 1670 QDF_TRACE(QDF_MODULE_ID_HIF, QDF_TRACE_LEVEL_FATAL, 1671 "ce%d:SW: sw_index %u write_index %u", 1672 ce_state->src_ring->sw_index, 1673 ce_state->src_ring->write_index); 1674 1675 QDF_TRACE(QDF_MODULE_ID_HIF, QDF_TRACE_LEVEL_FATAL, 1676 "ce%d:HW: read_index %u write_index %u", 1677 CE_SRC_RING_READ_IDX_GET_FROM_REGISTER(scn, ce_state->ctrl_addr), 1678 CE_SRC_RING_WRITE_IDX_GET_FROM_REGISTER(scn, ce_state->ctrl_addr)); 1679 } 1680 1681 if (ce_state->dest_ring) { 1682 QDF_TRACE(QDF_MODULE_ID_HIF, QDF_TRACE_LEVEL_FATAL, 1683 "ce%d:SW: sw_index %u write_index %u", 1684 ce_state->dest_ring->sw_index, 1685 ce_state->dest_ring->write_index); 1686 1687 QDF_TRACE(QDF_MODULE_ID_HIF, QDF_TRACE_LEVEL_FATAL, 1688 "ce%d:HW: read_index %u write_index %u", 1689 CE_DEST_RING_READ_IDX_GET_FROM_REGISTER(scn, ce_state->ctrl_addr), 1690 CE_DEST_RING_WRITE_IDX_GET_FROM_REGISTER(scn, ce_state->ctrl_addr)); 1691 } 1692 } 1693 } 1694 #endif 1695 1696 /** 1697 * hif_get_max_wmi_ep() - Get max WMI EPs configured in target svc map 1698 * @hif_ctx: hif opaque handle 1699 * 1700 * Description: 1701 * Gets number of WMI EPs configured in target svc map. Since EP map 1702 * include IN and OUT direction pipes, count only OUT pipes to get EPs 1703 * configured for WMI service. 1704 * 1705 * Return: 1706 * uint8_t: count for WMI eps in target svc map 1707 */ 1708 uint8_t hif_get_max_wmi_ep(struct hif_opaque_softc *hif_ctx) 1709 { 1710 struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); 1711 struct service_to_pipe *svc_map; 1712 uint32_t map_sz, map_len; 1713 int i; 1714 uint8_t wmi_ep_count = 0; 1715 1716 hif_select_service_to_pipe_map(scn, &svc_map, 1717 &map_sz); 1718 map_len = map_sz / sizeof(struct service_to_pipe); 1719 1720 for (i = 0; i < map_len; i++) { 1721 /* Count number of WMI EPs based on out direction */ 1722 if ((svc_map[i].pipedir == PIPEDIR_OUT) && 1723 ((svc_map[i].service_id == WMI_CONTROL_SVC) || 1724 (svc_map[i].service_id == WMI_CONTROL_SVC_WMAC1) || 1725 (svc_map[i].service_id == WMI_CONTROL_SVC_WMAC2))) { 1726 wmi_ep_count++; 1727 } 1728 } 1729 1730 return wmi_ep_count; 1731 } 1732 1733 /** 1734 * ce_ring_test_initial_indexes() - tests the initial ce ring indexes 1735 * @ce_id: ce in question 1736 * @ring: ring state being examined 1737 * @type: "src_ring" or "dest_ring" string for identifying the ring 1738 * 1739 * Warns on non-zero index values. 1740 * Causes a kernel panic if the ring is not empty during initialization. 1741 */ 1742 static void ce_ring_test_initial_indexes(int ce_id, struct CE_ring_state *ring, 1743 char *type) 1744 { 1745 if (ring->write_index != 0 || ring->sw_index != 0) 1746 hif_err("ce %d, %s, initial sw_index = %d, initial write_index =%d", 1747 ce_id, type, ring->sw_index, ring->write_index); 1748 if (ring->write_index != ring->sw_index) 1749 QDF_BUG(0); 1750 } 1751 1752 #ifdef IPA_OFFLOAD 1753 /** 1754 * ce_alloc_desc_ring() - Allocate copyengine descriptor ring 1755 * @scn: softc instance 1756 * @CE_id: ce in question 1757 * @base_addr: pointer to copyengine ring base address 1758 * @ce_ring: copyengine instance 1759 * @nentries: number of entries should be allocated 1760 * @desc_size: ce desc size 1761 * 1762 * Return: QDF_STATUS_SUCCESS - for success 1763 */ 1764 static QDF_STATUS ce_alloc_desc_ring(struct hif_softc *scn, unsigned int CE_id, 1765 qdf_dma_addr_t *base_addr, 1766 struct CE_ring_state *ce_ring, 1767 unsigned int nentries, uint32_t desc_size) 1768 { 1769 if ((CE_id == HIF_PCI_IPA_UC_ASSIGNED_CE) && 1770 !ce_srng_based(scn)) { 1771 if (!scn->ipa_ce_ring) { 1772 scn->ipa_ce_ring = qdf_mem_shared_mem_alloc( 1773 scn->qdf_dev, 1774 nentries * desc_size + CE_DESC_RING_ALIGN); 1775 if (!scn->ipa_ce_ring) { 1776 hif_err( 1777 "Failed to allocate memory for IPA ce ring"); 1778 return QDF_STATUS_E_NOMEM; 1779 } 1780 } 1781 *base_addr = qdf_mem_get_dma_addr(scn->qdf_dev, 1782 &scn->ipa_ce_ring->mem_info); 1783 ce_ring->base_addr_owner_space_unaligned = 1784 scn->ipa_ce_ring->vaddr; 1785 } else { 1786 ce_ring->base_addr_owner_space_unaligned = 1787 hif_mem_alloc_consistent_unaligned 1788 (scn, 1789 (nentries * desc_size + 1790 CE_DESC_RING_ALIGN), 1791 base_addr, 1792 ce_ring->hal_ring_type, 1793 &ce_ring->is_ring_prealloc); 1794 1795 if (!ce_ring->base_addr_owner_space_unaligned) { 1796 hif_err("Failed to allocate DMA memory for ce ring id: %u", 1797 CE_id); 1798 return QDF_STATUS_E_NOMEM; 1799 } 1800 } 1801 return QDF_STATUS_SUCCESS; 1802 } 1803 1804 /** 1805 * ce_free_desc_ring() - Frees copyengine descriptor ring 1806 * @scn: softc instance 1807 * @CE_id: ce in question 1808 * @ce_ring: copyengine instance 1809 * @desc_size: ce desc size 1810 * 1811 * Return: None 1812 */ 1813 static void ce_free_desc_ring(struct hif_softc *scn, unsigned int CE_id, 1814 struct CE_ring_state *ce_ring, uint32_t desc_size) 1815 { 1816 if ((CE_id == HIF_PCI_IPA_UC_ASSIGNED_CE) && 1817 !ce_srng_based(scn)) { 1818 if (scn->ipa_ce_ring) { 1819 qdf_mem_shared_mem_free(scn->qdf_dev, 1820 scn->ipa_ce_ring); 1821 scn->ipa_ce_ring = NULL; 1822 } 1823 ce_ring->base_addr_owner_space_unaligned = NULL; 1824 } else { 1825 hif_mem_free_consistent_unaligned 1826 (scn, 1827 ce_ring->nentries * desc_size + CE_DESC_RING_ALIGN, 1828 ce_ring->base_addr_owner_space_unaligned, 1829 ce_ring->base_addr_CE_space, 0, 1830 ce_ring->is_ring_prealloc); 1831 ce_ring->base_addr_owner_space_unaligned = NULL; 1832 } 1833 } 1834 #else 1835 static QDF_STATUS ce_alloc_desc_ring(struct hif_softc *scn, unsigned int CE_id, 1836 qdf_dma_addr_t *base_addr, 1837 struct CE_ring_state *ce_ring, 1838 unsigned int nentries, uint32_t desc_size) 1839 { 1840 ce_ring->base_addr_owner_space_unaligned = 1841 hif_mem_alloc_consistent_unaligned 1842 (scn, 1843 (nentries * desc_size + 1844 CE_DESC_RING_ALIGN), 1845 base_addr, 1846 ce_ring->hal_ring_type, 1847 &ce_ring->is_ring_prealloc); 1848 1849 if (!ce_ring->base_addr_owner_space_unaligned) { 1850 hif_err("Failed to allocate DMA memory for ce ring id: %u", 1851 CE_id); 1852 return QDF_STATUS_E_NOMEM; 1853 } 1854 return QDF_STATUS_SUCCESS; 1855 } 1856 1857 static void ce_free_desc_ring(struct hif_softc *scn, unsigned int CE_id, 1858 struct CE_ring_state *ce_ring, uint32_t desc_size) 1859 { 1860 hif_mem_free_consistent_unaligned 1861 (scn, 1862 ce_ring->nentries * desc_size + CE_DESC_RING_ALIGN, 1863 ce_ring->base_addr_owner_space_unaligned, 1864 ce_ring->base_addr_CE_space, 0, 1865 ce_ring->is_ring_prealloc); 1866 ce_ring->base_addr_owner_space_unaligned = NULL; 1867 } 1868 #endif /* IPA_OFFLOAD */ 1869 1870 /* 1871 * TODO: Need to explore the possibility of having this as part of a 1872 * target context instead of a global array. 1873 */ 1874 static struct ce_ops* (*ce_attach_register[CE_MAX_TARGET_TYPE])(void); 1875 1876 void ce_service_register_module(enum ce_target_type target_type, 1877 struct ce_ops* (*ce_attach)(void)) 1878 { 1879 if (target_type < CE_MAX_TARGET_TYPE) 1880 ce_attach_register[target_type] = ce_attach; 1881 } 1882 1883 qdf_export_symbol(ce_service_register_module); 1884 1885 /** 1886 * ce_srng_based() - Does this target use srng 1887 * @scn: pointer to the state context of the CE 1888 * 1889 * Description: 1890 * returns true if the target is SRNG based 1891 * 1892 * Return: 1893 * false (attribute set to false) 1894 * true (attribute set to true); 1895 */ 1896 bool ce_srng_based(struct hif_softc *scn) 1897 { 1898 struct hif_opaque_softc *hif_hdl = GET_HIF_OPAQUE_HDL(scn); 1899 struct hif_target_info *tgt_info = hif_get_target_info_handle(hif_hdl); 1900 1901 switch (tgt_info->target_type) { 1902 case TARGET_TYPE_QCA8074: 1903 case TARGET_TYPE_QCA8074V2: 1904 case TARGET_TYPE_QCA6290: 1905 case TARGET_TYPE_QCA6390: 1906 case TARGET_TYPE_QCA6490: 1907 case TARGET_TYPE_QCA6750: 1908 case TARGET_TYPE_QCA6018: 1909 case TARGET_TYPE_QCN9000: 1910 case TARGET_TYPE_QCN6122: 1911 case TARGET_TYPE_QCN9160: 1912 case TARGET_TYPE_QCA5018: 1913 case TARGET_TYPE_KIWI: 1914 case TARGET_TYPE_MANGO: 1915 case TARGET_TYPE_PEACH: 1916 case TARGET_TYPE_QCN9224: 1917 case TARGET_TYPE_QCA9574: 1918 case TARGET_TYPE_QCA5332: 1919 case TARGET_TYPE_QCN6432: 1920 return true; 1921 default: 1922 return false; 1923 } 1924 return false; 1925 } 1926 qdf_export_symbol(ce_srng_based); 1927 1928 #ifdef QCA_WIFI_SUPPORT_SRNG 1929 static struct ce_ops *ce_services_attach(struct hif_softc *scn) 1930 { 1931 struct ce_ops *ops = NULL; 1932 1933 if (ce_srng_based(scn)) { 1934 if (ce_attach_register[CE_SVC_SRNG]) 1935 ops = ce_attach_register[CE_SVC_SRNG](); 1936 } else if (ce_attach_register[CE_SVC_LEGACY]) { 1937 ops = ce_attach_register[CE_SVC_LEGACY](); 1938 } 1939 1940 return ops; 1941 } 1942 1943 1944 #else /* QCA_LITHIUM */ 1945 static struct ce_ops *ce_services_attach(struct hif_softc *scn) 1946 { 1947 if (ce_attach_register[CE_SVC_LEGACY]) 1948 return ce_attach_register[CE_SVC_LEGACY](); 1949 1950 return NULL; 1951 } 1952 #endif /* QCA_LITHIUM */ 1953 1954 static void hif_prepare_hal_shadow_register_cfg(struct hif_softc *scn, 1955 struct pld_shadow_reg_v2_cfg **shadow_config, 1956 int *num_shadow_registers_configured) { 1957 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 1958 1959 hif_state->ce_services->ce_prepare_shadow_register_v2_cfg( 1960 scn, shadow_config, num_shadow_registers_configured); 1961 1962 return; 1963 } 1964 1965 #ifdef CONFIG_SHADOW_V3 1966 static inline void 1967 hif_prepare_hal_shadow_reg_cfg_v3(struct hif_softc *scn, 1968 struct pld_wlan_enable_cfg *cfg) 1969 { 1970 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 1971 1972 if (!hif_state->ce_services->ce_prepare_shadow_register_v3_cfg) 1973 return; 1974 1975 hif_state->ce_services->ce_prepare_shadow_register_v3_cfg( 1976 scn, &cfg->shadow_reg_v3_cfg, 1977 &cfg->num_shadow_reg_v3_cfg); 1978 } 1979 #else 1980 static inline void 1981 hif_prepare_hal_shadow_reg_cfg_v3(struct hif_softc *scn, 1982 struct pld_wlan_enable_cfg *cfg) 1983 { 1984 } 1985 #endif 1986 1987 static inline uint32_t ce_get_desc_size(struct hif_softc *scn, 1988 uint8_t ring_type) 1989 { 1990 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 1991 1992 return hif_state->ce_services->ce_get_desc_size(ring_type); 1993 } 1994 1995 #ifdef QCA_WIFI_SUPPORT_SRNG 1996 static inline int32_t ce_ring_type_to_hal_ring_type(uint32_t ce_ring_type) 1997 { 1998 switch (ce_ring_type) { 1999 case CE_RING_SRC: 2000 return CE_SRC; 2001 case CE_RING_DEST: 2002 return CE_DST; 2003 case CE_RING_STATUS: 2004 return CE_DST_STATUS; 2005 default: 2006 return -EINVAL; 2007 } 2008 } 2009 #else 2010 static int32_t ce_ring_type_to_hal_ring_type(uint32_t ce_ring_type) 2011 { 2012 return 0; 2013 } 2014 #endif 2015 static struct CE_ring_state *ce_alloc_ring_state(struct CE_state *CE_state, 2016 uint8_t ring_type, uint32_t nentries) 2017 { 2018 uint32_t ce_nbytes; 2019 char *ptr; 2020 qdf_dma_addr_t base_addr; 2021 struct CE_ring_state *ce_ring; 2022 uint32_t desc_size; 2023 struct hif_softc *scn = CE_state->scn; 2024 2025 ce_nbytes = sizeof(struct CE_ring_state) 2026 + (nentries * sizeof(void *)); 2027 ptr = qdf_mem_malloc(ce_nbytes); 2028 if (!ptr) 2029 return NULL; 2030 2031 ce_ring = (struct CE_ring_state *)ptr; 2032 ptr += sizeof(struct CE_ring_state); 2033 ce_ring->nentries = nentries; 2034 ce_ring->nentries_mask = nentries - 1; 2035 2036 ce_ring->low_water_mark_nentries = 0; 2037 ce_ring->high_water_mark_nentries = nentries; 2038 ce_ring->per_transfer_context = (void **)ptr; 2039 ce_ring->hal_ring_type = ce_ring_type_to_hal_ring_type(ring_type); 2040 2041 desc_size = ce_get_desc_size(scn, ring_type); 2042 2043 /* Legacy platforms that do not support cache 2044 * coherent DMA are unsupported 2045 */ 2046 if (ce_alloc_desc_ring(scn, CE_state->id, &base_addr, 2047 ce_ring, nentries, 2048 desc_size) != 2049 QDF_STATUS_SUCCESS) { 2050 hif_err("ring has no DMA mem"); 2051 qdf_mem_free(ce_ring); 2052 return NULL; 2053 } 2054 ce_ring->base_addr_CE_space_unaligned = base_addr; 2055 2056 /* Correctly initialize memory to 0 to 2057 * prevent garbage data crashing system 2058 * when download firmware 2059 */ 2060 qdf_mem_zero(ce_ring->base_addr_owner_space_unaligned, 2061 nentries * desc_size + 2062 CE_DESC_RING_ALIGN); 2063 2064 if (ce_ring->base_addr_CE_space_unaligned & (CE_DESC_RING_ALIGN - 1)) { 2065 2066 ce_ring->base_addr_CE_space = 2067 (ce_ring->base_addr_CE_space_unaligned + 2068 CE_DESC_RING_ALIGN - 1) & ~(CE_DESC_RING_ALIGN - 1); 2069 2070 ce_ring->base_addr_owner_space = (void *) 2071 (((size_t) ce_ring->base_addr_owner_space_unaligned + 2072 CE_DESC_RING_ALIGN - 1) & ~(CE_DESC_RING_ALIGN - 1)); 2073 } else { 2074 ce_ring->base_addr_CE_space = 2075 ce_ring->base_addr_CE_space_unaligned; 2076 ce_ring->base_addr_owner_space = 2077 ce_ring->base_addr_owner_space_unaligned; 2078 } 2079 2080 return ce_ring; 2081 } 2082 2083 static int ce_ring_setup(struct hif_softc *scn, uint8_t ring_type, 2084 uint32_t ce_id, struct CE_ring_state *ring, 2085 struct CE_attr *attr) 2086 { 2087 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 2088 2089 return hif_state->ce_services->ce_ring_setup(scn, ring_type, ce_id, 2090 ring, attr); 2091 } 2092 2093 static void ce_srng_cleanup(struct hif_softc *scn, struct CE_state *CE_state, 2094 uint8_t ring_type) 2095 { 2096 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 2097 2098 if (hif_state->ce_services->ce_srng_cleanup) 2099 hif_state->ce_services->ce_srng_cleanup(scn, 2100 CE_state, ring_type); 2101 } 2102 2103 int hif_ce_bus_early_suspend(struct hif_softc *scn) 2104 { 2105 uint8_t ul_pipe, dl_pipe; 2106 int ce_id, status, ul_is_polled, dl_is_polled; 2107 struct CE_state *ce_state; 2108 2109 status = hif_map_service_to_pipe(&scn->osc, WMI_CONTROL_SVC, 2110 &ul_pipe, &dl_pipe, 2111 &ul_is_polled, &dl_is_polled); 2112 if (status) { 2113 hif_err("pipe_mapping failure"); 2114 return status; 2115 } 2116 2117 for (ce_id = 0; ce_id < scn->ce_count; ce_id++) { 2118 if (ce_id == ul_pipe) 2119 continue; 2120 if (ce_id == dl_pipe) 2121 continue; 2122 2123 ce_state = scn->ce_id_to_state[ce_id]; 2124 qdf_spin_lock_bh(&ce_state->ce_index_lock); 2125 if (ce_state->state == CE_RUNNING) 2126 ce_state->state = CE_PAUSED; 2127 qdf_spin_unlock_bh(&ce_state->ce_index_lock); 2128 } 2129 2130 return status; 2131 } 2132 2133 int hif_ce_bus_late_resume(struct hif_softc *scn) 2134 { 2135 int ce_id; 2136 struct CE_state *ce_state; 2137 int write_index = 0; 2138 bool index_updated; 2139 2140 for (ce_id = 0; ce_id < scn->ce_count; ce_id++) { 2141 ce_state = scn->ce_id_to_state[ce_id]; 2142 qdf_spin_lock_bh(&ce_state->ce_index_lock); 2143 if (ce_state->state == CE_PENDING) { 2144 write_index = ce_state->src_ring->write_index; 2145 CE_SRC_RING_WRITE_IDX_SET(scn, ce_state->ctrl_addr, 2146 write_index); 2147 ce_state->state = CE_RUNNING; 2148 index_updated = true; 2149 } else { 2150 index_updated = false; 2151 } 2152 2153 if (ce_state->state == CE_PAUSED) 2154 ce_state->state = CE_RUNNING; 2155 qdf_spin_unlock_bh(&ce_state->ce_index_lock); 2156 2157 if (index_updated) 2158 hif_record_ce_desc_event(scn, ce_id, 2159 RESUME_WRITE_INDEX_UPDATE, 2160 NULL, NULL, write_index, 0); 2161 } 2162 2163 return 0; 2164 } 2165 2166 /** 2167 * ce_oom_recovery() - try to recover rx ce from oom condition 2168 * @context: CE_state of the CE with oom rx ring 2169 * 2170 * the executing work Will continue to be rescheduled until 2171 * at least 1 descriptor is successfully posted to the rx ring. 2172 * 2173 * return: none 2174 */ 2175 static void ce_oom_recovery(void *context) 2176 { 2177 struct CE_state *ce_state = context; 2178 struct hif_softc *scn = ce_state->scn; 2179 struct HIF_CE_state *ce_softc = HIF_GET_CE_STATE(scn); 2180 struct HIF_CE_pipe_info *pipe_info = 2181 &ce_softc->pipe_info[ce_state->id]; 2182 2183 hif_post_recv_buffers_for_pipe(pipe_info); 2184 } 2185 2186 #ifdef HIF_CE_DEBUG_DATA_BUF 2187 /** 2188 * alloc_mem_ce_debug_hist_data() - Allocate mem for the data pointed by 2189 * the CE descriptors. 2190 * Allocate HIF_CE_HISTORY_MAX records by CE_DEBUG_MAX_DATA_BUF_SIZE 2191 * @scn: hif scn handle 2192 * @ce_id: Copy Engine Id 2193 * 2194 * Return: QDF_STATUS 2195 */ 2196 QDF_STATUS alloc_mem_ce_debug_hist_data(struct hif_softc *scn, uint32_t ce_id) 2197 { 2198 struct hif_ce_desc_event *event = NULL; 2199 struct hif_ce_desc_event *hist_ev = NULL; 2200 uint32_t index = 0; 2201 2202 hist_ev = 2203 (struct hif_ce_desc_event *)scn->hif_ce_desc_hist.hist_ev[ce_id]; 2204 2205 if (!hist_ev) 2206 return QDF_STATUS_E_NOMEM; 2207 2208 scn->hif_ce_desc_hist.data_enable[ce_id] = true; 2209 for (index = 0; index < HIF_CE_HISTORY_MAX; index++) { 2210 event = &hist_ev[index]; 2211 event->data = 2212 (uint8_t *)qdf_mem_malloc(CE_DEBUG_MAX_DATA_BUF_SIZE); 2213 if (!event->data) { 2214 hif_err_rl("ce debug data alloc failed"); 2215 scn->hif_ce_desc_hist.data_enable[ce_id] = false; 2216 return QDF_STATUS_E_NOMEM; 2217 } 2218 } 2219 return QDF_STATUS_SUCCESS; 2220 } 2221 2222 /** 2223 * free_mem_ce_debug_hist_data() - Free mem of the data pointed by 2224 * the CE descriptors. 2225 * @scn: hif scn handle 2226 * @ce_id: Copy Engine Id 2227 * 2228 * Return: 2229 */ 2230 void free_mem_ce_debug_hist_data(struct hif_softc *scn, uint32_t ce_id) 2231 { 2232 struct hif_ce_desc_event *event = NULL; 2233 struct hif_ce_desc_event *hist_ev = NULL; 2234 uint32_t index = 0; 2235 2236 hist_ev = 2237 (struct hif_ce_desc_event *)scn->hif_ce_desc_hist.hist_ev[ce_id]; 2238 2239 if (!hist_ev) 2240 return; 2241 2242 for (index = 0; index < HIF_CE_HISTORY_MAX; index++) { 2243 event = &hist_ev[index]; 2244 if (event->data) 2245 qdf_mem_free(event->data); 2246 event->data = NULL; 2247 event = NULL; 2248 } 2249 2250 } 2251 #endif /* HIF_CE_DEBUG_DATA_BUF */ 2252 2253 #ifndef HIF_CE_DEBUG_DATA_DYNAMIC_BUF 2254 #if defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF) 2255 2256 /* define below variables for crashscope parse */ 2257 struct hif_ce_desc_event *hif_ce_desc_history[CE_COUNT_MAX]; 2258 uint32_t hif_ce_history_max = HIF_CE_HISTORY_MAX; 2259 uint32_t hif_ce_count_max = CE_COUNT_MAX; 2260 2261 /* 2262 * for debug build, it will enable ce history for all ce, but for 2263 * perf build(if CONFIG_SLUB_DEBUG_ON is N), it only enable for 2264 * ce2(wmi event) & ce3(wmi cmd) history. 2265 */ 2266 #if defined(CONFIG_SLUB_DEBUG_ON) 2267 #define CE_DESC_HISTORY_BUFF_CNT CE_COUNT_MAX 2268 #define IS_CE_DEBUG_ONLY_FOR_CRIT_CE 0 2269 #else 2270 /* CE2, CE3, CE7 */ 2271 #define CE_DESC_HISTORY_BUFF_CNT 3 2272 #define IS_CE_DEBUG_ONLY_FOR_CRIT_CE (BIT(2) | BIT(3) | BIT(7)) 2273 #endif 2274 bool hif_ce_only_for_crit = IS_CE_DEBUG_ONLY_FOR_CRIT_CE; 2275 struct hif_ce_desc_event 2276 hif_ce_desc_history_buff[CE_DESC_HISTORY_BUFF_CNT][HIF_CE_HISTORY_MAX]; 2277 2278 static void 2279 __hif_ce_desc_history_log_register(struct hif_softc *scn) 2280 { 2281 qdf_ssr_driver_dump_register_region("hif_ce_desc_history_buff", 2282 hif_ce_desc_history_buff, 2283 sizeof(hif_ce_desc_history_buff)); 2284 qdf_ssr_driver_dump_register_region("hif_ce_desc_hist", 2285 &scn->hif_ce_desc_hist, 2286 sizeof(scn->hif_ce_desc_hist)); 2287 qdf_ssr_driver_dump_register_region("hif_ce_count_max", 2288 &hif_ce_count_max, 2289 sizeof(hif_ce_count_max)); 2290 qdf_ssr_driver_dump_register_region("hif_ce_history_max", 2291 &hif_ce_history_max, 2292 sizeof(hif_ce_history_max)); 2293 qdf_ssr_driver_dump_register_region("hif_ce_only_for_crit", 2294 &hif_ce_only_for_crit, 2295 sizeof(hif_ce_only_for_crit)); 2296 } 2297 2298 static void __hif_ce_desc_history_log_unregister(void) 2299 { 2300 qdf_ssr_driver_dump_unregister_region("hif_ce_only_for_crit"); 2301 qdf_ssr_driver_dump_unregister_region("hif_ce_history_max"); 2302 qdf_ssr_driver_dump_unregister_region("hif_ce_count_max"); 2303 qdf_ssr_driver_dump_unregister_region("hif_ce_desc_hist"); 2304 qdf_ssr_driver_dump_unregister_region("hif_ce_desc_history_buff"); 2305 } 2306 2307 static struct hif_ce_desc_event * 2308 hif_ce_debug_history_buf_get(struct hif_softc *scn, unsigned int ce_id) 2309 { 2310 struct ce_desc_hist *ce_hist = &scn->hif_ce_desc_hist; 2311 2312 hif_debug("get ce debug buffer ce_id %u, only_ce2/ce3=0x%lx, idx=%u", 2313 ce_id, IS_CE_DEBUG_ONLY_FOR_CRIT_CE, 2314 ce_hist->ce_id_hist_map[ce_id]); 2315 if (IS_CE_DEBUG_ONLY_FOR_CRIT_CE && 2316 (ce_id == CE_ID_2 || ce_id == CE_ID_3 || ce_id == CE_ID_7)) { 2317 uint8_t idx = ce_hist->ce_id_hist_map[ce_id]; 2318 2319 hif_ce_desc_history[ce_id] = hif_ce_desc_history_buff[idx]; 2320 } else { 2321 hif_ce_desc_history[ce_id] = 2322 hif_ce_desc_history_buff[ce_id]; 2323 } 2324 2325 return hif_ce_desc_history[ce_id]; 2326 } 2327 2328 /** 2329 * alloc_mem_ce_debug_history() - Allocate CE descriptor history 2330 * @scn: hif scn handle 2331 * @ce_id: Copy Engine Id 2332 * @src_nentries: source ce ring entries 2333 * Return: QDF_STATUS 2334 */ 2335 static QDF_STATUS 2336 alloc_mem_ce_debug_history(struct hif_softc *scn, unsigned int ce_id, 2337 uint32_t src_nentries) 2338 { 2339 struct ce_desc_hist *ce_hist = &scn->hif_ce_desc_hist; 2340 QDF_STATUS status = QDF_STATUS_SUCCESS; 2341 2342 /* For perf build, return directly for non ce2/ce3 */ 2343 if (IS_CE_DEBUG_ONLY_FOR_CRIT_CE && 2344 ce_id != CE_ID_2 && 2345 ce_id != CE_ID_3 && 2346 ce_id != CE_ID_7) { 2347 ce_hist->enable[ce_id] = false; 2348 ce_hist->data_enable[ce_id] = false; 2349 return QDF_STATUS_SUCCESS; 2350 } 2351 2352 ce_hist->hist_ev[ce_id] = hif_ce_debug_history_buf_get(scn, ce_id); 2353 ce_hist->enable[ce_id] = true; 2354 2355 if (src_nentries) { 2356 status = alloc_mem_ce_debug_hist_data(scn, ce_id); 2357 if (status != QDF_STATUS_SUCCESS) { 2358 ce_hist->enable[ce_id] = false; 2359 ce_hist->hist_ev[ce_id] = NULL; 2360 return status; 2361 } 2362 } else { 2363 ce_hist->data_enable[ce_id] = false; 2364 } 2365 2366 return QDF_STATUS_SUCCESS; 2367 } 2368 2369 /** 2370 * free_mem_ce_debug_history() - Free CE descriptor history 2371 * @scn: hif scn handle 2372 * @ce_id: Copy Engine Id 2373 * 2374 * Return: None 2375 */ 2376 static void free_mem_ce_debug_history(struct hif_softc *scn, unsigned int ce_id) 2377 { 2378 struct ce_desc_hist *ce_hist = &scn->hif_ce_desc_hist; 2379 2380 if (!ce_hist->enable[ce_id]) 2381 return; 2382 2383 ce_hist->enable[ce_id] = false; 2384 if (ce_hist->data_enable[ce_id]) { 2385 ce_hist->data_enable[ce_id] = false; 2386 free_mem_ce_debug_hist_data(scn, ce_id); 2387 } 2388 ce_hist->hist_ev[ce_id] = NULL; 2389 } 2390 #else 2391 2392 static void 2393 __hif_ce_desc_history_log_register(struct hif_softc *scn) 2394 { 2395 } 2396 2397 static void __hif_ce_desc_history_log_unregister(void) { } 2398 2399 static inline QDF_STATUS 2400 alloc_mem_ce_debug_history(struct hif_softc *scn, unsigned int CE_id, 2401 uint32_t src_nentries) 2402 { 2403 return QDF_STATUS_SUCCESS; 2404 } 2405 2406 static inline void 2407 free_mem_ce_debug_history(struct hif_softc *scn, unsigned int CE_id) { } 2408 #endif /* (HIF_CONFIG_SLUB_DEBUG_ON) || (HIF_CE_DEBUG_DATA_BUF) */ 2409 #else 2410 #if defined(HIF_CE_DEBUG_DATA_BUF) 2411 2412 static void 2413 __hif_ce_desc_history_log_register(struct hif_softc *scn) 2414 { 2415 } 2416 2417 static void __hif_ce_desc_history_log_unregister(void) { } 2418 2419 static QDF_STATUS 2420 alloc_mem_ce_debug_history(struct hif_softc *scn, unsigned int CE_id, 2421 uint32_t src_nentries) 2422 { 2423 scn->hif_ce_desc_hist.hist_ev[CE_id] = (struct hif_ce_desc_event *) 2424 qdf_mem_malloc(HIF_CE_HISTORY_MAX * sizeof(struct hif_ce_desc_event)); 2425 2426 if (!scn->hif_ce_desc_hist.hist_ev[CE_id]) { 2427 scn->hif_ce_desc_hist.enable[CE_id] = 0; 2428 return QDF_STATUS_E_NOMEM; 2429 } else { 2430 scn->hif_ce_desc_hist.enable[CE_id] = 1; 2431 return QDF_STATUS_SUCCESS; 2432 } 2433 } 2434 2435 static void free_mem_ce_debug_history(struct hif_softc *scn, unsigned int CE_id) 2436 { 2437 struct ce_desc_hist *ce_hist = &scn->hif_ce_desc_hist; 2438 struct hif_ce_desc_event *hist_ev = ce_hist->hist_ev[CE_id]; 2439 2440 if (!hist_ev) 2441 return; 2442 2443 if (ce_hist->data_enable[CE_id]) { 2444 ce_hist->data_enable[CE_id] = false; 2445 free_mem_ce_debug_hist_data(scn, CE_id); 2446 } 2447 2448 ce_hist->enable[CE_id] = false; 2449 qdf_mem_free(ce_hist->hist_ev[CE_id]); 2450 ce_hist->hist_ev[CE_id] = NULL; 2451 } 2452 2453 #else 2454 2455 static void 2456 __hif_ce_desc_history_log_register(struct hif_softc *scn) 2457 { 2458 } 2459 2460 static void __hif_ce_desc_history_log_unregister(void) { } 2461 2462 static inline QDF_STATUS 2463 alloc_mem_ce_debug_history(struct hif_softc *scn, unsigned int CE_id, 2464 uint32_t src_nentries) 2465 { 2466 return QDF_STATUS_SUCCESS; 2467 } 2468 2469 static inline void 2470 free_mem_ce_debug_history(struct hif_softc *scn, unsigned int CE_id) { } 2471 #endif /* HIF_CE_DEBUG_DATA_BUF */ 2472 #endif /* HIF_CE_DEBUG_DATA_DYNAMIC_BUF */ 2473 2474 #if defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF) 2475 /** 2476 * reset_ce_debug_history() - reset the index and ce id used for dumping the 2477 * CE records on the console using sysfs. 2478 * @scn: hif scn handle 2479 * 2480 * Return: 2481 */ 2482 static inline void reset_ce_debug_history(struct hif_softc *scn) 2483 { 2484 struct ce_desc_hist *ce_hist = &scn->hif_ce_desc_hist; 2485 /* Initialise the CE debug history sysfs interface inputs ce_id and 2486 * index. Disable data storing 2487 */ 2488 ce_hist->hist_index = 0; 2489 ce_hist->hist_id = 0; 2490 } 2491 #else /* defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF) */ 2492 static inline void reset_ce_debug_history(struct hif_softc *scn) { } 2493 #endif /*defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF) */ 2494 2495 void ce_enable_polling(void *cestate) 2496 { 2497 struct CE_state *CE_state = (struct CE_state *)cestate; 2498 2499 if (CE_state && CE_state->attr_flags & CE_ATTR_ENABLE_POLL) 2500 CE_state->timer_inited = true; 2501 } 2502 2503 void ce_disable_polling(void *cestate) 2504 { 2505 struct CE_state *CE_state = (struct CE_state *)cestate; 2506 2507 if (CE_state && CE_state->attr_flags & CE_ATTR_ENABLE_POLL) 2508 CE_state->timer_inited = false; 2509 } 2510 2511 #ifdef WLAN_FEATURE_SSR_DRIVER_DUMP 2512 #define MAX_CE_STR_LEN 50 2513 /** 2514 * ce_ring_dump_register_region() - Register CE ring with SSR dump 2515 * @CE_state: CE_state pointer 2516 * @CE_id: CE id 2517 * 2518 * Return: None 2519 */ 2520 static inline 2521 void ce_ring_dump_register_region(struct CE_state *CE_state, unsigned int CE_id) 2522 { 2523 struct CE_ring_state *ce_ring; 2524 char ce[MAX_CE_STR_LEN]; 2525 char CE_ring_state[MAX_CE_STR_LEN]; 2526 char srng[MAX_CE_STR_LEN]; 2527 2528 qdf_snprint(ce, MAX_CE_STR_LEN, "%s%d", "ce_", CE_id); 2529 qdf_ssr_driver_dump_register_region(ce, CE_state, sizeof(*CE_state)); 2530 2531 if (CE_state->status_ring) { 2532 ce_ring = CE_state->status_ring; 2533 qdf_snprint(CE_ring_state, MAX_CE_STR_LEN, 2534 "%s%s", ce, "_status_ring"); 2535 qdf_ssr_driver_dump_register_region(CE_ring_state, ce_ring, 2536 sizeof(struct CE_ring_state) 2537 ); 2538 qdf_snprint(srng, MAX_CE_STR_LEN, 2539 "%s%s", CE_ring_state, "_ctx"); 2540 qdf_ssr_driver_dump_register_region(srng, ce_ring->srng_ctx, 2541 sizeof(struct hal_srng)); 2542 } 2543 if (CE_state->dest_ring) { 2544 ce_ring = CE_state->dest_ring; 2545 qdf_snprint(CE_ring_state, MAX_CE_STR_LEN, 2546 "%s%s", ce, "_dest_ring"); 2547 qdf_ssr_driver_dump_register_region(CE_ring_state, ce_ring, 2548 sizeof(struct CE_ring_state) 2549 ); 2550 qdf_snprint(srng, MAX_CE_STR_LEN, 2551 "%s%s", CE_ring_state, "_ctx"); 2552 qdf_ssr_driver_dump_register_region(srng, ce_ring->srng_ctx, 2553 sizeof(struct hal_srng)); 2554 } 2555 if (CE_state->src_ring) { 2556 ce_ring = CE_state->src_ring; 2557 qdf_snprint(CE_ring_state, MAX_CE_STR_LEN, 2558 "%s%s", ce, "_src_ring"); 2559 qdf_ssr_driver_dump_register_region(CE_ring_state, ce_ring, 2560 sizeof(struct CE_ring_state) 2561 ); 2562 qdf_snprint(srng, MAX_CE_STR_LEN, 2563 "%s%s", CE_ring_state, "_ctx"); 2564 qdf_ssr_driver_dump_register_region(srng, ce_ring->srng_ctx, 2565 sizeof(struct hal_srng)); 2566 } 2567 } 2568 2569 /** 2570 * ce_ring_dump_unregister_region() - Unregister CE ring with SSR dump 2571 * @CE_state: CE_state pointer 2572 * @CE_id: CE id 2573 * 2574 * Return: None 2575 */ 2576 static inline void 2577 ce_ring_dump_unregister_region(struct CE_state *CE_state, unsigned int CE_id) 2578 { 2579 char ce[MAX_CE_STR_LEN]; 2580 char CE_ring_state[MAX_CE_STR_LEN]; 2581 char srng[MAX_CE_STR_LEN]; 2582 2583 qdf_snprint(ce, MAX_CE_STR_LEN, "%s%d", "ce_", CE_id); 2584 qdf_ssr_driver_dump_unregister_region(ce); 2585 if (CE_state->status_ring) { 2586 qdf_snprint(CE_ring_state, MAX_CE_STR_LEN, 2587 "%s%s", ce, "_status_ring"); 2588 qdf_snprint(srng, MAX_CE_STR_LEN, 2589 "%s%s", CE_ring_state, "_ctx"); 2590 qdf_ssr_driver_dump_unregister_region(CE_ring_state); 2591 qdf_ssr_driver_dump_unregister_region(srng); 2592 } 2593 if (CE_state->dest_ring) { 2594 qdf_snprint(CE_ring_state, MAX_CE_STR_LEN, 2595 "%s%s", ce, "_dest_ring"); 2596 qdf_snprint(srng, MAX_CE_STR_LEN, 2597 "%s%s", CE_ring_state, "_ctx"); 2598 qdf_ssr_driver_dump_unregister_region(CE_ring_state); 2599 qdf_ssr_driver_dump_unregister_region(srng); 2600 } 2601 if (CE_state->src_ring) { 2602 qdf_snprint(CE_ring_state, MAX_CE_STR_LEN, 2603 "%s%s", ce, "_src_ring"); 2604 qdf_snprint(srng, MAX_CE_STR_LEN, 2605 "%s%s", CE_ring_state, "_ctx"); 2606 qdf_ssr_driver_dump_unregister_region(CE_ring_state); 2607 qdf_ssr_driver_dump_unregister_region(srng); 2608 } 2609 } 2610 #else 2611 static inline 2612 void ce_ring_dump_register_region(struct CE_state *CE_state, unsigned int CE_id) 2613 { 2614 } 2615 2616 static inline void 2617 ce_ring_dump_unregister_region(struct CE_state *CE_state, unsigned int CE_id) 2618 { 2619 } 2620 #endif 2621 /* 2622 * Initialize a Copy Engine based on caller-supplied attributes. 2623 * This may be called once to initialize both source and destination 2624 * rings or it may be called twice for separate source and destination 2625 * initialization. It may be that only one side or the other is 2626 * initialized by software/firmware. 2627 * 2628 * This should be called during the initialization sequence before 2629 * interrupts are enabled, so we don't have to worry about thread safety. 2630 */ 2631 struct CE_handle *ce_init(struct hif_softc *scn, 2632 unsigned int CE_id, struct CE_attr *attr) 2633 { 2634 struct CE_state *CE_state; 2635 uint32_t ctrl_addr; 2636 unsigned int nentries; 2637 bool malloc_CE_state = false; 2638 bool malloc_src_ring = false; 2639 int status; 2640 QDF_STATUS mem_status = QDF_STATUS_SUCCESS; 2641 2642 QDF_ASSERT(CE_id < scn->ce_count); 2643 ctrl_addr = CE_BASE_ADDRESS(CE_id); 2644 CE_state = scn->ce_id_to_state[CE_id]; 2645 2646 if (!CE_state) { 2647 CE_state = 2648 (struct CE_state *)qdf_mem_malloc(sizeof(*CE_state)); 2649 if (!CE_state) 2650 return NULL; 2651 2652 malloc_CE_state = true; 2653 qdf_spinlock_create(&CE_state->ce_index_lock); 2654 #ifdef CE_TASKLET_SCHEDULE_ON_FULL 2655 qdf_spinlock_create(&CE_state->ce_interrupt_lock); 2656 #endif 2657 2658 CE_state->id = CE_id; 2659 CE_state->ctrl_addr = ctrl_addr; 2660 CE_state->state = CE_RUNNING; 2661 CE_state->attr_flags = attr->flags; 2662 } 2663 CE_state->scn = scn; 2664 CE_state->service = ce_engine_service_reg; 2665 2666 qdf_atomic_init(&CE_state->rx_pending); 2667 if (!attr) { 2668 /* Already initialized; caller wants the handle */ 2669 return (struct CE_handle *)CE_state; 2670 } 2671 2672 if (CE_state->src_sz_max) 2673 QDF_ASSERT(CE_state->src_sz_max == attr->src_sz_max); 2674 else 2675 CE_state->src_sz_max = attr->src_sz_max; 2676 2677 ce_init_ce_desc_event_log(scn, CE_id, 2678 attr->src_nentries + attr->dest_nentries); 2679 2680 /* source ring setup */ 2681 nentries = attr->src_nentries; 2682 if (nentries) { 2683 struct CE_ring_state *src_ring; 2684 2685 nentries = roundup_pwr2(nentries); 2686 if (CE_state->src_ring) { 2687 QDF_ASSERT(CE_state->src_ring->nentries == nentries); 2688 } else { 2689 src_ring = CE_state->src_ring = 2690 ce_alloc_ring_state(CE_state, 2691 CE_RING_SRC, 2692 nentries); 2693 if (!src_ring) { 2694 /* cannot allocate src ring. If the 2695 * CE_state is allocated locally free 2696 * CE_State and return error. 2697 */ 2698 hif_err("src ring has no mem"); 2699 if (malloc_CE_state) { 2700 /* allocated CE_state locally */ 2701 qdf_mem_free(CE_state); 2702 malloc_CE_state = false; 2703 } 2704 return NULL; 2705 } 2706 /* we can allocate src ring. Mark that the src ring is 2707 * allocated locally 2708 */ 2709 malloc_src_ring = true; 2710 2711 /* 2712 * Also allocate a shadow src ring in 2713 * regular mem to use for faster access. 2714 */ 2715 src_ring->shadow_base_unaligned = 2716 qdf_mem_malloc(nentries * 2717 sizeof(struct CE_src_desc) + 2718 CE_DESC_RING_ALIGN); 2719 if (!src_ring->shadow_base_unaligned) 2720 goto error_no_dma_mem; 2721 2722 src_ring->shadow_base = (struct CE_src_desc *) 2723 (((size_t) src_ring->shadow_base_unaligned + 2724 CE_DESC_RING_ALIGN - 1) & 2725 ~(CE_DESC_RING_ALIGN - 1)); 2726 2727 status = ce_ring_setup(scn, CE_RING_SRC, CE_id, 2728 src_ring, attr); 2729 if (status < 0) 2730 goto error_target_access; 2731 ce_ring_test_initial_indexes(CE_id, src_ring, 2732 "src_ring"); 2733 if (CE_state->attr_flags & CE_ATTR_ENABLE_POLL) { 2734 qdf_timer_init(scn->qdf_dev, 2735 &CE_state->poll_timer, 2736 ce_poll_timeout, 2737 CE_state, 2738 QDF_TIMER_TYPE_WAKE_APPS); 2739 ce_enable_polling(CE_state); 2740 qdf_timer_mod(&CE_state->poll_timer, 2741 CE_POLL_TIMEOUT); 2742 } 2743 } 2744 } 2745 2746 /* destination ring setup */ 2747 nentries = attr->dest_nentries; 2748 if (nentries) { 2749 struct CE_ring_state *dest_ring; 2750 2751 nentries = roundup_pwr2(nentries); 2752 if (CE_state->dest_ring) { 2753 QDF_ASSERT(CE_state->dest_ring->nentries == nentries); 2754 } else { 2755 dest_ring = CE_state->dest_ring = 2756 ce_alloc_ring_state(CE_state, 2757 CE_RING_DEST, 2758 nentries); 2759 if (!dest_ring) { 2760 /* cannot allocate dst ring. If the CE_state 2761 * or src ring is allocated locally free 2762 * CE_State and src ring and return error. 2763 */ 2764 hif_err("dest ring has no mem"); 2765 goto error_no_dma_mem; 2766 } 2767 2768 status = ce_ring_setup(scn, CE_RING_DEST, CE_id, 2769 dest_ring, attr); 2770 if (status < 0) 2771 goto error_target_access; 2772 2773 ce_ring_test_initial_indexes(CE_id, dest_ring, 2774 "dest_ring"); 2775 2776 /* For srng based target, init status ring here */ 2777 if (ce_srng_based(CE_state->scn)) { 2778 CE_state->status_ring = 2779 ce_alloc_ring_state(CE_state, 2780 CE_RING_STATUS, 2781 nentries); 2782 if (!CE_state->status_ring) { 2783 /*Allocation failed. Cleanup*/ 2784 qdf_mem_free(CE_state->dest_ring); 2785 if (malloc_src_ring) { 2786 qdf_mem_free 2787 (CE_state->src_ring); 2788 CE_state->src_ring = NULL; 2789 malloc_src_ring = false; 2790 } 2791 if (malloc_CE_state) { 2792 /* allocated CE_state locally */ 2793 scn->ce_id_to_state[CE_id] = 2794 NULL; 2795 qdf_mem_free(CE_state); 2796 malloc_CE_state = false; 2797 } 2798 2799 return NULL; 2800 } 2801 2802 status = ce_ring_setup(scn, CE_RING_STATUS, 2803 CE_id, CE_state->status_ring, 2804 attr); 2805 if (status < 0) 2806 goto error_target_access; 2807 2808 } 2809 2810 /* epping */ 2811 /* poll timer */ 2812 if (CE_state->attr_flags & CE_ATTR_ENABLE_POLL) { 2813 qdf_timer_init(scn->qdf_dev, 2814 &CE_state->poll_timer, 2815 ce_poll_timeout, 2816 CE_state, 2817 QDF_TIMER_TYPE_WAKE_APPS); 2818 ce_enable_polling(CE_state); 2819 qdf_timer_mod(&CE_state->poll_timer, 2820 CE_POLL_TIMEOUT); 2821 } 2822 } 2823 } 2824 2825 if (!ce_srng_based(scn)) { 2826 /* Enable CE error interrupts */ 2827 if (Q_TARGET_ACCESS_BEGIN(scn) < 0) 2828 goto error_target_access; 2829 CE_ERROR_INTR_ENABLE(scn, ctrl_addr); 2830 if (Q_TARGET_ACCESS_END(scn) < 0) 2831 goto error_target_access; 2832 } 2833 2834 qdf_create_work(scn->qdf_dev, &CE_state->oom_allocation_work, 2835 ce_oom_recovery, CE_state); 2836 2837 /* update the htt_data attribute */ 2838 ce_mark_datapath(CE_state); 2839 scn->ce_id_to_state[CE_id] = CE_state; 2840 2841 ce_ring_dump_register_region(CE_state, CE_id); 2842 2843 mem_status = alloc_mem_ce_debug_history(scn, CE_id, attr->src_nentries); 2844 if (mem_status != QDF_STATUS_SUCCESS) 2845 goto error_target_access; 2846 2847 ce_update_msi_batch_intr_flags(CE_state); 2848 ce_update_wrt_idx_offset(scn, CE_state, 2849 attr->src_nentries ? 2850 CE_RING_SRC : CE_RING_DEST); 2851 2852 return (struct CE_handle *)CE_state; 2853 2854 error_target_access: 2855 error_no_dma_mem: 2856 ce_fini((struct CE_handle *)CE_state); 2857 return NULL; 2858 } 2859 2860 void hif_ce_desc_history_log_register(struct hif_softc *scn) 2861 { 2862 __hif_ce_desc_history_log_register(scn); 2863 } 2864 2865 /** 2866 * hif_is_polled_mode_enabled - API to query if polling is enabled on all CEs 2867 * @hif_ctx: HIF Context 2868 * 2869 * API to check if polling is enabled on all CEs. Returns true when polling 2870 * is enabled on all CEs. 2871 * 2872 * Return: bool 2873 */ 2874 bool hif_is_polled_mode_enabled(struct hif_opaque_softc *hif_ctx) 2875 { 2876 struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); 2877 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 2878 struct CE_attr *attr; 2879 int id; 2880 2881 for (id = 0; id < scn->ce_count; id++) { 2882 attr = &hif_state->host_ce_config[id]; 2883 if (attr && (attr->dest_nentries) && 2884 !(attr->flags & CE_ATTR_ENABLE_POLL)) 2885 return false; 2886 } 2887 return true; 2888 } 2889 qdf_export_symbol(hif_is_polled_mode_enabled); 2890 2891 static int hif_get_pktlog_ce_num(struct hif_softc *scn) 2892 { 2893 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 2894 int id; 2895 2896 for (id = 0; id < hif_state->sz_tgt_svc_map; id++) { 2897 if (hif_state->tgt_svc_map[id].service_id == PACKET_LOG_SVC) 2898 return hif_state->tgt_svc_map[id].pipenum; 2899 } 2900 return -EINVAL; 2901 } 2902 2903 #ifdef WLAN_FEATURE_CE_RX_BUFFER_REUSE 2904 2905 #define HIF_CE_RX_NBUF_WMI_POOL_SIZE 32 2906 2907 static qdf_nbuf_t hif_ce_rx_nbuf_alloc(struct hif_softc *scn, uint8_t ce_id) 2908 { 2909 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 2910 struct HIF_CE_pipe_info *pipe_info = &hif_state->pipe_info[ce_id]; 2911 qdf_nbuf_t nbuf; 2912 2913 nbuf = wbuff_buff_get(scn->wbuff_handle, ce_id, 0, __func__, 2914 __LINE__); 2915 if (!nbuf) 2916 nbuf = qdf_nbuf_alloc(scn->qdf_dev, pipe_info->buf_sz, 2917 0, 4, false); 2918 2919 if (!nbuf) 2920 return NULL; 2921 2922 return nbuf; 2923 } 2924 2925 static void hif_ce_rx_nbuf_free(qdf_nbuf_t nbuf) 2926 { 2927 nbuf = wbuff_buff_put(nbuf); 2928 if (nbuf) 2929 qdf_nbuf_free(nbuf); 2930 } 2931 2932 static int 2933 hif_calc_wbuff_pool_size(struct hif_softc *scn, struct CE_state *ce_state) 2934 { 2935 int ul_is_polled, dl_is_polled; 2936 bool is_wmi_svc, wmi_diag_svc; 2937 uint8_t ul_pipe, dl_pipe; 2938 int pool_size; 2939 int status; 2940 int ce_id; 2941 2942 if (!ce_state) 2943 return 0; 2944 2945 ce_id = ce_state->id; 2946 2947 status = hif_map_service_to_pipe(&scn->osc, WMI_CONTROL_SVC, 2948 &ul_pipe, &dl_pipe, 2949 &ul_is_polled, &dl_is_polled); 2950 is_wmi_svc = !status && (dl_pipe == ce_id); 2951 2952 status = hif_map_service_to_pipe(GET_HIF_OPAQUE_HDL(scn), 2953 WMI_CONTROL_DIAG_SVC, 2954 &ul_pipe, &dl_pipe, 2955 &ul_is_polled, &dl_is_polled); 2956 wmi_diag_svc = !status; 2957 2958 if (is_wmi_svc && !wmi_diag_svc) 2959 pool_size = ce_state->dest_ring->nentries + 2960 HIF_CE_RX_NBUF_WMI_POOL_SIZE; 2961 else if (is_wmi_svc && wmi_diag_svc) 2962 pool_size = ce_state->dest_ring->nentries + 2963 HIF_CE_RX_NBUF_WMI_POOL_SIZE / 2; 2964 else if (!is_wmi_svc && wmi_diag_svc && ce_id == dl_pipe) 2965 pool_size = ce_state->dest_ring->nentries + 2966 HIF_CE_RX_NBUF_WMI_POOL_SIZE / 2; 2967 else 2968 pool_size = ce_state->dest_ring->nentries; 2969 2970 return pool_size; 2971 } 2972 2973 static void hif_ce_rx_wbuff_register(struct hif_softc *scn) 2974 { 2975 struct wbuff_alloc_request wbuff_alloc[CE_COUNT_MAX] = {0}; 2976 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 2977 struct HIF_CE_pipe_info *pipe_info; 2978 struct CE_state *ce_state; 2979 int ce_id; 2980 2981 for (ce_id = 0; ce_id < scn->ce_count; ce_id++) { 2982 pipe_info = &hif_state->pipe_info[ce_id]; 2983 ce_state = scn->ce_id_to_state[ce_id]; 2984 2985 if (!pipe_info->buf_sz) 2986 continue; 2987 2988 /* Only RX CEs need WBUFF registration. recv_bufs_needed 2989 * contains valid count for RX CEs during init time. 2990 */ 2991 if (!atomic_read(&pipe_info->recv_bufs_needed)) 2992 continue; 2993 2994 wbuff_alloc[ce_id].pool_id = ce_id; 2995 wbuff_alloc[ce_id].buffer_size = pipe_info->buf_sz; 2996 wbuff_alloc[ce_id].pool_size = 2997 hif_calc_wbuff_pool_size(scn, ce_state); 2998 } 2999 3000 scn->wbuff_handle = 3001 wbuff_module_register(wbuff_alloc, CE_COUNT_MAX, 0, 4, 3002 WBUFF_MODULE_CE_RX); 3003 } 3004 3005 static void hif_ce_rx_wbuff_deregister(struct hif_softc *scn) 3006 { 3007 wbuff_module_deregister(scn->wbuff_handle); 3008 scn->wbuff_handle = NULL; 3009 } 3010 #else 3011 static inline qdf_nbuf_t 3012 hif_ce_rx_nbuf_alloc(struct hif_softc *scn, uint8_t ce_id) 3013 { 3014 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 3015 struct HIF_CE_pipe_info *pipe_info = &hif_state->pipe_info[ce_id]; 3016 3017 return qdf_nbuf_alloc(scn->qdf_dev, pipe_info->buf_sz, 0, 4, false); 3018 } 3019 3020 static inline void hif_ce_rx_nbuf_free(qdf_nbuf_t nbuf) 3021 { 3022 return qdf_nbuf_free(nbuf); 3023 } 3024 3025 static inline void hif_ce_rx_wbuff_register(struct hif_softc *scn) 3026 { 3027 } 3028 3029 static inline void hif_ce_rx_wbuff_deregister(struct hif_softc *scn) 3030 { 3031 } 3032 #endif /* WLAN_FEATURE_CE_RX_BUFFER_REUSE */ 3033 3034 #ifdef WLAN_FEATURE_FASTPATH 3035 /** 3036 * hif_enable_fastpath() - Update that we have enabled fastpath mode 3037 * @hif_ctx: HIF context 3038 * 3039 * For use in data path 3040 * 3041 * Return: void 3042 */ 3043 void hif_enable_fastpath(struct hif_opaque_softc *hif_ctx) 3044 { 3045 struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); 3046 3047 if (ce_srng_based(scn)) { 3048 hif_warn("srng rings do not support fastpath"); 3049 return; 3050 } 3051 hif_debug("Enabling fastpath mode"); 3052 scn->fastpath_mode_on = true; 3053 } 3054 3055 /** 3056 * hif_is_fastpath_mode_enabled - API to query if fasthpath mode is enabled 3057 * @hif_ctx: HIF Context 3058 * 3059 * For use in data path to skip HTC 3060 * 3061 * Return: bool 3062 */ 3063 bool hif_is_fastpath_mode_enabled(struct hif_opaque_softc *hif_ctx) 3064 { 3065 struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); 3066 3067 return scn->fastpath_mode_on; 3068 } 3069 3070 /** 3071 * hif_get_ce_handle - API to get CE handle for FastPath mode 3072 * @hif_ctx: HIF Context 3073 * @id: CopyEngine Id 3074 * 3075 * API to return CE handle for fastpath mode 3076 * 3077 * Return: void 3078 */ 3079 void *hif_get_ce_handle(struct hif_opaque_softc *hif_ctx, int id) 3080 { 3081 struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); 3082 3083 return scn->ce_id_to_state[id]; 3084 } 3085 qdf_export_symbol(hif_get_ce_handle); 3086 3087 /** 3088 * ce_h2t_tx_ce_cleanup() - Place holder function for H2T CE cleanup. 3089 * No processing is required inside this function. 3090 * @ce_hdl: Cope engine handle 3091 * Using an assert, this function makes sure that, 3092 * the TX CE has been processed completely. 3093 * 3094 * This is called while dismantling CE structures. No other thread 3095 * should be using these structures while dismantling is occurring 3096 * therefore no locking is needed. 3097 * 3098 * Return: none 3099 */ 3100 void ce_h2t_tx_ce_cleanup(struct CE_handle *ce_hdl) 3101 { 3102 struct CE_state *ce_state = (struct CE_state *)ce_hdl; 3103 struct CE_ring_state *src_ring = ce_state->src_ring; 3104 struct hif_softc *sc = ce_state->scn; 3105 uint32_t sw_index, write_index; 3106 3107 if (hif_is_nss_wifi_enabled(sc)) 3108 return; 3109 3110 if (sc->fastpath_mode_on && ce_state->htt_tx_data) { 3111 hif_debug("Fastpath mode ON, Cleaning up HTT Tx CE"); 3112 sw_index = src_ring->sw_index; 3113 write_index = src_ring->sw_index; 3114 3115 /* At this point Tx CE should be clean */ 3116 qdf_assert_always(sw_index == write_index); 3117 } 3118 } 3119 3120 /** 3121 * ce_t2h_msg_ce_cleanup() - Cleanup buffers on the t2h datapath msg queue. 3122 * @ce_hdl: Handle to CE 3123 * 3124 * These buffers are never allocated on the fly, but 3125 * are allocated only once during HIF start and freed 3126 * only once during HIF stop. 3127 * NOTE: 3128 * The assumption here is there is no in-flight DMA in progress 3129 * currently, so that buffers can be freed up safely. 3130 * 3131 * Return: NONE 3132 */ 3133 void ce_t2h_msg_ce_cleanup(struct CE_handle *ce_hdl) 3134 { 3135 struct CE_state *ce_state = (struct CE_state *)ce_hdl; 3136 struct CE_ring_state *dst_ring = ce_state->dest_ring; 3137 qdf_nbuf_t nbuf; 3138 int i; 3139 3140 if (ce_state->scn->fastpath_mode_on == false) 3141 return; 3142 3143 if (!ce_state->htt_rx_data) 3144 return; 3145 3146 /* 3147 * when fastpath_mode is on and for datapath CEs. Unlike other CE's, 3148 * this CE is completely full: does not leave one blank space, to 3149 * distinguish between empty queue & full queue. So free all the 3150 * entries. 3151 */ 3152 for (i = 0; i < dst_ring->nentries; i++) { 3153 nbuf = dst_ring->per_transfer_context[i]; 3154 3155 /* 3156 * The reasons for doing this check are: 3157 * 1) Protect against calling cleanup before allocating buffers 3158 * 2) In a corner case, FASTPATH_mode_on may be set, but we 3159 * could have a partially filled ring, because of a memory 3160 * allocation failure in the middle of allocating ring. 3161 * This check accounts for that case, checking 3162 * fastpath_mode_on flag or started flag would not have 3163 * covered that case. This is not in performance path, 3164 * so OK to do this. 3165 */ 3166 if (nbuf) { 3167 qdf_nbuf_unmap_single(ce_state->scn->qdf_dev, nbuf, 3168 QDF_DMA_FROM_DEVICE); 3169 hif_ce_rx_nbuf_free(nbuf); 3170 } 3171 } 3172 } 3173 3174 /** 3175 * hif_update_fastpath_recv_bufs_cnt() - Increments the Rx buf count by 1 3176 * @scn: HIF handle 3177 * 3178 * Datapath Rx CEs are special case, where we reuse all the message buffers. 3179 * Hence we have to post all the entries in the pipe, even, in the beginning 3180 * unlike for other CE pipes where one less than dest_nentries are filled in 3181 * the beginning. 3182 * 3183 * Return: None 3184 */ 3185 static void hif_update_fastpath_recv_bufs_cnt(struct hif_softc *scn) 3186 { 3187 int pipe_num; 3188 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 3189 3190 if (scn->fastpath_mode_on == false) 3191 return; 3192 3193 for (pipe_num = 0; pipe_num < scn->ce_count; pipe_num++) { 3194 struct HIF_CE_pipe_info *pipe_info = 3195 &hif_state->pipe_info[pipe_num]; 3196 struct CE_state *ce_state = 3197 scn->ce_id_to_state[pipe_info->pipe_num]; 3198 3199 if (ce_state->htt_rx_data) 3200 atomic_inc(&pipe_info->recv_bufs_needed); 3201 } 3202 } 3203 #else 3204 static inline void hif_update_fastpath_recv_bufs_cnt(struct hif_softc *scn) 3205 { 3206 } 3207 3208 static inline bool ce_is_fastpath_enabled(struct hif_softc *scn) 3209 { 3210 return false; 3211 } 3212 #endif /* WLAN_FEATURE_FASTPATH */ 3213 3214 void ce_fini(struct CE_handle *copyeng) 3215 { 3216 struct CE_state *CE_state = (struct CE_state *)copyeng; 3217 unsigned int CE_id = CE_state->id; 3218 struct hif_softc *scn = CE_state->scn; 3219 uint32_t desc_size; 3220 3221 bool inited = CE_state->timer_inited; 3222 CE_state->state = CE_UNUSED; 3223 scn->ce_id_to_state[CE_id] = NULL; 3224 /* Set the flag to false first to stop processing in ce_poll_timeout */ 3225 ce_disable_polling(CE_state); 3226 3227 qdf_lro_deinit(CE_state->lro_data); 3228 3229 ce_ring_dump_unregister_region(CE_state, CE_id); 3230 3231 if (CE_state->src_ring) { 3232 /* Cleanup the datapath Tx ring */ 3233 ce_h2t_tx_ce_cleanup(copyeng); 3234 3235 desc_size = ce_get_desc_size(scn, CE_RING_SRC); 3236 if (CE_state->src_ring->shadow_base_unaligned) 3237 qdf_mem_free(CE_state->src_ring->shadow_base_unaligned); 3238 if (CE_state->src_ring->base_addr_owner_space_unaligned) 3239 ce_free_desc_ring(scn, CE_state->id, 3240 CE_state->src_ring, 3241 desc_size); 3242 ce_srng_cleanup(scn, CE_state, CE_RING_SRC); 3243 qdf_mem_free(CE_state->src_ring); 3244 } 3245 if (CE_state->dest_ring) { 3246 /* Cleanup the datapath Rx ring */ 3247 ce_t2h_msg_ce_cleanup(copyeng); 3248 3249 desc_size = ce_get_desc_size(scn, CE_RING_DEST); 3250 if (CE_state->dest_ring->base_addr_owner_space_unaligned) 3251 ce_free_desc_ring(scn, CE_state->id, 3252 CE_state->dest_ring, 3253 desc_size); 3254 ce_srng_cleanup(scn, CE_state, CE_RING_DEST); 3255 qdf_mem_free(CE_state->dest_ring); 3256 3257 /* epping */ 3258 if (inited) { 3259 qdf_timer_free(&CE_state->poll_timer); 3260 } 3261 } 3262 if ((ce_srng_based(CE_state->scn)) && (CE_state->status_ring)) { 3263 /* Cleanup the datapath Tx ring */ 3264 ce_h2t_tx_ce_cleanup(copyeng); 3265 3266 if (CE_state->status_ring->shadow_base_unaligned) 3267 qdf_mem_free( 3268 CE_state->status_ring->shadow_base_unaligned); 3269 3270 desc_size = ce_get_desc_size(scn, CE_RING_STATUS); 3271 if (CE_state->status_ring->base_addr_owner_space_unaligned) 3272 ce_free_desc_ring(scn, CE_state->id, 3273 CE_state->status_ring, 3274 desc_size); 3275 ce_srng_cleanup(scn, CE_state, CE_RING_STATUS); 3276 qdf_mem_free(CE_state->status_ring); 3277 } 3278 3279 free_mem_ce_debug_history(scn, CE_id); 3280 reset_ce_debug_history(scn); 3281 ce_deinit_ce_desc_event_log(scn, CE_id); 3282 3283 qdf_spinlock_destroy(&CE_state->ce_index_lock); 3284 #ifdef CE_TASKLET_SCHEDULE_ON_FULL 3285 qdf_spinlock_destroy(&CE_state->ce_interrupt_lock); 3286 #endif 3287 qdf_mem_free(CE_state); 3288 } 3289 3290 void hif_ce_desc_history_log_unregister(void) 3291 { 3292 __hif_ce_desc_history_log_unregister(); 3293 } 3294 3295 void hif_detach_htc(struct hif_opaque_softc *hif_ctx) 3296 { 3297 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(hif_ctx); 3298 3299 qdf_mem_zero(&hif_state->msg_callbacks_pending, 3300 sizeof(hif_state->msg_callbacks_pending)); 3301 qdf_mem_zero(&hif_state->msg_callbacks_current, 3302 sizeof(hif_state->msg_callbacks_current)); 3303 } 3304 3305 /* Send the first nbytes bytes of the buffer */ 3306 QDF_STATUS 3307 hif_send_head(struct hif_opaque_softc *hif_ctx, 3308 uint8_t pipe, unsigned int transfer_id, unsigned int nbytes, 3309 qdf_nbuf_t nbuf, unsigned int data_attr) 3310 { 3311 struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); 3312 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(hif_ctx); 3313 struct HIF_CE_pipe_info *pipe_info = &(hif_state->pipe_info[pipe]); 3314 struct CE_handle *ce_hdl = pipe_info->ce_hdl; 3315 int bytes = nbytes, nfrags = 0; 3316 struct ce_sendlist sendlist; 3317 int i = 0; 3318 QDF_STATUS status; 3319 unsigned int mux_id = 0; 3320 3321 if (nbytes > qdf_nbuf_len(nbuf)) { 3322 hif_err("nbytes: %d nbuf_len: %d", nbytes, 3323 (uint32_t)qdf_nbuf_len(nbuf)); 3324 QDF_ASSERT(0); 3325 } 3326 3327 transfer_id = 3328 (mux_id & MUX_ID_MASK) | 3329 (transfer_id & TRANSACTION_ID_MASK); 3330 data_attr &= DESC_DATA_FLAG_MASK; 3331 /* 3332 * The common case involves sending multiple fragments within a 3333 * single download (the tx descriptor and the tx frame header). 3334 * So, optimize for the case of multiple fragments by not even 3335 * checking whether it's necessary to use a sendlist. 3336 * The overhead of using a sendlist for a single buffer download 3337 * is not a big deal, since it happens rarely (for WMI messages). 3338 */ 3339 ce_sendlist_init(&sendlist); 3340 do { 3341 qdf_dma_addr_t frag_paddr; 3342 int frag_bytes; 3343 3344 frag_paddr = qdf_nbuf_get_frag_paddr(nbuf, nfrags); 3345 frag_bytes = qdf_nbuf_get_frag_len(nbuf, nfrags); 3346 /* 3347 * Clear the packet offset for all but the first CE desc. 3348 */ 3349 if (i++ > 0) 3350 data_attr &= ~CE_DESC_PKT_OFFSET_BIT_M; 3351 3352 status = ce_sendlist_buf_add(&sendlist, frag_paddr, 3353 frag_bytes > 3354 bytes ? bytes : frag_bytes, 3355 qdf_nbuf_get_frag_is_wordstream 3356 (nbuf, 3357 nfrags) ? 0 : 3358 CE_SEND_FLAG_SWAP_DISABLE, 3359 data_attr); 3360 if (status != QDF_STATUS_SUCCESS) { 3361 hif_err("frag_num: %d larger than limit (status=%d)", 3362 nfrags, status); 3363 return status; 3364 } 3365 bytes -= frag_bytes; 3366 nfrags++; 3367 } while (bytes > 0); 3368 3369 /* Make sure we have resources to handle this request */ 3370 qdf_spin_lock_bh(&pipe_info->completion_freeq_lock); 3371 if (pipe_info->num_sends_allowed < nfrags) { 3372 qdf_spin_unlock_bh(&pipe_info->completion_freeq_lock); 3373 ce_pkt_error_count_incr(hif_state, HIF_PIPE_NO_RESOURCE); 3374 return QDF_STATUS_E_RESOURCES; 3375 } 3376 pipe_info->num_sends_allowed -= nfrags; 3377 qdf_spin_unlock_bh(&pipe_info->completion_freeq_lock); 3378 3379 if (qdf_unlikely(!ce_hdl)) { 3380 hif_err("CE handle is null"); 3381 return A_ERROR; 3382 } 3383 3384 QDF_NBUF_UPDATE_TX_PKT_COUNT(nbuf, QDF_NBUF_TX_PKT_HIF); 3385 DPTRACE(qdf_dp_trace(nbuf, QDF_DP_TRACE_HIF_PACKET_PTR_RECORD, 3386 QDF_TRACE_DEFAULT_PDEV_ID, qdf_nbuf_data_addr(nbuf), 3387 sizeof(qdf_nbuf_data(nbuf)), QDF_TX)); 3388 status = ce_sendlist_send(ce_hdl, nbuf, &sendlist, transfer_id); 3389 QDF_ASSERT(status == QDF_STATUS_SUCCESS); 3390 3391 return status; 3392 } 3393 3394 void hif_send_complete_check(struct hif_opaque_softc *hif_ctx, uint8_t pipe, 3395 int force) 3396 { 3397 struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); 3398 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(hif_ctx); 3399 3400 if (!force) { 3401 int resources; 3402 /* 3403 * Decide whether to actually poll for completions, or just 3404 * wait for a later chance. If there seem to be plenty of 3405 * resources left, then just wait, since checking involves 3406 * reading a CE register, which is a relatively expensive 3407 * operation. 3408 */ 3409 resources = hif_get_free_queue_number(hif_ctx, pipe); 3410 /* 3411 * If at least 50% of the total resources are still available, 3412 * don't bother checking again yet. 3413 */ 3414 if (resources > (hif_state->host_ce_config[pipe].src_nentries >> 3415 1)) 3416 return; 3417 } 3418 #ifdef ATH_11AC_TXCOMPACT 3419 ce_per_engine_servicereap(scn, pipe); 3420 #else 3421 ce_per_engine_service(scn, pipe); 3422 #endif 3423 } 3424 3425 #ifdef CUSTOM_CB_SCHEDULER_SUPPORT 3426 QDF_STATUS 3427 hif_register_ce_custom_cb(struct hif_opaque_softc *hif_ctx, uint8_t pipe, 3428 void (*custom_cb)(void *), void *custom_cb_context) 3429 { 3430 struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); 3431 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 3432 struct HIF_CE_pipe_info *pipe_info; 3433 3434 if (pipe >= CE_COUNT_MAX) 3435 return QDF_STATUS_E_INVAL; 3436 3437 pipe_info = &hif_state->pipe_info[pipe]; 3438 ce_register_custom_cb(pipe_info->ce_hdl, custom_cb, custom_cb_context); 3439 3440 return QDF_STATUS_SUCCESS; 3441 } 3442 3443 QDF_STATUS 3444 hif_unregister_ce_custom_cb(struct hif_opaque_softc *hif_ctx, uint8_t pipe) 3445 { 3446 struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); 3447 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 3448 struct HIF_CE_pipe_info *pipe_info; 3449 3450 if (pipe >= CE_COUNT_MAX) 3451 return QDF_STATUS_E_INVAL; 3452 3453 pipe_info = &hif_state->pipe_info[pipe]; 3454 ce_unregister_custom_cb(pipe_info->ce_hdl); 3455 3456 return QDF_STATUS_SUCCESS; 3457 } 3458 3459 QDF_STATUS 3460 hif_enable_ce_custom_cb(struct hif_opaque_softc *hif_ctx, uint8_t pipe) 3461 { 3462 struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); 3463 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 3464 struct HIF_CE_pipe_info *pipe_info; 3465 3466 if (pipe >= CE_COUNT_MAX) 3467 return QDF_STATUS_E_INVAL; 3468 3469 pipe_info = &hif_state->pipe_info[pipe]; 3470 ce_enable_custom_cb(pipe_info->ce_hdl); 3471 ce_dispatch_interrupt(pipe, &hif_state->tasklets[pipe]); 3472 3473 return QDF_STATUS_SUCCESS; 3474 } 3475 3476 QDF_STATUS 3477 hif_disable_ce_custom_cb(struct hif_opaque_softc *hif_ctx, uint8_t pipe) 3478 { 3479 struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); 3480 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 3481 struct HIF_CE_pipe_info *pipe_info; 3482 3483 if (pipe >= CE_COUNT_MAX) 3484 return QDF_STATUS_E_INVAL; 3485 3486 pipe_info = &hif_state->pipe_info[pipe]; 3487 ce_disable_custom_cb(pipe_info->ce_hdl); 3488 3489 return QDF_STATUS_SUCCESS; 3490 } 3491 #endif /* CUSTOM_CB_SCHEDULER_SUPPORT */ 3492 3493 #if defined(CE_TASKLET_SCHEDULE_ON_FULL) && defined(CE_TASKLET_DEBUG_ENABLE) 3494 #define CE_RING_FULL_THRESHOLD_TIME 3000000 3495 #define CE_RING_FULL_THRESHOLD 1024 3496 /* This function is called from htc_send path. If there is no resourse to send 3497 * packet via HTC, then check if interrupts are not processed from that 3498 * CE for last 3 seconds. If so, schedule a tasklet to reap available entries. 3499 * Also if Queue has reached 1024 entries within 3 seconds, then also schedule 3500 * tasklet. 3501 */ 3502 void hif_schedule_ce_tasklet(struct hif_opaque_softc *hif_ctx, uint8_t pipe) 3503 { 3504 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(hif_ctx); 3505 int64_t diff_time = qdf_get_log_timestamp_usecs() - 3506 hif_state->stats.tasklet_sched_entry_ts[pipe]; 3507 3508 hif_state->stats.ce_ring_full_count[pipe]++; 3509 3510 if (diff_time >= CE_RING_FULL_THRESHOLD_TIME || 3511 hif_state->stats.ce_ring_full_count[pipe] >= 3512 CE_RING_FULL_THRESHOLD) { 3513 hif_state->stats.ce_ring_full_count[pipe] = 0; 3514 hif_state->stats.ce_manual_tasklet_schedule_count[pipe]++; 3515 hif_state->stats.ce_last_manual_tasklet_schedule_ts[pipe] = 3516 qdf_get_log_timestamp_usecs(); 3517 ce_dispatch_interrupt(pipe, &hif_state->tasklets[pipe]); 3518 } 3519 } 3520 #else 3521 void hif_schedule_ce_tasklet(struct hif_opaque_softc *hif_ctx, uint8_t pipe) 3522 { 3523 } 3524 #endif 3525 3526 uint16_t 3527 hif_get_free_queue_number(struct hif_opaque_softc *hif_ctx, uint8_t pipe) 3528 { 3529 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(hif_ctx); 3530 struct HIF_CE_pipe_info *pipe_info = &(hif_state->pipe_info[pipe]); 3531 uint16_t rv; 3532 3533 qdf_spin_lock_bh(&pipe_info->completion_freeq_lock); 3534 rv = pipe_info->num_sends_allowed; 3535 qdf_spin_unlock_bh(&pipe_info->completion_freeq_lock); 3536 return rv; 3537 } 3538 3539 /* Called by lower (CE) layer when a send to Target completes. */ 3540 static void 3541 hif_pci_ce_send_done(struct CE_handle *copyeng, void *ce_context, 3542 void *transfer_context, qdf_dma_addr_t CE_data, 3543 unsigned int nbytes, unsigned int transfer_id, 3544 unsigned int sw_index, unsigned int hw_index, 3545 unsigned int toeplitz_hash_result) 3546 { 3547 struct HIF_CE_pipe_info *pipe_info = 3548 (struct HIF_CE_pipe_info *)ce_context; 3549 unsigned int sw_idx = sw_index, hw_idx = hw_index; 3550 struct hif_msg_callbacks *msg_callbacks = 3551 &pipe_info->pipe_callbacks; 3552 3553 do { 3554 /* 3555 * The upper layer callback will be triggered 3556 * when last fragment is complteted. 3557 */ 3558 if (transfer_context != CE_SENDLIST_ITEM_CTXT) 3559 msg_callbacks->txCompletionHandler( 3560 msg_callbacks->Context, 3561 transfer_context, transfer_id, 3562 toeplitz_hash_result); 3563 3564 qdf_spin_lock_bh(&pipe_info->completion_freeq_lock); 3565 pipe_info->num_sends_allowed++; 3566 qdf_spin_unlock_bh(&pipe_info->completion_freeq_lock); 3567 } while (ce_completed_send_next(copyeng, 3568 &ce_context, &transfer_context, 3569 &CE_data, &nbytes, &transfer_id, 3570 &sw_idx, &hw_idx, 3571 &toeplitz_hash_result) == QDF_STATUS_SUCCESS); 3572 } 3573 3574 /** 3575 * hif_ce_do_recv(): send message from copy engine to upper layers 3576 * @msg_callbacks: structure containing callback and callback context 3577 * @netbuf: skb containing message 3578 * @nbytes: number of bytes in the message 3579 * @pipe_info: used for the pipe_number info 3580 * 3581 * Checks the packet length, configures the length in the netbuff, 3582 * and calls the upper layer callback. 3583 * 3584 * return: None 3585 */ 3586 static inline void hif_ce_do_recv(struct hif_msg_callbacks *msg_callbacks, 3587 qdf_nbuf_t netbuf, int nbytes, 3588 struct HIF_CE_pipe_info *pipe_info) { 3589 if (nbytes <= pipe_info->buf_sz) { 3590 qdf_nbuf_set_pktlen(netbuf, nbytes); 3591 msg_callbacks-> 3592 rxCompletionHandler(msg_callbacks->Context, 3593 netbuf, pipe_info->pipe_num); 3594 } else { 3595 hif_err("Invalid Rx msg buf: %pK nbytes: %d", netbuf, nbytes); 3596 hif_ce_rx_nbuf_free(netbuf); 3597 } 3598 } 3599 3600 #ifdef WLAN_FEATURE_WMI_DIAG_OVER_CE7 3601 /** 3602 * hif_ce_rtpm_mark_last_busy() - record and mark last busy for RTPM 3603 * @scn: hif_softc pointer. 3604 * @ce_id: ce ID 3605 * 3606 * Return: None 3607 */ 3608 static inline void 3609 hif_ce_rtpm_mark_last_busy(struct hif_softc *scn, uint32_t ce_id) 3610 { 3611 /* do NOT mark last busy for diag event, to avoid impacting RTPM */ 3612 if (ce_id == CE_ID_7) 3613 return; 3614 3615 hif_rtpm_record_ce_last_busy_evt(scn, ce_id); 3616 hif_rtpm_mark_last_busy(HIF_RTPM_ID_CE); 3617 } 3618 #else 3619 static inline void 3620 hif_ce_rtpm_mark_last_busy(struct hif_softc *scn, uint32_t ce_id) 3621 { 3622 hif_rtpm_record_ce_last_busy_evt(scn, ce_id); 3623 hif_rtpm_mark_last_busy(HIF_RTPM_ID_CE); 3624 } 3625 #endif 3626 3627 /* Called by lower (CE) layer when data is received from the Target. */ 3628 static void 3629 hif_pci_ce_recv_data(struct CE_handle *copyeng, void *ce_context, 3630 void *transfer_context, qdf_dma_addr_t CE_data, 3631 unsigned int nbytes, unsigned int transfer_id, 3632 unsigned int flags) 3633 { 3634 struct HIF_CE_pipe_info *pipe_info = 3635 (struct HIF_CE_pipe_info *)ce_context; 3636 struct HIF_CE_state *hif_state = pipe_info->HIF_CE_state; 3637 struct CE_state *ce_state = (struct CE_state *) copyeng; 3638 struct hif_softc *scn = HIF_GET_SOFTC(hif_state); 3639 struct hif_msg_callbacks *msg_callbacks = &pipe_info->pipe_callbacks; 3640 3641 do { 3642 hif_ce_rtpm_mark_last_busy(scn, ce_state->id); 3643 qdf_nbuf_unmap_single(scn->qdf_dev, 3644 (qdf_nbuf_t) transfer_context, 3645 QDF_DMA_FROM_DEVICE); 3646 3647 atomic_inc(&pipe_info->recv_bufs_needed); 3648 hif_post_recv_buffers_for_pipe(pipe_info); 3649 if (scn->target_status == TARGET_STATUS_RESET) 3650 hif_ce_rx_nbuf_free(transfer_context); 3651 else 3652 hif_ce_do_recv(msg_callbacks, transfer_context, 3653 nbytes, pipe_info); 3654 3655 /* Set up force_break flag if num of receices reaches 3656 * MAX_NUM_OF_RECEIVES 3657 */ 3658 ce_state->receive_count++; 3659 if (qdf_unlikely(hif_ce_service_should_yield(scn, ce_state))) { 3660 ce_state->force_break = 1; 3661 break; 3662 } 3663 } while (ce_completed_recv_next(copyeng, &ce_context, &transfer_context, 3664 &CE_data, &nbytes, &transfer_id, 3665 &flags) == QDF_STATUS_SUCCESS); 3666 3667 } 3668 3669 /* TBDXXX: Set CE High Watermark; invoke txResourceAvailHandler in response */ 3670 3671 void 3672 hif_post_init(struct hif_opaque_softc *hif_ctx, void *unused, 3673 struct hif_msg_callbacks *callbacks) 3674 { 3675 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(hif_ctx); 3676 3677 #ifdef CONFIG_ATH_PCIE_ACCESS_DEBUG 3678 spin_lock_init(&pcie_access_log_lock); 3679 #endif 3680 /* Save callbacks for later installation */ 3681 qdf_mem_copy(&hif_state->msg_callbacks_pending, callbacks, 3682 sizeof(hif_state->msg_callbacks_pending)); 3683 3684 } 3685 3686 static int hif_completion_thread_startup_by_ceid(struct HIF_CE_state *hif_state, 3687 int pipe_num) 3688 { 3689 struct CE_attr attr; 3690 struct hif_softc *scn = HIF_GET_SOFTC(hif_state); 3691 struct hif_msg_callbacks *hif_msg_callbacks = 3692 &hif_state->msg_callbacks_current; 3693 struct HIF_CE_pipe_info *pipe_info; 3694 struct CE_state *ce_state; 3695 3696 if (pipe_num >= CE_COUNT_MAX) 3697 return -EINVAL; 3698 3699 pipe_info = &hif_state->pipe_info[pipe_num]; 3700 ce_state = scn->ce_id_to_state[pipe_num]; 3701 3702 if (!hif_msg_callbacks || 3703 !hif_msg_callbacks->rxCompletionHandler || 3704 !hif_msg_callbacks->txCompletionHandler) { 3705 hif_err("no completion handler registered"); 3706 return -EFAULT; 3707 } 3708 3709 attr = hif_state->host_ce_config[pipe_num]; 3710 if (attr.src_nentries) { 3711 /* pipe used to send to target */ 3712 hif_debug("pipe_num:%d pipe_info:0x%pK\n", 3713 pipe_num, pipe_info); 3714 ce_send_cb_register(pipe_info->ce_hdl, 3715 hif_pci_ce_send_done, pipe_info, 3716 attr.flags & CE_ATTR_DISABLE_INTR); 3717 pipe_info->num_sends_allowed = attr.src_nentries - 1; 3718 } 3719 if (attr.dest_nentries) { 3720 hif_debug("pipe_num:%d pipe_info:0x%pK\n", 3721 pipe_num, pipe_info); 3722 /* pipe used to receive from target */ 3723 ce_recv_cb_register(pipe_info->ce_hdl, 3724 hif_pci_ce_recv_data, pipe_info, 3725 attr.flags & CE_ATTR_DISABLE_INTR); 3726 } 3727 3728 if (attr.src_nentries) 3729 qdf_spinlock_create(&pipe_info->completion_freeq_lock); 3730 3731 if (!(ce_state->attr_flags & CE_ATTR_INIT_ON_DEMAND)) 3732 qdf_mem_copy(&pipe_info->pipe_callbacks, hif_msg_callbacks, 3733 sizeof(pipe_info->pipe_callbacks)); 3734 3735 return 0; 3736 } 3737 3738 static int hif_completion_thread_startup(struct HIF_CE_state *hif_state) 3739 { 3740 struct CE_handle *ce_diag = hif_state->ce_diag; 3741 int pipe_num, ret; 3742 struct hif_softc *scn = HIF_GET_SOFTC(hif_state); 3743 3744 /* daemonize("hif_compl_thread"); */ 3745 3746 if (scn->ce_count == 0) { 3747 hif_err("ce_count is 0"); 3748 return -EINVAL; 3749 } 3750 3751 3752 A_TARGET_ACCESS_LIKELY(scn); 3753 for (pipe_num = 0; pipe_num < scn->ce_count; pipe_num++) { 3754 struct HIF_CE_pipe_info *pipe_info; 3755 3756 pipe_info = &hif_state->pipe_info[pipe_num]; 3757 if (pipe_info->ce_hdl == ce_diag) 3758 continue; /* Handle Diagnostic CE specially */ 3759 3760 ret = hif_completion_thread_startup_by_ceid(hif_state, 3761 pipe_num); 3762 if (ret < 0) 3763 return ret; 3764 3765 } 3766 3767 A_TARGET_ACCESS_UNLIKELY(scn); 3768 return 0; 3769 } 3770 3771 /* 3772 * Install pending msg callbacks. 3773 * 3774 * TBDXXX: This hack is needed because upper layers install msg callbacks 3775 * for use with HTC before BMI is done; yet this HIF implementation 3776 * needs to continue to use BMI msg callbacks. Really, upper layers 3777 * should not register HTC callbacks until AFTER BMI phase. 3778 */ 3779 static void hif_msg_callbacks_install(struct hif_softc *scn) 3780 { 3781 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 3782 3783 qdf_mem_copy(&hif_state->msg_callbacks_current, 3784 &hif_state->msg_callbacks_pending, 3785 sizeof(hif_state->msg_callbacks_pending)); 3786 } 3787 3788 void hif_get_default_pipe(struct hif_opaque_softc *hif_hdl, uint8_t *ULPipe, 3789 uint8_t *DLPipe) 3790 { 3791 int ul_is_polled, dl_is_polled; 3792 3793 (void)hif_map_service_to_pipe(hif_hdl, HTC_CTRL_RSVD_SVC, 3794 ULPipe, DLPipe, &ul_is_polled, &dl_is_polled); 3795 } 3796 3797 /** 3798 * hif_dump_pipe_debug_count() - Log error count 3799 * @scn: hif_softc pointer. 3800 * 3801 * Output the pipe error counts of each pipe to log file 3802 * 3803 * Return: N/A 3804 */ 3805 void hif_dump_pipe_debug_count(struct hif_softc *scn) 3806 { 3807 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 3808 int pipe_num; 3809 3810 if (!hif_state) { 3811 hif_err("hif_state is NULL"); 3812 return; 3813 } 3814 for (pipe_num = 0; pipe_num < scn->ce_count; pipe_num++) { 3815 struct HIF_CE_pipe_info *pipe_info; 3816 3817 pipe_info = &hif_state->pipe_info[pipe_num]; 3818 3819 if (pipe_info->nbuf_alloc_err_count > 0 || 3820 pipe_info->nbuf_dma_err_count > 0 || 3821 pipe_info->nbuf_ce_enqueue_err_count) 3822 hif_err( 3823 "pipe_id = %d, recv_bufs_needed = %d, nbuf_alloc_err_count = %u, nbuf_dma_err_count = %u, nbuf_ce_enqueue_err_count = %u", 3824 pipe_info->pipe_num, 3825 atomic_read(&pipe_info->recv_bufs_needed), 3826 pipe_info->nbuf_alloc_err_count, 3827 pipe_info->nbuf_dma_err_count, 3828 pipe_info->nbuf_ce_enqueue_err_count); 3829 } 3830 } 3831 3832 static void hif_post_recv_buffers_failure(struct HIF_CE_pipe_info *pipe_info, 3833 void *nbuf, uint32_t *error_cnt, 3834 enum hif_ce_event_type failure_type, 3835 const char *failure_type_string) 3836 { 3837 int bufs_needed_tmp = atomic_inc_return(&pipe_info->recv_bufs_needed); 3838 struct CE_state *CE_state = (struct CE_state *)pipe_info->ce_hdl; 3839 struct hif_softc *scn = HIF_GET_SOFTC(pipe_info->HIF_CE_state); 3840 int ce_id = CE_state->id; 3841 uint32_t error_cnt_tmp; 3842 3843 qdf_spin_lock_bh(&pipe_info->recv_bufs_needed_lock); 3844 error_cnt_tmp = ++(*error_cnt); 3845 qdf_spin_unlock_bh(&pipe_info->recv_bufs_needed_lock); 3846 hif_debug("pipe_num: %d, needed: %d, err_cnt: %u, fail_type: %s", 3847 pipe_info->pipe_num, bufs_needed_tmp, error_cnt_tmp, 3848 failure_type_string); 3849 hif_record_ce_desc_event(scn, ce_id, failure_type, 3850 NULL, nbuf, bufs_needed_tmp, 0); 3851 /* if we fail to allocate the last buffer for an rx pipe, 3852 * there is no trigger to refill the ce and we will 3853 * eventually crash 3854 */ 3855 if (bufs_needed_tmp == CE_state->dest_ring->nentries - 1 || 3856 (ce_srng_based(scn) && 3857 bufs_needed_tmp == CE_state->dest_ring->nentries - 2)) 3858 qdf_sched_work(scn->qdf_dev, &CE_state->oom_allocation_work); 3859 3860 } 3861 3862 3863 3864 3865 QDF_STATUS hif_post_recv_buffers_for_pipe(struct HIF_CE_pipe_info *pipe_info) 3866 { 3867 struct CE_handle *ce_hdl; 3868 qdf_size_t buf_sz; 3869 struct hif_softc *scn = HIF_GET_SOFTC(pipe_info->HIF_CE_state); 3870 QDF_STATUS status; 3871 uint32_t bufs_posted = 0; 3872 unsigned int ce_id; 3873 3874 buf_sz = pipe_info->buf_sz; 3875 if (buf_sz == 0) { 3876 /* Unused Copy Engine */ 3877 return QDF_STATUS_SUCCESS; 3878 } 3879 3880 ce_hdl = pipe_info->ce_hdl; 3881 if (!ce_hdl) { 3882 hif_err("ce_hdl is NULL"); 3883 return QDF_STATUS_E_INVAL; 3884 } 3885 3886 ce_id = ((struct CE_state *)ce_hdl)->id; 3887 3888 qdf_spin_lock_bh(&pipe_info->recv_bufs_needed_lock); 3889 while (atomic_read(&pipe_info->recv_bufs_needed) > 0) { 3890 qdf_dma_addr_t CE_data; /* CE space buffer address */ 3891 qdf_nbuf_t nbuf; 3892 3893 atomic_dec(&pipe_info->recv_bufs_needed); 3894 qdf_spin_unlock_bh(&pipe_info->recv_bufs_needed_lock); 3895 3896 hif_record_ce_desc_event(scn, ce_id, 3897 HIF_RX_DESC_PRE_NBUF_ALLOC, NULL, NULL, 3898 0, 0); 3899 nbuf = hif_ce_rx_nbuf_alloc(scn, ce_id); 3900 if (!nbuf) { 3901 hif_post_recv_buffers_failure(pipe_info, nbuf, 3902 &pipe_info->nbuf_alloc_err_count, 3903 HIF_RX_NBUF_ALLOC_FAILURE, 3904 "HIF_RX_NBUF_ALLOC_FAILURE"); 3905 return QDF_STATUS_E_NOMEM; 3906 } 3907 3908 hif_record_ce_desc_event(scn, ce_id, 3909 HIF_RX_DESC_PRE_NBUF_MAP, NULL, nbuf, 3910 0, 0); 3911 /* 3912 * qdf_nbuf_peek_header(nbuf, &data, &unused); 3913 * CE_data = dma_map_single(dev, data, buf_sz, ); 3914 * DMA_FROM_DEVICE); 3915 */ 3916 status = qdf_nbuf_map_single(scn->qdf_dev, nbuf, 3917 QDF_DMA_FROM_DEVICE); 3918 3919 if (qdf_unlikely(status != QDF_STATUS_SUCCESS)) { 3920 hif_post_recv_buffers_failure(pipe_info, nbuf, 3921 &pipe_info->nbuf_dma_err_count, 3922 HIF_RX_NBUF_MAP_FAILURE, 3923 "HIF_RX_NBUF_MAP_FAILURE"); 3924 hif_ce_rx_nbuf_free(nbuf); 3925 return status; 3926 } 3927 3928 CE_data = qdf_nbuf_get_frag_paddr(nbuf, 0); 3929 hif_record_ce_desc_event(scn, ce_id, 3930 HIF_RX_DESC_POST_NBUF_MAP, NULL, nbuf, 3931 0, 0); 3932 qdf_mem_dma_sync_single_for_device(scn->qdf_dev, CE_data, 3933 buf_sz, DMA_FROM_DEVICE); 3934 status = ce_recv_buf_enqueue(ce_hdl, (void *)nbuf, CE_data); 3935 if (qdf_unlikely(status != QDF_STATUS_SUCCESS)) { 3936 hif_post_recv_buffers_failure(pipe_info, nbuf, 3937 &pipe_info->nbuf_ce_enqueue_err_count, 3938 HIF_RX_NBUF_ENQUEUE_FAILURE, 3939 "HIF_RX_NBUF_ENQUEUE_FAILURE"); 3940 3941 qdf_nbuf_unmap_single(scn->qdf_dev, nbuf, 3942 QDF_DMA_FROM_DEVICE); 3943 hif_ce_rx_nbuf_free(nbuf); 3944 return status; 3945 } 3946 3947 qdf_spin_lock_bh(&pipe_info->recv_bufs_needed_lock); 3948 bufs_posted++; 3949 } 3950 pipe_info->nbuf_alloc_err_count = 3951 (pipe_info->nbuf_alloc_err_count > bufs_posted) ? 3952 pipe_info->nbuf_alloc_err_count - bufs_posted : 0; 3953 pipe_info->nbuf_dma_err_count = 3954 (pipe_info->nbuf_dma_err_count > bufs_posted) ? 3955 pipe_info->nbuf_dma_err_count - bufs_posted : 0; 3956 pipe_info->nbuf_ce_enqueue_err_count = 3957 (pipe_info->nbuf_ce_enqueue_err_count > bufs_posted) ? 3958 pipe_info->nbuf_ce_enqueue_err_count - bufs_posted : 0; 3959 3960 qdf_spin_unlock_bh(&pipe_info->recv_bufs_needed_lock); 3961 3962 return QDF_STATUS_SUCCESS; 3963 } 3964 3965 #ifdef FEATURE_DIRECT_LINK 3966 static QDF_STATUS 3967 hif_alloc_pages_for_direct_link_recv_pipe(struct HIF_CE_state *hif_ce_state, 3968 int pipe_num) 3969 { 3970 struct hif_softc *scn = HIF_GET_SOFTC(hif_ce_state); 3971 struct service_to_pipe *tgt_svc_cfg; 3972 struct HIF_CE_pipe_info *pipe_info; 3973 int32_t recv_bufs_needed; 3974 qdf_dma_addr_t dma_addr; 3975 uint16_t num_elem_per_page; 3976 uint16_t i; 3977 bool is_found = false; 3978 3979 tgt_svc_cfg = hif_ce_state->tgt_svc_map; 3980 3981 for (i = 0; i < hif_ce_state->sz_tgt_svc_map; i++) { 3982 if (tgt_svc_cfg[i].service_id != LPASS_DATA_MSG_SVC || 3983 tgt_svc_cfg[i].pipedir != PIPEDIR_IN || 3984 tgt_svc_cfg[i].pipenum != pipe_num) 3985 continue; 3986 3987 pipe_info = &hif_ce_state->pipe_info[pipe_num]; 3988 recv_bufs_needed = atomic_read(&pipe_info->recv_bufs_needed); 3989 3990 if (!pipe_info->buf_sz || !recv_bufs_needed) 3991 continue; 3992 3993 is_found = true; 3994 break; 3995 } 3996 3997 if (!is_found) 3998 return QDF_STATUS_E_NOSUPPORT; 3999 4000 scn->dl_recv_pipe_num = pipe_num; 4001 4002 hif_prealloc_get_multi_pages(scn, QDF_DP_RX_DIRECT_LINK_CE_BUF_TYPE, 4003 pipe_info->buf_sz, recv_bufs_needed, 4004 &scn->dl_recv_pages, false); 4005 if (!scn->dl_recv_pages.num_pages) 4006 return QDF_STATUS_E_NOMEM; 4007 4008 num_elem_per_page = scn->dl_recv_pages.num_element_per_page; 4009 for (i = 0; i < recv_bufs_needed; i++) { 4010 dma_addr = scn->dl_recv_pages.dma_pages[i / num_elem_per_page].page_p_addr; 4011 dma_addr += (i % num_elem_per_page) * pipe_info->buf_sz; 4012 ce_recv_buf_enqueue(pipe_info->ce_hdl, NULL, dma_addr); 4013 } 4014 4015 return QDF_STATUS_SUCCESS; 4016 } 4017 4018 static QDF_STATUS 4019 hif_free_pages_for_direct_link_recv_pipe(struct HIF_CE_state *hif_ce_state, 4020 int pipe_num) 4021 { 4022 struct hif_softc *scn = HIF_GET_SOFTC(hif_ce_state); 4023 4024 if (pipe_num != scn->dl_recv_pipe_num) 4025 return QDF_STATUS_E_NOSUPPORT; 4026 4027 hif_prealloc_put_multi_pages(scn, QDF_DP_RX_DIRECT_LINK_CE_BUF_TYPE, 4028 &scn->dl_recv_pages, false); 4029 4030 return QDF_STATUS_SUCCESS; 4031 } 4032 #else 4033 static inline QDF_STATUS 4034 hif_alloc_pages_for_direct_link_recv_pipe(struct HIF_CE_state *hif_ce_state, 4035 int pipe_num) 4036 { 4037 return QDF_STATUS_E_NOSUPPORT; 4038 } 4039 4040 static inline QDF_STATUS 4041 hif_free_pages_for_direct_link_recv_pipe(struct HIF_CE_state *hif_ce_state, 4042 int pipe_num) 4043 { 4044 return QDF_STATUS_E_NOSUPPORT; 4045 } 4046 #endif 4047 4048 /* 4049 * Try to post all desired receive buffers for all pipes. 4050 * Returns 0 for non fastpath rx copy engine as 4051 * oom_allocation_work will be scheduled to recover any 4052 * failures, non-zero if unable to completely replenish 4053 * receive buffers for fastpath rx Copy engine. 4054 */ 4055 static QDF_STATUS hif_post_recv_buffers(struct hif_softc *scn) 4056 { 4057 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 4058 int pipe_num; 4059 struct CE_state *ce_state = NULL; 4060 QDF_STATUS qdf_status; 4061 4062 A_TARGET_ACCESS_LIKELY(scn); 4063 for (pipe_num = 0; pipe_num < scn->ce_count; pipe_num++) { 4064 struct HIF_CE_pipe_info *pipe_info; 4065 4066 if (pipe_num >= CE_COUNT_MAX) { 4067 A_TARGET_ACCESS_UNLIKELY(scn); 4068 return QDF_STATUS_E_INVAL; 4069 } 4070 4071 ce_state = scn->ce_id_to_state[pipe_num]; 4072 pipe_info = &hif_state->pipe_info[pipe_num]; 4073 4074 if (!ce_state) 4075 continue; 4076 4077 /* Do not init dynamic CEs, during initial load */ 4078 if (ce_state->attr_flags & CE_ATTR_INIT_ON_DEMAND) 4079 continue; 4080 4081 if (hif_is_nss_wifi_enabled(scn) && 4082 ce_state && (ce_state->htt_rx_data)) 4083 continue; 4084 4085 qdf_status = 4086 hif_alloc_pages_for_direct_link_recv_pipe(hif_state, 4087 pipe_num); 4088 if (QDF_IS_STATUS_SUCCESS(qdf_status)) 4089 continue; 4090 4091 qdf_status = hif_post_recv_buffers_for_pipe(pipe_info); 4092 if (!QDF_IS_STATUS_SUCCESS(qdf_status) && ce_state && 4093 ce_state->htt_rx_data && 4094 scn->fastpath_mode_on) { 4095 A_TARGET_ACCESS_UNLIKELY(scn); 4096 return qdf_status; 4097 } 4098 } 4099 4100 A_TARGET_ACCESS_UNLIKELY(scn); 4101 4102 return QDF_STATUS_SUCCESS; 4103 } 4104 4105 QDF_STATUS hif_start(struct hif_opaque_softc *hif_ctx) 4106 { 4107 struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); 4108 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 4109 QDF_STATUS qdf_status = QDF_STATUS_SUCCESS; 4110 4111 hif_update_fastpath_recv_bufs_cnt(scn); 4112 4113 hif_msg_callbacks_install(scn); 4114 4115 if (hif_completion_thread_startup(hif_state)) 4116 return QDF_STATUS_E_FAILURE; 4117 4118 hif_ce_rx_wbuff_register(scn); 4119 4120 /* enable buffer cleanup */ 4121 hif_state->started = true; 4122 4123 /* Post buffers once to start things off. */ 4124 qdf_status = hif_post_recv_buffers(scn); 4125 if (!QDF_IS_STATUS_SUCCESS(qdf_status)) { 4126 /* cleanup is done in hif_ce_disable */ 4127 hif_err("Failed to post buffers"); 4128 return qdf_status; 4129 } 4130 4131 return qdf_status; 4132 } 4133 4134 static void hif_recv_buffer_cleanup_on_pipe(struct HIF_CE_pipe_info *pipe_info) 4135 { 4136 struct hif_softc *scn; 4137 struct CE_handle *ce_hdl; 4138 uint32_t buf_sz; 4139 struct HIF_CE_state *hif_state; 4140 qdf_nbuf_t netbuf; 4141 qdf_dma_addr_t CE_data; 4142 void *per_CE_context; 4143 QDF_STATUS status; 4144 4145 buf_sz = pipe_info->buf_sz; 4146 /* Unused Copy Engine */ 4147 if (buf_sz == 0) 4148 return; 4149 4150 4151 hif_state = pipe_info->HIF_CE_state; 4152 if (!hif_state->started) 4153 return; 4154 4155 scn = HIF_GET_SOFTC(hif_state); 4156 ce_hdl = pipe_info->ce_hdl; 4157 4158 if (!scn->qdf_dev) 4159 return; 4160 4161 status = hif_free_pages_for_direct_link_recv_pipe(hif_state, 4162 pipe_info->pipe_num); 4163 if (QDF_IS_STATUS_SUCCESS(status)) 4164 return; 4165 4166 while (ce_revoke_recv_next 4167 (ce_hdl, &per_CE_context, (void **)&netbuf, 4168 &CE_data) == QDF_STATUS_SUCCESS) { 4169 if (netbuf) { 4170 qdf_nbuf_unmap_single(scn->qdf_dev, netbuf, 4171 QDF_DMA_FROM_DEVICE); 4172 hif_ce_rx_nbuf_free(netbuf); 4173 } 4174 } 4175 } 4176 4177 static void hif_send_buffer_cleanup_on_pipe(struct HIF_CE_pipe_info *pipe_info) 4178 { 4179 struct CE_handle *ce_hdl; 4180 struct HIF_CE_state *hif_state; 4181 struct hif_softc *scn; 4182 qdf_nbuf_t netbuf; 4183 void *per_CE_context; 4184 qdf_dma_addr_t CE_data; 4185 unsigned int nbytes; 4186 unsigned int id; 4187 uint32_t buf_sz; 4188 uint32_t toeplitz_hash_result; 4189 4190 buf_sz = pipe_info->buf_sz; 4191 if (buf_sz == 0) { 4192 /* Unused Copy Engine */ 4193 return; 4194 } 4195 4196 hif_state = pipe_info->HIF_CE_state; 4197 if (!hif_state->started) { 4198 return; 4199 } 4200 4201 scn = HIF_GET_SOFTC(hif_state); 4202 4203 ce_hdl = pipe_info->ce_hdl; 4204 4205 while (ce_cancel_send_next 4206 (ce_hdl, &per_CE_context, 4207 (void **)&netbuf, &CE_data, &nbytes, 4208 &id, &toeplitz_hash_result) == QDF_STATUS_SUCCESS) { 4209 if (netbuf != CE_SENDLIST_ITEM_CTXT) { 4210 /* 4211 * Packets enqueued by htt_h2t_ver_req_msg() and 4212 * htt_h2t_rx_ring_cfg_msg_ll() have already been 4213 * freed in htt_htc_misc_pkt_pool_free() in 4214 * wlantl_close(), so do not free them here again 4215 * by checking whether it's the endpoint 4216 * which they are queued in. 4217 */ 4218 if (id == scn->htc_htt_tx_endpoint) 4219 return; 4220 /* Indicate the completion to higher 4221 * layer to free the buffer 4222 */ 4223 if (pipe_info->pipe_callbacks.txCompletionHandler) 4224 pipe_info->pipe_callbacks. 4225 txCompletionHandler(pipe_info-> 4226 pipe_callbacks.Context, 4227 netbuf, id, toeplitz_hash_result); 4228 } 4229 } 4230 } 4231 4232 /* 4233 * Cleanup residual buffers for device shutdown: 4234 * buffers that were enqueued for receive 4235 * buffers that were to be sent 4236 * Note: Buffers that had completed but which were 4237 * not yet processed are on a completion queue. They 4238 * are handled when the completion thread shuts down. 4239 */ 4240 static void hif_buffer_cleanup(struct HIF_CE_state *hif_state) 4241 { 4242 int pipe_num; 4243 struct hif_softc *scn = HIF_GET_SOFTC(hif_state); 4244 struct CE_state *ce_state; 4245 4246 for (pipe_num = 0; pipe_num < scn->ce_count; pipe_num++) { 4247 struct HIF_CE_pipe_info *pipe_info; 4248 4249 ce_state = scn->ce_id_to_state[pipe_num]; 4250 if (hif_is_nss_wifi_enabled(scn) && ce_state && 4251 ((ce_state->htt_tx_data) || 4252 (ce_state->htt_rx_data))) { 4253 continue; 4254 } 4255 4256 pipe_info = &hif_state->pipe_info[pipe_num]; 4257 hif_recv_buffer_cleanup_on_pipe(pipe_info); 4258 hif_send_buffer_cleanup_on_pipe(pipe_info); 4259 } 4260 } 4261 4262 void hif_flush_surprise_remove(struct hif_opaque_softc *hif_ctx) 4263 { 4264 struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); 4265 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 4266 4267 hif_buffer_cleanup(hif_state); 4268 } 4269 4270 static void hif_destroy_oom_work(struct hif_softc *scn) 4271 { 4272 struct CE_state *ce_state; 4273 int ce_id; 4274 4275 for (ce_id = 0; ce_id < scn->ce_count; ce_id++) { 4276 ce_state = scn->ce_id_to_state[ce_id]; 4277 if (ce_state) 4278 qdf_destroy_work(scn->qdf_dev, 4279 &ce_state->oom_allocation_work); 4280 } 4281 } 4282 4283 void hif_ce_stop(struct hif_softc *scn) 4284 { 4285 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 4286 int pipe_num; 4287 4288 /* 4289 * before cleaning up any memory, ensure irq & 4290 * bottom half contexts will not be re-entered 4291 */ 4292 hif_disable_isr(&scn->osc); 4293 hif_destroy_oom_work(scn); 4294 scn->hif_init_done = false; 4295 4296 /* 4297 * At this point, asynchronous threads are stopped, 4298 * The Target should not DMA nor interrupt, Host code may 4299 * not initiate anything more. So we just need to clean 4300 * up Host-side state. 4301 */ 4302 4303 if (scn->athdiag_procfs_inited) { 4304 athdiag_procfs_remove(); 4305 scn->athdiag_procfs_inited = false; 4306 } 4307 4308 hif_buffer_cleanup(hif_state); 4309 4310 for (pipe_num = 0; pipe_num < scn->ce_count; pipe_num++) { 4311 struct HIF_CE_pipe_info *pipe_info; 4312 struct CE_attr attr; 4313 struct CE_handle *ce_diag = hif_state->ce_diag; 4314 4315 pipe_info = &hif_state->pipe_info[pipe_num]; 4316 if (pipe_info->ce_hdl) { 4317 if (pipe_info->ce_hdl != ce_diag && 4318 hif_state->started) { 4319 attr = hif_state->host_ce_config[pipe_num]; 4320 if (attr.src_nentries) 4321 qdf_spinlock_destroy(&pipe_info-> 4322 completion_freeq_lock); 4323 } 4324 ce_fini(pipe_info->ce_hdl); 4325 pipe_info->ce_hdl = NULL; 4326 pipe_info->buf_sz = 0; 4327 qdf_spinlock_destroy(&pipe_info->recv_bufs_needed_lock); 4328 } 4329 } 4330 4331 hif_ce_rx_wbuff_deregister(scn); 4332 4333 if (hif_state->sleep_timer_init) { 4334 qdf_timer_stop(&hif_state->sleep_timer); 4335 qdf_timer_free(&hif_state->sleep_timer); 4336 hif_state->sleep_timer_init = false; 4337 } 4338 4339 hif_state->started = false; 4340 } 4341 4342 #ifdef CONFIG_SHADOW_V3 4343 void hif_preare_shadow_register_cfg_v3(struct hif_softc *scn) 4344 { 4345 int shadow_cfg_idx = scn->num_shadow_registers_configured; 4346 int i; 4347 4348 /* shadow reg config for CE SRC registers */ 4349 for (i = 0; i < scn->ce_count; i++) { 4350 scn->shadow_regs[shadow_cfg_idx].addr = 4351 CE_BASE_ADDRESS(i) + SR_WR_INDEX_ADDRESS; 4352 shadow_cfg_idx++; 4353 } 4354 4355 /* shadow reg config for CE DST registers */ 4356 for (i = 0; i < scn->ce_count; i++) { 4357 scn->shadow_regs[shadow_cfg_idx].addr = 4358 CE_BASE_ADDRESS(i) + DST_WR_INDEX_ADDRESS; 4359 shadow_cfg_idx++; 4360 } 4361 4362 scn->num_shadow_registers_configured = shadow_cfg_idx; 4363 } 4364 4365 void hif_get_shadow_reg_config_v3(struct hif_softc *scn, 4366 struct pld_shadow_reg_v3_cfg **shadow_config, 4367 int *num_shadow_registers_configured) 4368 { 4369 *shadow_config = scn->shadow_regs; 4370 *num_shadow_registers_configured = 4371 scn->num_shadow_registers_configured; 4372 } 4373 #endif 4374 4375 static void hif_get_shadow_reg_cfg(struct hif_softc *scn, 4376 struct shadow_reg_cfg 4377 **target_shadow_reg_cfg_ret, 4378 uint32_t *shadow_cfg_sz_ret) 4379 { 4380 if (target_shadow_reg_cfg_ret) 4381 *target_shadow_reg_cfg_ret = target_shadow_reg_cfg; 4382 if (shadow_cfg_sz_ret) 4383 *shadow_cfg_sz_ret = shadow_cfg_sz; 4384 } 4385 4386 /** 4387 * hif_get_target_ce_config() - get copy engine configuration 4388 * @scn: HIF context 4389 * @target_ce_config_ret: basic copy engine configuration 4390 * @target_ce_config_sz_ret: size of the basic configuration in bytes 4391 * @target_service_to_ce_map_ret: service mapping for the copy engines 4392 * @target_service_to_ce_map_sz_ret: size of the mapping in bytes 4393 * @target_shadow_reg_cfg_ret: shadow register configuration 4394 * @shadow_cfg_sz_ret: size of the shadow register configuration in bytes 4395 * 4396 * providing accessor to these values outside of this file. 4397 * currently these are stored in static pointers to const sections. 4398 * there are multiple configurations that are selected from at compile time. 4399 * Runtime selection would need to consider mode, target type and bus type. 4400 * 4401 * Return: return by parameter. 4402 */ 4403 void hif_get_target_ce_config(struct hif_softc *scn, 4404 struct CE_pipe_config **target_ce_config_ret, 4405 uint32_t *target_ce_config_sz_ret, 4406 struct service_to_pipe **target_service_to_ce_map_ret, 4407 uint32_t *target_service_to_ce_map_sz_ret, 4408 struct shadow_reg_cfg **target_shadow_reg_cfg_ret, 4409 uint32_t *shadow_cfg_sz_ret) 4410 { 4411 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 4412 4413 *target_ce_config_ret = hif_state->target_ce_config; 4414 *target_ce_config_sz_ret = hif_state->target_ce_config_sz; 4415 4416 hif_select_service_to_pipe_map(scn, target_service_to_ce_map_ret, 4417 target_service_to_ce_map_sz_ret); 4418 hif_get_shadow_reg_cfg(scn, target_shadow_reg_cfg_ret, 4419 shadow_cfg_sz_ret); 4420 } 4421 4422 #ifdef CONFIG_SHADOW_V3 4423 static void hif_print_hal_shadow_register_cfg(struct pld_wlan_enable_cfg *cfg) 4424 { 4425 int i; 4426 4427 hif_info("v3: num_config %d", cfg->num_shadow_reg_v3_cfg); 4428 for (i = 0; i < cfg->num_shadow_reg_v3_cfg; i++) 4429 hif_info("i %d, val %x", i, cfg->shadow_reg_v3_cfg[i].addr); 4430 } 4431 4432 #elif defined(CONFIG_SHADOW_V2) 4433 static void hif_print_hal_shadow_register_cfg(struct pld_wlan_enable_cfg *cfg) 4434 { 4435 int i; 4436 4437 hif_info("v2: num_config %d", cfg->num_shadow_reg_v2_cfg); 4438 for (i = 0; i < cfg->num_shadow_reg_v2_cfg; i++) 4439 hif_info("i %d, val %x", i, cfg->shadow_reg_v2_cfg[i].addr); 4440 } 4441 4442 #else 4443 static void hif_print_hal_shadow_register_cfg(struct pld_wlan_enable_cfg *cfg) 4444 { 4445 hif_info("CONFIG_SHADOW V2/V3 not defined"); 4446 } 4447 #endif 4448 4449 #ifdef ADRASTEA_RRI_ON_DDR 4450 /** 4451 * hif_get_src_ring_read_index(): Called to get the SRRI 4452 * 4453 * @scn: hif_softc pointer 4454 * @CE_ctrl_addr: base address of the CE whose RRI is to be read 4455 * 4456 * This function returns the SRRI to the caller. For CEs that 4457 * dont have interrupts enabled, we look at the DDR based SRRI 4458 * 4459 * Return: SRRI 4460 */ 4461 inline unsigned int hif_get_src_ring_read_index(struct hif_softc *scn, 4462 uint32_t CE_ctrl_addr) 4463 { 4464 struct CE_attr attr; 4465 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 4466 4467 attr = hif_state->host_ce_config[COPY_ENGINE_ID(CE_ctrl_addr)]; 4468 if (attr.flags & CE_ATTR_DISABLE_INTR) { 4469 return CE_SRC_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr); 4470 } else { 4471 if (TARGET_REGISTER_ACCESS_ALLOWED(scn)) 4472 return A_TARGET_READ(scn, 4473 (CE_ctrl_addr) + CURRENT_SRRI_ADDRESS); 4474 else 4475 return CE_SRC_RING_READ_IDX_GET_FROM_DDR(scn, 4476 CE_ctrl_addr); 4477 } 4478 } 4479 4480 /** 4481 * hif_get_dst_ring_read_index(): Called to get the DRRI 4482 * 4483 * @scn: hif_softc pointer 4484 * @CE_ctrl_addr: base address of the CE whose RRI is to be read 4485 * 4486 * This function returns the DRRI to the caller. For CEs that 4487 * dont have interrupts enabled, we look at the DDR based DRRI 4488 * 4489 * Return: DRRI 4490 */ 4491 inline unsigned int hif_get_dst_ring_read_index(struct hif_softc *scn, 4492 uint32_t CE_ctrl_addr) 4493 { 4494 struct CE_attr attr; 4495 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 4496 4497 attr = hif_state->host_ce_config[COPY_ENGINE_ID(CE_ctrl_addr)]; 4498 4499 if (attr.flags & CE_ATTR_DISABLE_INTR) { 4500 return CE_DEST_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr); 4501 } else { 4502 if (TARGET_REGISTER_ACCESS_ALLOWED(scn)) 4503 return A_TARGET_READ(scn, 4504 (CE_ctrl_addr) + CURRENT_DRRI_ADDRESS); 4505 else 4506 return CE_DEST_RING_READ_IDX_GET_FROM_DDR(scn, 4507 CE_ctrl_addr); 4508 } 4509 } 4510 4511 /** 4512 * hif_alloc_rri_on_ddr() - Allocate memory for rri on ddr 4513 * @scn: hif_softc pointer 4514 * 4515 * Return: qdf status 4516 */ 4517 static inline QDF_STATUS hif_alloc_rri_on_ddr(struct hif_softc *scn) 4518 { 4519 qdf_dma_addr_t paddr_rri_on_ddr = 0; 4520 4521 scn->vaddr_rri_on_ddr = 4522 (void *)qdf_mem_alloc_consistent(scn->qdf_dev, 4523 scn->qdf_dev->dev, RRI_ON_DDR_MEM_SIZE, 4524 &paddr_rri_on_ddr); 4525 4526 if (!scn->vaddr_rri_on_ddr) { 4527 hif_err("dmaable page alloc fail"); 4528 return QDF_STATUS_E_NOMEM; 4529 } 4530 4531 scn->paddr_rri_on_ddr = paddr_rri_on_ddr; 4532 4533 qdf_mem_zero(scn->vaddr_rri_on_ddr, RRI_ON_DDR_MEM_SIZE); 4534 4535 return QDF_STATUS_SUCCESS; 4536 } 4537 #endif 4538 4539 #if (!defined(QCN7605_SUPPORT)) && defined(ADRASTEA_RRI_ON_DDR) 4540 /** 4541 * hif_config_rri_on_ddr(): Configure the RRI on DDR mechanism 4542 * 4543 * @scn: hif_softc pointer 4544 * 4545 * This function allocates non cached memory on ddr and sends 4546 * the physical address of this memory to the CE hardware. The 4547 * hardware updates the RRI on this particular location. 4548 * 4549 * Return: None 4550 */ 4551 #ifdef QCA_WIFI_WCN6450 4552 static inline void hif_config_rri_on_ddr(struct hif_softc *scn) 4553 { 4554 unsigned int i; 4555 uint32_t high_paddr, low_paddr; 4556 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 4557 struct CE_attr *attr; 4558 4559 if (hif_alloc_rri_on_ddr(scn) != QDF_STATUS_SUCCESS) 4560 return; 4561 4562 low_paddr = RRI_ON_DDR_PADDR_LOW(scn->paddr_rri_on_ddr); 4563 high_paddr = RRI_ON_DDR_PADDR_HIGH(scn->paddr_rri_on_ddr); 4564 4565 hif_debug("using srri and drri from DDR"); 4566 4567 WRITE_CE_DDR_ADDRESS_FOR_RRI_LOW(scn, low_paddr); 4568 WRITE_CE_DDR_ADDRESS_FOR_RRI_HIGH(scn, high_paddr); 4569 4570 for (i = 0; i < CE_COUNT; i++) { 4571 attr = &hif_state->host_ce_config[i]; 4572 if (attr->src_nentries || attr->dest_nentries) 4573 CE_IDX_UPD_EN_SET(scn, CE_BASE_ADDRESS(i)); 4574 } 4575 } 4576 #else 4577 static inline void hif_config_rri_on_ddr(struct hif_softc *scn) 4578 { 4579 unsigned int i; 4580 uint32_t high_paddr, low_paddr; 4581 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 4582 struct CE_pipe_config *ce_config; 4583 4584 if (hif_alloc_rri_on_ddr(scn) != QDF_STATUS_SUCCESS) 4585 return; 4586 4587 low_paddr = RRI_ON_DDR_PADDR_LOW(scn->paddr_rri_on_ddr); 4588 high_paddr = RRI_ON_DDR_PADDR_HIGH(scn->paddr_rri_on_ddr); 4589 4590 hif_debug("using srri and drri from DDR"); 4591 4592 WRITE_CE_DDR_ADDRESS_FOR_RRI_LOW(scn, low_paddr); 4593 WRITE_CE_DDR_ADDRESS_FOR_RRI_HIGH(scn, high_paddr); 4594 4595 for (i = 0; i < CE_COUNT; i++) { 4596 ce_config = &hif_state->target_ce_config[i]; 4597 /* 4598 * For DST channel program both IDX_UPD_EN and 4599 * DMAX length(behalf of F.W) at once to avoid 4600 * race with F.W register update. 4601 */ 4602 if (ce_config->pipedir == PIPEDIR_IN && ce_config->nbytes_max) 4603 CE_IDX_UPD_EN_DMAX_LEN_SET(scn, CE_BASE_ADDRESS(i), 4604 ce_config->nbytes_max); 4605 else 4606 CE_IDX_UPD_EN_SET(scn, CE_BASE_ADDRESS(i)); 4607 } 4608 } 4609 #endif 4610 4611 #else 4612 /** 4613 * hif_config_rri_on_ddr(): Configure the RRI on DDR mechanism 4614 * 4615 * @scn: hif_softc pointer 4616 * 4617 * This is a dummy implementation for platforms that don't 4618 * support this functionality. 4619 * 4620 * Return: None 4621 */ 4622 static inline void hif_config_rri_on_ddr(struct hif_softc *scn) 4623 { 4624 } 4625 #endif 4626 4627 /** 4628 * hif_update_rri_over_ddr_config() - update rri_over_ddr config for 4629 * QMI command 4630 * @scn: hif context 4631 * @cfg: wlan enable config 4632 * 4633 * In case of Genoa, rri_over_ddr memory configuration is passed 4634 * to firmware through QMI configure command. 4635 */ 4636 #if defined(QCN7605_SUPPORT) && defined(ADRASTEA_RRI_ON_DDR) 4637 static void hif_update_rri_over_ddr_config(struct hif_softc *scn, 4638 struct pld_wlan_enable_cfg *cfg) 4639 { 4640 if (hif_alloc_rri_on_ddr(scn) != QDF_STATUS_SUCCESS) 4641 return; 4642 4643 cfg->rri_over_ddr_cfg_valid = true; 4644 cfg->rri_over_ddr_cfg.base_addr_low = 4645 BITS0_TO_31(scn->paddr_rri_on_ddr); 4646 cfg->rri_over_ddr_cfg.base_addr_high = 4647 BITS32_TO_35(scn->paddr_rri_on_ddr); 4648 } 4649 #else 4650 static void hif_update_rri_over_ddr_config(struct hif_softc *scn, 4651 struct pld_wlan_enable_cfg *cfg) 4652 { 4653 } 4654 #endif 4655 4656 /** 4657 * hif_wlan_enable(): call the platform driver to enable wlan 4658 * @scn: HIF Context 4659 * 4660 * This function passes the con_mode and CE configuration to 4661 * platform driver to enable wlan. 4662 * 4663 * Return: linux error code 4664 */ 4665 int hif_wlan_enable(struct hif_softc *scn) 4666 { 4667 struct hif_opaque_softc *hif_hdl = GET_HIF_OPAQUE_HDL(scn); 4668 struct hif_target_info *tgt_info = hif_get_target_info_handle(hif_hdl); 4669 struct pld_wlan_enable_cfg cfg = { 0 }; 4670 enum pld_driver_mode mode; 4671 uint32_t con_mode = hif_get_conparam(scn); 4672 4673 hif_get_target_ce_config(scn, 4674 (struct CE_pipe_config **)&cfg.ce_tgt_cfg, 4675 &cfg.num_ce_tgt_cfg, 4676 (struct service_to_pipe **)&cfg.ce_svc_cfg, 4677 &cfg.num_ce_svc_pipe_cfg, 4678 (struct shadow_reg_cfg **)&cfg.shadow_reg_cfg, 4679 &cfg.num_shadow_reg_cfg); 4680 4681 /* translate from structure size to array size */ 4682 cfg.num_ce_tgt_cfg /= sizeof(struct CE_pipe_config); 4683 cfg.num_ce_svc_pipe_cfg /= sizeof(struct service_to_pipe); 4684 cfg.num_shadow_reg_cfg /= sizeof(struct shadow_reg_cfg); 4685 4686 switch (tgt_info->target_type) { 4687 case TARGET_TYPE_KIWI: 4688 case TARGET_TYPE_MANGO: 4689 case TARGET_TYPE_PEACH: 4690 case TARGET_TYPE_WCN6450: 4691 hif_prepare_hal_shadow_reg_cfg_v3(scn, &cfg); 4692 break; 4693 default: 4694 hif_prepare_hal_shadow_register_cfg(scn, 4695 &cfg.shadow_reg_v2_cfg, 4696 &cfg.num_shadow_reg_v2_cfg); 4697 break; 4698 } 4699 4700 hif_print_hal_shadow_register_cfg(&cfg); 4701 4702 hif_update_rri_over_ddr_config(scn, &cfg); 4703 4704 if (QDF_GLOBAL_FTM_MODE == con_mode) 4705 mode = PLD_FTM; 4706 else if (QDF_GLOBAL_COLDBOOT_CALIB_MODE == con_mode) 4707 mode = PLD_COLDBOOT_CALIBRATION; 4708 else if (QDF_GLOBAL_FTM_COLDBOOT_CALIB_MODE == con_mode) 4709 mode = PLD_FTM_COLDBOOT_CALIBRATION; 4710 else if (QDF_IS_EPPING_ENABLED(con_mode)) 4711 mode = PLD_EPPING; 4712 else 4713 mode = PLD_MISSION; 4714 4715 if (BYPASS_QMI) 4716 return 0; 4717 else 4718 return pld_wlan_enable(scn->qdf_dev->dev, &cfg, mode); 4719 } 4720 4721 #ifdef WLAN_FEATURE_EPPING 4722 4723 #define CE_EPPING_USES_IRQ true 4724 4725 void hif_ce_prepare_epping_config(struct hif_softc *scn, 4726 struct HIF_CE_state *hif_state) 4727 { 4728 if (CE_EPPING_USES_IRQ) 4729 hif_state->host_ce_config = host_ce_config_wlan_epping_irq; 4730 else 4731 hif_state->host_ce_config = host_ce_config_wlan_epping_poll; 4732 hif_state->target_ce_config = target_ce_config_wlan_epping; 4733 hif_state->target_ce_config_sz = sizeof(target_ce_config_wlan_epping); 4734 target_shadow_reg_cfg = target_shadow_reg_cfg_epping; 4735 shadow_cfg_sz = sizeof(target_shadow_reg_cfg_epping); 4736 scn->ce_count = EPPING_HOST_CE_COUNT; 4737 } 4738 #endif 4739 4740 #ifdef QCN7605_SUPPORT 4741 static inline 4742 void hif_set_ce_config_qcn7605(struct hif_softc *scn, 4743 struct HIF_CE_state *hif_state) 4744 { 4745 hif_state->host_ce_config = host_ce_config_wlan_qcn7605; 4746 hif_state->target_ce_config = target_ce_config_wlan_qcn7605; 4747 hif_state->target_ce_config_sz = 4748 sizeof(target_ce_config_wlan_qcn7605); 4749 target_shadow_reg_cfg = target_shadow_reg_cfg_map_qcn7605; 4750 shadow_cfg_sz = sizeof(target_shadow_reg_cfg_map_qcn7605); 4751 scn->ce_count = QCN7605_CE_COUNT; 4752 } 4753 #else 4754 static inline 4755 void hif_set_ce_config_qcn7605(struct hif_softc *scn, 4756 struct HIF_CE_state *hif_state) 4757 { 4758 hif_err("QCN7605 not supported"); 4759 } 4760 #endif 4761 4762 #ifdef CE_SVC_CMN_INIT 4763 #ifdef QCA_WIFI_SUPPORT_SRNG 4764 static inline void hif_ce_service_init(void) 4765 { 4766 ce_service_srng_init(); 4767 } 4768 #else 4769 static inline void hif_ce_service_init(void) 4770 { 4771 ce_service_legacy_init(); 4772 } 4773 #endif 4774 #else 4775 static inline void hif_ce_service_init(void) 4776 { 4777 } 4778 #endif 4779 4780 #ifdef FEATURE_DIRECT_LINK 4781 /** 4782 * hif_ce_select_config_kiwi() - Select the host and target CE 4783 * configuration for Kiwi 4784 * @hif_state: HIF CE context 4785 * 4786 * Return: None 4787 */ 4788 static inline 4789 void hif_ce_select_config_kiwi(struct HIF_CE_state *hif_state) 4790 { 4791 struct hif_softc *hif_ctx = HIF_GET_SOFTC(hif_state); 4792 4793 if (pld_is_direct_link_supported(hif_ctx->qdf_dev->dev)) { 4794 hif_state->host_ce_config = 4795 host_ce_config_wlan_kiwi_direct_link; 4796 hif_state->target_ce_config = 4797 target_ce_config_wlan_kiwi_direct_link; 4798 hif_state->target_ce_config_sz = 4799 sizeof(target_ce_config_wlan_kiwi_direct_link); 4800 } else { 4801 hif_state->host_ce_config = host_ce_config_wlan_kiwi; 4802 hif_state->target_ce_config = target_ce_config_wlan_kiwi; 4803 hif_state->target_ce_config_sz = 4804 sizeof(target_ce_config_wlan_kiwi); 4805 } 4806 } 4807 #else 4808 static inline 4809 void hif_ce_select_config_kiwi(struct HIF_CE_state *hif_state) 4810 { 4811 hif_state->host_ce_config = host_ce_config_wlan_kiwi; 4812 hif_state->target_ce_config = target_ce_config_wlan_kiwi; 4813 hif_state->target_ce_config_sz = sizeof(target_ce_config_wlan_kiwi); 4814 } 4815 #endif 4816 4817 /** 4818 * hif_ce_prepare_config() - load the correct static tables. 4819 * @scn: hif context 4820 * 4821 * Epping uses different static attribute tables than mission mode. 4822 */ 4823 void hif_ce_prepare_config(struct hif_softc *scn) 4824 { 4825 uint32_t mode = hif_get_conparam(scn); 4826 struct hif_opaque_softc *hif_hdl = GET_HIF_OPAQUE_HDL(scn); 4827 struct hif_target_info *tgt_info = hif_get_target_info_handle(hif_hdl); 4828 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 4829 int ret; 4830 int msi_data_count = 0; 4831 int msi_data_start = 0; 4832 int msi_irq_start = 0; 4833 4834 hif_ce_service_init(); 4835 hif_state->ce_services = ce_services_attach(scn); 4836 4837 ret = pld_get_user_msi_assignment(scn->qdf_dev->dev, "CE", 4838 &msi_data_count, &msi_data_start, 4839 &msi_irq_start); 4840 4841 scn->ce_count = HOST_CE_COUNT; 4842 scn->int_assignment = &ce_int_context[msi_data_count]; 4843 scn->free_irq_done = false; 4844 /* if epping is enabled we need to use the epping configuration. */ 4845 if (QDF_IS_EPPING_ENABLED(mode)) { 4846 hif_ce_prepare_epping_config(scn, hif_state); 4847 return; 4848 } 4849 4850 switch (tgt_info->target_type) { 4851 default: 4852 hif_state->host_ce_config = host_ce_config_wlan; 4853 hif_state->target_ce_config = target_ce_config_wlan; 4854 hif_state->target_ce_config_sz = sizeof(target_ce_config_wlan); 4855 break; 4856 case TARGET_TYPE_QCN7605: 4857 hif_set_ce_config_qcn7605(scn, hif_state); 4858 break; 4859 case TARGET_TYPE_AR900B: 4860 case TARGET_TYPE_QCA9984: 4861 case TARGET_TYPE_QCA9888: 4862 if (hif_is_attribute_set(scn, HIF_LOWDESC_CE_NO_PKTLOG_CFG)) { 4863 hif_state->host_ce_config = 4864 host_lowdesc_ce_cfg_wlan_ar900b_nopktlog; 4865 } else if (hif_is_attribute_set(scn, HIF_LOWDESC_CE_CFG)) { 4866 hif_state->host_ce_config = 4867 host_lowdesc_ce_cfg_wlan_ar900b; 4868 } else { 4869 hif_state->host_ce_config = host_ce_config_wlan_ar900b; 4870 } 4871 4872 hif_state->target_ce_config = target_ce_config_wlan_ar900b; 4873 hif_state->target_ce_config_sz = 4874 sizeof(target_ce_config_wlan_ar900b); 4875 4876 break; 4877 4878 case TARGET_TYPE_AR9888: 4879 case TARGET_TYPE_AR9888V2: 4880 if (hif_is_attribute_set(scn, HIF_LOWDESC_CE_CFG)) { 4881 hif_state->host_ce_config = host_lowdesc_ce_cfg_wlan_ar9888; 4882 } else { 4883 hif_state->host_ce_config = host_ce_config_wlan_ar9888; 4884 } 4885 4886 hif_state->target_ce_config = target_ce_config_wlan_ar9888; 4887 hif_state->target_ce_config_sz = 4888 sizeof(target_ce_config_wlan_ar9888); 4889 4890 break; 4891 4892 case TARGET_TYPE_QCA8074: 4893 case TARGET_TYPE_QCA8074V2: 4894 case TARGET_TYPE_QCA6018: 4895 if (scn->bus_type == QDF_BUS_TYPE_PCI) { 4896 hif_state->host_ce_config = 4897 host_ce_config_wlan_qca8074_pci; 4898 hif_state->target_ce_config = 4899 target_ce_config_wlan_qca8074_pci; 4900 hif_state->target_ce_config_sz = 4901 sizeof(target_ce_config_wlan_qca8074_pci); 4902 } else { 4903 hif_state->host_ce_config = host_ce_config_wlan_qca8074; 4904 hif_state->target_ce_config = 4905 target_ce_config_wlan_qca8074; 4906 hif_state->target_ce_config_sz = 4907 sizeof(target_ce_config_wlan_qca8074); 4908 } 4909 break; 4910 case TARGET_TYPE_QCA6290: 4911 hif_state->host_ce_config = host_ce_config_wlan_qca6290; 4912 hif_state->target_ce_config = target_ce_config_wlan_qca6290; 4913 hif_state->target_ce_config_sz = 4914 sizeof(target_ce_config_wlan_qca6290); 4915 4916 scn->ce_count = QCA_6290_CE_COUNT; 4917 break; 4918 case TARGET_TYPE_QCN9000: 4919 hif_state->host_ce_config = host_ce_config_wlan_qcn9000; 4920 hif_state->target_ce_config = target_ce_config_wlan_qcn9000; 4921 hif_state->target_ce_config_sz = 4922 sizeof(target_ce_config_wlan_qcn9000); 4923 scn->ce_count = QCN_9000_CE_COUNT; 4924 scn->ini_cfg.disable_wake_irq = 1; 4925 break; 4926 case TARGET_TYPE_QCN9224: 4927 hif_set_ce_config_qcn9224(scn, hif_state); 4928 break; 4929 case TARGET_TYPE_QCA5332: 4930 hif_state->host_ce_config = host_ce_config_wlan_qca5332; 4931 hif_state->target_ce_config = target_ce_config_wlan_qca5332; 4932 hif_state->target_ce_config_sz = 4933 sizeof(target_ce_config_wlan_qca5332); 4934 scn->ce_count = QCA_5332_CE_COUNT; 4935 break; 4936 case TARGET_TYPE_QCN6122: 4937 hif_state->host_ce_config = host_ce_config_wlan_qcn6122; 4938 hif_state->target_ce_config = target_ce_config_wlan_qcn6122; 4939 hif_state->target_ce_config_sz = 4940 sizeof(target_ce_config_wlan_qcn6122); 4941 scn->ce_count = QCN_6122_CE_COUNT; 4942 scn->ini_cfg.disable_wake_irq = 1; 4943 break; 4944 case TARGET_TYPE_QCN9160: 4945 hif_state->host_ce_config = host_ce_config_wlan_qcn9160; 4946 hif_state->target_ce_config = target_ce_config_wlan_qcn9160; 4947 hif_state->target_ce_config_sz = 4948 sizeof(target_ce_config_wlan_qcn9160); 4949 scn->ce_count = QCN_9160_CE_COUNT; 4950 scn->ini_cfg.disable_wake_irq = 1; 4951 break; 4952 case TARGET_TYPE_QCN6432: 4953 hif_state->host_ce_config = host_ce_config_wlan_qcn6432; 4954 hif_state->target_ce_config = target_ce_config_wlan_qcn6432; 4955 hif_state->target_ce_config_sz = 4956 sizeof(target_ce_config_wlan_qcn6432); 4957 scn->ce_count = QCN_6432_CE_COUNT; 4958 scn->ini_cfg.disable_wake_irq = 1; 4959 break; 4960 case TARGET_TYPE_QCA5018: 4961 hif_state->host_ce_config = host_ce_config_wlan_qca5018; 4962 hif_state->target_ce_config = target_ce_config_wlan_qca5018; 4963 hif_state->target_ce_config_sz = 4964 sizeof(target_ce_config_wlan_qca5018); 4965 scn->ce_count = QCA_5018_CE_COUNT; 4966 break; 4967 case TARGET_TYPE_QCA9574: 4968 hif_state->host_ce_config = host_ce_config_wlan_qca9574; 4969 hif_state->target_ce_config = target_ce_config_wlan_qca9574; 4970 hif_state->target_ce_config_sz = 4971 sizeof(target_ce_config_wlan_qca9574); 4972 break; 4973 case TARGET_TYPE_QCA6390: 4974 hif_state->host_ce_config = host_ce_config_wlan_qca6390; 4975 hif_state->target_ce_config = target_ce_config_wlan_qca6390; 4976 hif_state->target_ce_config_sz = 4977 sizeof(target_ce_config_wlan_qca6390); 4978 4979 scn->ce_count = QCA_6390_CE_COUNT; 4980 break; 4981 case TARGET_TYPE_QCA6490: 4982 hif_state->host_ce_config = host_ce_config_wlan_qca6490; 4983 hif_state->target_ce_config = target_ce_config_wlan_qca6490; 4984 hif_state->target_ce_config_sz = 4985 sizeof(target_ce_config_wlan_qca6490); 4986 4987 scn->ce_count = QCA_6490_CE_COUNT; 4988 break; 4989 case TARGET_TYPE_QCA6750: 4990 hif_state->host_ce_config = host_ce_config_wlan_qca6750; 4991 hif_state->target_ce_config = target_ce_config_wlan_qca6750; 4992 hif_state->target_ce_config_sz = 4993 sizeof(target_ce_config_wlan_qca6750); 4994 4995 scn->ce_count = QCA_6750_CE_COUNT; 4996 break; 4997 case TARGET_TYPE_KIWI: 4998 case TARGET_TYPE_MANGO: 4999 case TARGET_TYPE_PEACH: 5000 hif_ce_select_config_kiwi(hif_state); 5001 scn->ce_count = KIWI_CE_COUNT; 5002 break; 5003 case TARGET_TYPE_ADRASTEA: 5004 if (hif_is_attribute_set(scn, HIF_LOWDESC_CE_NO_PKTLOG_CFG)) { 5005 hif_state->host_ce_config = 5006 host_lowdesc_ce_config_wlan_adrastea_nopktlog; 5007 hif_state->target_ce_config = 5008 target_lowdesc_ce_config_wlan_adrastea_nopktlog; 5009 hif_state->target_ce_config_sz = 5010 sizeof(target_lowdesc_ce_config_wlan_adrastea_nopktlog); 5011 } else { 5012 hif_state->host_ce_config = 5013 host_ce_config_wlan_adrastea; 5014 hif_state->target_ce_config = 5015 target_ce_config_wlan_adrastea; 5016 hif_state->target_ce_config_sz = 5017 sizeof(target_ce_config_wlan_adrastea); 5018 } 5019 break; 5020 case TARGET_TYPE_WCN6450: 5021 hif_state->host_ce_config = host_ce_config_wlan_wcn6450; 5022 hif_state->target_ce_config = target_ce_config_wlan_wcn6450; 5023 hif_state->target_ce_config_sz = 5024 sizeof(target_ce_config_wlan_wcn6450); 5025 break; 5026 } 5027 QDF_BUG(scn->ce_count <= CE_COUNT_MAX); 5028 } 5029 5030 /** 5031 * hif_ce_open() - do ce specific allocations 5032 * @hif_sc: pointer to hif context 5033 * 5034 * return: 0 for success or QDF_STATUS_E_NOMEM 5035 */ 5036 QDF_STATUS hif_ce_open(struct hif_softc *hif_sc) 5037 { 5038 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(hif_sc); 5039 5040 qdf_spinlock_create(&hif_state->irq_reg_lock); 5041 qdf_spinlock_create(&hif_state->keep_awake_lock); 5042 return QDF_STATUS_SUCCESS; 5043 } 5044 5045 /** 5046 * hif_ce_close() - do ce specific free 5047 * @hif_sc: pointer to hif context 5048 */ 5049 void hif_ce_close(struct hif_softc *hif_sc) 5050 { 5051 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(hif_sc); 5052 5053 qdf_spinlock_destroy(&hif_state->irq_reg_lock); 5054 qdf_spinlock_destroy(&hif_state->keep_awake_lock); 5055 } 5056 5057 /** 5058 * hif_unconfig_ce() - ensure resources from hif_config_ce are freed 5059 * @hif_sc: hif context 5060 * 5061 * uses state variables to support cleaning up when hif_config_ce fails. 5062 */ 5063 void hif_unconfig_ce(struct hif_softc *hif_sc) 5064 { 5065 int pipe_num; 5066 struct HIF_CE_pipe_info *pipe_info; 5067 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(hif_sc); 5068 struct hif_opaque_softc *hif_hdl = GET_HIF_OPAQUE_HDL(hif_sc); 5069 5070 for (pipe_num = 0; pipe_num < hif_sc->ce_count; pipe_num++) { 5071 pipe_info = &hif_state->pipe_info[pipe_num]; 5072 if (pipe_info->ce_hdl) { 5073 ce_unregister_irq(hif_state, (1 << pipe_num)); 5074 } 5075 } 5076 deinit_tasklet_workers(hif_hdl); 5077 for (pipe_num = 0; pipe_num < hif_sc->ce_count; pipe_num++) { 5078 pipe_info = &hif_state->pipe_info[pipe_num]; 5079 if (pipe_info->ce_hdl) { 5080 ce_fini(pipe_info->ce_hdl); 5081 pipe_info->ce_hdl = NULL; 5082 pipe_info->buf_sz = 0; 5083 qdf_spinlock_destroy(&pipe_info->recv_bufs_needed_lock); 5084 } 5085 } 5086 if (hif_sc->athdiag_procfs_inited) { 5087 athdiag_procfs_remove(); 5088 hif_sc->athdiag_procfs_inited = false; 5089 } 5090 } 5091 5092 #ifdef CONFIG_BYPASS_QMI 5093 #ifdef QCN7605_SUPPORT 5094 /** 5095 * hif_post_static_buf_to_target() - post static buffer to WLAN FW 5096 * @scn: pointer to HIF structure 5097 * 5098 * WLAN FW needs 2MB memory from DDR when QMI is disabled. 5099 * 5100 * Return: void 5101 */ 5102 static void hif_post_static_buf_to_target(struct hif_softc *scn) 5103 { 5104 phys_addr_t target_pa; 5105 struct ce_info *ce_info_ptr; 5106 uint32_t msi_data_start; 5107 uint32_t msi_data_count; 5108 uint32_t msi_irq_start; 5109 uint32_t i = 0; 5110 int ret; 5111 5112 scn->vaddr_qmi_bypass = 5113 (uint32_t *)qdf_mem_alloc_consistent(scn->qdf_dev, 5114 scn->qdf_dev->dev, 5115 FW_SHARED_MEM, 5116 &target_pa); 5117 if (!scn->vaddr_qmi_bypass) { 5118 hif_err("Memory allocation failed could not post target buf"); 5119 return; 5120 } 5121 5122 scn->paddr_qmi_bypass = target_pa; 5123 5124 ce_info_ptr = (struct ce_info *)scn->vaddr_qmi_bypass; 5125 5126 if (scn->vaddr_rri_on_ddr) { 5127 ce_info_ptr->rri_over_ddr_low_paddr = 5128 BITS0_TO_31(scn->paddr_rri_on_ddr); 5129 ce_info_ptr->rri_over_ddr_high_paddr = 5130 BITS32_TO_35(scn->paddr_rri_on_ddr); 5131 } 5132 5133 ret = pld_get_user_msi_assignment(scn->qdf_dev->dev, "CE", 5134 &msi_data_count, &msi_data_start, 5135 &msi_irq_start); 5136 if (ret) { 5137 hif_err("Failed to get CE msi config"); 5138 return; 5139 } 5140 5141 for (i = 0; i < CE_COUNT_MAX; i++) { 5142 ce_info_ptr->cfg[i].ce_id = i; 5143 ce_info_ptr->cfg[i].msi_vector = 5144 (i % msi_data_count) + msi_irq_start; 5145 } 5146 5147 hif_write32_mb(scn, scn->mem + BYPASS_QMI_TEMP_REGISTER, target_pa); 5148 hif_info("target va %pK target pa %pa", scn->vaddr_qmi_bypass, 5149 &target_pa); 5150 } 5151 5152 /** 5153 * hif_cleanup_static_buf_to_target() - clean up static buffer to WLAN FW 5154 * @scn: pointer to HIF structure 5155 * 5156 * 5157 * Return: void 5158 */ 5159 void hif_cleanup_static_buf_to_target(struct hif_softc *scn) 5160 { 5161 void *target_va = scn->vaddr_qmi_bypass; 5162 phys_addr_t target_pa = scn->paddr_qmi_bypass; 5163 5164 qdf_mem_free_consistent(scn->qdf_dev, scn->qdf_dev->dev, 5165 FW_SHARED_MEM, target_va, 5166 target_pa, 0); 5167 hif_write32_mb(scn, scn->mem + BYPASS_QMI_TEMP_REGISTER, 0); 5168 } 5169 #else 5170 /** 5171 * hif_post_static_buf_to_target() - post static buffer to WLAN FW 5172 * @scn: pointer to HIF structure 5173 * 5174 * WLAN FW needs 2MB memory from DDR when QMI is disabled. 5175 * 5176 * Return: void 5177 */ 5178 static void hif_post_static_buf_to_target(struct hif_softc *scn) 5179 { 5180 qdf_dma_addr_t target_pa; 5181 5182 scn->vaddr_qmi_bypass = 5183 (uint32_t *)qdf_mem_alloc_consistent(scn->qdf_dev, 5184 scn->qdf_dev->dev, 5185 FW_SHARED_MEM, 5186 &target_pa); 5187 if (!scn->vaddr_qmi_bypass) { 5188 hif_err("Memory allocation failed could not post target buf"); 5189 return; 5190 } 5191 5192 scn->paddr_qmi_bypass = target_pa; 5193 hif_write32_mb(scn, scn->mem + BYPASS_QMI_TEMP_REGISTER, target_pa); 5194 } 5195 5196 /** 5197 * hif_cleanup_static_buf_to_target() - clean up static buffer to WLAN FW 5198 * @scn: pointer to HIF structure 5199 * 5200 * 5201 * Return: void 5202 */ 5203 void hif_cleanup_static_buf_to_target(struct hif_softc *scn) 5204 { 5205 void *target_va = scn->vaddr_qmi_bypass; 5206 phys_addr_t target_pa = scn->paddr_qmi_bypass; 5207 5208 qdf_mem_free_consistent(scn->qdf_dev, scn->qdf_dev->dev, 5209 FW_SHARED_MEM, target_va, 5210 target_pa, 0); 5211 hif_write32_mb(scn, scn->mem + BYPASS_QMI_TEMP_REGISTER, 0); 5212 } 5213 #endif 5214 5215 #else 5216 static inline void hif_post_static_buf_to_target(struct hif_softc *scn) 5217 { 5218 } 5219 5220 void hif_cleanup_static_buf_to_target(struct hif_softc *scn) 5221 { 5222 } 5223 #endif 5224 5225 static int hif_srng_sleep_state_adjust(struct hif_softc *scn, bool sleep_ok, 5226 bool wait_for_it) 5227 { 5228 /* todo */ 5229 return 0; 5230 } 5231 5232 int hif_config_ce_by_id(struct hif_softc *scn, int pipe_num) 5233 { 5234 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 5235 struct hif_opaque_softc *hif_hdl = GET_HIF_OPAQUE_HDL(scn); 5236 struct HIF_CE_pipe_info *pipe_info; 5237 struct CE_state *ce_state = NULL; 5238 struct CE_attr *attr; 5239 int rv = 0; 5240 5241 if (pipe_num >= CE_COUNT_MAX) 5242 return -EINVAL; 5243 5244 pipe_info = &hif_state->pipe_info[pipe_num]; 5245 pipe_info->pipe_num = pipe_num; 5246 pipe_info->HIF_CE_state = hif_state; 5247 attr = &hif_state->host_ce_config[pipe_num]; 5248 ce_state = scn->ce_id_to_state[pipe_num]; 5249 5250 if (ce_state) { 5251 /* Do not reinitialize the CE if its done already */ 5252 rv = QDF_STATUS_E_BUSY; 5253 goto err; 5254 } 5255 5256 pipe_info->ce_hdl = ce_init(scn, pipe_num, attr); 5257 ce_state = scn->ce_id_to_state[pipe_num]; 5258 if (!ce_state) { 5259 A_TARGET_ACCESS_UNLIKELY(scn); 5260 rv = QDF_STATUS_E_FAILURE; 5261 goto err; 5262 } 5263 qdf_spinlock_create(&pipe_info->recv_bufs_needed_lock); 5264 QDF_ASSERT(pipe_info->ce_hdl); 5265 if (!pipe_info->ce_hdl) { 5266 rv = QDF_STATUS_E_FAILURE; 5267 A_TARGET_ACCESS_UNLIKELY(scn); 5268 goto err; 5269 } 5270 5271 ce_state->lro_data = qdf_lro_init(); 5272 5273 if (attr->flags & CE_ATTR_DIAG) { 5274 /* Reserve the ultimate CE for 5275 * Diagnostic Window support 5276 */ 5277 hif_state->ce_diag = pipe_info->ce_hdl; 5278 goto skip; 5279 } 5280 5281 if (hif_is_nss_wifi_enabled(scn) && ce_state && 5282 (ce_state->htt_rx_data)) { 5283 goto skip; 5284 } 5285 5286 pipe_info->buf_sz = (qdf_size_t)(attr->src_sz_max); 5287 if (attr->dest_nentries > 0) { 5288 atomic_set(&pipe_info->recv_bufs_needed, 5289 init_buffer_count(attr->dest_nentries - 1)); 5290 /*SRNG based CE has one entry less */ 5291 if (ce_srng_based(scn)) 5292 atomic_dec(&pipe_info->recv_bufs_needed); 5293 } else { 5294 atomic_set(&pipe_info->recv_bufs_needed, 0); 5295 } 5296 ce_tasklet_init(hif_state, (1 << pipe_num)); 5297 ce_register_irq(hif_state, (1 << pipe_num)); 5298 5299 init_tasklet_worker_by_ceid(hif_hdl, pipe_num); 5300 skip: 5301 return 0; 5302 err: 5303 return rv; 5304 } 5305 5306 #if defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF) 5307 static inline void hif_gen_ce_id_history_idx_mapping(struct hif_softc *scn) 5308 { 5309 struct ce_desc_hist *ce_hist = &scn->hif_ce_desc_hist; 5310 uint8_t ce_id, hist_idx = 0; 5311 5312 for (ce_id = 0; ce_id < scn->ce_count; ce_id++) { 5313 if (IS_CE_DEBUG_ONLY_FOR_CRIT_CE & (1 << ce_id)) 5314 ce_hist->ce_id_hist_map[ce_id] = hist_idx++; 5315 else 5316 ce_hist->ce_id_hist_map[ce_id] = -1; 5317 } 5318 } 5319 #else 5320 static inline void hif_gen_ce_id_history_idx_mapping(struct hif_softc *scn) 5321 { 5322 } 5323 #endif 5324 5325 /** 5326 * hif_config_ce() - configure copy engines 5327 * @scn: hif context 5328 * 5329 * Prepares fw, copy engine hardware and host sw according 5330 * to the attributes selected by hif_ce_prepare_config. 5331 * 5332 * also calls athdiag_procfs_init 5333 * 5334 * return: 0 for success nonzero for failure. 5335 */ 5336 int hif_config_ce(struct hif_softc *scn) 5337 { 5338 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 5339 struct HIF_CE_pipe_info *pipe_info; 5340 int pipe_num; 5341 5342 #ifdef ADRASTEA_SHADOW_REGISTERS 5343 int i; 5344 #endif 5345 QDF_STATUS rv = QDF_STATUS_SUCCESS; 5346 5347 scn->notice_send = true; 5348 scn->ce_service_max_rx_ind_flush = MSG_FLUSH_NUM; 5349 5350 hif_post_static_buf_to_target(scn); 5351 5352 hif_state->fw_indicator_address = FW_INDICATOR_ADDRESS; 5353 5354 hif_config_rri_on_ddr(scn); 5355 5356 if (ce_srng_based(scn)) 5357 scn->bus_ops.hif_target_sleep_state_adjust = 5358 &hif_srng_sleep_state_adjust; 5359 5360 /* Initialise the CE debug history sysfs interface inputs ce_id and 5361 * index. Disable data storing 5362 */ 5363 reset_ce_debug_history(scn); 5364 hif_gen_ce_id_history_idx_mapping(scn); 5365 5366 for (pipe_num = 0; pipe_num < scn->ce_count; pipe_num++) { 5367 struct CE_attr *attr; 5368 5369 pipe_info = &hif_state->pipe_info[pipe_num]; 5370 attr = &hif_state->host_ce_config[pipe_num]; 5371 5372 if (attr->flags & CE_ATTR_INIT_ON_DEMAND) 5373 continue; 5374 5375 if (hif_config_ce_by_id(scn, pipe_num)) 5376 goto err; 5377 } 5378 5379 if (athdiag_procfs_init(scn) != 0) { 5380 A_TARGET_ACCESS_UNLIKELY(scn); 5381 goto err; 5382 } 5383 scn->athdiag_procfs_inited = true; 5384 5385 hif_debug("ce_init done"); 5386 hif_debug("X, ret = %d", rv); 5387 5388 #ifdef ADRASTEA_SHADOW_REGISTERS 5389 hif_debug("Using Shadow Registers instead of CE Registers"); 5390 for (i = 0; i < NUM_SHADOW_REGISTERS; i++) { 5391 hif_debug("Shadow Register%d is mapped to address %x", 5392 i, 5393 (A_TARGET_READ(scn, (SHADOW_ADDRESS(i))) << 2)); 5394 } 5395 #endif 5396 5397 return rv != QDF_STATUS_SUCCESS; 5398 err: 5399 /* Failure, so clean up */ 5400 hif_unconfig_ce(scn); 5401 hif_info("X, ret = %d", rv); 5402 return QDF_STATUS_SUCCESS != QDF_STATUS_E_FAILURE; 5403 } 5404 5405 /** 5406 * hif_config_ce_pktlog() - configure copy engines 5407 * @hif_hdl: hif context 5408 * 5409 * Prepares fw, copy engine hardware and host sw according 5410 * to the attributes selected by hif_ce_prepare_config. 5411 * 5412 * also calls athdiag_procfs_init 5413 * 5414 * return: 0 for success nonzero for failure. 5415 */ 5416 int hif_config_ce_pktlog(struct hif_opaque_softc *hif_hdl) 5417 { 5418 struct hif_softc *scn = HIF_GET_SOFTC(hif_hdl); 5419 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 5420 int pipe_num; 5421 QDF_STATUS qdf_status = QDF_STATUS_E_FAILURE; 5422 struct HIF_CE_pipe_info *pipe_info; 5423 5424 if (!scn) 5425 goto err; 5426 5427 if (scn->pktlog_init) 5428 return QDF_STATUS_SUCCESS; 5429 5430 pipe_num = hif_get_pktlog_ce_num(scn); 5431 if (pipe_num < 0) { 5432 qdf_status = QDF_STATUS_E_FAILURE; 5433 goto err; 5434 } 5435 5436 pipe_info = &hif_state->pipe_info[pipe_num]; 5437 5438 qdf_status = hif_config_ce_by_id(scn, pipe_num); 5439 /* CE Already initialized. Do not try to reinitialized again */ 5440 if (qdf_status == QDF_STATUS_E_BUSY) 5441 return QDF_STATUS_SUCCESS; 5442 5443 qdf_status = hif_config_irq_by_ceid(scn, pipe_num); 5444 if (qdf_status < 0) 5445 goto err; 5446 5447 qdf_status = hif_completion_thread_startup_by_ceid(hif_state, pipe_num); 5448 if (!QDF_IS_STATUS_SUCCESS(qdf_status)) { 5449 hif_err("Failed to start hif thread"); 5450 goto err; 5451 } 5452 5453 /* Post buffers for pktlog copy engine. */ 5454 qdf_status = hif_post_recv_buffers_for_pipe(pipe_info); 5455 if (!QDF_IS_STATUS_SUCCESS(qdf_status)) { 5456 /* cleanup is done in hif_ce_disable */ 5457 hif_err("Failed to post buffers"); 5458 return qdf_status; 5459 } 5460 scn->pktlog_init = true; 5461 return qdf_status != QDF_STATUS_SUCCESS; 5462 5463 err: 5464 hif_debug("X, ret = %d", qdf_status); 5465 return QDF_STATUS_SUCCESS != QDF_STATUS_E_FAILURE; 5466 } 5467 5468 #ifdef IPA_OFFLOAD 5469 /** 5470 * hif_ce_ipa_get_ce_resource() - get uc resource on hif 5471 * @scn: bus context 5472 * @ce_sr: copyengine source ring base physical address 5473 * @ce_sr_ring_size: copyengine source ring size 5474 * @ce_reg_paddr: copyengine register physical address 5475 * 5476 * IPA micro controller data path offload feature enabled, 5477 * HIF should release copy engine related resource information to IPA UC 5478 * IPA UC will access hardware resource with released information 5479 * 5480 * Return: None 5481 */ 5482 void hif_ce_ipa_get_ce_resource(struct hif_softc *scn, 5483 qdf_shared_mem_t **ce_sr, 5484 uint32_t *ce_sr_ring_size, 5485 qdf_dma_addr_t *ce_reg_paddr) 5486 { 5487 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 5488 struct HIF_CE_pipe_info *pipe_info = 5489 &(hif_state->pipe_info[HIF_PCI_IPA_UC_ASSIGNED_CE]); 5490 struct CE_handle *ce_hdl = pipe_info->ce_hdl; 5491 5492 ce_ipa_get_resource(ce_hdl, ce_sr, ce_sr_ring_size, 5493 ce_reg_paddr); 5494 } 5495 #endif /* IPA_OFFLOAD */ 5496 5497 5498 #ifdef ADRASTEA_SHADOW_REGISTERS 5499 5500 /* 5501 * Current shadow register config 5502 * 5503 * ----------------------------------------------------------- 5504 * Shadow Register | CE | src/dst write index 5505 * ----------------------------------------------------------- 5506 * 0 | 0 | src 5507 * 1 No Config - Doesn't point to anything 5508 * 2 No Config - Doesn't point to anything 5509 * 3 | 3 | src 5510 * 4 | 4 | src 5511 * 5 | 5 | src 5512 * 6 No Config - Doesn't point to anything 5513 * 7 | 7 | src 5514 * 8 No Config - Doesn't point to anything 5515 * 9 No Config - Doesn't point to anything 5516 * 10 No Config - Doesn't point to anything 5517 * 11 No Config - Doesn't point to anything 5518 * ----------------------------------------------------------- 5519 * 12 No Config - Doesn't point to anything 5520 * 13 | 1 | dst 5521 * 14 | 2 | dst 5522 * 15 No Config - Doesn't point to anything 5523 * 16 No Config - Doesn't point to anything 5524 * 17 No Config - Doesn't point to anything 5525 * 18 No Config - Doesn't point to anything 5526 * 19 | 7 | dst 5527 * 20 | 8 | dst 5528 * 21 No Config - Doesn't point to anything 5529 * 22 No Config - Doesn't point to anything 5530 * 23 No Config - Doesn't point to anything 5531 * ----------------------------------------------------------- 5532 * 5533 * 5534 * ToDo - Move shadow register config to following in the future 5535 * This helps free up a block of shadow registers towards the end. 5536 * Can be used for other purposes 5537 * 5538 * ----------------------------------------------------------- 5539 * Shadow Register | CE | src/dst write index 5540 * ----------------------------------------------------------- 5541 * 0 | 0 | src 5542 * 1 | 3 | src 5543 * 2 | 4 | src 5544 * 3 | 5 | src 5545 * 4 | 7 | src 5546 * ----------------------------------------------------------- 5547 * 5 | 1 | dst 5548 * 6 | 2 | dst 5549 * 7 | 7 | dst 5550 * 8 | 8 | dst 5551 * ----------------------------------------------------------- 5552 * 9 No Config - Doesn't point to anything 5553 * 12 No Config - Doesn't point to anything 5554 * 13 No Config - Doesn't point to anything 5555 * 14 No Config - Doesn't point to anything 5556 * 15 No Config - Doesn't point to anything 5557 * 16 No Config - Doesn't point to anything 5558 * 17 No Config - Doesn't point to anything 5559 * 18 No Config - Doesn't point to anything 5560 * 19 No Config - Doesn't point to anything 5561 * 20 No Config - Doesn't point to anything 5562 * 21 No Config - Doesn't point to anything 5563 * 22 No Config - Doesn't point to anything 5564 * 23 No Config - Doesn't point to anything 5565 * ----------------------------------------------------------- 5566 */ 5567 #ifndef QCN7605_SUPPORT 5568 u32 shadow_sr_wr_ind_addr(struct hif_softc *scn, u32 ctrl_addr) 5569 { 5570 u32 addr = 0; 5571 u32 ce = COPY_ENGINE_ID(ctrl_addr); 5572 5573 switch (ce) { 5574 case 0: 5575 addr = SHADOW_VALUE0; 5576 break; 5577 case 3: 5578 addr = SHADOW_VALUE3; 5579 break; 5580 case 4: 5581 addr = SHADOW_VALUE4; 5582 break; 5583 case 5: 5584 addr = SHADOW_VALUE5; 5585 break; 5586 case 7: 5587 addr = SHADOW_VALUE7; 5588 break; 5589 default: 5590 hif_err("Invalid CE ctrl_addr (CE=%d)", ce); 5591 QDF_ASSERT(0); 5592 } 5593 return addr; 5594 5595 } 5596 5597 u32 shadow_dst_wr_ind_addr(struct hif_softc *scn, u32 ctrl_addr) 5598 { 5599 u32 addr = 0; 5600 u32 ce = COPY_ENGINE_ID(ctrl_addr); 5601 5602 switch (ce) { 5603 case 1: 5604 addr = SHADOW_VALUE13; 5605 break; 5606 case 2: 5607 addr = SHADOW_VALUE14; 5608 break; 5609 case 5: 5610 addr = SHADOW_VALUE17; 5611 break; 5612 case 7: 5613 addr = SHADOW_VALUE19; 5614 break; 5615 case 8: 5616 addr = SHADOW_VALUE20; 5617 break; 5618 case 9: 5619 addr = SHADOW_VALUE21; 5620 break; 5621 case 10: 5622 addr = SHADOW_VALUE22; 5623 break; 5624 case 11: 5625 addr = SHADOW_VALUE23; 5626 break; 5627 default: 5628 hif_err("Invalid CE ctrl_addr (CE=%d)", ce); 5629 QDF_ASSERT(0); 5630 } 5631 5632 return addr; 5633 5634 } 5635 #else 5636 u32 shadow_sr_wr_ind_addr(struct hif_softc *scn, u32 ctrl_addr) 5637 { 5638 u32 addr = 0; 5639 u32 ce = COPY_ENGINE_ID(ctrl_addr); 5640 5641 switch (ce) { 5642 case 0: 5643 addr = SHADOW_VALUE0; 5644 break; 5645 case 3: 5646 addr = SHADOW_VALUE3; 5647 break; 5648 case 4: 5649 addr = SHADOW_VALUE4; 5650 break; 5651 case 5: 5652 addr = SHADOW_VALUE5; 5653 break; 5654 default: 5655 hif_err("Invalid CE ctrl_addr (CE=%d)", ce); 5656 QDF_ASSERT(0); 5657 } 5658 return addr; 5659 } 5660 5661 u32 shadow_dst_wr_ind_addr(struct hif_softc *scn, u32 ctrl_addr) 5662 { 5663 u32 addr = 0; 5664 u32 ce = COPY_ENGINE_ID(ctrl_addr); 5665 5666 switch (ce) { 5667 case 1: 5668 addr = SHADOW_VALUE13; 5669 break; 5670 case 2: 5671 addr = SHADOW_VALUE14; 5672 break; 5673 case 3: 5674 addr = SHADOW_VALUE15; 5675 break; 5676 case 5: 5677 addr = SHADOW_VALUE17; 5678 break; 5679 case 7: 5680 addr = SHADOW_VALUE19; 5681 break; 5682 case 8: 5683 addr = SHADOW_VALUE20; 5684 break; 5685 case 9: 5686 addr = SHADOW_VALUE21; 5687 break; 5688 case 10: 5689 addr = SHADOW_VALUE22; 5690 break; 5691 case 11: 5692 addr = SHADOW_VALUE23; 5693 break; 5694 default: 5695 hif_err("Invalid CE ctrl_addr (CE=%d)", ce); 5696 QDF_ASSERT(0); 5697 } 5698 5699 return addr; 5700 } 5701 #endif 5702 #endif 5703 5704 #if defined(FEATURE_LRO) 5705 void *hif_ce_get_lro_ctx(struct hif_opaque_softc *hif_hdl, int ctx_id) 5706 { 5707 struct CE_state *ce_state; 5708 struct hif_softc *scn = HIF_GET_SOFTC(hif_hdl); 5709 5710 ce_state = scn->ce_id_to_state[ctx_id]; 5711 5712 return ce_state->lro_data; 5713 } 5714 #endif 5715 5716 /** 5717 * hif_map_service_to_pipe() - returns the ce ids pertaining to 5718 * this service 5719 * @hif_hdl: hif_softc pointer. 5720 * @svc_id: Service ID for which the mapping is needed. 5721 * @ul_pipe: address of the container in which ul pipe is returned. 5722 * @dl_pipe: address of the container in which dl pipe is returned. 5723 * @ul_is_polled: address of the container in which a bool 5724 * indicating if the UL CE for this service 5725 * is polled is returned. 5726 * @dl_is_polled: address of the container in which a bool 5727 * indicating if the DL CE for this service 5728 * is polled is returned. 5729 * 5730 * Return: Indicates whether the service has been found in the table. 5731 * Upon return, ul_is_polled is updated only if ul_pipe is updated. 5732 * There will be warning logs if either leg has not been updated 5733 * because it missed the entry in the table (but this is not an err). 5734 */ 5735 int hif_map_service_to_pipe(struct hif_opaque_softc *hif_hdl, uint16_t svc_id, 5736 uint8_t *ul_pipe, uint8_t *dl_pipe, int *ul_is_polled, 5737 int *dl_is_polled) 5738 { 5739 int status = -EINVAL; 5740 unsigned int i; 5741 struct service_to_pipe element; 5742 struct service_to_pipe *tgt_svc_map_to_use; 5743 uint32_t sz_tgt_svc_map_to_use; 5744 struct hif_softc *scn = HIF_GET_SOFTC(hif_hdl); 5745 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 5746 bool dl_updated = false; 5747 bool ul_updated = false; 5748 5749 hif_select_service_to_pipe_map(scn, &tgt_svc_map_to_use, 5750 &sz_tgt_svc_map_to_use); 5751 5752 *dl_is_polled = 0; /* polling for received messages not supported */ 5753 5754 for (i = 0; i < (sz_tgt_svc_map_to_use/sizeof(element)); i++) { 5755 5756 memcpy(&element, &tgt_svc_map_to_use[i], sizeof(element)); 5757 if (element.service_id == svc_id) { 5758 if (element.pipedir == PIPEDIR_OUT) { 5759 *ul_pipe = element.pipenum; 5760 *ul_is_polled = 5761 (hif_state->host_ce_config[*ul_pipe].flags & 5762 CE_ATTR_DISABLE_INTR) != 0; 5763 ul_updated = true; 5764 } else if (element.pipedir == PIPEDIR_IN) { 5765 *dl_pipe = element.pipenum; 5766 dl_updated = true; 5767 } 5768 status = 0; 5769 } 5770 } 5771 if (ul_updated == false) 5772 hif_debug("ul pipe is NOT updated for service %d", svc_id); 5773 if (dl_updated == false) 5774 hif_debug("dl pipe is NOT updated for service %d", svc_id); 5775 5776 return status; 5777 } 5778 5779 #ifdef SHADOW_REG_DEBUG 5780 inline uint32_t DEBUG_CE_SRC_RING_READ_IDX_GET(struct hif_softc *scn, 5781 uint32_t CE_ctrl_addr) 5782 { 5783 uint32_t read_from_hw, srri_from_ddr = 0; 5784 5785 read_from_hw = A_TARGET_READ(scn, CE_ctrl_addr + CURRENT_SRRI_ADDRESS); 5786 5787 srri_from_ddr = SRRI_FROM_DDR_ADDR(VADDR_FOR_CE(scn, CE_ctrl_addr)); 5788 5789 if (read_from_hw != srri_from_ddr) { 5790 hif_err("read from ddr = %d actual read from register = %d, CE_MISC_INT_STATUS_GET = 0x%x", 5791 srri_from_ddr, read_from_hw, 5792 CE_MISC_INT_STATUS_GET(scn, CE_ctrl_addr)); 5793 QDF_ASSERT(0); 5794 } 5795 return srri_from_ddr; 5796 } 5797 5798 5799 inline uint32_t DEBUG_CE_DEST_RING_READ_IDX_GET(struct hif_softc *scn, 5800 uint32_t CE_ctrl_addr) 5801 { 5802 uint32_t read_from_hw, drri_from_ddr = 0; 5803 5804 read_from_hw = A_TARGET_READ(scn, CE_ctrl_addr + CURRENT_DRRI_ADDRESS); 5805 5806 drri_from_ddr = DRRI_FROM_DDR_ADDR(VADDR_FOR_CE(scn, CE_ctrl_addr)); 5807 5808 if (read_from_hw != drri_from_ddr) { 5809 hif_err("read from ddr = %d actual read from register = %d, CE_MISC_INT_STATUS_GET = 0x%x", 5810 drri_from_ddr, read_from_hw, 5811 CE_MISC_INT_STATUS_GET(scn, CE_ctrl_addr)); 5812 QDF_ASSERT(0); 5813 } 5814 return drri_from_ddr; 5815 } 5816 5817 #endif 5818 5819 /** 5820 * hif_dump_ce_registers() - dump ce registers 5821 * @scn: hif_opaque_softc pointer. 5822 * 5823 * Output the copy engine registers 5824 * 5825 * Return: 0 for success or error code 5826 */ 5827 int hif_dump_ce_registers(struct hif_softc *scn) 5828 { 5829 struct hif_opaque_softc *hif_hdl = GET_HIF_OPAQUE_HDL(scn); 5830 uint32_t ce_reg_address = CE0_BASE_ADDRESS; 5831 uint32_t ce_reg_values[CE_USEFUL_SIZE >> 2]; 5832 uint32_t ce_reg_word_size = CE_USEFUL_SIZE >> 2; 5833 uint16_t i; 5834 QDF_STATUS status; 5835 5836 for (i = 0; i < scn->ce_count; i++, ce_reg_address += CE_OFFSET) { 5837 if (!scn->ce_id_to_state[i]) { 5838 hif_debug("CE%d not used", i); 5839 continue; 5840 } 5841 5842 status = hif_diag_read_mem(hif_hdl, ce_reg_address, 5843 (uint8_t *) &ce_reg_values[0], 5844 ce_reg_word_size * sizeof(uint32_t)); 5845 5846 if (status != QDF_STATUS_SUCCESS) { 5847 hif_err("Dumping CE register failed!"); 5848 return -EACCES; 5849 } 5850 hif_debug("CE%d=>", i); 5851 qdf_trace_hex_dump(QDF_MODULE_ID_HIF, QDF_TRACE_LEVEL_DEBUG, 5852 (uint8_t *) &ce_reg_values[0], 5853 ce_reg_word_size * sizeof(uint32_t)); 5854 qdf_print("ADDR:[0x%08X], SR_WR_INDEX:%d", (ce_reg_address 5855 + SR_WR_INDEX_ADDRESS), 5856 ce_reg_values[SR_WR_INDEX_ADDRESS/4]); 5857 qdf_print("ADDR:[0x%08X], CURRENT_SRRI:%d", (ce_reg_address 5858 + CURRENT_SRRI_ADDRESS), 5859 ce_reg_values[CURRENT_SRRI_ADDRESS/4]); 5860 qdf_print("ADDR:[0x%08X], DST_WR_INDEX:%d", (ce_reg_address 5861 + DST_WR_INDEX_ADDRESS), 5862 ce_reg_values[DST_WR_INDEX_ADDRESS/4]); 5863 qdf_print("ADDR:[0x%08X], CURRENT_DRRI:%d", (ce_reg_address 5864 + CURRENT_DRRI_ADDRESS), 5865 ce_reg_values[CURRENT_DRRI_ADDRESS/4]); 5866 qdf_print("---"); 5867 } 5868 return 0; 5869 } 5870 qdf_export_symbol(hif_dump_ce_registers); 5871 #ifdef QCA_NSS_WIFI_OFFLOAD_SUPPORT 5872 struct hif_pipe_addl_info *hif_get_addl_pipe_info(struct hif_opaque_softc *osc, 5873 struct hif_pipe_addl_info *hif_info, uint32_t pipe) 5874 { 5875 struct hif_softc *scn = HIF_GET_SOFTC(osc); 5876 struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn); 5877 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(osc); 5878 struct HIF_CE_pipe_info *pipe_info = &(hif_state->pipe_info[pipe]); 5879 struct CE_handle *ce_hdl = pipe_info->ce_hdl; 5880 struct CE_state *ce_state = (struct CE_state *)ce_hdl; 5881 struct CE_ring_state *src_ring = ce_state->src_ring; 5882 struct CE_ring_state *dest_ring = ce_state->dest_ring; 5883 5884 if (src_ring) { 5885 hif_info->ul_pipe.nentries = src_ring->nentries; 5886 hif_info->ul_pipe.nentries_mask = src_ring->nentries_mask; 5887 hif_info->ul_pipe.sw_index = src_ring->sw_index; 5888 hif_info->ul_pipe.write_index = src_ring->write_index; 5889 hif_info->ul_pipe.hw_index = src_ring->hw_index; 5890 hif_info->ul_pipe.base_addr_CE_space = 5891 src_ring->base_addr_CE_space; 5892 hif_info->ul_pipe.base_addr_owner_space = 5893 src_ring->base_addr_owner_space; 5894 } 5895 5896 5897 if (dest_ring) { 5898 hif_info->dl_pipe.nentries = dest_ring->nentries; 5899 hif_info->dl_pipe.nentries_mask = dest_ring->nentries_mask; 5900 hif_info->dl_pipe.sw_index = dest_ring->sw_index; 5901 hif_info->dl_pipe.write_index = dest_ring->write_index; 5902 hif_info->dl_pipe.hw_index = dest_ring->hw_index; 5903 hif_info->dl_pipe.base_addr_CE_space = 5904 dest_ring->base_addr_CE_space; 5905 hif_info->dl_pipe.base_addr_owner_space = 5906 dest_ring->base_addr_owner_space; 5907 } 5908 5909 hif_info->pci_mem = pci_resource_start(sc->pdev, 0); 5910 hif_info->ctrl_addr = ce_state->ctrl_addr; 5911 5912 return hif_info; 5913 } 5914 qdf_export_symbol(hif_get_addl_pipe_info); 5915 5916 uint32_t hif_set_nss_wifiol_mode(struct hif_opaque_softc *osc, uint32_t mode) 5917 { 5918 struct hif_softc *scn = HIF_GET_SOFTC(osc); 5919 5920 scn->nss_wifi_ol_mode = mode; 5921 return 0; 5922 } 5923 qdf_export_symbol(hif_set_nss_wifiol_mode); 5924 #endif 5925 5926 void hif_set_attribute(struct hif_opaque_softc *osc, uint8_t hif_attrib) 5927 { 5928 struct hif_softc *scn = HIF_GET_SOFTC(osc); 5929 scn->hif_attribute = hif_attrib; 5930 } 5931 5932 5933 /* disable interrupts (only applicable for legacy copy engine currently */ 5934 void hif_disable_interrupt(struct hif_opaque_softc *osc, uint32_t pipe_num) 5935 { 5936 struct hif_softc *scn = HIF_GET_SOFTC(osc); 5937 struct CE_state *CE_state = scn->ce_id_to_state[pipe_num]; 5938 uint32_t ctrl_addr = CE_state->ctrl_addr; 5939 5940 Q_TARGET_ACCESS_BEGIN(scn); 5941 CE_COPY_COMPLETE_INTR_DISABLE(scn, ctrl_addr); 5942 Q_TARGET_ACCESS_END(scn); 5943 } 5944 qdf_export_symbol(hif_disable_interrupt); 5945 5946 /** 5947 * hif_fw_event_handler() - hif fw event handler 5948 * @hif_state: pointer to hif ce state structure 5949 * 5950 * Process fw events and raise HTC callback to process fw events. 5951 * 5952 * Return: none 5953 */ 5954 static inline void hif_fw_event_handler(struct HIF_CE_state *hif_state) 5955 { 5956 struct hif_msg_callbacks *msg_callbacks = 5957 &hif_state->msg_callbacks_current; 5958 5959 if (!msg_callbacks->fwEventHandler) 5960 return; 5961 5962 msg_callbacks->fwEventHandler(msg_callbacks->Context, 5963 QDF_STATUS_E_FAILURE); 5964 } 5965 5966 #ifndef QCA_WIFI_3_0 5967 /** 5968 * hif_fw_interrupt_handler() - FW interrupt handler 5969 * @irq: irq number 5970 * @arg: the user pointer 5971 * 5972 * Called from the PCI interrupt handler when a 5973 * firmware-generated interrupt to the Host. 5974 * 5975 * only registered for legacy ce devices 5976 * 5977 * Return: status of handled irq 5978 */ 5979 irqreturn_t hif_fw_interrupt_handler(int irq, void *arg) 5980 { 5981 struct hif_softc *scn = arg; 5982 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 5983 uint32_t fw_indicator_address, fw_indicator; 5984 5985 if (Q_TARGET_ACCESS_BEGIN(scn) < 0) 5986 return ATH_ISR_NOSCHED; 5987 5988 fw_indicator_address = hif_state->fw_indicator_address; 5989 /* For sudden unplug this will return ~0 */ 5990 fw_indicator = A_TARGET_READ(scn, fw_indicator_address); 5991 5992 if ((fw_indicator != ~0) && (fw_indicator & FW_IND_EVENT_PENDING)) { 5993 /* ACK: clear Target-side pending event */ 5994 A_TARGET_WRITE(scn, fw_indicator_address, 5995 fw_indicator & ~FW_IND_EVENT_PENDING); 5996 if (Q_TARGET_ACCESS_END(scn) < 0) 5997 return ATH_ISR_SCHED; 5998 5999 if (hif_state->started) { 6000 hif_fw_event_handler(hif_state); 6001 } else { 6002 /* 6003 * Probable Target failure before we're prepared 6004 * to handle it. Generally unexpected. 6005 * fw_indicator used as bitmap, and defined as below: 6006 * FW_IND_EVENT_PENDING 0x1 6007 * FW_IND_INITIALIZED 0x2 6008 * FW_IND_NEEDRECOVER 0x4 6009 */ 6010 AR_DEBUG_PRINTF(ATH_DEBUG_ERR, 6011 ("%s: Early firmware event indicated 0x%x\n", 6012 __func__, fw_indicator)); 6013 } 6014 } else { 6015 if (Q_TARGET_ACCESS_END(scn) < 0) 6016 return ATH_ISR_SCHED; 6017 } 6018 6019 return ATH_ISR_SCHED; 6020 } 6021 #else 6022 irqreturn_t hif_fw_interrupt_handler(int irq, void *arg) 6023 { 6024 return ATH_ISR_SCHED; 6025 } 6026 #endif /* #ifdef QCA_WIFI_3_0 */ 6027 6028 6029 /** 6030 * hif_wlan_disable(): call the platform driver to disable wlan 6031 * @scn: HIF Context 6032 * 6033 * This function passes the con_mode to platform driver to disable 6034 * wlan. 6035 * 6036 * Return: void 6037 */ 6038 void hif_wlan_disable(struct hif_softc *scn) 6039 { 6040 enum pld_driver_mode mode; 6041 uint32_t con_mode = hif_get_conparam(scn); 6042 6043 if (scn->target_status == TARGET_STATUS_RESET) 6044 return; 6045 6046 if (QDF_GLOBAL_FTM_MODE == con_mode) 6047 mode = PLD_FTM; 6048 else if (QDF_IS_EPPING_ENABLED(con_mode)) 6049 mode = PLD_EPPING; 6050 else 6051 mode = PLD_MISSION; 6052 6053 pld_wlan_disable(scn->qdf_dev->dev, mode); 6054 } 6055 6056 int hif_get_wake_ce_id(struct hif_softc *scn, uint8_t *ce_id) 6057 { 6058 int status; 6059 uint8_t ul_pipe, dl_pipe; 6060 int ul_is_polled, dl_is_polled; 6061 6062 /* DL pipe for HTC_CTRL_RSVD_SVC should map to the wake CE */ 6063 status = hif_map_service_to_pipe(GET_HIF_OPAQUE_HDL(scn), 6064 HTC_CTRL_RSVD_SVC, 6065 &ul_pipe, &dl_pipe, 6066 &ul_is_polled, &dl_is_polled); 6067 if (status) { 6068 hif_err("Failed to map pipe: %d", status); 6069 return status; 6070 } 6071 6072 *ce_id = dl_pipe; 6073 6074 return 0; 6075 } 6076 6077 int hif_get_fw_diag_ce_id(struct hif_softc *scn, uint8_t *ce_id) 6078 { 6079 int status; 6080 uint8_t ul_pipe, dl_pipe; 6081 int ul_is_polled, dl_is_polled; 6082 6083 /* DL pipe for WMI_CONTROL_DIAG_SVC should map to the FW DIAG CE_ID */ 6084 status = hif_map_service_to_pipe(GET_HIF_OPAQUE_HDL(scn), 6085 WMI_CONTROL_DIAG_SVC, 6086 &ul_pipe, &dl_pipe, 6087 &ul_is_polled, &dl_is_polled); 6088 if (status) { 6089 hif_err("Failed to map pipe: %d", status); 6090 return status; 6091 } 6092 6093 *ce_id = dl_pipe; 6094 6095 return 0; 6096 } 6097 6098 #ifdef HIF_CE_LOG_INFO 6099 /** 6100 * ce_get_index_info(): Get CE index info 6101 * @scn: HIF Context 6102 * @ce_state: CE opaque handle 6103 * @info: CE info 6104 * 6105 * Return: 0 for success and non zero for failure 6106 */ 6107 static 6108 int ce_get_index_info(struct hif_softc *scn, void *ce_state, 6109 struct ce_index *info) 6110 { 6111 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 6112 6113 return hif_state->ce_services->ce_get_index_info(scn, ce_state, info); 6114 } 6115 6116 void hif_log_ce_info(struct hif_softc *scn, uint8_t *data, 6117 unsigned int *offset) 6118 { 6119 struct hang_event_info info = {0}; 6120 static uint32_t tracked_ce = BIT(CE_ID_1) | BIT(CE_ID_2) | 6121 BIT(CE_ID_3) | BIT(CE_ID_4) | BIT(CE_ID_9) | BIT(CE_ID_10); 6122 uint8_t curr_index = 0; 6123 uint8_t i; 6124 uint16_t size; 6125 6126 info.active_tasklet_count = qdf_atomic_read(&scn->active_tasklet_cnt); 6127 info.active_grp_tasklet_cnt = 6128 qdf_atomic_read(&scn->active_grp_tasklet_cnt); 6129 6130 for (i = 0; i < scn->ce_count; i++) { 6131 if (!(tracked_ce & BIT(i)) || !scn->ce_id_to_state[i]) 6132 continue; 6133 6134 if (ce_get_index_info(scn, scn->ce_id_to_state[i], 6135 &info.ce_info[curr_index])) 6136 continue; 6137 6138 curr_index++; 6139 } 6140 6141 info.ce_count = curr_index; 6142 size = sizeof(info) - 6143 (CE_COUNT_MAX - info.ce_count) * sizeof(struct ce_index); 6144 6145 if (*offset + size > QDF_WLAN_HANG_FW_OFFSET) 6146 return; 6147 6148 QDF_HANG_EVT_SET_HDR(&info.tlv_header, HANG_EVT_TAG_CE_INFO, 6149 size - QDF_HANG_EVENT_TLV_HDR_SIZE); 6150 6151 qdf_mem_copy(data + *offset, &info, size); 6152 *offset = *offset + size; 6153 } 6154 #endif 6155 6156 #ifdef FEATURE_DIRECT_LINK 6157 QDF_STATUS 6158 hif_set_irq_config_by_ceid(struct hif_opaque_softc *scn, uint8_t ce_id, 6159 uint64_t addr, uint32_t data) 6160 { 6161 struct hif_softc *hif_ctx = HIF_GET_SOFTC(scn); 6162 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 6163 6164 if (hif_state->ce_services->ce_set_irq_config_by_ceid) 6165 return hif_state->ce_services->ce_set_irq_config_by_ceid( 6166 hif_ctx, 6167 ce_id, 6168 addr, 6169 data); 6170 6171 return QDF_STATUS_E_NOSUPPORT; 6172 } 6173 6174 uint16_t hif_get_direct_link_ce_dest_srng_buffers(struct hif_opaque_softc *scn, 6175 uint64_t **dma_addr, 6176 uint32_t *buf_size) 6177 { 6178 struct hif_softc *hif_ctx = HIF_GET_SOFTC(scn); 6179 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 6180 struct ce_ops *ce_services = hif_state->ce_services; 6181 6182 if (ce_services->ce_get_direct_link_dest_buffers) 6183 return ce_services->ce_get_direct_link_dest_buffers(hif_ctx, 6184 dma_addr, 6185 buf_size); 6186 6187 return 0; 6188 } 6189 6190 QDF_STATUS 6191 hif_get_direct_link_ce_srng_info(struct hif_opaque_softc *scn, 6192 struct hif_direct_link_ce_info *info, 6193 uint8_t max_ce_info_len) 6194 { 6195 struct hif_softc *hif_ctx = HIF_GET_SOFTC(scn); 6196 struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); 6197 struct ce_ops *ce_services = hif_state->ce_services; 6198 6199 if (ce_services->ce_get_direct_link_ring_info) 6200 return ce_services->ce_get_direct_link_ring_info(hif_ctx, 6201 info, 6202 max_ce_info_len); 6203 6204 return QDF_STATUS_E_NOSUPPORT; 6205 } 6206 #endif 6207