1 /* 2 * Copyright (c) 2013,2016 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #if defined(AR9888_HEADERS_DEF) 20 #define AR9888 1 21 22 #define WLAN_HEADERS 1 23 #include "common_drv.h" 24 #include "AR9888/v2/soc_addrs.h" 25 #include "AR9888/v2/hw/apb_athr_wlan_map.h" 26 #include "AR9888/v2/hw/gpio_athr_wlan_reg.h" 27 #include "AR9888/v2/hw/rtc_soc_reg.h" 28 #include "AR9888/v2/hw/rtc_wlan_reg.h" 29 #include "AR9888/v2/hw/si_reg.h" 30 #include "AR9888/v2/extra/hw/pcie_local_reg.h" 31 32 #include "AR9888/v2/extra/hw/soc_core_reg.h" 33 #include "AR9888/v2/hw/soc_pcie_reg.h" 34 #include "AR9888/v2/extra/hw/ce_reg_csr.h" 35 #include "AR9888/v2/hw/ce_wrapper_reg_csr.h" 36 37 #include <AR9888/v2/hw/mac_descriptors/rx_attention.h> 38 #include <AR9888/v2/hw/mac_descriptors/rx_frag_info.h> 39 #include <AR9888/v2/hw/mac_descriptors/rx_msdu_start.h> 40 #include <AR9888/v2/hw/mac_descriptors/rx_msdu_end.h> 41 #include <AR9888/v2/hw/mac_descriptors/rx_mpdu_start.h> 42 #include <AR9888/v2/hw/mac_descriptors/rx_mpdu_end.h> 43 #include <AR9888/v2/hw/mac_descriptors/rx_ppdu_start.h> 44 #include <AR9888/v2/hw/mac_descriptors/rx_ppdu_end.h> 45 46 /* TBDXXX: Eventually, this Base Address will be defined in HW header files */ 47 #define PCIE_LOCAL_BASE_ADDRESS 0x80000 48 49 #define FW_EVENT_PENDING_ADDRESS (SOC_CORE_BASE_ADDRESS+SCRATCH_3_ADDRESS) 50 #define DRAM_BASE_ADDRESS TARG_DRAM_START 51 52 /* Backwards compatibility -- TBDXXX */ 53 54 #define MISSING 0 55 56 #define SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET 57 #define WLAN_SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET 58 #define WLAN_RESET_CONTROL_OFFSET SOC_RESET_CONTROL_OFFSET 59 #define CLOCK_CONTROL_OFFSET SOC_CLOCK_CONTROL_OFFSET 60 #define CLOCK_CONTROL_SI0_CLK_MASK SOC_CLOCK_CONTROL_SI0_CLK_MASK 61 #define RESET_CONTROL_MBOX_RST_MASK MISSING 62 #define RESET_CONTROL_SI0_RST_MASK SOC_RESET_CONTROL_SI0_RST_MASK 63 #define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS 64 #define GPIO_PIN0_OFFSET WLAN_GPIO_PIN0_ADDRESS 65 #define GPIO_PIN1_OFFSET WLAN_GPIO_PIN1_ADDRESS 66 #define GPIO_PIN0_CONFIG_MASK WLAN_GPIO_PIN0_CONFIG_MASK 67 #define GPIO_PIN1_CONFIG_MASK WLAN_GPIO_PIN1_CONFIG_MASK 68 #define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS 69 #define SCRATCH_BASE_ADDRESS SOC_CORE_BASE_ADDRESS 70 #define LOCAL_SCRATCH_OFFSET 0x18 71 #define CPU_CLOCK_OFFSET SOC_CPU_CLOCK_OFFSET 72 #define LPO_CAL_OFFSET SOC_LPO_CAL_OFFSET 73 #define GPIO_PIN10_OFFSET WLAN_GPIO_PIN10_ADDRESS 74 #define GPIO_PIN11_OFFSET WLAN_GPIO_PIN11_ADDRESS 75 #define GPIO_PIN12_OFFSET WLAN_GPIO_PIN12_ADDRESS 76 #define GPIO_PIN13_OFFSET WLAN_GPIO_PIN13_ADDRESS 77 #define CPU_CLOCK_STANDARD_LSB SOC_CPU_CLOCK_STANDARD_LSB 78 #define CPU_CLOCK_STANDARD_MASK SOC_CPU_CLOCK_STANDARD_MASK 79 #define LPO_CAL_ENABLE_LSB SOC_LPO_CAL_ENABLE_LSB 80 #define LPO_CAL_ENABLE_MASK SOC_LPO_CAL_ENABLE_MASK 81 #define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS 82 #define MBOX_BASE_ADDRESS MISSING 83 #define INT_STATUS_ENABLE_ERROR_LSB MISSING 84 #define INT_STATUS_ENABLE_ERROR_MASK MISSING 85 #define INT_STATUS_ENABLE_CPU_LSB MISSING 86 #define INT_STATUS_ENABLE_CPU_MASK MISSING 87 #define INT_STATUS_ENABLE_COUNTER_LSB MISSING 88 #define INT_STATUS_ENABLE_COUNTER_MASK MISSING 89 #define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING 90 #define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING 91 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING 92 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING 93 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING 94 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING 95 #define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING 96 #define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING 97 #define INT_STATUS_ENABLE_ADDRESS MISSING 98 #define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING 99 #define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING 100 #define HOST_INT_STATUS_ADDRESS MISSING 101 #define CPU_INT_STATUS_ADDRESS MISSING 102 #define ERROR_INT_STATUS_ADDRESS MISSING 103 #define ERROR_INT_STATUS_WAKEUP_MASK MISSING 104 #define ERROR_INT_STATUS_WAKEUP_LSB MISSING 105 #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING 106 #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING 107 #define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING 108 #define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING 109 #define COUNT_DEC_ADDRESS MISSING 110 #define HOST_INT_STATUS_CPU_MASK MISSING 111 #define HOST_INT_STATUS_CPU_LSB MISSING 112 #define HOST_INT_STATUS_ERROR_MASK MISSING 113 #define HOST_INT_STATUS_ERROR_LSB MISSING 114 #define HOST_INT_STATUS_COUNTER_MASK MISSING 115 #define HOST_INT_STATUS_COUNTER_LSB MISSING 116 #define RX_LOOKAHEAD_VALID_ADDRESS MISSING 117 #define WINDOW_DATA_ADDRESS MISSING 118 #define WINDOW_READ_ADDR_ADDRESS MISSING 119 #define WINDOW_WRITE_ADDR_ADDRESS MISSING 120 /* MAC descriptor */ 121 #define RX_ATTENTION_0_PHY_DATA_TYPE_MASK MISSING 122 #define RX_MSDU_END_8_LRO_ELIGIBLE_MASK MISSING 123 #define RX_MSDU_END_8_LRO_ELIGIBLE_LSB MISSING 124 #define RX_MSDU_END_8_L3_HEADER_PADDING_LSB MISSING 125 #define RX_MSDU_END_8_L3_HEADER_PADDING_MASK MISSING 126 #define RX_PPDU_END_ANTENNA_OFFSET_DWORD (RX_PPDU_END_19_RX_ANTENNA_OFFSET >> 2) 127 #define MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK MISSING 128 #define MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK MISSING 129 #define MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK MISSING 130 #define MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK MISSING 131 #define MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB MISSING 132 #define MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB MISSING 133 #define MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB MISSING 134 #define MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB MISSING 135 /* GPIO Register */ 136 137 #define GPIO_ENABLE_W1TS_LOW_ADDRESS WLAN_GPIO_ENABLE_W1TS_LOW_ADDRESS 138 #define GPIO_PIN0_CONFIG_LSB WLAN_GPIO_PIN0_CONFIG_LSB 139 #define GPIO_PIN0_PAD_PULL_LSB WLAN_GPIO_PIN0_PAD_PULL_LSB 140 #define GPIO_PIN0_PAD_PULL_MASK WLAN_GPIO_PIN0_PAD_PULL_MASK 141 /* CE descriptor */ 142 #define CE_SRC_DESC_SIZE_DWORD 2 143 #define CE_DEST_DESC_SIZE_DWORD 2 144 #define CE_SRC_DESC_SRC_PTR_OFFSET_DWORD 0 145 #define CE_SRC_DESC_INFO_OFFSET_DWORD 1 146 #define CE_DEST_DESC_DEST_PTR_OFFSET_DWORD 0 147 #define CE_DEST_DESC_INFO_OFFSET_DWORD 1 148 #define CE_SRC_DESC_INFO_HOST_INT_DISABLE_MASK MISSING 149 #define CE_SRC_DESC_INFO_HOST_INT_DISABLE_SHIFT MISSING 150 #define CE_SRC_DESC_INFO_TARGET_INT_DISABLE_MASK MISSING 151 #define CE_SRC_DESC_INFO_TARGET_INT_DISABLE_SHIFT MISSING 152 #define CE_DEST_DESC_INFO_HOST_INT_DISABLE_MASK MISSING 153 #define CE_DEST_DESC_INFO_HOST_INT_DISABLE_SHIFT MISSING 154 #define CE_DEST_DESC_INFO_TARGET_INT_DISABLE_MASK MISSING 155 #define CE_DEST_DESC_INFO_TARGET_INT_DISABLE_SHIFT MISSING 156 #if _BYTE_ORDER == _BIG_ENDIAN 157 #define CE_SRC_DESC_INFO_NBYTES_MASK 0xFFFF0000 158 #define CE_SRC_DESC_INFO_NBYTES_SHIFT 16 159 #define CE_SRC_DESC_INFO_GATHER_MASK 0x00008000 160 #define CE_SRC_DESC_INFO_GATHER_SHIFT 15 161 #define CE_SRC_DESC_INFO_BYTE_SWAP_MASK 0x00004000 162 #define CE_SRC_DESC_INFO_BYTE_SWAP_SHIFT 14 163 #define CE_SRC_DESC_INFO_META_DATA_MASK 0x00003FFF 164 #define CE_SRC_DESC_INFO_META_DATA_SHIFT 0 165 #else 166 #define CE_SRC_DESC_INFO_NBYTES_MASK 0x0000FFFF 167 #define CE_SRC_DESC_INFO_NBYTES_SHIFT 0 168 #define CE_SRC_DESC_INFO_GATHER_MASK 0x00010000 169 #define CE_SRC_DESC_INFO_GATHER_SHIFT 16 170 #define CE_SRC_DESC_INFO_BYTE_SWAP_MASK 0x00020000 171 #define CE_SRC_DESC_INFO_BYTE_SWAP_SHIFT 17 172 #define CE_SRC_DESC_INFO_META_DATA_MASK 0xFFFC0000 173 #define CE_SRC_DESC_INFO_META_DATA_SHIFT 18 174 #endif 175 #if _BYTE_ORDER == _BIG_ENDIAN 176 #define CE_DEST_DESC_INFO_NBYTES_MASK 0xFFFF0000 177 #define CE_DEST_DESC_INFO_NBYTES_SHIFT 16 178 #define CE_DEST_DESC_INFO_GATHER_MASK 0x00008000 179 #define CE_DEST_DESC_INFO_GATHER_SHIFT 15 180 #define CE_DEST_DESC_INFO_BYTE_SWAP_MASK 0x00004000 181 #define CE_DEST_DESC_INFO_BYTE_SWAP_SHIFT 14 182 #define CE_DEST_DESC_INFO_META_DATA_MASK 0x00003FFF 183 #define CE_DEST_DESC_INFO_META_DATA_SHIFT 0 184 #else 185 #define CE_DEST_DESC_INFO_NBYTES_MASK 0x0000FFFF 186 #define CE_DEST_DESC_INFO_NBYTES_SHIFT 0 187 #define CE_DEST_DESC_INFO_GATHER_MASK 0x00010000 188 #define CE_DEST_DESC_INFO_GATHER_SHIFT 16 189 #define CE_DEST_DESC_INFO_BYTE_SWAP_MASK 0x00020000 190 #define CE_DEST_DESC_INFO_BYTE_SWAP_SHIFT 17 191 #define CE_DEST_DESC_INFO_META_DATA_MASK 0xFFFC0000 192 #define CE_DEST_DESC_INFO_META_DATA_SHIFT 18 193 #endif 194 195 #define MY_TARGET_DEF AR9888_TARGETdef 196 #define MY_HOST_DEF AR9888_HOSTdef 197 #define MY_CEREG_DEF AR9888_CE_TARGETdef 198 #define MY_TARGET_BOARD_DATA_SZ AR9888_BOARD_DATA_SZ 199 #define MY_TARGET_BOARD_EXT_DATA_SZ AR9888_BOARD_EXT_DATA_SZ 200 #include "targetdef.h" 201 #include "hostdef.h" 202 #else 203 #include "common_drv.h" 204 #include "targetdef.h" 205 #include "hostdef.h" 206 struct targetdef_s *AR9888_TARGETdef; 207 struct hostdef_s *AR9888_HOSTdef; 208 #endif /*AR9888_HEADERS_DEF */ 209