1 /* 2 * Copyright (c) 2013-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _AR6320V2DEF_H_ 20 #define _AR6320V2DEF_H_ 21 22 /* Base Addresses */ 23 #define AR6320V2_RTC_SOC_BASE_ADDRESS 0x00000800 24 #define AR6320V2_RTC_WMAC_BASE_ADDRESS 0x00001000 25 #define AR6320V2_MAC_COEX_BASE_ADDRESS 0x0000f000 26 #define AR6320V2_BT_COEX_BASE_ADDRESS 0x00002000 27 #define AR6320V2_SOC_PCIE_BASE_ADDRESS 0x00038000 28 #define AR6320V2_SOC_CORE_BASE_ADDRESS 0x0003a000 29 #define AR6320V2_WLAN_UART_BASE_ADDRESS 0x0000c000 30 #define AR6320V2_WLAN_SI_BASE_ADDRESS 0x00010000 31 #define AR6320V2_WLAN_GPIO_BASE_ADDRESS 0x00005000 32 #define AR6320V2_WLAN_ANALOG_INTF_BASE_ADDRESS 0x00006000 33 #define AR6320V2_WLAN_MAC_BASE_ADDRESS 0x00010000 34 #define AR6320V2_EFUSE_BASE_ADDRESS 0x00024000 35 #define AR6320V2_FPGA_REG_BASE_ADDRESS 0x00039000 36 #define AR6320V2_WLAN_UART2_BASE_ADDRESS 0x00054c00 37 #define AR6320V2_DBI_BASE_ADDRESS 0x0003c000 38 39 #define AR6320V2_SCRATCH_3_ADDRESS 0x0028 40 #define AR6320V2_TARG_DRAM_START 0x00400000 41 #define AR6320V2_SOC_SYSTEM_SLEEP_OFFSET 0x000000c0 42 #define AR6320V2_SOC_RESET_CONTROL_OFFSET 0x00000000 43 #define AR6320V2_SOC_CLOCK_CONTROL_OFFSET 0x00000028 44 #define AR6320V2_SOC_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001 45 #define AR6320V2_SOC_RESET_CONTROL_SI0_RST_MASK 0x00000000 46 #define AR6320V2_WLAN_GPIO_PIN0_ADDRESS 0x00000068 47 #define AR6320V2_WLAN_GPIO_PIN1_ADDRESS 0x0000006c 48 #define AR6320V2_WLAN_GPIO_PIN0_CONFIG_MASK 0x00007800 49 #define AR6320V2_WLAN_GPIO_PIN1_CONFIG_MASK 0x00007800 50 #define AR6320V2_SOC_CPU_CLOCK_OFFSET 0x00000020 51 #define AR6320V2_SOC_LPO_CAL_OFFSET 0x000000e0 52 #define AR6320V2_WLAN_GPIO_PIN10_ADDRESS 0x00000090 53 #define AR6320V2_WLAN_GPIO_PIN11_ADDRESS 0x00000094 54 #define AR6320V2_WLAN_GPIO_PIN12_ADDRESS 0x00000098 55 #define AR6320V2_WLAN_GPIO_PIN13_ADDRESS 0x0000009c 56 #define AR6320V2_SOC_CPU_CLOCK_STANDARD_LSB 0 57 #define AR6320V2_SOC_CPU_CLOCK_STANDARD_MASK 0x00000003 58 #define AR6320V2_SOC_LPO_CAL_ENABLE_LSB 20 59 #define AR6320V2_SOC_LPO_CAL_ENABLE_MASK 0x00100000 60 61 #define AR6320V2_WLAN_SYSTEM_SLEEP_DISABLE_LSB 0 62 #define AR6320V2_WLAN_SYSTEM_SLEEP_DISABLE_MASK 0x00000001 63 #define AR6320V2_WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000008 64 #define AR6320V2_WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000004 65 #define AR6320V2_SI_CONFIG_BIDIR_OD_DATA_LSB 18 66 #define AR6320V2_SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000 67 #define AR6320V2_SI_CONFIG_I2C_LSB 16 68 #define AR6320V2_SI_CONFIG_I2C_MASK 0x00010000 69 #define AR6320V2_SI_CONFIG_POS_SAMPLE_LSB 7 70 #define AR6320V2_SI_CONFIG_POS_SAMPLE_MASK 0x00000080 71 #define AR6320V2_SI_CONFIG_INACTIVE_CLK_LSB 4 72 #define AR6320V2_SI_CONFIG_INACTIVE_CLK_MASK 0x00000010 73 #define AR6320V2_SI_CONFIG_INACTIVE_DATA_LSB 5 74 #define AR6320V2_SI_CONFIG_INACTIVE_DATA_MASK 0x00000020 75 #define AR6320V2_SI_CONFIG_DIVIDER_LSB 0 76 #define AR6320V2_SI_CONFIG_DIVIDER_MASK 0x0000000f 77 #define AR6320V2_SI_CONFIG_OFFSET 0x00000000 78 #define AR6320V2_SI_TX_DATA0_OFFSET 0x00000008 79 #define AR6320V2_SI_TX_DATA1_OFFSET 0x0000000c 80 #define AR6320V2_SI_RX_DATA0_OFFSET 0x00000010 81 #define AR6320V2_SI_RX_DATA1_OFFSET 0x00000014 82 #define AR6320V2_SI_CS_OFFSET 0x00000004 83 #define AR6320V2_SI_CS_DONE_ERR_MASK 0x00000400 84 #define AR6320V2_SI_CS_DONE_INT_MASK 0x00000200 85 #define AR6320V2_SI_CS_START_LSB 8 86 #define AR6320V2_SI_CS_START_MASK 0x00000100 87 #define AR6320V2_SI_CS_RX_CNT_LSB 4 88 #define AR6320V2_SI_CS_RX_CNT_MASK 0x000000f0 89 #define AR6320V2_SI_CS_TX_CNT_LSB 0 90 #define AR6320V2_SI_CS_TX_CNT_MASK 0x0000000f 91 #define AR6320V2_CE_COUNT 8 92 #define AR6320V2_SR_WR_INDEX_ADDRESS 0x003c 93 #define AR6320V2_DST_WATERMARK_ADDRESS 0x0050 94 #define AR6320V2_RX_MSDU_END_4_FIRST_MSDU_LSB 14 95 #define AR6320V2_RX_MSDU_END_4_FIRST_MSDU_MASK 0x00004000 96 #define AR6320V2_RX_MPDU_START_0_RETRY_LSB 14 97 #define AR6320V2_RX_MPDU_START_0_RETRY_MASK 0x00004000 98 #define AR6320V2_RX_MPDU_START_0_SEQ_NUM_LSB 16 99 #define AR6320V2_RX_MPDU_START_0_SEQ_NUM_MASK 0x0fff0000 100 #define AR6320V2_RX_MPDU_START_2_PN_47_32_LSB 0 101 #define AR6320V2_RX_MPDU_START_2_PN_47_32_MASK 0x0000ffff 102 #define AR6320V2_RX_MPDU_START_2_TID_LSB 28 103 #define AR6320V2_RX_MPDU_START_2_TID_MASK 0xf0000000 104 #define AR6320V2_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB 16 105 #define AR6320V2_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK 0xffff0000 106 #define AR6320V2_RX_MSDU_END_4_LAST_MSDU_LSB 15 107 #define AR6320V2_RX_MSDU_END_4_LAST_MSDU_MASK 0x00008000 108 #define AR6320V2_RX_ATTENTION_0_MCAST_BCAST_LSB 2 109 #define AR6320V2_RX_ATTENTION_0_MCAST_BCAST_MASK 0x00000004 110 #define AR6320V2_RX_ATTENTION_0_FRAGMENT_LSB 13 111 #define AR6320V2_RX_ATTENTION_0_FRAGMENT_MASK 0x00002000 112 #define AR6320V2_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK 0x08000000 113 #define AR6320V2_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB 16 114 #define AR6320V2_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK 0x00ff0000 115 #define AR6320V2_RX_MSDU_START_0_MSDU_LENGTH_LSB 0 116 #define AR6320V2_RX_MSDU_START_0_MSDU_LENGTH_MASK 0x00003fff 117 118 #define AR6320V2_RX_MSDU_START_2_DECAP_FORMAT_OFFSET 0x00000008 119 #define AR6320V2_RX_MSDU_START_2_DECAP_FORMAT_LSB 8 120 #define AR6320V2_RX_MSDU_START_2_DECAP_FORMAT_MASK 0x00000300 121 #define AR6320V2_RX_MPDU_START_0_ENCRYPTED_LSB 13 122 #define AR6320V2_RX_MPDU_START_0_ENCRYPTED_MASK 0x00002000 123 #define AR6320V2_RX_ATTENTION_0_MORE_DATA_MASK 0x00000400 124 #define AR6320V2_RX_ATTENTION_0_MSDU_DONE_MASK 0x80000000 125 #define AR6320V2_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK 0x00040000 126 #define AR6320V2_DST_WR_INDEX_ADDRESS 0x0040 127 #define AR6320V2_SRC_WATERMARK_ADDRESS 0x004c 128 #define AR6320V2_SRC_WATERMARK_LOW_MASK 0xffff0000 129 #define AR6320V2_SRC_WATERMARK_HIGH_MASK 0x0000ffff 130 #define AR6320V2_DST_WATERMARK_LOW_MASK 0xffff0000 131 #define AR6320V2_DST_WATERMARK_HIGH_MASK 0x0000ffff 132 #define AR6320V2_CURRENT_SRRI_ADDRESS 0x0044 133 #define AR6320V2_CURRENT_DRRI_ADDRESS 0x0048 134 #define AR6320V2_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK 0x00000002 135 #define AR6320V2_HOST_IS_SRC_RING_LOW_WATERMARK_MASK 0x00000004 136 #define AR6320V2_HOST_IS_DST_RING_HIGH_WATERMARK_MASK 0x00000008 137 #define AR6320V2_HOST_IS_DST_RING_LOW_WATERMARK_MASK 0x00000010 138 #define AR6320V2_HOST_IS_ADDRESS 0x0030 139 #define AR6320V2_HOST_IS_COPY_COMPLETE_MASK 0x00000001 140 #define AR6320V2_HOST_IE_ADDRESS 0x002c 141 #define AR6320V2_HOST_IE_COPY_COMPLETE_MASK 0x00000001 142 #define AR6320V2_SR_BA_ADDRESS 0x0000 143 #define AR6320V2_SR_SIZE_ADDRESS 0x0004 144 #define AR6320V2_DR_BA_ADDRESS 0x0008 145 #define AR6320V2_DR_SIZE_ADDRESS 0x000c 146 #define AR6320V2_MISC_IE_ADDRESS 0x0034 147 #define AR6320V2_MISC_IS_AXI_ERR_MASK 0x00000400 148 #define AR6320V2_MISC_IS_DST_ADDR_ERR_MASK 0x00000200 149 #define AR6320V2_MISC_IS_SRC_LEN_ERR_MASK 0x00000100 150 #define AR6320V2_MISC_IS_DST_MAX_LEN_VIO_MASK 0x00000080 151 #define AR6320V2_MISC_IS_DST_RING_OVERFLOW_MASK 0x00000040 152 #define AR6320V2_MISC_IS_SRC_RING_OVERFLOW_MASK 0x00000020 153 #define AR6320V2_SRC_WATERMARK_LOW_LSB 16 154 #define AR6320V2_SRC_WATERMARK_HIGH_LSB 0 155 #define AR6320V2_DST_WATERMARK_LOW_LSB 16 156 #define AR6320V2_DST_WATERMARK_HIGH_LSB 0 157 #define AR6320V2_SOC_GLOBAL_RESET_ADDRESS 0x0008 158 #define AR6320V2_RTC_STATE_ADDRESS 0x0000 159 #define AR6320V2_RTC_STATE_COLD_RESET_MASK 0x00002000 160 #define AR6320V2_RTC_STATE_V_MASK 0x00000007 161 #define AR6320V2_RTC_STATE_V_LSB 0 162 #define AR6320V2_RTC_STATE_V_ON 3 163 #define AR6320V2_FW_IND_EVENT_PENDING 1 164 #define AR6320V2_FW_IND_INITIALIZED 2 165 #define AR6320V2_CPU_INTR_ADDRESS 0x0010 166 #define AR6320V2_SOC_LF_TIMER_CONTROL0_ADDRESS 0x00000050 167 #define AR6320V2_SOC_LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004 168 #define AR6320V2_SOC_LF_TIMER_STATUS0_ADDRESS 0x00000054 169 #define AR6320V2_SOC_RESET_CONTROL_ADDRESS 0x00000000 170 #define AR6320V2_SOC_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040 171 #define AR6320V2_CORE_CTRL_ADDRESS 0x0000 172 #define AR6320V2_CORE_CTRL_CPU_INTR_MASK 0x00002000 173 #define AR6320V2_LOCAL_SCRATCH_OFFSET 0x000000c0 174 #define AR6320V2_CLOCK_GPIO_OFFSET 0xffffffff 175 #define AR6320V2_CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0 176 #define AR6320V2_CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0 177 #define AR6320V2_SOC_CHIP_ID_ADDRESS 0x000000f0 178 #define AR6320V2_SOC_CHIP_ID_VERSION_MASK 0xfffc0000 179 #define AR6320V2_SOC_CHIP_ID_VERSION_LSB 18 180 #define AR6320V2_SOC_CHIP_ID_REVISION_MASK 0x00000f00 181 #define AR6320V2_SOC_CHIP_ID_REVISION_LSB 8 182 #if defined(HIF_SDIO) 183 #define AR6320V2_FW_IND_HELPER 4 184 #endif 185 #if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB) 186 #define AR6320V2_CE_WRAPPER_BASE_ADDRESS 0x00034000 187 #define AR6320V2_CE0_BASE_ADDRESS 0x00034400 188 #define AR6320V2_CE1_BASE_ADDRESS 0x00034800 189 #define AR6320V2_CE2_BASE_ADDRESS 0x00034c00 190 #define AR6320V2_CE3_BASE_ADDRESS 0x00035000 191 #define AR6320V2_CE4_BASE_ADDRESS 0x00035400 192 #define AR6320V2_CE5_BASE_ADDRESS 0x00035800 193 #define AR6320V2_CE6_BASE_ADDRESS 0x00035c00 194 #define AR6320V2_CE7_BASE_ADDRESS 0x00036000 195 #define AR6320V2_WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS 0x00007800 196 #define AR6320V2_CE_CTRL1_ADDRESS 0x0010 197 #define AR6320V2_CE_CTRL1_DMAX_LENGTH_MASK 0x0000ffff 198 #define AR6320V2_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS 0x0000 199 #define AR6320V2_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK 0x0000ff00 200 #define AR6320V2_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB 8 201 #define AR6320V2_CE_CTRL1_DMAX_LENGTH_LSB 0 202 #define AR6320V2_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK 0x00010000 203 #define AR6320V2_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK 0x00020000 204 #define AR6320V2_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB 16 205 #define AR6320V2_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB 17 206 #define AR6320V2_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK 0x00000020 207 #define AR6320V2_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB 5 208 #define AR6320V2_PCIE_SOC_WAKE_RESET 0x00000000 209 #define AR6320V2_PCIE_SOC_WAKE_ADDRESS 0x0004 210 #define AR6320V2_PCIE_SOC_WAKE_V_MASK 0x00000001 211 #define AR6320V2_MUX_ID_MASK 0x0000 212 #define AR6320V2_TRANSACTION_ID_MASK 0x3fff 213 #define AR6320V2_PCIE_LOCAL_BASE_ADDRESS 0x80000 214 #define AR6320V2_FW_IND_HELPER 4 215 #define AR6320V2_PCIE_INTR_ENABLE_ADDRESS 0x0008 216 #define AR6320V2_PCIE_INTR_CLR_ADDRESS 0x0014 217 #define AR6320V2_PCIE_INTR_FIRMWARE_MASK 0x00000400 218 #define AR6320V2_PCIE_INTR_CE0_MASK 0x00000800 219 #define AR6320V2_PCIE_INTR_CE_MASK_ALL 0x0007f800 220 #define AR6320V2_PCIE_INTR_CAUSE_ADDRESS 0x000c 221 #define AR6320V2_SOC_RESET_CONTROL_CE_RST_MASK 0x00000001 222 #define AR6320V2_SOC_POWER_REG_OFFSET 0x0000010c 223 /* Copy Engine Debug */ 224 #define AR6320V2_WLAN_DEBUG_INPUT_SEL_OFFSET 0x0000010c 225 #define AR6320V2_WLAN_DEBUG_INPUT_SEL_SRC_MSB 3 226 #define AR6320V2_WLAN_DEBUG_INPUT_SEL_SRC_LSB 0 227 #define AR6320V2_WLAN_DEBUG_INPUT_SEL_SRC_MASK 0x0000000f 228 #define AR6320V2_WLAN_DEBUG_CONTROL_OFFSET 0x00000108 229 #define AR6320V2_WLAN_DEBUG_CONTROL_ENABLE_MSB 0 230 #define AR6320V2_WLAN_DEBUG_CONTROL_ENABLE_LSB 0 231 #define AR6320V2_WLAN_DEBUG_CONTROL_ENABLE_MASK 0x00000001 232 #define AR6320V2_WLAN_DEBUG_OUT_OFFSET 0x00000110 233 #define AR6320V2_WLAN_DEBUG_OUT_DATA_MSB 19 234 #define AR6320V2_WLAN_DEBUG_OUT_DATA_LSB 0 235 #define AR6320V2_WLAN_DEBUG_OUT_DATA_MASK 0x000fffff 236 #define AR6320V2_AMBA_DEBUG_BUS_OFFSET 0x0000011c 237 #define AR6320V2_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB 13 238 #define AR6320V2_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB 8 239 #define AR6320V2_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK 0x00003f00 240 #define AR6320V2_AMBA_DEBUG_BUS_SEL_MSB 4 241 #define AR6320V2_AMBA_DEBUG_BUS_SEL_LSB 0 242 #define AR6320V2_AMBA_DEBUG_BUS_SEL_MASK 0x0000001f 243 #define AR6320V2_CE_WRAPPER_DEBUG_OFFSET 0x0008 244 #define AR6320V2_CE_WRAPPER_DEBUG_SEL_MSB 5 245 #define AR6320V2_CE_WRAPPER_DEBUG_SEL_LSB 0 246 #define AR6320V2_CE_WRAPPER_DEBUG_SEL_MASK 0x0000003f 247 #define AR6320V2_CE_DEBUG_OFFSET 0x0054 248 #define AR6320V2_CE_DEBUG_SEL_MSB 5 249 #define AR6320V2_CE_DEBUG_SEL_LSB 0 250 #define AR6320V2_CE_DEBUG_SEL_MASK 0x0000003f 251 /* End */ 252 253 /* PLL start */ 254 #define AR6320V2_EFUSE_OFFSET 0x0000032c 255 #define AR6320V2_EFUSE_XTAL_SEL_MSB 10 256 #define AR6320V2_EFUSE_XTAL_SEL_LSB 8 257 #define AR6320V2_EFUSE_XTAL_SEL_MASK 0x00000700 258 #define AR6320V2_BB_PLL_CONFIG_OFFSET 0x000002f4 259 #define AR6320V2_BB_PLL_CONFIG_OUTDIV_MSB 20 260 #define AR6320V2_BB_PLL_CONFIG_OUTDIV_LSB 18 261 #define AR6320V2_BB_PLL_CONFIG_OUTDIV_MASK 0x001c0000 262 #define AR6320V2_BB_PLL_CONFIG_FRAC_MSB 17 263 #define AR6320V2_BB_PLL_CONFIG_FRAC_LSB 0 264 #define AR6320V2_BB_PLL_CONFIG_FRAC_MASK 0x0003ffff 265 #define AR6320V2_WLAN_PLL_SETTLE_TIME_MSB 10 266 #define AR6320V2_WLAN_PLL_SETTLE_TIME_LSB 0 267 #define AR6320V2_WLAN_PLL_SETTLE_TIME_MASK 0x000007ff 268 #define AR6320V2_WLAN_PLL_SETTLE_OFFSET 0x0018 269 #define AR6320V2_WLAN_PLL_SETTLE_SW_MASK 0x000007ff 270 #define AR6320V2_WLAN_PLL_SETTLE_RSTMASK 0xffffffff 271 #define AR6320V2_WLAN_PLL_SETTLE_RESET 0x00000400 272 #define AR6320V2_WLAN_PLL_CONTROL_NOPWD_MSB 18 273 #define AR6320V2_WLAN_PLL_CONTROL_NOPWD_LSB 18 274 #define AR6320V2_WLAN_PLL_CONTROL_NOPWD_MASK 0x00040000 275 #define AR6320V2_WLAN_PLL_CONTROL_BYPASS_MSB 16 276 #define AR6320V2_WLAN_PLL_CONTROL_BYPASS_LSB 16 277 #define AR6320V2_WLAN_PLL_CONTROL_BYPASS_MASK 0x00010000 278 #define AR6320V2_WLAN_PLL_CONTROL_BYPASS_RESET 0x1 279 #define AR6320V2_WLAN_PLL_CONTROL_CLK_SEL_MSB 15 280 #define AR6320V2_WLAN_PLL_CONTROL_CLK_SEL_LSB 14 281 #define AR6320V2_WLAN_PLL_CONTROL_CLK_SEL_MASK 0x0000c000 282 #define AR6320V2_WLAN_PLL_CONTROL_CLK_SEL_RESET 0x0 283 #define AR6320V2_WLAN_PLL_CONTROL_REFDIV_MSB 13 284 #define AR6320V2_WLAN_PLL_CONTROL_REFDIV_LSB 10 285 #define AR6320V2_WLAN_PLL_CONTROL_REFDIV_MASK 0x00003c00 286 #define AR6320V2_WLAN_PLL_CONTROL_REFDIV_RESET 0x0 287 #define AR6320V2_WLAN_PLL_CONTROL_DIV_MSB 9 288 #define AR6320V2_WLAN_PLL_CONTROL_DIV_LSB 0 289 #define AR6320V2_WLAN_PLL_CONTROL_DIV_MASK 0x000003ff 290 #define AR6320V2_WLAN_PLL_CONTROL_DIV_RESET 0x11 291 #define AR6320V2_WLAN_PLL_CONTROL_OFFSET 0x0014 292 #define AR6320V2_WLAN_PLL_CONTROL_SW_MASK 0x001fffff 293 #define AR6320V2_WLAN_PLL_CONTROL_RSTMASK 0xffffffff 294 #define AR6320V2_WLAN_PLL_CONTROL_RESET 0x00010011 295 #define AR6320V2_SOC_CORE_CLK_CTRL_OFFSET 0x00000114 296 #define AR6320V2_SOC_CORE_CLK_CTRL_DIV_MSB 2 297 #define AR6320V2_SOC_CORE_CLK_CTRL_DIV_LSB 0 298 #define AR6320V2_SOC_CORE_CLK_CTRL_DIV_MASK 0x00000007 299 #define AR6320V2_RTC_SYNC_STATUS_PLL_CHANGING_MSB 5 300 #define AR6320V2_RTC_SYNC_STATUS_PLL_CHANGING_LSB 5 301 #define AR6320V2_RTC_SYNC_STATUS_PLL_CHANGING_MASK 0x00000020 302 #define AR6320V2_RTC_SYNC_STATUS_PLL_CHANGING_RESET 0x0 303 #define AR6320V2_RTC_SYNC_STATUS_OFFSET 0x0244 304 #define AR6320V2_SOC_CPU_CLOCK_OFFSET 0x00000020 305 #define AR6320V2_SOC_CPU_CLOCK_STANDARD_MSB 1 306 #define AR6320V2_SOC_CPU_CLOCK_STANDARD_LSB 0 307 #define AR6320V2_SOC_CPU_CLOCK_STANDARD_MASK 0x00000003 308 /* PLL end */ 309 310 #define AR6320V2_PCIE_INTR_CE_MASK(n) \ 311 (AR6320V2_PCIE_INTR_CE0_MASK << (n)) 312 #endif 313 #define AR6320V2_DRAM_BASE_ADDRESS AR6320V2_TARG_DRAM_START 314 #define AR6320V2_FW_INDICATOR_ADDRESS \ 315 (AR6320V2_SOC_CORE_BASE_ADDRESS + AR6320V2_SCRATCH_3_ADDRESS) 316 #define AR6320V2_SYSTEM_SLEEP_OFFSET AR6320V2_SOC_SYSTEM_SLEEP_OFFSET 317 #define AR6320V2_WLAN_SYSTEM_SLEEP_OFFSET 0x002c 318 #define AR6320V2_WLAN_RESET_CONTROL_OFFSET AR6320V2_SOC_RESET_CONTROL_OFFSET 319 #define AR6320V2_CLOCK_CONTROL_OFFSET AR6320V2_SOC_CLOCK_CONTROL_OFFSET 320 #define AR6320V2_CLOCK_CONTROL_SI0_CLK_MASK \ 321 AR6320V2_SOC_CLOCK_CONTROL_SI0_CLK_MASK 322 #define AR6320V2_RESET_CONTROL_MBOX_RST_MASK 0x00000004 323 #define AR6320V2_RESET_CONTROL_SI0_RST_MASK \ 324 AR6320V2_SOC_RESET_CONTROL_SI0_RST_MASK 325 #define AR6320V2_GPIO_BASE_ADDRESS AR6320V2_WLAN_GPIO_BASE_ADDRESS 326 #define AR6320V2_GPIO_PIN0_OFFSET AR6320V2_WLAN_GPIO_PIN0_ADDRESS 327 #define AR6320V2_GPIO_PIN1_OFFSET AR6320V2_WLAN_GPIO_PIN1_ADDRESS 328 #define AR6320V2_GPIO_PIN0_CONFIG_MASK AR6320V2_WLAN_GPIO_PIN0_CONFIG_MASK 329 #define AR6320V2_GPIO_PIN1_CONFIG_MASK AR6320V2_WLAN_GPIO_PIN1_CONFIG_MASK 330 #define AR6320V2_SI_BASE_ADDRESS 0x00050000 331 #define AR6320V2_CPU_CLOCK_OFFSET AR6320V2_SOC_CPU_CLOCK_OFFSET 332 #define AR6320V2_LPO_CAL_OFFSET AR6320V2_SOC_LPO_CAL_OFFSET 333 #define AR6320V2_GPIO_PIN10_OFFSET AR6320V2_WLAN_GPIO_PIN10_ADDRESS 334 #define AR6320V2_GPIO_PIN11_OFFSET AR6320V2_WLAN_GPIO_PIN11_ADDRESS 335 #define AR6320V2_GPIO_PIN12_OFFSET AR6320V2_WLAN_GPIO_PIN12_ADDRESS 336 #define AR6320V2_GPIO_PIN13_OFFSET AR6320V2_WLAN_GPIO_PIN13_ADDRESS 337 #define AR6320V2_CPU_CLOCK_STANDARD_LSB AR6320V2_SOC_CPU_CLOCK_STANDARD_LSB 338 #define AR6320V2_CPU_CLOCK_STANDARD_MASK AR6320V2_SOC_CPU_CLOCK_STANDARD_MASK 339 #define AR6320V2_LPO_CAL_ENABLE_LSB AR6320V2_SOC_LPO_CAL_ENABLE_LSB 340 #define AR6320V2_LPO_CAL_ENABLE_MASK AR6320V2_SOC_LPO_CAL_ENABLE_MASK 341 #define AR6320V2_ANALOG_INTF_BASE_ADDRESS \ 342 AR6320V2_WLAN_ANALOG_INTF_BASE_ADDRESS 343 #define AR6320V2_MBOX_BASE_ADDRESS 0x00008000 344 #define AR6320V2_INT_STATUS_ENABLE_ERROR_LSB 7 345 #define AR6320V2_INT_STATUS_ENABLE_ERROR_MASK 0x00000080 346 #define AR6320V2_INT_STATUS_ENABLE_CPU_LSB 6 347 #define AR6320V2_INT_STATUS_ENABLE_CPU_MASK 0x00000040 348 #define AR6320V2_INT_STATUS_ENABLE_COUNTER_LSB 4 349 #define AR6320V2_INT_STATUS_ENABLE_COUNTER_MASK 0x00000010 350 #define AR6320V2_INT_STATUS_ENABLE_MBOX_DATA_LSB 0 351 #define AR6320V2_INT_STATUS_ENABLE_MBOX_DATA_MASK 0x0000000f 352 #define AR6320V2_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB 17 353 #define AR6320V2_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK 0x00020000 354 #define AR6320V2_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB 16 355 #define AR6320V2_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK 0x00010000 356 #define AR6320V2_COUNTER_INT_STATUS_ENABLE_BIT_LSB 24 357 #define AR6320V2_COUNTER_INT_STATUS_ENABLE_BIT_MASK 0xff000000 358 #define AR6320V2_INT_STATUS_ENABLE_ADDRESS 0x0828 359 #define AR6320V2_CPU_INT_STATUS_ENABLE_BIT_LSB 8 360 #define AR6320V2_CPU_INT_STATUS_ENABLE_BIT_MASK 0x0000ff00 361 #define AR6320V2_HOST_INT_STATUS_ADDRESS 0x0800 362 #define AR6320V2_CPU_INT_STATUS_ADDRESS 0x0801 363 #define AR6320V2_ERROR_INT_STATUS_ADDRESS 0x0802 364 #define AR6320V2_ERROR_INT_STATUS_WAKEUP_MASK 0x00040000 365 #define AR6320V2_ERROR_INT_STATUS_WAKEUP_LSB 18 366 #define AR6320V2_ERROR_INT_STATUS_RX_UNDERFLOW_MASK 0x00020000 367 #define AR6320V2_ERROR_INT_STATUS_RX_UNDERFLOW_LSB 17 368 #define AR6320V2_ERROR_INT_STATUS_TX_OVERFLOW_MASK 0x00010000 369 #define AR6320V2_ERROR_INT_STATUS_TX_OVERFLOW_LSB 16 370 #define AR6320V2_COUNT_DEC_ADDRESS 0x0840 371 #define AR6320V2_HOST_INT_STATUS_CPU_MASK 0x00000040 372 #define AR6320V2_HOST_INT_STATUS_CPU_LSB 6 373 #define AR6320V2_HOST_INT_STATUS_ERROR_MASK 0x00000080 374 #define AR6320V2_HOST_INT_STATUS_ERROR_LSB 7 375 #define AR6320V2_HOST_INT_STATUS_COUNTER_MASK 0x00000010 376 #define AR6320V2_HOST_INT_STATUS_COUNTER_LSB 4 377 #define AR6320V2_RX_LOOKAHEAD_VALID_ADDRESS 0x0805 378 #define AR6320V2_WINDOW_DATA_ADDRESS 0x0874 379 #define AR6320V2_WINDOW_READ_ADDR_ADDRESS 0x087c 380 #define AR6320V2_WINDOW_WRITE_ADDR_ADDRESS 0x0878 381 #define AR6320V2_HOST_INT_STATUS_MBOX_DATA_MASK 0x0f 382 #define AR6320V2_HOST_INT_STATUS_MBOX_DATA_LSB 0 383 384 struct targetdef_s ar6320v2_targetdef = { 385 .d_RTC_SOC_BASE_ADDRESS = AR6320V2_RTC_SOC_BASE_ADDRESS, 386 .d_RTC_WMAC_BASE_ADDRESS = AR6320V2_RTC_WMAC_BASE_ADDRESS, 387 .d_SYSTEM_SLEEP_OFFSET = AR6320V2_WLAN_SYSTEM_SLEEP_OFFSET, 388 .d_WLAN_SYSTEM_SLEEP_OFFSET = AR6320V2_WLAN_SYSTEM_SLEEP_OFFSET, 389 .d_WLAN_SYSTEM_SLEEP_DISABLE_LSB = 390 AR6320V2_WLAN_SYSTEM_SLEEP_DISABLE_LSB, 391 .d_WLAN_SYSTEM_SLEEP_DISABLE_MASK = 392 AR6320V2_WLAN_SYSTEM_SLEEP_DISABLE_MASK, 393 .d_CLOCK_CONTROL_OFFSET = AR6320V2_CLOCK_CONTROL_OFFSET, 394 .d_CLOCK_CONTROL_SI0_CLK_MASK = AR6320V2_CLOCK_CONTROL_SI0_CLK_MASK, 395 .d_RESET_CONTROL_OFFSET = AR6320V2_SOC_RESET_CONTROL_OFFSET, 396 .d_RESET_CONTROL_MBOX_RST_MASK = AR6320V2_RESET_CONTROL_MBOX_RST_MASK, 397 .d_RESET_CONTROL_SI0_RST_MASK = AR6320V2_RESET_CONTROL_SI0_RST_MASK, 398 .d_WLAN_RESET_CONTROL_OFFSET = AR6320V2_WLAN_RESET_CONTROL_OFFSET, 399 .d_WLAN_RESET_CONTROL_COLD_RST_MASK = 400 AR6320V2_WLAN_RESET_CONTROL_COLD_RST_MASK, 401 .d_WLAN_RESET_CONTROL_WARM_RST_MASK = 402 AR6320V2_WLAN_RESET_CONTROL_WARM_RST_MASK, 403 .d_GPIO_BASE_ADDRESS = AR6320V2_GPIO_BASE_ADDRESS, 404 .d_GPIO_PIN0_OFFSET = AR6320V2_GPIO_PIN0_OFFSET, 405 .d_GPIO_PIN1_OFFSET = AR6320V2_GPIO_PIN1_OFFSET, 406 .d_GPIO_PIN0_CONFIG_MASK = AR6320V2_GPIO_PIN0_CONFIG_MASK, 407 .d_GPIO_PIN1_CONFIG_MASK = AR6320V2_GPIO_PIN1_CONFIG_MASK, 408 .d_SI_CONFIG_BIDIR_OD_DATA_LSB = AR6320V2_SI_CONFIG_BIDIR_OD_DATA_LSB, 409 .d_SI_CONFIG_BIDIR_OD_DATA_MASK = 410 AR6320V2_SI_CONFIG_BIDIR_OD_DATA_MASK, 411 .d_SI_CONFIG_I2C_LSB = AR6320V2_SI_CONFIG_I2C_LSB, 412 .d_SI_CONFIG_I2C_MASK = AR6320V2_SI_CONFIG_I2C_MASK, 413 .d_SI_CONFIG_POS_SAMPLE_LSB = AR6320V2_SI_CONFIG_POS_SAMPLE_LSB, 414 .d_SI_CONFIG_POS_SAMPLE_MASK = AR6320V2_SI_CONFIG_POS_SAMPLE_MASK, 415 .d_SI_CONFIG_INACTIVE_CLK_LSB = AR6320V2_SI_CONFIG_INACTIVE_CLK_LSB, 416 .d_SI_CONFIG_INACTIVE_CLK_MASK = AR6320V2_SI_CONFIG_INACTIVE_CLK_MASK, 417 .d_SI_CONFIG_INACTIVE_DATA_LSB = AR6320V2_SI_CONFIG_INACTIVE_DATA_LSB, 418 .d_SI_CONFIG_INACTIVE_DATA_MASK = 419 AR6320V2_SI_CONFIG_INACTIVE_DATA_MASK, 420 .d_SI_CONFIG_DIVIDER_LSB = AR6320V2_SI_CONFIG_DIVIDER_LSB, 421 .d_SI_CONFIG_DIVIDER_MASK = AR6320V2_SI_CONFIG_DIVIDER_MASK, 422 .d_SI_BASE_ADDRESS = AR6320V2_SI_BASE_ADDRESS, 423 .d_SI_CONFIG_OFFSET = AR6320V2_SI_CONFIG_OFFSET, 424 .d_SI_TX_DATA0_OFFSET = AR6320V2_SI_TX_DATA0_OFFSET, 425 .d_SI_TX_DATA1_OFFSET = AR6320V2_SI_TX_DATA1_OFFSET, 426 .d_SI_RX_DATA0_OFFSET = AR6320V2_SI_RX_DATA0_OFFSET, 427 .d_SI_RX_DATA1_OFFSET = AR6320V2_SI_RX_DATA1_OFFSET, 428 .d_SI_CS_OFFSET = AR6320V2_SI_CS_OFFSET, 429 .d_SI_CS_DONE_ERR_MASK = AR6320V2_SI_CS_DONE_ERR_MASK, 430 .d_SI_CS_DONE_INT_MASK = AR6320V2_SI_CS_DONE_INT_MASK, 431 .d_SI_CS_START_LSB = AR6320V2_SI_CS_START_LSB, 432 .d_SI_CS_START_MASK = AR6320V2_SI_CS_START_MASK, 433 .d_SI_CS_RX_CNT_LSB = AR6320V2_SI_CS_RX_CNT_LSB, 434 .d_SI_CS_RX_CNT_MASK = AR6320V2_SI_CS_RX_CNT_MASK, 435 .d_SI_CS_TX_CNT_LSB = AR6320V2_SI_CS_TX_CNT_LSB, 436 .d_SI_CS_TX_CNT_MASK = AR6320V2_SI_CS_TX_CNT_MASK, 437 .d_BOARD_DATA_SZ = AR6320_BOARD_DATA_SZ, 438 .d_BOARD_EXT_DATA_SZ = AR6320_BOARD_EXT_DATA_SZ, 439 .d_MBOX_BASE_ADDRESS = AR6320V2_MBOX_BASE_ADDRESS, 440 .d_LOCAL_SCRATCH_OFFSET = AR6320V2_LOCAL_SCRATCH_OFFSET, 441 .d_CPU_CLOCK_OFFSET = AR6320V2_CPU_CLOCK_OFFSET, 442 .d_LPO_CAL_OFFSET = AR6320V2_LPO_CAL_OFFSET, 443 .d_GPIO_PIN10_OFFSET = AR6320V2_GPIO_PIN10_OFFSET, 444 .d_GPIO_PIN11_OFFSET = AR6320V2_GPIO_PIN11_OFFSET, 445 .d_GPIO_PIN12_OFFSET = AR6320V2_GPIO_PIN12_OFFSET, 446 .d_GPIO_PIN13_OFFSET = AR6320V2_GPIO_PIN13_OFFSET, 447 .d_CLOCK_GPIO_OFFSET = AR6320V2_CLOCK_GPIO_OFFSET, 448 .d_CPU_CLOCK_STANDARD_LSB = AR6320V2_CPU_CLOCK_STANDARD_LSB, 449 .d_CPU_CLOCK_STANDARD_MASK = AR6320V2_CPU_CLOCK_STANDARD_MASK, 450 .d_LPO_CAL_ENABLE_LSB = AR6320V2_LPO_CAL_ENABLE_LSB, 451 .d_LPO_CAL_ENABLE_MASK = AR6320V2_LPO_CAL_ENABLE_MASK, 452 .d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB = 453 AR6320V2_CLOCK_GPIO_BT_CLK_OUT_EN_LSB, 454 .d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK = 455 AR6320V2_CLOCK_GPIO_BT_CLK_OUT_EN_MASK, 456 .d_ANALOG_INTF_BASE_ADDRESS = AR6320V2_ANALOG_INTF_BASE_ADDRESS, 457 .d_WLAN_MAC_BASE_ADDRESS = AR6320V2_WLAN_MAC_BASE_ADDRESS, 458 .d_FW_INDICATOR_ADDRESS = AR6320V2_FW_INDICATOR_ADDRESS, 459 .d_DRAM_BASE_ADDRESS = AR6320V2_DRAM_BASE_ADDRESS, 460 .d_SOC_CORE_BASE_ADDRESS = AR6320V2_SOC_CORE_BASE_ADDRESS, 461 .d_CORE_CTRL_ADDRESS = AR6320V2_CORE_CTRL_ADDRESS, 462 #if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB) 463 .d_MSI_NUM_REQUEST = MSI_NUM_REQUEST, 464 .d_MSI_ASSIGN_FW = MSI_ASSIGN_FW, 465 #endif 466 .d_CORE_CTRL_CPU_INTR_MASK = AR6320V2_CORE_CTRL_CPU_INTR_MASK, 467 .d_SR_WR_INDEX_ADDRESS = AR6320V2_SR_WR_INDEX_ADDRESS, 468 .d_DST_WATERMARK_ADDRESS = AR6320V2_DST_WATERMARK_ADDRESS, 469 /* htt_rx.c */ 470 .d_RX_MSDU_END_4_FIRST_MSDU_MASK = 471 AR6320V2_RX_MSDU_END_4_FIRST_MSDU_MASK, 472 .d_RX_MSDU_END_4_FIRST_MSDU_LSB = 473 AR6320V2_RX_MSDU_END_4_FIRST_MSDU_LSB, 474 .d_RX_MPDU_START_0_RETRY_MASK = 475 AR6320V2_RX_MPDU_START_0_RETRY_MASK, 476 .d_RX_MPDU_START_0_SEQ_NUM_MASK = 477 AR6320V2_RX_MPDU_START_0_SEQ_NUM_MASK, 478 .d_RX_MPDU_START_0_SEQ_NUM_MASK = 479 AR6320V2_RX_MPDU_START_0_SEQ_NUM_MASK, 480 .d_RX_MPDU_START_0_SEQ_NUM_LSB = AR6320V2_RX_MPDU_START_0_SEQ_NUM_LSB, 481 .d_RX_MPDU_START_2_PN_47_32_LSB = 482 AR6320V2_RX_MPDU_START_2_PN_47_32_LSB, 483 .d_RX_MPDU_START_2_PN_47_32_MASK = 484 AR6320V2_RX_MPDU_START_2_PN_47_32_MASK, 485 .d_RX_MPDU_START_2_TID_LSB = 486 AR6320V2_RX_MPDU_START_2_TID_LSB, 487 .d_RX_MPDU_START_2_TID_MASK = 488 AR6320V2_RX_MPDU_START_2_TID_MASK, 489 .d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK = 490 AR6320V2_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK, 491 .d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB = 492 AR6320V2_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB, 493 .d_RX_MSDU_END_4_LAST_MSDU_MASK = 494 AR6320V2_RX_MSDU_END_4_LAST_MSDU_MASK, 495 .d_RX_MSDU_END_4_LAST_MSDU_LSB = AR6320V2_RX_MSDU_END_4_LAST_MSDU_LSB, 496 .d_RX_ATTENTION_0_MCAST_BCAST_MASK = 497 AR6320V2_RX_ATTENTION_0_MCAST_BCAST_MASK, 498 .d_RX_ATTENTION_0_MCAST_BCAST_LSB = 499 AR6320V2_RX_ATTENTION_0_MCAST_BCAST_LSB, 500 .d_RX_ATTENTION_0_FRAGMENT_MASK = 501 AR6320V2_RX_ATTENTION_0_FRAGMENT_MASK, 502 .d_RX_ATTENTION_0_FRAGMENT_LSB = AR6320V2_RX_ATTENTION_0_FRAGMENT_LSB, 503 .d_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK = 504 AR6320V2_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK, 505 .d_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK = 506 AR6320V2_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK, 507 .d_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB = 508 AR6320V2_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB, 509 .d_RX_MSDU_START_0_MSDU_LENGTH_MASK = 510 AR6320V2_RX_MSDU_START_0_MSDU_LENGTH_MASK, 511 .d_RX_MSDU_START_0_MSDU_LENGTH_LSB = 512 AR6320V2_RX_MSDU_START_0_MSDU_LENGTH_LSB, 513 .d_RX_MSDU_START_2_DECAP_FORMAT_OFFSET = 514 AR6320V2_RX_MSDU_START_2_DECAP_FORMAT_OFFSET, 515 .d_RX_MSDU_START_2_DECAP_FORMAT_MASK = 516 AR6320V2_RX_MSDU_START_2_DECAP_FORMAT_MASK, 517 .d_RX_MSDU_START_2_DECAP_FORMAT_LSB = 518 AR6320V2_RX_MSDU_START_2_DECAP_FORMAT_LSB, 519 .d_RX_MPDU_START_0_ENCRYPTED_MASK = 520 AR6320V2_RX_MPDU_START_0_ENCRYPTED_MASK, 521 .d_RX_MPDU_START_0_ENCRYPTED_LSB = 522 AR6320V2_RX_MPDU_START_0_ENCRYPTED_LSB, 523 .d_RX_ATTENTION_0_MORE_DATA_MASK = 524 AR6320V2_RX_ATTENTION_0_MORE_DATA_MASK, 525 .d_RX_ATTENTION_0_MSDU_DONE_MASK = 526 AR6320V2_RX_ATTENTION_0_MSDU_DONE_MASK, 527 .d_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK = 528 AR6320V2_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK, 529 #if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB) 530 .d_CE_COUNT = AR6320V2_CE_COUNT, 531 .d_MSI_ASSIGN_CE_INITIAL = MSI_ASSIGN_CE_INITIAL, 532 .d_PCIE_INTR_ENABLE_ADDRESS = AR6320V2_PCIE_INTR_ENABLE_ADDRESS, 533 .d_PCIE_INTR_CLR_ADDRESS = AR6320V2_PCIE_INTR_CLR_ADDRESS, 534 .d_PCIE_INTR_FIRMWARE_MASK = AR6320V2_PCIE_INTR_FIRMWARE_MASK, 535 .d_PCIE_INTR_CE_MASK_ALL = AR6320V2_PCIE_INTR_CE_MASK_ALL, 536 /* PLL start */ 537 .d_EFUSE_OFFSET = AR6320V2_EFUSE_OFFSET, 538 .d_EFUSE_XTAL_SEL_MSB = AR6320V2_EFUSE_XTAL_SEL_MSB, 539 .d_EFUSE_XTAL_SEL_LSB = AR6320V2_EFUSE_XTAL_SEL_LSB, 540 .d_EFUSE_XTAL_SEL_MASK = AR6320V2_EFUSE_XTAL_SEL_MASK, 541 .d_BB_PLL_CONFIG_OFFSET = AR6320V2_BB_PLL_CONFIG_OFFSET, 542 .d_BB_PLL_CONFIG_OUTDIV_MSB = AR6320V2_BB_PLL_CONFIG_OUTDIV_MSB, 543 .d_BB_PLL_CONFIG_OUTDIV_LSB = AR6320V2_BB_PLL_CONFIG_OUTDIV_LSB, 544 .d_BB_PLL_CONFIG_OUTDIV_MASK = AR6320V2_BB_PLL_CONFIG_OUTDIV_MASK, 545 .d_BB_PLL_CONFIG_FRAC_MSB = AR6320V2_BB_PLL_CONFIG_FRAC_MSB, 546 .d_BB_PLL_CONFIG_FRAC_LSB = AR6320V2_BB_PLL_CONFIG_FRAC_LSB, 547 .d_BB_PLL_CONFIG_FRAC_MASK = AR6320V2_BB_PLL_CONFIG_FRAC_MASK, 548 .d_WLAN_PLL_SETTLE_TIME_MSB = AR6320V2_WLAN_PLL_SETTLE_TIME_MSB, 549 .d_WLAN_PLL_SETTLE_TIME_LSB = AR6320V2_WLAN_PLL_SETTLE_TIME_LSB, 550 .d_WLAN_PLL_SETTLE_TIME_MASK = AR6320V2_WLAN_PLL_SETTLE_TIME_MASK, 551 .d_WLAN_PLL_SETTLE_OFFSET = AR6320V2_WLAN_PLL_SETTLE_OFFSET, 552 .d_WLAN_PLL_SETTLE_SW_MASK = AR6320V2_WLAN_PLL_SETTLE_SW_MASK, 553 .d_WLAN_PLL_SETTLE_RSTMASK = AR6320V2_WLAN_PLL_SETTLE_RSTMASK, 554 .d_WLAN_PLL_SETTLE_RESET = AR6320V2_WLAN_PLL_SETTLE_RESET, 555 .d_WLAN_PLL_CONTROL_NOPWD_MSB = AR6320V2_WLAN_PLL_CONTROL_NOPWD_MSB, 556 .d_WLAN_PLL_CONTROL_NOPWD_LSB = AR6320V2_WLAN_PLL_CONTROL_NOPWD_LSB, 557 .d_WLAN_PLL_CONTROL_NOPWD_MASK = AR6320V2_WLAN_PLL_CONTROL_NOPWD_MASK, 558 .d_WLAN_PLL_CONTROL_BYPASS_MSB = AR6320V2_WLAN_PLL_CONTROL_BYPASS_MSB, 559 .d_WLAN_PLL_CONTROL_BYPASS_LSB = AR6320V2_WLAN_PLL_CONTROL_BYPASS_LSB, 560 .d_WLAN_PLL_CONTROL_BYPASS_MASK = 561 AR6320V2_WLAN_PLL_CONTROL_BYPASS_MASK, 562 .d_WLAN_PLL_CONTROL_BYPASS_RESET = 563 AR6320V2_WLAN_PLL_CONTROL_BYPASS_RESET, 564 .d_WLAN_PLL_CONTROL_CLK_SEL_MSB = 565 AR6320V2_WLAN_PLL_CONTROL_CLK_SEL_MSB, 566 .d_WLAN_PLL_CONTROL_CLK_SEL_LSB = 567 AR6320V2_WLAN_PLL_CONTROL_CLK_SEL_LSB, 568 .d_WLAN_PLL_CONTROL_CLK_SEL_MASK = 569 AR6320V2_WLAN_PLL_CONTROL_CLK_SEL_MASK, 570 .d_WLAN_PLL_CONTROL_CLK_SEL_RESET = 571 AR6320V2_WLAN_PLL_CONTROL_CLK_SEL_RESET, 572 .d_WLAN_PLL_CONTROL_REFDIV_MSB = AR6320V2_WLAN_PLL_CONTROL_REFDIV_MSB, 573 .d_WLAN_PLL_CONTROL_REFDIV_LSB = AR6320V2_WLAN_PLL_CONTROL_REFDIV_LSB, 574 .d_WLAN_PLL_CONTROL_REFDIV_MASK = 575 AR6320V2_WLAN_PLL_CONTROL_REFDIV_MASK, 576 .d_WLAN_PLL_CONTROL_REFDIV_RESET = 577 AR6320V2_WLAN_PLL_CONTROL_REFDIV_RESET, 578 .d_WLAN_PLL_CONTROL_DIV_MSB = AR6320V2_WLAN_PLL_CONTROL_DIV_MSB, 579 .d_WLAN_PLL_CONTROL_DIV_LSB = AR6320V2_WLAN_PLL_CONTROL_DIV_LSB, 580 .d_WLAN_PLL_CONTROL_DIV_MASK = AR6320V2_WLAN_PLL_CONTROL_DIV_MASK, 581 .d_WLAN_PLL_CONTROL_DIV_RESET = AR6320V2_WLAN_PLL_CONTROL_DIV_RESET, 582 .d_WLAN_PLL_CONTROL_OFFSET = AR6320V2_WLAN_PLL_CONTROL_OFFSET, 583 .d_WLAN_PLL_CONTROL_SW_MASK = AR6320V2_WLAN_PLL_CONTROL_SW_MASK, 584 .d_WLAN_PLL_CONTROL_RSTMASK = AR6320V2_WLAN_PLL_CONTROL_RSTMASK, 585 .d_WLAN_PLL_CONTROL_RESET = AR6320V2_WLAN_PLL_CONTROL_RESET, 586 .d_SOC_CORE_CLK_CTRL_OFFSET = AR6320V2_SOC_CORE_CLK_CTRL_OFFSET, 587 .d_SOC_CORE_CLK_CTRL_DIV_MSB = AR6320V2_SOC_CORE_CLK_CTRL_DIV_MSB, 588 .d_SOC_CORE_CLK_CTRL_DIV_LSB = AR6320V2_SOC_CORE_CLK_CTRL_DIV_LSB, 589 .d_SOC_CORE_CLK_CTRL_DIV_MASK = AR6320V2_SOC_CORE_CLK_CTRL_DIV_MASK, 590 .d_RTC_SYNC_STATUS_PLL_CHANGING_MSB = 591 AR6320V2_RTC_SYNC_STATUS_PLL_CHANGING_MSB, 592 .d_RTC_SYNC_STATUS_PLL_CHANGING_LSB = 593 AR6320V2_RTC_SYNC_STATUS_PLL_CHANGING_LSB, 594 .d_RTC_SYNC_STATUS_PLL_CHANGING_MASK = 595 AR6320V2_RTC_SYNC_STATUS_PLL_CHANGING_MASK, 596 .d_RTC_SYNC_STATUS_PLL_CHANGING_RESET = 597 AR6320V2_RTC_SYNC_STATUS_PLL_CHANGING_RESET, 598 .d_RTC_SYNC_STATUS_OFFSET = AR6320V2_RTC_SYNC_STATUS_OFFSET, 599 .d_SOC_CPU_CLOCK_OFFSET = AR6320V2_SOC_CPU_CLOCK_OFFSET, 600 .d_SOC_CPU_CLOCK_STANDARD_MSB = AR6320V2_SOC_CPU_CLOCK_STANDARD_MSB, 601 .d_SOC_CPU_CLOCK_STANDARD_LSB = AR6320V2_SOC_CPU_CLOCK_STANDARD_LSB, 602 .d_SOC_CPU_CLOCK_STANDARD_MASK = AR6320V2_SOC_CPU_CLOCK_STANDARD_MASK, 603 /* PLL end */ 604 .d_SOC_POWER_REG_OFFSET = AR6320V2_SOC_POWER_REG_OFFSET, 605 .d_PCIE_INTR_CAUSE_ADDRESS = AR6320V2_PCIE_INTR_CAUSE_ADDRESS, 606 .d_SOC_RESET_CONTROL_ADDRESS = AR6320V2_SOC_RESET_CONTROL_ADDRESS, 607 .d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK = 608 AR6320V2_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK, 609 .d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB = 610 AR6320V2_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB, 611 .d_SOC_RESET_CONTROL_CE_RST_MASK = 612 AR6320V2_SOC_RESET_CONTROL_CE_RST_MASK, 613 .d_WLAN_DEBUG_INPUT_SEL_OFFSET = AR6320V2_WLAN_DEBUG_INPUT_SEL_OFFSET, 614 .d_WLAN_DEBUG_INPUT_SEL_SRC_MSB = 615 AR6320V2_WLAN_DEBUG_INPUT_SEL_SRC_MSB, 616 .d_WLAN_DEBUG_INPUT_SEL_SRC_LSB = 617 AR6320V2_WLAN_DEBUG_INPUT_SEL_SRC_LSB, 618 .d_WLAN_DEBUG_INPUT_SEL_SRC_MASK = 619 AR6320V2_WLAN_DEBUG_INPUT_SEL_SRC_MASK, 620 .d_WLAN_DEBUG_CONTROL_OFFSET = AR6320V2_WLAN_DEBUG_CONTROL_OFFSET, 621 .d_WLAN_DEBUG_CONTROL_ENABLE_MSB = 622 AR6320V2_WLAN_DEBUG_CONTROL_ENABLE_MSB, 623 .d_WLAN_DEBUG_CONTROL_ENABLE_LSB = 624 AR6320V2_WLAN_DEBUG_CONTROL_ENABLE_LSB, 625 .d_WLAN_DEBUG_CONTROL_ENABLE_MASK = 626 AR6320V2_WLAN_DEBUG_CONTROL_ENABLE_MASK, 627 .d_WLAN_DEBUG_OUT_OFFSET = AR6320V2_WLAN_DEBUG_OUT_OFFSET, 628 .d_WLAN_DEBUG_OUT_DATA_MSB = AR6320V2_WLAN_DEBUG_OUT_DATA_MSB, 629 .d_WLAN_DEBUG_OUT_DATA_LSB = AR6320V2_WLAN_DEBUG_OUT_DATA_LSB, 630 .d_WLAN_DEBUG_OUT_DATA_MASK = AR6320V2_WLAN_DEBUG_OUT_DATA_MASK, 631 .d_AMBA_DEBUG_BUS_OFFSET = AR6320V2_AMBA_DEBUG_BUS_OFFSET, 632 .d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB = 633 AR6320V2_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB, 634 .d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB = 635 AR6320V2_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB, 636 .d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK = 637 AR6320V2_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK, 638 .d_AMBA_DEBUG_BUS_SEL_MSB = AR6320V2_AMBA_DEBUG_BUS_SEL_MSB, 639 .d_AMBA_DEBUG_BUS_SEL_LSB = AR6320V2_AMBA_DEBUG_BUS_SEL_LSB, 640 .d_AMBA_DEBUG_BUS_SEL_MASK = AR6320V2_AMBA_DEBUG_BUS_SEL_MASK, 641 #endif 642 .d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK = 643 AR6320V2_SOC_RESET_CONTROL_CPU_WARM_RST_MASK, 644 .d_CPU_INTR_ADDRESS = AR6320V2_CPU_INTR_ADDRESS, 645 .d_SOC_LF_TIMER_CONTROL0_ADDRESS = 646 AR6320V2_SOC_LF_TIMER_CONTROL0_ADDRESS, 647 .d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK = 648 AR6320V2_SOC_LF_TIMER_CONTROL0_ENABLE_MASK, 649 .d_SOC_LF_TIMER_STATUS0_ADDRESS = 650 AR6320V2_SOC_LF_TIMER_STATUS0_ADDRESS, 651 /* chip id start */ 652 .d_SOC_CHIP_ID_ADDRESS = AR6320V2_SOC_CHIP_ID_ADDRESS, 653 .d_SOC_CHIP_ID_VERSION_MASK = AR6320V2_SOC_CHIP_ID_VERSION_MASK, 654 .d_SOC_CHIP_ID_VERSION_LSB = AR6320V2_SOC_CHIP_ID_VERSION_LSB, 655 .d_SOC_CHIP_ID_REVISION_MASK = AR6320V2_SOC_CHIP_ID_REVISION_MASK, 656 .d_SOC_CHIP_ID_REVISION_LSB = AR6320V2_SOC_CHIP_ID_REVISION_LSB, 657 /* chip id end */ 658 }; 659 660 struct hostdef_s ar6320v2_hostdef = { 661 .d_INT_STATUS_ENABLE_ERROR_LSB = AR6320V2_INT_STATUS_ENABLE_ERROR_LSB, 662 .d_INT_STATUS_ENABLE_ERROR_MASK = 663 AR6320V2_INT_STATUS_ENABLE_ERROR_MASK, 664 .d_INT_STATUS_ENABLE_CPU_LSB = AR6320V2_INT_STATUS_ENABLE_CPU_LSB, 665 .d_INT_STATUS_ENABLE_CPU_MASK = AR6320V2_INT_STATUS_ENABLE_CPU_MASK, 666 .d_INT_STATUS_ENABLE_COUNTER_LSB = 667 AR6320V2_INT_STATUS_ENABLE_COUNTER_LSB, 668 .d_INT_STATUS_ENABLE_COUNTER_MASK = 669 AR6320V2_INT_STATUS_ENABLE_COUNTER_MASK, 670 .d_INT_STATUS_ENABLE_MBOX_DATA_LSB = 671 AR6320V2_INT_STATUS_ENABLE_MBOX_DATA_LSB, 672 .d_INT_STATUS_ENABLE_MBOX_DATA_MASK = 673 AR6320V2_INT_STATUS_ENABLE_MBOX_DATA_MASK, 674 .d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB = 675 AR6320V2_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB, 676 .d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK = 677 AR6320V2_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK, 678 .d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB = 679 AR6320V2_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB, 680 .d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK = 681 AR6320V2_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK, 682 .d_COUNTER_INT_STATUS_ENABLE_BIT_LSB = 683 AR6320V2_COUNTER_INT_STATUS_ENABLE_BIT_LSB, 684 .d_COUNTER_INT_STATUS_ENABLE_BIT_MASK = 685 AR6320V2_COUNTER_INT_STATUS_ENABLE_BIT_MASK, 686 .d_INT_STATUS_ENABLE_ADDRESS = AR6320V2_INT_STATUS_ENABLE_ADDRESS, 687 .d_CPU_INT_STATUS_ENABLE_BIT_LSB = 688 AR6320V2_CPU_INT_STATUS_ENABLE_BIT_LSB, 689 .d_CPU_INT_STATUS_ENABLE_BIT_MASK = 690 AR6320V2_CPU_INT_STATUS_ENABLE_BIT_MASK, 691 .d_HOST_INT_STATUS_ADDRESS = AR6320V2_HOST_INT_STATUS_ADDRESS, 692 .d_CPU_INT_STATUS_ADDRESS = AR6320V2_CPU_INT_STATUS_ADDRESS, 693 .d_ERROR_INT_STATUS_ADDRESS = AR6320V2_ERROR_INT_STATUS_ADDRESS, 694 .d_ERROR_INT_STATUS_WAKEUP_MASK = 695 AR6320V2_ERROR_INT_STATUS_WAKEUP_MASK, 696 .d_ERROR_INT_STATUS_WAKEUP_LSB = AR6320V2_ERROR_INT_STATUS_WAKEUP_LSB, 697 .d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK = 698 AR6320V2_ERROR_INT_STATUS_RX_UNDERFLOW_MASK, 699 .d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB = 700 AR6320V2_ERROR_INT_STATUS_RX_UNDERFLOW_LSB, 701 .d_ERROR_INT_STATUS_TX_OVERFLOW_MASK = 702 AR6320V2_ERROR_INT_STATUS_TX_OVERFLOW_MASK, 703 .d_ERROR_INT_STATUS_TX_OVERFLOW_LSB = 704 AR6320V2_ERROR_INT_STATUS_TX_OVERFLOW_LSB, 705 .d_COUNT_DEC_ADDRESS = AR6320V2_COUNT_DEC_ADDRESS, 706 .d_HOST_INT_STATUS_CPU_MASK = AR6320V2_HOST_INT_STATUS_CPU_MASK, 707 .d_HOST_INT_STATUS_CPU_LSB = AR6320V2_HOST_INT_STATUS_CPU_LSB, 708 .d_HOST_INT_STATUS_ERROR_MASK = AR6320V2_HOST_INT_STATUS_ERROR_MASK, 709 .d_HOST_INT_STATUS_ERROR_LSB = AR6320V2_HOST_INT_STATUS_ERROR_LSB, 710 .d_HOST_INT_STATUS_COUNTER_MASK = 711 AR6320V2_HOST_INT_STATUS_COUNTER_MASK, 712 .d_HOST_INT_STATUS_COUNTER_LSB = AR6320V2_HOST_INT_STATUS_COUNTER_LSB, 713 .d_RX_LOOKAHEAD_VALID_ADDRESS = AR6320V2_RX_LOOKAHEAD_VALID_ADDRESS, 714 .d_WINDOW_DATA_ADDRESS = AR6320V2_WINDOW_DATA_ADDRESS, 715 .d_WINDOW_READ_ADDR_ADDRESS = AR6320V2_WINDOW_READ_ADDR_ADDRESS, 716 .d_WINDOW_WRITE_ADDR_ADDRESS = AR6320V2_WINDOW_WRITE_ADDR_ADDRESS, 717 .d_SOC_GLOBAL_RESET_ADDRESS = AR6320V2_SOC_GLOBAL_RESET_ADDRESS, 718 .d_RTC_STATE_ADDRESS = AR6320V2_RTC_STATE_ADDRESS, 719 .d_RTC_STATE_COLD_RESET_MASK = AR6320V2_RTC_STATE_COLD_RESET_MASK, 720 .d_RTC_STATE_V_MASK = AR6320V2_RTC_STATE_V_MASK, 721 .d_RTC_STATE_V_LSB = AR6320V2_RTC_STATE_V_LSB, 722 .d_FW_IND_EVENT_PENDING = AR6320V2_FW_IND_EVENT_PENDING, 723 .d_FW_IND_INITIALIZED = AR6320V2_FW_IND_INITIALIZED, 724 .d_RTC_STATE_V_ON = AR6320V2_RTC_STATE_V_ON, 725 #if defined(SDIO_3_0) 726 .d_HOST_INT_STATUS_MBOX_DATA_MASK = 727 AR6320V2_HOST_INT_STATUS_MBOX_DATA_MASK, 728 .d_HOST_INT_STATUS_MBOX_DATA_LSB = 729 AR6320V2_HOST_INT_STATUS_MBOX_DATA_LSB, 730 #endif 731 #if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB) 732 .d_FW_IND_HELPER = AR6320V2_FW_IND_HELPER, 733 .d_MUX_ID_MASK = AR6320V2_MUX_ID_MASK, 734 .d_TRANSACTION_ID_MASK = AR6320V2_TRANSACTION_ID_MASK, 735 .d_PCIE_LOCAL_BASE_ADDRESS = AR6320V2_PCIE_LOCAL_BASE_ADDRESS, 736 .d_PCIE_SOC_WAKE_RESET = AR6320V2_PCIE_SOC_WAKE_RESET, 737 .d_PCIE_SOC_WAKE_ADDRESS = AR6320V2_PCIE_SOC_WAKE_ADDRESS, 738 .d_PCIE_SOC_WAKE_V_MASK = AR6320V2_PCIE_SOC_WAKE_V_MASK, 739 .d_PCIE_SOC_RDY_STATUS_ADDRESS = PCIE_SOC_RDY_STATUS_ADDRESS, 740 .d_PCIE_SOC_RDY_STATUS_BAR_MASK = PCIE_SOC_RDY_STATUS_BAR_MASK, 741 .d_SOC_PCIE_BASE_ADDRESS = SOC_PCIE_BASE_ADDRESS, 742 .d_MSI_MAGIC_ADR_ADDRESS = MSI_MAGIC_ADR_ADDRESS, 743 .d_MSI_MAGIC_ADDRESS = MSI_MAGIC_ADDRESS, 744 .d_HOST_CE_COUNT = 8, 745 .d_ENABLE_MSI = 0, 746 #endif 747 #if defined(HIF_SDIO) 748 .d_FW_IND_HELPER = AR6320V2_FW_IND_HELPER, 749 #endif 750 }; 751 752 #if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB) 753 struct ce_reg_def ar6320v2_ce_targetdef = { 754 /* copy_engine.c */ 755 .d_DST_WR_INDEX_ADDRESS = AR6320V2_DST_WR_INDEX_ADDRESS, 756 .d_SRC_WATERMARK_ADDRESS = AR6320V2_SRC_WATERMARK_ADDRESS, 757 .d_SRC_WATERMARK_LOW_MASK = AR6320V2_SRC_WATERMARK_LOW_MASK, 758 .d_SRC_WATERMARK_HIGH_MASK = AR6320V2_SRC_WATERMARK_HIGH_MASK, 759 .d_DST_WATERMARK_LOW_MASK = AR6320V2_DST_WATERMARK_LOW_MASK, 760 .d_DST_WATERMARK_HIGH_MASK = AR6320V2_DST_WATERMARK_HIGH_MASK, 761 .d_CURRENT_SRRI_ADDRESS = AR6320V2_CURRENT_SRRI_ADDRESS, 762 .d_CURRENT_DRRI_ADDRESS = AR6320V2_CURRENT_DRRI_ADDRESS, 763 .d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK = 764 AR6320V2_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK, 765 .d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK = 766 AR6320V2_HOST_IS_SRC_RING_LOW_WATERMARK_MASK, 767 .d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK = 768 AR6320V2_HOST_IS_DST_RING_HIGH_WATERMARK_MASK, 769 .d_HOST_IS_DST_RING_LOW_WATERMARK_MASK = 770 AR6320V2_HOST_IS_DST_RING_LOW_WATERMARK_MASK, 771 .d_HOST_IS_ADDRESS = AR6320V2_HOST_IS_ADDRESS, 772 .d_HOST_IS_COPY_COMPLETE_MASK = AR6320V2_HOST_IS_COPY_COMPLETE_MASK, 773 .d_CE_WRAPPER_BASE_ADDRESS = AR6320V2_CE_WRAPPER_BASE_ADDRESS, 774 .d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS = 775 AR6320V2_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS, 776 .d_HOST_IE_ADDRESS = AR6320V2_HOST_IE_ADDRESS, 777 .d_HOST_IE_COPY_COMPLETE_MASK = AR6320V2_HOST_IE_COPY_COMPLETE_MASK, 778 .d_SR_BA_ADDRESS = AR6320V2_SR_BA_ADDRESS, 779 .d_SR_SIZE_ADDRESS = AR6320V2_SR_SIZE_ADDRESS, 780 .d_CE_CTRL1_ADDRESS = AR6320V2_CE_CTRL1_ADDRESS, 781 .d_CE_CTRL1_DMAX_LENGTH_MASK = AR6320V2_CE_CTRL1_DMAX_LENGTH_MASK, 782 .d_DR_BA_ADDRESS = AR6320V2_DR_BA_ADDRESS, 783 .d_DR_SIZE_ADDRESS = AR6320V2_DR_SIZE_ADDRESS, 784 .d_MISC_IE_ADDRESS = AR6320V2_MISC_IE_ADDRESS, 785 .d_MISC_IS_AXI_ERR_MASK = AR6320V2_MISC_IS_AXI_ERR_MASK, 786 .d_MISC_IS_DST_ADDR_ERR_MASK = AR6320V2_MISC_IS_DST_ADDR_ERR_MASK, 787 .d_MISC_IS_SRC_LEN_ERR_MASK = AR6320V2_MISC_IS_SRC_LEN_ERR_MASK, 788 .d_MISC_IS_DST_MAX_LEN_VIO_MASK = 789 AR6320V2_MISC_IS_DST_MAX_LEN_VIO_MASK, 790 .d_MISC_IS_DST_RING_OVERFLOW_MASK = 791 AR6320V2_MISC_IS_DST_RING_OVERFLOW_MASK, 792 .d_MISC_IS_SRC_RING_OVERFLOW_MASK = 793 AR6320V2_MISC_IS_SRC_RING_OVERFLOW_MASK, 794 .d_SRC_WATERMARK_LOW_LSB = AR6320V2_SRC_WATERMARK_LOW_LSB, 795 .d_SRC_WATERMARK_HIGH_LSB = AR6320V2_SRC_WATERMARK_HIGH_LSB, 796 .d_DST_WATERMARK_LOW_LSB = AR6320V2_DST_WATERMARK_LOW_LSB, 797 .d_DST_WATERMARK_HIGH_LSB = AR6320V2_DST_WATERMARK_HIGH_LSB, 798 .d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK = 799 AR6320V2_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK, 800 .d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB = 801 AR6320V2_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB, 802 .d_CE_CTRL1_DMAX_LENGTH_LSB = AR6320V2_CE_CTRL1_DMAX_LENGTH_LSB, 803 .d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK = 804 AR6320V2_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK, 805 .d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK = 806 AR6320V2_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK, 807 .d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB = 808 AR6320V2_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB, 809 .d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB = 810 AR6320V2_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB, 811 .d_CE_WRAPPER_DEBUG_OFFSET = AR6320V2_CE_WRAPPER_DEBUG_OFFSET, 812 .d_CE_WRAPPER_DEBUG_SEL_MSB = AR6320V2_CE_WRAPPER_DEBUG_SEL_MSB, 813 .d_CE_WRAPPER_DEBUG_SEL_LSB = AR6320V2_CE_WRAPPER_DEBUG_SEL_LSB, 814 .d_CE_WRAPPER_DEBUG_SEL_MASK = AR6320V2_CE_WRAPPER_DEBUG_SEL_MASK, 815 .d_CE_DEBUG_OFFSET = AR6320V2_CE_DEBUG_OFFSET, 816 .d_CE_DEBUG_SEL_MSB = AR6320V2_CE_DEBUG_SEL_MSB, 817 .d_CE_DEBUG_SEL_LSB = AR6320V2_CE_DEBUG_SEL_LSB, 818 .d_CE_DEBUG_SEL_MASK = AR6320V2_CE_DEBUG_SEL_MASK, 819 .d_CE0_BASE_ADDRESS = AR6320V2_CE0_BASE_ADDRESS, 820 .d_CE1_BASE_ADDRESS = AR6320V2_CE1_BASE_ADDRESS, 821 822 }; 823 #endif 824 #endif 825