1 /* 2 * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef TARGET_REG_INIT_H 20 #define TARGET_REG_INIT_H 21 #include "reg_struct.h" 22 #include "targaddrs.h" 23 /*** WARNING : Add to the end of the TABLE! do not change the order ****/ 24 struct targetdef_s; 25 26 27 28 #define ATH_UNSUPPORTED_REG_OFFSET UNSUPPORTED_REGISTER_OFFSET 29 #define ATH_SUPPORTED_BY_TARGET(reg_offset) \ 30 ((reg_offset) != ATH_UNSUPPORTED_REG_OFFSET) 31 32 #if defined(MY_TARGET_DEF) 33 34 /* Cross-platform compatibility */ 35 #if !defined(SOC_RESET_CONTROL_OFFSET) && defined(RESET_CONTROL_OFFSET) 36 #define SOC_RESET_CONTROL_OFFSET RESET_CONTROL_OFFSET 37 #endif 38 39 #if !defined(CLOCK_GPIO_OFFSET) 40 #define CLOCK_GPIO_OFFSET ATH_UNSUPPORTED_REG_OFFSET 41 #define CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0 42 #define CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0 43 #endif 44 45 #if !defined(WLAN_MAC_BASE_ADDRESS) 46 #define WLAN_MAC_BASE_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 47 #endif 48 49 #if !defined(CE0_BASE_ADDRESS) 50 #define CE0_BASE_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 51 #define CE1_BASE_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 52 #define CE_COUNT 0 53 #endif 54 55 #if !defined(MSI_NUM_REQUEST) 56 #define MSI_NUM_REQUEST 0 57 #define MSI_ASSIGN_FW 0 58 #define MSI_ASSIGN_CE_INITIAL 0 59 #endif 60 61 #if !defined(FW_INDICATOR_ADDRESS) 62 #define FW_INDICATOR_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 63 #endif 64 65 #if !defined(FW_CPU_PLL_CONFIG) 66 #define FW_CPU_PLL_CONFIG ATH_UNSUPPORTED_REG_OFFSET 67 #endif 68 69 #if !defined(DRAM_BASE_ADDRESS) 70 #define DRAM_BASE_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 71 #endif 72 73 #if !defined(SOC_CORE_BASE_ADDRESS) 74 #define SOC_CORE_BASE_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 75 #endif 76 77 #if !defined(CPU_INTR_ADDRESS) 78 #define CPU_INTR_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 79 #endif 80 81 #if !defined(SOC_LF_TIMER_CONTROL0_ADDRESS) 82 #define SOC_LF_TIMER_CONTROL0_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 83 #define SOC_LF_TIMER_CONTROL0_ENABLE_MASK ATH_UNSUPPORTED_REG_OFFSET 84 #endif 85 86 #if !defined(SOC_LF_TIMER_STATUS0_ADDRESS) 87 #define SOC_LF_TIMER_STATUS0_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 88 #endif 89 90 #if !defined(SOC_RESET_CONTROL_ADDRESS) 91 #define SOC_RESET_CONTROL_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 92 #define SOC_RESET_CONTROL_CE_RST_MASK ATH_UNSUPPORTED_REG_OFFSET 93 #define SOC_RESET_CONTROL_CPU_WARM_RST_MASK ATH_UNSUPPORTED_REG_OFFSET 94 #endif 95 96 #if !defined(CORE_CTRL_ADDRESS) 97 #define CORE_CTRL_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 98 #define CORE_CTRL_CPU_INTR_MASK 0 99 #endif 100 101 #if !defined(PCIE_INTR_ENABLE_ADDRESS) 102 #define PCIE_INTR_ENABLE_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 103 #define PCIE_INTR_CLR_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 104 #define PCIE_INTR_FIRMWARE_MASK ATH_UNSUPPORTED_REG_OFFSET 105 #define PCIE_INTR_CE_MASK_ALL ATH_UNSUPPORTED_REG_OFFSET 106 #define PCIE_INTR_CAUSE_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 107 #endif 108 109 #if !defined(WIFICMN_PCIE_BAR_REG_ADDRESS) 110 #define WIFICMN_PCIE_BAR_REG_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 111 #endif 112 113 #if !defined(WIFICMN_INT_STATUS_ADDRESS) 114 #define WIFICMN_INT_STATUS_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 115 #endif 116 117 #if !defined(FW_AXI_MSI_ADDR) 118 #define FW_AXI_MSI_ADDR ATH_UNSUPPORTED_REG_OFFSET 119 #endif 120 121 #if !defined(FW_AXI_MSI_DATA) 122 #define FW_AXI_MSI_DATA ATH_UNSUPPORTED_REG_OFFSET 123 #endif 124 125 #if !defined(WLAN_SUBSYSTEM_CORE_ID_ADDRESS) 126 #define WLAN_SUBSYSTEM_CORE_ID_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 127 #endif 128 129 #if !defined(FPGA_VERSION_ADDRESS) 130 #define FPGA_VERSION_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 131 #endif 132 133 #if !defined(SI_CONFIG_ADDRESS) 134 #define SI_CONFIG_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 135 #define SI_CONFIG_BIDIR_OD_DATA_LSB 0 136 #define SI_CONFIG_BIDIR_OD_DATA_MASK 0 137 #define SI_CONFIG_I2C_LSB 0 138 #define SI_CONFIG_I2C_MASK 0 139 #define SI_CONFIG_POS_SAMPLE_LSB 0 140 #define SI_CONFIG_POS_SAMPLE_MASK 0 141 #define SI_CONFIG_INACTIVE_CLK_LSB 0 142 #define SI_CONFIG_INACTIVE_CLK_MASK 0 143 #define SI_CONFIG_INACTIVE_DATA_LSB 0 144 #define SI_CONFIG_INACTIVE_DATA_MASK 0 145 #define SI_CONFIG_DIVIDER_LSB 0 146 #define SI_CONFIG_DIVIDER_MASK 0 147 #define SI_CONFIG_OFFSET 0 148 #define SI_TX_DATA0_OFFSET ATH_UNSUPPORTED_REG_OFFSET 149 #define SI_TX_DATA1_OFFSET ATH_UNSUPPORTED_REG_OFFSET 150 #define SI_RX_DATA0_OFFSET ATH_UNSUPPORTED_REG_OFFSET 151 #define SI_RX_DATA1_OFFSET ATH_UNSUPPORTED_REG_OFFSET 152 #define SI_CS_OFFSET ATH_UNSUPPORTED_REG_OFFSET 153 #define SI_CS_DONE_ERR_MASK 0 154 #define SI_CS_DONE_INT_MASK 0 155 #define SI_CS_START_LSB 0 156 #define SI_CS_START_MASK 0 157 #define SI_CS_RX_CNT_LSB 0 158 #define SI_CS_RX_CNT_MASK 0 159 #define SI_CS_TX_CNT_LSB 0 160 #define SI_CS_TX_CNT_MASK 0 161 #endif 162 163 #ifndef SI_BASE_ADDRESS 164 #define SI_BASE_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 165 #endif 166 167 #ifndef WLAN_GPIO_PIN10_ADDRESS 168 #define WLAN_GPIO_PIN10_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 169 #endif 170 171 #ifndef WLAN_GPIO_PIN11_ADDRESS 172 #define WLAN_GPIO_PIN11_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 173 #endif 174 175 #ifndef WLAN_GPIO_PIN12_ADDRESS 176 #define WLAN_GPIO_PIN12_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 177 #endif 178 179 #ifndef WLAN_GPIO_PIN13_ADDRESS 180 #define WLAN_GPIO_PIN13_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 181 #endif 182 183 #ifndef WIFICMN_INT_STATUS_ADDRESS 184 #define WIFICMN_INT_STATUS_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 185 #endif 186 187 static struct targetdef_s my_target_def = { 188 .d_RTC_SOC_BASE_ADDRESS = RTC_SOC_BASE_ADDRESS, 189 .d_RTC_WMAC_BASE_ADDRESS = RTC_WMAC_BASE_ADDRESS, 190 .d_SYSTEM_SLEEP_OFFSET = WLAN_SYSTEM_SLEEP_OFFSET, 191 .d_WLAN_SYSTEM_SLEEP_OFFSET = WLAN_SYSTEM_SLEEP_OFFSET, 192 .d_WLAN_SYSTEM_SLEEP_DISABLE_LSB = WLAN_SYSTEM_SLEEP_DISABLE_LSB, 193 .d_WLAN_SYSTEM_SLEEP_DISABLE_MASK = WLAN_SYSTEM_SLEEP_DISABLE_MASK, 194 .d_CLOCK_CONTROL_OFFSET = CLOCK_CONTROL_OFFSET, 195 .d_CLOCK_CONTROL_SI0_CLK_MASK = CLOCK_CONTROL_SI0_CLK_MASK, 196 .d_RESET_CONTROL_OFFSET = SOC_RESET_CONTROL_OFFSET, 197 .d_RESET_CONTROL_SI0_RST_MASK = RESET_CONTROL_SI0_RST_MASK, 198 .d_WLAN_RESET_CONTROL_OFFSET = WLAN_RESET_CONTROL_OFFSET, 199 .d_WLAN_RESET_CONTROL_COLD_RST_MASK = WLAN_RESET_CONTROL_COLD_RST_MASK, 200 .d_WLAN_RESET_CONTROL_WARM_RST_MASK = WLAN_RESET_CONTROL_WARM_RST_MASK, 201 .d_GPIO_BASE_ADDRESS = GPIO_BASE_ADDRESS, 202 .d_GPIO_PIN0_OFFSET = GPIO_PIN0_OFFSET, 203 .d_GPIO_PIN1_OFFSET = GPIO_PIN1_OFFSET, 204 .d_GPIO_PIN0_CONFIG_MASK = GPIO_PIN0_CONFIG_MASK, 205 .d_GPIO_PIN1_CONFIG_MASK = GPIO_PIN1_CONFIG_MASK, 206 .d_SI_CONFIG_BIDIR_OD_DATA_LSB = SI_CONFIG_BIDIR_OD_DATA_LSB, 207 .d_SI_CONFIG_BIDIR_OD_DATA_MASK = SI_CONFIG_BIDIR_OD_DATA_MASK, 208 .d_SI_CONFIG_I2C_LSB = SI_CONFIG_I2C_LSB, 209 .d_SI_CONFIG_I2C_MASK = SI_CONFIG_I2C_MASK, 210 .d_SI_CONFIG_POS_SAMPLE_LSB = SI_CONFIG_POS_SAMPLE_LSB, 211 .d_SI_CONFIG_POS_SAMPLE_MASK = SI_CONFIG_POS_SAMPLE_MASK, 212 .d_SI_CONFIG_INACTIVE_CLK_LSB = SI_CONFIG_INACTIVE_CLK_LSB, 213 .d_SI_CONFIG_INACTIVE_CLK_MASK = SI_CONFIG_INACTIVE_CLK_MASK, 214 .d_SI_CONFIG_INACTIVE_DATA_LSB = SI_CONFIG_INACTIVE_DATA_LSB, 215 .d_SI_CONFIG_INACTIVE_DATA_MASK = SI_CONFIG_INACTIVE_DATA_MASK, 216 .d_SI_CONFIG_DIVIDER_LSB = SI_CONFIG_DIVIDER_LSB, 217 .d_SI_CONFIG_DIVIDER_MASK = SI_CONFIG_DIVIDER_MASK, 218 .d_SI_BASE_ADDRESS = SI_BASE_ADDRESS, 219 .d_SI_CONFIG_OFFSET = SI_CONFIG_OFFSET, 220 .d_SI_TX_DATA0_OFFSET = SI_TX_DATA0_OFFSET, 221 .d_SI_TX_DATA1_OFFSET = SI_TX_DATA1_OFFSET, 222 .d_SI_RX_DATA0_OFFSET = SI_RX_DATA0_OFFSET, 223 .d_SI_RX_DATA1_OFFSET = SI_RX_DATA1_OFFSET, 224 .d_SI_CS_OFFSET = SI_CS_OFFSET, 225 .d_SI_CS_DONE_ERR_MASK = SI_CS_DONE_ERR_MASK, 226 .d_SI_CS_DONE_INT_MASK = SI_CS_DONE_INT_MASK, 227 .d_SI_CS_START_LSB = SI_CS_START_LSB, 228 .d_SI_CS_START_MASK = SI_CS_START_MASK, 229 .d_SI_CS_RX_CNT_LSB = SI_CS_RX_CNT_LSB, 230 .d_SI_CS_RX_CNT_MASK = SI_CS_RX_CNT_MASK, 231 .d_SI_CS_TX_CNT_LSB = SI_CS_TX_CNT_LSB, 232 .d_SI_CS_TX_CNT_MASK = SI_CS_TX_CNT_MASK, 233 .d_BOARD_DATA_SZ = MY_TARGET_BOARD_DATA_SZ, 234 .d_BOARD_EXT_DATA_SZ = MY_TARGET_BOARD_EXT_DATA_SZ, 235 .d_MBOX_BASE_ADDRESS = MBOX_BASE_ADDRESS, 236 .d_LOCAL_SCRATCH_OFFSET = LOCAL_SCRATCH_OFFSET, 237 .d_CPU_CLOCK_OFFSET = CPU_CLOCK_OFFSET, 238 .d_GPIO_PIN10_OFFSET = GPIO_PIN10_OFFSET, 239 .d_GPIO_PIN11_OFFSET = GPIO_PIN11_OFFSET, 240 .d_GPIO_PIN12_OFFSET = GPIO_PIN12_OFFSET, 241 .d_GPIO_PIN13_OFFSET = GPIO_PIN13_OFFSET, 242 .d_CLOCK_GPIO_OFFSET = CLOCK_GPIO_OFFSET, 243 .d_CPU_CLOCK_STANDARD_LSB = CPU_CLOCK_STANDARD_LSB, 244 .d_CPU_CLOCK_STANDARD_MASK = CPU_CLOCK_STANDARD_MASK, 245 .d_LPO_CAL_ENABLE_LSB = LPO_CAL_ENABLE_LSB, 246 .d_LPO_CAL_ENABLE_MASK = LPO_CAL_ENABLE_MASK, 247 .d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB = CLOCK_GPIO_BT_CLK_OUT_EN_LSB, 248 .d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK = CLOCK_GPIO_BT_CLK_OUT_EN_MASK, 249 .d_ANALOG_INTF_BASE_ADDRESS = ANALOG_INTF_BASE_ADDRESS, 250 .d_WLAN_MAC_BASE_ADDRESS = WLAN_MAC_BASE_ADDRESS, 251 .d_FW_INDICATOR_ADDRESS = FW_INDICATOR_ADDRESS, 252 .d_FW_CPU_PLL_CONFIG = FW_CPU_PLL_CONFIG, 253 .d_DRAM_BASE_ADDRESS = DRAM_BASE_ADDRESS, 254 .d_SOC_CORE_BASE_ADDRESS = SOC_CORE_BASE_ADDRESS, 255 .d_CORE_CTRL_ADDRESS = CORE_CTRL_ADDRESS, 256 .d_CE_COUNT = CE_COUNT, 257 .d_MSI_NUM_REQUEST = MSI_NUM_REQUEST, 258 .d_MSI_ASSIGN_FW = MSI_ASSIGN_FW, 259 .d_MSI_ASSIGN_CE_INITIAL = MSI_ASSIGN_CE_INITIAL, 260 .d_PCIE_INTR_ENABLE_ADDRESS = PCIE_INTR_ENABLE_ADDRESS, 261 .d_PCIE_INTR_CLR_ADDRESS = PCIE_INTR_CLR_ADDRESS, 262 .d_PCIE_INTR_FIRMWARE_MASK = PCIE_INTR_FIRMWARE_MASK, 263 .d_PCIE_INTR_CE_MASK_ALL = PCIE_INTR_CE_MASK_ALL, 264 .d_CORE_CTRL_CPU_INTR_MASK = CORE_CTRL_CPU_INTR_MASK, 265 .d_WIFICMN_PCIE_BAR_REG_ADDRESS = WIFICMN_PCIE_BAR_REG_ADDRESS, 266 /* htt_rx.c */ 267 /* htt tx */ 268 .d_MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK 269 = MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK, 270 .d_MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK 271 = MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK, 272 .d_MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK 273 = MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK, 274 .d_MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK 275 = MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK, 276 .d_MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB 277 = MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB, 278 .d_MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB 279 = MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB, 280 .d_MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB 281 = MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB, 282 .d_MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB 283 = MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB, 284 /* copy_engine.c */ 285 .d_SR_WR_INDEX_ADDRESS = SR_WR_INDEX_ADDRESS, 286 .d_DST_WATERMARK_ADDRESS = DST_WATERMARK_ADDRESS, 287 288 .d_PCIE_INTR_CAUSE_ADDRESS = PCIE_INTR_CAUSE_ADDRESS, 289 .d_SOC_RESET_CONTROL_ADDRESS = SOC_RESET_CONTROL_ADDRESS, 290 .d_SOC_RESET_CONTROL_CE_RST_MASK = SOC_RESET_CONTROL_CE_RST_MASK, 291 .d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK 292 = SOC_RESET_CONTROL_CPU_WARM_RST_MASK, 293 .d_CPU_INTR_ADDRESS = CPU_INTR_ADDRESS, 294 .d_SOC_LF_TIMER_CONTROL0_ADDRESS = SOC_LF_TIMER_CONTROL0_ADDRESS, 295 .d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK 296 = SOC_LF_TIMER_CONTROL0_ENABLE_MASK, 297 .d_SOC_LF_TIMER_STATUS0_ADDRESS = SOC_LF_TIMER_STATUS0_ADDRESS, 298 .d_SI_CONFIG_ERR_INT_MASK = SI_CONFIG_ERR_INT_MASK, 299 .d_SI_CONFIG_ERR_INT_LSB = SI_CONFIG_ERR_INT_LSB, 300 .d_GPIO_ENABLE_W1TS_LOW_ADDRESS = GPIO_ENABLE_W1TS_LOW_ADDRESS, 301 .d_GPIO_PIN0_CONFIG_LSB = GPIO_PIN0_CONFIG_LSB, 302 .d_GPIO_PIN0_PAD_PULL_LSB = GPIO_PIN0_PAD_PULL_LSB, 303 .d_GPIO_PIN0_PAD_PULL_MASK = GPIO_PIN0_PAD_PULL_MASK, 304 .d_SOC_CHIP_ID_ADDRESS = SOC_CHIP_ID_ADDRESS, 305 .d_SOC_CHIP_ID_REVISION_MASK = SOC_CHIP_ID_REVISION_MASK, 306 .d_SOC_CHIP_ID_REVISION_LSB = SOC_CHIP_ID_REVISION_LSB, 307 .d_SOC_CHIP_ID_REVISION_MSB = SOC_CHIP_ID_REVISION_MSB, 308 .d_WIFICMN_PCIE_BAR_REG_ADDRESS = WIFICMN_PCIE_BAR_REG_ADDRESS, 309 .d_FW_AXI_MSI_ADDR = FW_AXI_MSI_ADDR, 310 .d_FW_AXI_MSI_DATA = FW_AXI_MSI_DATA, 311 .d_WLAN_SUBSYSTEM_CORE_ID_ADDRESS = WLAN_SUBSYSTEM_CORE_ID_ADDRESS, 312 .d_WIFICMN_INT_STATUS_ADDRESS = WIFICMN_INT_STATUS_ADDRESS, 313 }; 314 315 struct targetdef_s *MY_TARGET_DEF = &my_target_def; 316 #else 317 #endif 318 319 #if defined(MY_CEREG_DEF) 320 321 #if !defined(CE_DDR_ADDRESS_FOR_RRI_LOW) 322 #define CE_DDR_ADDRESS_FOR_RRI_LOW ATH_UNSUPPORTED_REG_OFFSET 323 #endif 324 #if !defined(CE_DDR_ADDRESS_FOR_RRI_HIGH) 325 #define CE_DDR_ADDRESS_FOR_RRI_HIGH ATH_UNSUPPORTED_REG_OFFSET 326 #endif 327 #if !defined(SR_BA_ADDRESS_HIGH) 328 #define SR_BA_ADDRESS_HIGH ATH_UNSUPPORTED_REG_OFFSET 329 #endif 330 #if !defined(DR_BA_ADDRESS_HIGH) 331 #define DR_BA_ADDRESS_HIGH ATH_UNSUPPORTED_REG_OFFSET 332 #endif 333 #if !defined(CE_CMD_REGISTER) 334 #define CE_CMD_REGISTER ATH_UNSUPPORTED_REG_OFFSET 335 #endif 336 #if !defined(CE_MSI_ADDRESS) 337 #define CE_MSI_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 338 #endif 339 #if !defined(CE_MSI_ADDRESS_HIGH) 340 #define CE_MSI_ADDRESS_HIGH ATH_UNSUPPORTED_REG_OFFSET 341 #endif 342 #if !defined(CE_MSI_DATA) 343 #define CE_MSI_DATA ATH_UNSUPPORTED_REG_OFFSET 344 #endif 345 #if !defined(CE_MSI_ENABLE_BIT) 346 #define CE_MSI_ENABLE_BIT ATH_UNSUPPORTED_REG_OFFSET 347 #endif 348 #if !defined(CE_CTRL1_IDX_UPD_EN_MASK) 349 #define CE_CTRL1_IDX_UPD_EN_MASK ATH_UNSUPPORTED_REG_OFFSET 350 #endif 351 #if !defined(CE_WRAPPER_DEBUG_OFFSET) 352 #define CE_WRAPPER_DEBUG_OFFSET ATH_UNSUPPORTED_REG_OFFSET 353 #endif 354 #if !defined(CE_DEBUG_OFFSET) 355 #define CE_DEBUG_OFFSET ATH_UNSUPPORTED_REG_OFFSET 356 #endif 357 #if !defined(A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES) 358 #define A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES ATH_UNSUPPORTED_REG_OFFSET 359 #endif 360 #if !defined(A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_STATUS) 361 #define A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_STATUS ATH_UNSUPPORTED_REG_OFFSET 362 #endif 363 #if !defined(HOST_IE_ADDRESS_2) 364 #define HOST_IE_ADDRESS_2 ATH_UNSUPPORTED_REG_OFFSET 365 #endif 366 #if !defined(HOST_IE_ADDRESS_3) 367 #define HOST_IE_ADDRESS_3 ATH_UNSUPPORTED_REG_OFFSET 368 #endif 369 #if !defined(HOST_IE_REG1_CE_LSB) 370 #define HOST_IE_REG1_CE_LSB 0 371 #endif 372 #if !defined(HOST_IE_REG2_CE_LSB) 373 #define HOST_IE_REG2_CE_LSB 0 374 #endif 375 #if !defined(HOST_IE_REG3_CE_LSB) 376 #define HOST_IE_REG3_CE_LSB 0 377 #endif 378 #if !defined(HOST_CE_ADDRESS) 379 #define HOST_CE_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 380 #endif 381 382 static struct ce_reg_def my_ce_reg_def = { 383 /* copy_engine.c */ 384 .d_DST_WR_INDEX_ADDRESS = DST_WR_INDEX_ADDRESS, 385 .d_SRC_WATERMARK_ADDRESS = SRC_WATERMARK_ADDRESS, 386 .d_SRC_WATERMARK_LOW_MASK = SRC_WATERMARK_LOW_MASK, 387 .d_SRC_WATERMARK_HIGH_MASK = SRC_WATERMARK_HIGH_MASK, 388 .d_DST_WATERMARK_LOW_MASK = DST_WATERMARK_LOW_MASK, 389 .d_DST_WATERMARK_HIGH_MASK = DST_WATERMARK_HIGH_MASK, 390 .d_CURRENT_SRRI_ADDRESS = CURRENT_SRRI_ADDRESS, 391 .d_CURRENT_DRRI_ADDRESS = CURRENT_DRRI_ADDRESS, 392 .d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK 393 = HOST_IS_SRC_RING_HIGH_WATERMARK_MASK, 394 .d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK 395 = HOST_IS_SRC_RING_LOW_WATERMARK_MASK, 396 .d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK 397 = HOST_IS_DST_RING_HIGH_WATERMARK_MASK, 398 .d_HOST_IS_DST_RING_LOW_WATERMARK_MASK 399 = HOST_IS_DST_RING_LOW_WATERMARK_MASK, 400 .d_HOST_IS_ADDRESS = HOST_IS_ADDRESS, 401 .d_MISC_IS_ADDRESS = MISC_IS_ADDRESS, 402 .d_HOST_IS_COPY_COMPLETE_MASK = HOST_IS_COPY_COMPLETE_MASK, 403 .d_CE_WRAPPER_BASE_ADDRESS = CE_WRAPPER_BASE_ADDRESS, 404 .d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS 405 = CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS, 406 .d_CE_DDR_ADDRESS_FOR_RRI_LOW = CE_DDR_ADDRESS_FOR_RRI_LOW, 407 .d_CE_DDR_ADDRESS_FOR_RRI_HIGH = CE_DDR_ADDRESS_FOR_RRI_HIGH, 408 .d_HOST_IE_ADDRESS = HOST_IE_ADDRESS, 409 .d_HOST_IE_REG1_CE_LSB = HOST_IE_REG1_CE_LSB, 410 .d_HOST_IE_ADDRESS_2 = HOST_IE_ADDRESS_2, 411 .d_HOST_IE_REG2_CE_LSB = HOST_IE_REG2_CE_LSB, 412 .d_HOST_IE_ADDRESS_3 = HOST_IE_ADDRESS_3, 413 .d_HOST_IE_REG3_CE_LSB = HOST_IE_REG3_CE_LSB, 414 .d_HOST_IE_COPY_COMPLETE_MASK = HOST_IE_COPY_COMPLETE_MASK, 415 .d_SR_BA_ADDRESS = SR_BA_ADDRESS, 416 .d_SR_BA_ADDRESS_HIGH = SR_BA_ADDRESS_HIGH, 417 .d_SR_SIZE_ADDRESS = SR_SIZE_ADDRESS, 418 .d_CE_CTRL1_ADDRESS = CE_CTRL1_ADDRESS, 419 .d_CE_CTRL1_DMAX_LENGTH_MASK = CE_CTRL1_DMAX_LENGTH_MASK, 420 .d_DR_BA_ADDRESS = DR_BA_ADDRESS, 421 .d_DR_BA_ADDRESS_HIGH = DR_BA_ADDRESS_HIGH, 422 .d_DR_SIZE_ADDRESS = DR_SIZE_ADDRESS, 423 .d_CE_CMD_REGISTER = CE_CMD_REGISTER, 424 .d_CE_MSI_ADDRESS = CE_MSI_ADDRESS, 425 .d_CE_MSI_ADDRESS_HIGH = CE_MSI_ADDRESS_HIGH, 426 .d_CE_MSI_DATA = CE_MSI_DATA, 427 .d_CE_MSI_ENABLE_BIT = CE_MSI_ENABLE_BIT, 428 .d_MISC_IE_ADDRESS = MISC_IE_ADDRESS, 429 .d_MISC_IS_AXI_ERR_MASK = MISC_IS_AXI_ERR_MASK, 430 .d_MISC_IS_DST_ADDR_ERR_MASK = MISC_IS_DST_ADDR_ERR_MASK, 431 .d_MISC_IS_SRC_LEN_ERR_MASK = MISC_IS_SRC_LEN_ERR_MASK, 432 .d_MISC_IS_DST_MAX_LEN_VIO_MASK = MISC_IS_DST_MAX_LEN_VIO_MASK, 433 .d_MISC_IS_DST_RING_OVERFLOW_MASK = MISC_IS_DST_RING_OVERFLOW_MASK, 434 .d_MISC_IS_SRC_RING_OVERFLOW_MASK = MISC_IS_SRC_RING_OVERFLOW_MASK, 435 .d_SRC_WATERMARK_LOW_LSB = SRC_WATERMARK_LOW_LSB, 436 .d_SRC_WATERMARK_HIGH_LSB = SRC_WATERMARK_HIGH_LSB, 437 .d_DST_WATERMARK_LOW_LSB = DST_WATERMARK_LOW_LSB, 438 .d_DST_WATERMARK_HIGH_LSB = DST_WATERMARK_HIGH_LSB, 439 .d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK 440 = CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK, 441 .d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB 442 = CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB, 443 .d_CE_CTRL1_DMAX_LENGTH_LSB = CE_CTRL1_DMAX_LENGTH_LSB, 444 .d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK 445 = CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK, 446 .d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK 447 = CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK, 448 .d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB 449 = CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB, 450 .d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB 451 = CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB, 452 .d_CE_CTRL1_IDX_UPD_EN_MASK = CE_CTRL1_IDX_UPD_EN_MASK, 453 .d_CE_WRAPPER_DEBUG_OFFSET = CE_WRAPPER_DEBUG_OFFSET, 454 .d_CE_WRAPPER_DEBUG_SEL_MSB = CE_WRAPPER_DEBUG_SEL_MSB, 455 .d_CE_WRAPPER_DEBUG_SEL_LSB = CE_WRAPPER_DEBUG_SEL_LSB, 456 .d_CE_WRAPPER_DEBUG_SEL_MASK = CE_WRAPPER_DEBUG_SEL_MASK, 457 .d_CE_DEBUG_OFFSET = CE_DEBUG_OFFSET, 458 .d_CE_DEBUG_SEL_MSB = CE_DEBUG_SEL_MSB, 459 .d_CE_DEBUG_SEL_LSB = CE_DEBUG_SEL_LSB, 460 .d_CE_DEBUG_SEL_MASK = CE_DEBUG_SEL_MASK, 461 .d_CE0_BASE_ADDRESS = CE0_BASE_ADDRESS, 462 .d_CE1_BASE_ADDRESS = CE1_BASE_ADDRESS, 463 .d_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES 464 = A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES, 465 .d_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_STATUS 466 = A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_STATUS, 467 .d_HOST_CE_ADDRESS = HOST_CE_ADDRESS 468 }; 469 470 struct ce_reg_def *MY_CEREG_DEF = &my_ce_reg_def; 471 472 #else 473 #endif 474 #endif 475