1 /* 2 * Copyright (c) 2011-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _REGTABLE_PCIE_H_ 20 #define _REGTABLE_PCIE_H_ 21 22 #define MISSING 0 23 24 #define A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK \ 25 (scn->targetdef->d_A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK) 26 #define A_SOC_CORE_PCIE_INTR_CAUSE_GRP1 \ 27 (scn->targetdef->d_A_SOC_CORE_PCIE_INTR_CAUSE_GRP1) 28 #define A_SOC_CORE_SPARE_1_REGISTER \ 29 (scn->targetdef->d_A_SOC_CORE_SPARE_1_REGISTER) 30 #define A_SOC_CORE_PCIE_INTR_CLR_GRP1 \ 31 (scn->targetdef->d_A_SOC_CORE_PCIE_INTR_CLR_GRP1) 32 #define A_SOC_CORE_PCIE_INTR_ENABLE_GRP1 \ 33 (scn->targetdef->d_A_SOC_CORE_PCIE_INTR_ENABLE_GRP1) 34 #define A_SOC_PCIE_PCIE_SCRATCH_0 \ 35 (scn->targetdef->d_A_SOC_PCIE_PCIE_SCRATCH_0) 36 #define A_SOC_PCIE_PCIE_SCRATCH_1 \ 37 (scn->targetdef->d_A_SOC_PCIE_PCIE_SCRATCH_1) 38 #define A_WIFI_APB_1_A_WFSS_CE_TARGET_HOST_DELTA \ 39 (scn->targetdef->d_A_WIFI_APB_1_A_WFSS_CE_TARGET_HOST_DELTA) 40 #define A_SOC_PCIE_PCIE_SCRATCH_2 \ 41 (scn->targetdef->d_A_SOC_PCIE_PCIE_SCRATCH_2) 42 /* end Q6 iHelium emu registers */ 43 44 #define PCIE_INTR_FIRMWARE_ROUTE_MASK \ 45 (scn->targetdef->d_PCIE_INTR_FIRMWARE_ROUTE_MASK) 46 #define A_SOC_CORE_SPARE_0_REGISTER \ 47 (scn->targetdef->d_A_SOC_CORE_SPARE_0_REGISTER) 48 #define A_SOC_CORE_SCRATCH_0_ADDRESS \ 49 (scn->targetdef->d_A_SOC_CORE_SCRATCH_0_ADDRESS) 50 #define A_SOC_CORE_SCRATCH_1_ADDRESS \ 51 (scn->targetdef->d_A_SOC_CORE_SCRATCH_1_ADDRESS) 52 #define A_SOC_CORE_SCRATCH_2_ADDRESS \ 53 (scn->targetdef->d_A_SOC_CORE_SCRATCH_2_ADDRESS) 54 #define A_SOC_CORE_SCRATCH_3_ADDRESS \ 55 (scn->targetdef->d_A_SOC_CORE_SCRATCH_3_ADDRESS) 56 #define A_SOC_CORE_SCRATCH_4_ADDRESS \ 57 (scn->targetdef->d_A_SOC_CORE_SCRATCH_4_ADDRESS) 58 #define A_SOC_CORE_SCRATCH_5_ADDRESS \ 59 (scn->targetdef->d_A_SOC_CORE_SCRATCH_5_ADDRESS) 60 #define A_SOC_CORE_SCRATCH_6_ADDRESS \ 61 (scn->targetdef->d_A_SOC_CORE_SCRATCH_6_ADDRESS) 62 #define A_SOC_CORE_SCRATCH_7_ADDRESS \ 63 (scn->targetdef->d_A_SOC_CORE_SCRATCH_7_ADDRESS) 64 #define RTC_SOC_BASE_ADDRESS (scn->targetdef->d_RTC_SOC_BASE_ADDRESS) 65 #define RTC_WMAC_BASE_ADDRESS (scn->targetdef->d_RTC_WMAC_BASE_ADDRESS) 66 #define SYSTEM_SLEEP_OFFSET (scn->targetdef->d_SYSTEM_SLEEP_OFFSET) 67 #define WLAN_SYSTEM_SLEEP_OFFSET \ 68 (scn->targetdef->d_WLAN_SYSTEM_SLEEP_OFFSET) 69 #define WLAN_SYSTEM_SLEEP_DISABLE_LSB \ 70 (scn->targetdef->d_WLAN_SYSTEM_SLEEP_DISABLE_LSB) 71 #define WLAN_SYSTEM_SLEEP_DISABLE_MASK \ 72 (scn->targetdef->d_WLAN_SYSTEM_SLEEP_DISABLE_MASK) 73 #define CLOCK_CONTROL_OFFSET (scn->targetdef->d_CLOCK_CONTROL_OFFSET) 74 #define CLOCK_CONTROL_SI0_CLK_MASK \ 75 (scn->targetdef->d_CLOCK_CONTROL_SI0_CLK_MASK) 76 #define RESET_CONTROL_OFFSET (scn->targetdef->d_RESET_CONTROL_OFFSET) 77 #define RESET_CONTROL_MBOX_RST_MASK \ 78 (scn->targetdef->d_RESET_CONTROL_MBOX_RST_MASK) 79 #define RESET_CONTROL_SI0_RST_MASK \ 80 (scn->targetdef->d_RESET_CONTROL_SI0_RST_MASK) 81 #define WLAN_RESET_CONTROL_OFFSET \ 82 (scn->targetdef->d_WLAN_RESET_CONTROL_OFFSET) 83 #define WLAN_RESET_CONTROL_COLD_RST_MASK \ 84 (scn->targetdef->d_WLAN_RESET_CONTROL_COLD_RST_MASK) 85 #define WLAN_RESET_CONTROL_WARM_RST_MASK \ 86 (scn->targetdef->d_WLAN_RESET_CONTROL_WARM_RST_MASK) 87 #define GPIO_BASE_ADDRESS (scn->targetdef->d_GPIO_BASE_ADDRESS) 88 #define GPIO_PIN0_OFFSET (scn->targetdef->d_GPIO_PIN0_OFFSET) 89 #define GPIO_PIN1_OFFSET (scn->targetdef->d_GPIO_PIN1_OFFSET) 90 #define GPIO_PIN0_CONFIG_MASK (scn->targetdef->d_GPIO_PIN0_CONFIG_MASK) 91 #define GPIO_PIN1_CONFIG_MASK (scn->targetdef->d_GPIO_PIN1_CONFIG_MASK) 92 #define A_SOC_CORE_SCRATCH_0 (scn->targetdef->d_A_SOC_CORE_SCRATCH_0) 93 #define SI_CONFIG_BIDIR_OD_DATA_LSB \ 94 (scn->targetdef->d_SI_CONFIG_BIDIR_OD_DATA_LSB) 95 #define SI_CONFIG_BIDIR_OD_DATA_MASK \ 96 (scn->targetdef->d_SI_CONFIG_BIDIR_OD_DATA_MASK) 97 #define SI_CONFIG_I2C_LSB (scn->targetdef->d_SI_CONFIG_I2C_LSB) 98 #define SI_CONFIG_I2C_MASK \ 99 (scn->targetdef->d_SI_CONFIG_I2C_MASK) 100 #define SI_CONFIG_POS_SAMPLE_LSB \ 101 (scn->targetdef->d_SI_CONFIG_POS_SAMPLE_LSB) 102 #define SI_CONFIG_POS_SAMPLE_MASK \ 103 (scn->targetdef->d_SI_CONFIG_POS_SAMPLE_MASK) 104 #define SI_CONFIG_INACTIVE_CLK_LSB \ 105 (scn->targetdef->d_SI_CONFIG_INACTIVE_CLK_LSB) 106 #define SI_CONFIG_INACTIVE_CLK_MASK \ 107 (scn->targetdef->d_SI_CONFIG_INACTIVE_CLK_MASK) 108 #define SI_CONFIG_INACTIVE_DATA_LSB \ 109 (scn->targetdef->d_SI_CONFIG_INACTIVE_DATA_LSB) 110 #define SI_CONFIG_INACTIVE_DATA_MASK \ 111 (scn->targetdef->d_SI_CONFIG_INACTIVE_DATA_MASK) 112 #define SI_CONFIG_DIVIDER_LSB (scn->targetdef->d_SI_CONFIG_DIVIDER_LSB) 113 #define SI_CONFIG_DIVIDER_MASK (scn->targetdef->d_SI_CONFIG_DIVIDER_MASK) 114 #define SI_BASE_ADDRESS (scn->targetdef->d_SI_BASE_ADDRESS) 115 #define SI_CONFIG_OFFSET (scn->targetdef->d_SI_CONFIG_OFFSET) 116 #define SI_TX_DATA0_OFFSET (scn->targetdef->d_SI_TX_DATA0_OFFSET) 117 #define SI_TX_DATA1_OFFSET (scn->targetdef->d_SI_TX_DATA1_OFFSET) 118 #define SI_RX_DATA0_OFFSET (scn->targetdef->d_SI_RX_DATA0_OFFSET) 119 #define SI_RX_DATA1_OFFSET (scn->targetdef->d_SI_RX_DATA1_OFFSET) 120 #define SI_CS_OFFSET (scn->targetdef->d_SI_CS_OFFSET) 121 #define SI_CS_DONE_ERR_MASK (scn->targetdef->d_SI_CS_DONE_ERR_MASK) 122 #define SI_CS_DONE_INT_MASK (scn->targetdef->d_SI_CS_DONE_INT_MASK) 123 #define SI_CS_START_LSB (scn->targetdef->d_SI_CS_START_LSB) 124 #define SI_CS_START_MASK (scn->targetdef->d_SI_CS_START_MASK) 125 #define SI_CS_RX_CNT_LSB (scn->targetdef->d_SI_CS_RX_CNT_LSB) 126 #define SI_CS_RX_CNT_MASK (scn->targetdef->d_SI_CS_RX_CNT_MASK) 127 #define SI_CS_TX_CNT_LSB (scn->targetdef->d_SI_CS_TX_CNT_LSB) 128 #define SI_CS_TX_CNT_MASK (scn->targetdef->d_SI_CS_TX_CNT_MASK) 129 #define EEPROM_SZ (scn->targetdef->d_BOARD_DATA_SZ) 130 #define EEPROM_EXT_SZ (scn->targetdef->d_BOARD_EXT_DATA_SZ) 131 #define MBOX_BASE_ADDRESS (scn->targetdef->d_MBOX_BASE_ADDRESS) 132 #define LOCAL_SCRATCH_OFFSET (scn->targetdef->d_LOCAL_SCRATCH_OFFSET) 133 #define CPU_CLOCK_OFFSET (scn->targetdef->d_CPU_CLOCK_OFFSET) 134 #define LPO_CAL_OFFSET (scn->targetdef->d_LPO_CAL_OFFSET) 135 #define GPIO_PIN10_OFFSET (scn->targetdef->d_GPIO_PIN10_OFFSET) 136 #define GPIO_PIN11_OFFSET (scn->targetdef->d_GPIO_PIN11_OFFSET) 137 #define GPIO_PIN12_OFFSET (scn->targetdef->d_GPIO_PIN12_OFFSET) 138 #define GPIO_PIN13_OFFSET (scn->targetdef->d_GPIO_PIN13_OFFSET) 139 #define CLOCK_GPIO_OFFSET (scn->targetdef->d_CLOCK_GPIO_OFFSET) 140 #define CPU_CLOCK_STANDARD_LSB (scn->targetdef->d_CPU_CLOCK_STANDARD_LSB) 141 #define CPU_CLOCK_STANDARD_MASK (scn->targetdef->d_CPU_CLOCK_STANDARD_MASK) 142 #define LPO_CAL_ENABLE_LSB (scn->targetdef->d_LPO_CAL_ENABLE_LSB) 143 #define LPO_CAL_ENABLE_MASK (scn->targetdef->d_LPO_CAL_ENABLE_MASK) 144 #define CLOCK_GPIO_BT_CLK_OUT_EN_LSB \ 145 (scn->targetdef->d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB) 146 #define CLOCK_GPIO_BT_CLK_OUT_EN_MASK \ 147 (scn->targetdef->d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK) 148 #define ANALOG_INTF_BASE_ADDRESS (scn->targetdef->d_ANALOG_INTF_BASE_ADDRESS) 149 #define WLAN_MAC_BASE_ADDRESS (scn->targetdef->d_WLAN_MAC_BASE_ADDRESS) 150 #define FW_INDICATOR_ADDRESS (scn->targetdef->d_FW_INDICATOR_ADDRESS) 151 #define DRAM_BASE_ADDRESS (scn->targetdef->d_DRAM_BASE_ADDRESS) 152 #define SOC_CORE_BASE_ADDRESS (scn->targetdef->d_SOC_CORE_BASE_ADDRESS) 153 #define CORE_CTRL_ADDRESS (scn->targetdef->d_CORE_CTRL_ADDRESS) 154 #define CE_COUNT (scn->targetdef->d_CE_COUNT) 155 #define PCIE_INTR_ENABLE_ADDRESS (scn->targetdef->d_PCIE_INTR_ENABLE_ADDRESS) 156 #define PCIE_INTR_CLR_ADDRESS (scn->targetdef->d_PCIE_INTR_CLR_ADDRESS) 157 #define PCIE_INTR_FIRMWARE_MASK (scn->targetdef->d_PCIE_INTR_FIRMWARE_MASK) 158 #define PCIE_INTR_CE_MASK_ALL (scn->targetdef->d_PCIE_INTR_CE_MASK_ALL) 159 #define CORE_CTRL_CPU_INTR_MASK (scn->targetdef->d_CORE_CTRL_CPU_INTR_MASK) 160 #define PCIE_INTR_CAUSE_ADDRESS (scn->targetdef->d_PCIE_INTR_CAUSE_ADDRESS) 161 #define SOC_RESET_CONTROL_ADDRESS (scn->targetdef->d_SOC_RESET_CONTROL_ADDRESS) 162 #define HOST_GROUP0_MASK (PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL | \ 163 A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK) 164 #define SOC_RESET_CONTROL_CE_RST_MASK \ 165 (scn->targetdef->d_SOC_RESET_CONTROL_CE_RST_MASK) 166 #define SOC_RESET_CONTROL_CPU_WARM_RST_MASK \ 167 (scn->targetdef->d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK) 168 #define CPU_INTR_ADDRESS (scn->targetdef->d_CPU_INTR_ADDRESS) 169 #define SOC_LF_TIMER_CONTROL0_ADDRESS \ 170 (scn->targetdef->d_SOC_LF_TIMER_CONTROL0_ADDRESS) 171 #define SOC_LF_TIMER_CONTROL0_ENABLE_MASK \ 172 (scn->targetdef->d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK) 173 #define SOC_LF_TIMER_STATUS0_ADDRESS \ 174 (scn->targetdef->d_SOC_LF_TIMER_STATUS0_ADDRESS) 175 #define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB \ 176 (scn->targetdef->d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB) 177 #define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK \ 178 (scn->targetdef->d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK) 179 180 #define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_GET(x) \ 181 (((x) & SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK) >> \ 182 SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB) 183 #define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_SET(x) \ 184 (((x) << SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB) & \ 185 SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK) 186 187 /* hif_pci.c */ 188 #define CHIP_ID_ADDRESS (scn->targetdef->d_SOC_CHIP_ID_ADDRESS) 189 #define SOC_CHIP_ID_REVISION_MASK (scn->targetdef->d_SOC_CHIP_ID_REVISION_MASK) 190 #define SOC_CHIP_ID_REVISION_LSB (scn->targetdef->d_SOC_CHIP_ID_REVISION_LSB) 191 #define SOC_CHIP_ID_VERSION_MASK (scn->targetdef->d_SOC_CHIP_ID_VERSION_MASK) 192 #define SOC_CHIP_ID_VERSION_LSB (scn->targetdef->d_SOC_CHIP_ID_VERSION_LSB) 193 #define CHIP_ID_REVISION_GET(x) \ 194 (((x) & SOC_CHIP_ID_REVISION_MASK) >> SOC_CHIP_ID_REVISION_LSB) 195 #define CHIP_ID_VERSION_GET(x) \ 196 (((x) & SOC_CHIP_ID_VERSION_MASK) >> SOC_CHIP_ID_VERSION_LSB) 197 /* hif_pci.c end */ 198 199 /* misc */ 200 #define SR_WR_INDEX_ADDRESS (scn->targetdef->d_SR_WR_INDEX_ADDRESS) 201 #define DST_WATERMARK_ADDRESS (scn->targetdef->d_DST_WATERMARK_ADDRESS) 202 #define SOC_POWER_REG_OFFSET (scn->targetdef->d_SOC_POWER_REG_OFFSET) 203 /* end */ 204 205 #if !defined(CONFIG_WIN) 206 /* htt_rx.c */ 207 #define RX_MSDU_END_4_FIRST_MSDU_MASK \ 208 (pdev->targetdef->d_RX_MSDU_END_4_FIRST_MSDU_MASK) 209 #define RX_MSDU_END_4_FIRST_MSDU_LSB \ 210 (pdev->targetdef->d_RX_MSDU_END_4_FIRST_MSDU_LSB) 211 #define RX_MPDU_START_0_RETRY_LSB \ 212 (pdev->targetdef->d_RX_MPDU_START_0_RETRY_LSB) 213 #define RX_MPDU_START_0_RETRY_MASK \ 214 (pdev->targetdef->d_RX_MPDU_START_0_RETRY_MASK) 215 #define RX_MPDU_START_0_SEQ_NUM_MASK \ 216 (pdev->targetdef->d_RX_MPDU_START_0_SEQ_NUM_MASK) 217 #define RX_MPDU_START_0_SEQ_NUM_LSB \ 218 (pdev->targetdef->d_RX_MPDU_START_0_SEQ_NUM_LSB) 219 #define RX_MPDU_START_2_PN_47_32_LSB \ 220 (pdev->targetdef->d_RX_MPDU_START_2_PN_47_32_LSB) 221 #define RX_MPDU_START_2_PN_47_32_MASK \ 222 (pdev->targetdef->d_RX_MPDU_START_2_PN_47_32_MASK) 223 #define RX_MPDU_START_2_TID_LSB \ 224 (pdev->targetdef->d_RX_MPDU_START_2_TID_LSB) 225 #define RX_MPDU_START_2_TID_MASK \ 226 (pdev->targetdef->d_RX_MPDU_START_2_TID_MASK) 227 #define RX_MSDU_END_1_KEY_ID_OCT_MASK \ 228 (pdev->targetdef->d_RX_MSDU_END_1_KEY_ID_OCT_MASK) 229 #define RX_MSDU_END_1_KEY_ID_OCT_LSB \ 230 (pdev->targetdef->d_RX_MSDU_END_1_KEY_ID_OCT_LSB) 231 #define RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK \ 232 (pdev->targetdef->d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK) 233 #define RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB \ 234 (pdev->targetdef->d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB) 235 #define RX_MSDU_END_4_LAST_MSDU_MASK \ 236 (pdev->targetdef->d_RX_MSDU_END_4_LAST_MSDU_MASK) 237 #define RX_MSDU_END_4_LAST_MSDU_LSB \ 238 (pdev->targetdef->d_RX_MSDU_END_4_LAST_MSDU_LSB) 239 #define RX_ATTENTION_0_MCAST_BCAST_MASK \ 240 (pdev->targetdef->d_RX_ATTENTION_0_MCAST_BCAST_MASK) 241 #define RX_ATTENTION_0_MCAST_BCAST_LSB \ 242 (pdev->targetdef->d_RX_ATTENTION_0_MCAST_BCAST_LSB) 243 #define RX_ATTENTION_0_FRAGMENT_MASK \ 244 (pdev->targetdef->d_RX_ATTENTION_0_FRAGMENT_MASK) 245 #define RX_ATTENTION_0_FRAGMENT_LSB \ 246 (pdev->targetdef->d_RX_ATTENTION_0_FRAGMENT_LSB) 247 #define RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK \ 248 (pdev->targetdef->d_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK) 249 #define RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK \ 250 (pdev->targetdef->d_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK) 251 #define RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB \ 252 (pdev->targetdef->d_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB) 253 #define RX_MSDU_START_0_MSDU_LENGTH_MASK \ 254 (pdev->targetdef->d_RX_MSDU_START_0_MSDU_LENGTH_MASK) 255 #define RX_MSDU_START_0_MSDU_LENGTH_LSB \ 256 (pdev->targetdef->d_RX_MSDU_START_0_MSDU_LENGTH_LSB) 257 #define RX_MPDU_START_0_ENCRYPTED_MASK \ 258 (pdev->targetdef->d_RX_MPDU_START_0_ENCRYPTED_MASK) 259 #define RX_MPDU_START_0_ENCRYPTED_LSB \ 260 (pdev->targetdef->d_RX_MPDU_START_0_ENCRYPTED_LSB) 261 #define RX_ATTENTION_0_MORE_DATA_MASK \ 262 (pdev->targetdef->d_RX_ATTENTION_0_MORE_DATA_MASK) 263 #define RX_ATTENTION_0_MSDU_DONE_MASK \ 264 (pdev->targetdef->d_RX_ATTENTION_0_MSDU_DONE_MASK) 265 #define RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK \ 266 (pdev->targetdef->d_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK) 267 #if !defined(QCA6290_HEADERS_DEF) && !defined(QCA6390_HEADERS_DEF) 268 #ifndef RX_MSDU_START_2_DECAP_FORMAT_OFFSET 269 #define RX_MSDU_START_2_DECAP_FORMAT_OFFSET \ 270 (pdev->targetdef->d_RX_MSDU_START_2_DECAP_FORMAT_OFFSET) 271 #endif 272 #ifndef RX_MSDU_START_2_DECAP_FORMAT_LSB 273 #define RX_MSDU_START_2_DECAP_FORMAT_LSB \ 274 (pdev->targetdef->d_RX_MSDU_START_2_DECAP_FORMAT_LSB) 275 #endif 276 #ifndef RX_MSDU_START_2_DECAP_FORMAT_MASK 277 #define RX_MSDU_START_2_DECAP_FORMAT_MASK \ 278 (pdev->targetdef->d_RX_MSDU_START_2_DECAP_FORMAT_MASK) 279 #endif 280 #endif /*!QCA6290_HEADERS_DEF && !QCA6390_HEADERS_DEF */ 281 /* end */ 282 #endif 283 284 /* copy_engine.c */ 285 /* end */ 286 /* PLL start */ 287 #define EFUSE_OFFSET (scn->targetdef->d_EFUSE_OFFSET) 288 #define EFUSE_XTAL_SEL_MSB (scn->targetdef->d_EFUSE_XTAL_SEL_MSB) 289 #define EFUSE_XTAL_SEL_LSB (scn->targetdef->d_EFUSE_XTAL_SEL_LSB) 290 #define EFUSE_XTAL_SEL_MASK (scn->targetdef->d_EFUSE_XTAL_SEL_MASK) 291 #define BB_PLL_CONFIG_OFFSET (scn->targetdef->d_BB_PLL_CONFIG_OFFSET) 292 #define BB_PLL_CONFIG_OUTDIV_MSB (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_MSB) 293 #define BB_PLL_CONFIG_OUTDIV_LSB (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_LSB) 294 #define BB_PLL_CONFIG_OUTDIV_MASK (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_MASK) 295 #define BB_PLL_CONFIG_FRAC_MSB (scn->targetdef->d_BB_PLL_CONFIG_FRAC_MSB) 296 #define BB_PLL_CONFIG_FRAC_LSB (scn->targetdef->d_BB_PLL_CONFIG_FRAC_LSB) 297 #define BB_PLL_CONFIG_FRAC_MASK (scn->targetdef->d_BB_PLL_CONFIG_FRAC_MASK) 298 #define WLAN_PLL_SETTLE_TIME_MSB (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_MSB) 299 #define WLAN_PLL_SETTLE_TIME_LSB (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_LSB) 300 #define WLAN_PLL_SETTLE_TIME_MASK (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_MASK) 301 #define WLAN_PLL_SETTLE_OFFSET (scn->targetdef->d_WLAN_PLL_SETTLE_OFFSET) 302 #define WLAN_PLL_SETTLE_SW_MASK (scn->targetdef->d_WLAN_PLL_SETTLE_SW_MASK) 303 #define WLAN_PLL_SETTLE_RSTMASK (scn->targetdef->d_WLAN_PLL_SETTLE_RSTMASK) 304 #define WLAN_PLL_SETTLE_RESET (scn->targetdef->d_WLAN_PLL_SETTLE_RESET) 305 #define WLAN_PLL_CONTROL_NOPWD_MSB \ 306 (scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_MSB) 307 #define WLAN_PLL_CONTROL_NOPWD_LSB \ 308 (scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_LSB) 309 #define WLAN_PLL_CONTROL_NOPWD_MASK \ 310 (scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_MASK) 311 #define WLAN_PLL_CONTROL_BYPASS_MSB \ 312 (scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_MSB) 313 #define WLAN_PLL_CONTROL_BYPASS_LSB \ 314 (scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_LSB) 315 #define WLAN_PLL_CONTROL_BYPASS_MASK \ 316 (scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_MASK) 317 #define WLAN_PLL_CONTROL_BYPASS_RESET \ 318 (scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_RESET) 319 #define WLAN_PLL_CONTROL_CLK_SEL_MSB \ 320 (scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_MSB) 321 #define WLAN_PLL_CONTROL_CLK_SEL_LSB \ 322 (scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_LSB) 323 #define WLAN_PLL_CONTROL_CLK_SEL_MASK \ 324 (scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_MASK) 325 #define WLAN_PLL_CONTROL_CLK_SEL_RESET \ 326 (scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_RESET) 327 #define WLAN_PLL_CONTROL_REFDIV_MSB \ 328 (scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_MSB) 329 #define WLAN_PLL_CONTROL_REFDIV_LSB \ 330 (scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_LSB) 331 #define WLAN_PLL_CONTROL_REFDIV_MASK \ 332 (scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_MASK) 333 #define WLAN_PLL_CONTROL_REFDIV_RESET \ 334 (scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_RESET) 335 #define WLAN_PLL_CONTROL_DIV_MSB (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_MSB) 336 #define WLAN_PLL_CONTROL_DIV_LSB (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_LSB) 337 #define WLAN_PLL_CONTROL_DIV_MASK (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_MASK) 338 #define WLAN_PLL_CONTROL_DIV_RESET \ 339 (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_RESET) 340 #define WLAN_PLL_CONTROL_OFFSET (scn->targetdef->d_WLAN_PLL_CONTROL_OFFSET) 341 #define WLAN_PLL_CONTROL_SW_MASK (scn->targetdef->d_WLAN_PLL_CONTROL_SW_MASK) 342 #define WLAN_PLL_CONTROL_RSTMASK (scn->targetdef->d_WLAN_PLL_CONTROL_RSTMASK) 343 #define WLAN_PLL_CONTROL_RESET (scn->targetdef->d_WLAN_PLL_CONTROL_RESET) 344 #define SOC_CORE_CLK_CTRL_OFFSET (scn->targetdef->d_SOC_CORE_CLK_CTRL_OFFSET) 345 #define SOC_CORE_CLK_CTRL_DIV_MSB (scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_MSB) 346 #define SOC_CORE_CLK_CTRL_DIV_LSB (scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_LSB) 347 #define SOC_CORE_CLK_CTRL_DIV_MASK \ 348 (scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_MASK) 349 #define RTC_SYNC_STATUS_PLL_CHANGING_MSB \ 350 (scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_MSB) 351 #define RTC_SYNC_STATUS_PLL_CHANGING_LSB \ 352 (scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_LSB) 353 #define RTC_SYNC_STATUS_PLL_CHANGING_MASK \ 354 (scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_MASK) 355 #define RTC_SYNC_STATUS_PLL_CHANGING_RESET \ 356 (scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_RESET) 357 #define RTC_SYNC_STATUS_OFFSET (scn->targetdef->d_RTC_SYNC_STATUS_OFFSET) 358 #define SOC_CPU_CLOCK_OFFSET (scn->targetdef->d_SOC_CPU_CLOCK_OFFSET) 359 #define SOC_CPU_CLOCK_STANDARD_MSB \ 360 (scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_MSB) 361 #define SOC_CPU_CLOCK_STANDARD_LSB \ 362 (scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_LSB) 363 #define SOC_CPU_CLOCK_STANDARD_MASK \ 364 (scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_MASK) 365 /* PLL end */ 366 367 #define FW_CPU_PLL_CONFIG \ 368 (scn->targetdef->d_FW_CPU_PLL_CONFIG) 369 370 #define WIFICMN_PCIE_BAR_REG_ADDRESS \ 371 (sc->targetdef->d_WIFICMN_PCIE_BAR_REG_ADDRESS) 372 373 /* htt tx */ 374 #define MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK \ 375 (pdev->targetdef->d_MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK) 376 #define MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK \ 377 (pdev->targetdef->d_MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK) 378 #define MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK \ 379 (pdev->targetdef->d_MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK) 380 #define MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK \ 381 (pdev->targetdef->d_MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK) 382 #define MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB \ 383 (pdev->targetdef->d_MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB) 384 #define MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB \ 385 (pdev->targetdef->d_MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB) 386 #define MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB \ 387 (pdev->targetdef->d_MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB) 388 #define MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB \ 389 (pdev->targetdef->d_MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB) 390 391 #define CE_CMD_ADDRESS \ 392 (scn->targetdef->d_CE_CMD_ADDRESS) 393 #define CE_CMD_HALT_MASK \ 394 (scn->targetdef->d_CE_CMD_HALT_MASK) 395 #define CE_CMD_HALT_STATUS_MASK \ 396 (scn->targetdef->d_CE_CMD_HALT_STATUS_MASK) 397 #define CE_CMD_HALT_STATUS_LSB \ 398 (scn->targetdef->d_CE_CMD_HALT_STATUS_LSB) 399 400 #define SI_CONFIG_ERR_INT_MASK \ 401 (scn->targetdef->d_SI_CONFIG_ERR_INT_MASK) 402 #define SI_CONFIG_ERR_INT_LSB \ 403 (scn->targetdef->d_SI_CONFIG_ERR_INT_LSB) 404 #define GPIO_ENABLE_W1TS_LOW_ADDRESS \ 405 (scn->targetdef->d_GPIO_ENABLE_W1TS_LOW_ADDRESS) 406 #define GPIO_PIN0_CONFIG_LSB \ 407 (scn->targetdef->d_GPIO_PIN0_CONFIG_LSB) 408 #define GPIO_PIN0_PAD_PULL_LSB \ 409 (scn->targetdef->d_GPIO_PIN0_PAD_PULL_LSB) 410 #define GPIO_PIN0_PAD_PULL_MASK \ 411 (scn->targetdef->d_GPIO_PIN0_PAD_PULL_MASK) 412 413 #define SOC_CHIP_ID_REVISION_MSB \ 414 (scn->targetdef->d_SOC_CHIP_ID_REVISION_MSB) 415 416 #define FW_AXI_MSI_ADDR \ 417 (scn->targetdef->d_FW_AXI_MSI_ADDR) 418 #define FW_AXI_MSI_DATA \ 419 (scn->targetdef->d_FW_AXI_MSI_DATA) 420 #define WLAN_SUBSYSTEM_CORE_ID_ADDRESS \ 421 (scn->targetdef->d_WLAN_SUBSYSTEM_CORE_ID_ADDRESS) 422 #define FPGA_VERSION_ADDRESS \ 423 (scn->targetdef->d_FPGA_VERSION_ADDRESS) 424 425 /* SET macros */ 426 #define WLAN_SYSTEM_SLEEP_DISABLE_SET(x) \ 427 (((x) << WLAN_SYSTEM_SLEEP_DISABLE_LSB) & \ 428 WLAN_SYSTEM_SLEEP_DISABLE_MASK) 429 #define SI_CONFIG_BIDIR_OD_DATA_SET(x) \ 430 (((x) << SI_CONFIG_BIDIR_OD_DATA_LSB) & SI_CONFIG_BIDIR_OD_DATA_MASK) 431 #define SI_CONFIG_I2C_SET(x) (((x) << SI_CONFIG_I2C_LSB) & SI_CONFIG_I2C_MASK) 432 #define SI_CONFIG_POS_SAMPLE_SET(x) \ 433 (((x) << SI_CONFIG_POS_SAMPLE_LSB) & SI_CONFIG_POS_SAMPLE_MASK) 434 #define SI_CONFIG_INACTIVE_CLK_SET(x) \ 435 (((x) << SI_CONFIG_INACTIVE_CLK_LSB) & SI_CONFIG_INACTIVE_CLK_MASK) 436 #define SI_CONFIG_INACTIVE_DATA_SET(x) \ 437 (((x) << SI_CONFIG_INACTIVE_DATA_LSB) & SI_CONFIG_INACTIVE_DATA_MASK) 438 #define SI_CONFIG_DIVIDER_SET(x) \ 439 (((x) << SI_CONFIG_DIVIDER_LSB) & SI_CONFIG_DIVIDER_MASK) 440 #define SI_CS_START_SET(x) (((x) << SI_CS_START_LSB) & SI_CS_START_MASK) 441 #define SI_CS_RX_CNT_SET(x) (((x) << SI_CS_RX_CNT_LSB) & SI_CS_RX_CNT_MASK) 442 #define SI_CS_TX_CNT_SET(x) (((x) << SI_CS_TX_CNT_LSB) & SI_CS_TX_CNT_MASK) 443 #define LPO_CAL_ENABLE_SET(x) \ 444 (((x) << LPO_CAL_ENABLE_LSB) & LPO_CAL_ENABLE_MASK) 445 #define CPU_CLOCK_STANDARD_SET(x) \ 446 (((x) << CPU_CLOCK_STANDARD_LSB) & CPU_CLOCK_STANDARD_MASK) 447 #define CLOCK_GPIO_BT_CLK_OUT_EN_SET(x) \ 448 (((x) << CLOCK_GPIO_BT_CLK_OUT_EN_LSB) & CLOCK_GPIO_BT_CLK_OUT_EN_MASK) 449 /* copy_engine.c */ 450 /* end */ 451 /* PLL start */ 452 #define EFUSE_XTAL_SEL_GET(x) \ 453 (((x) & EFUSE_XTAL_SEL_MASK) >> EFUSE_XTAL_SEL_LSB) 454 #define EFUSE_XTAL_SEL_SET(x) \ 455 (((x) << EFUSE_XTAL_SEL_LSB) & EFUSE_XTAL_SEL_MASK) 456 #define BB_PLL_CONFIG_OUTDIV_GET(x) \ 457 (((x) & BB_PLL_CONFIG_OUTDIV_MASK) >> BB_PLL_CONFIG_OUTDIV_LSB) 458 #define BB_PLL_CONFIG_OUTDIV_SET(x) \ 459 (((x) << BB_PLL_CONFIG_OUTDIV_LSB) & BB_PLL_CONFIG_OUTDIV_MASK) 460 #define BB_PLL_CONFIG_FRAC_GET(x) \ 461 (((x) & BB_PLL_CONFIG_FRAC_MASK) >> BB_PLL_CONFIG_FRAC_LSB) 462 #define BB_PLL_CONFIG_FRAC_SET(x) \ 463 (((x) << BB_PLL_CONFIG_FRAC_LSB) & BB_PLL_CONFIG_FRAC_MASK) 464 #define WLAN_PLL_SETTLE_TIME_GET(x) \ 465 (((x) & WLAN_PLL_SETTLE_TIME_MASK) >> WLAN_PLL_SETTLE_TIME_LSB) 466 #define WLAN_PLL_SETTLE_TIME_SET(x) \ 467 (((x) << WLAN_PLL_SETTLE_TIME_LSB) & WLAN_PLL_SETTLE_TIME_MASK) 468 #define WLAN_PLL_CONTROL_NOPWD_GET(x) \ 469 (((x) & WLAN_PLL_CONTROL_NOPWD_MASK) >> WLAN_PLL_CONTROL_NOPWD_LSB) 470 #define WLAN_PLL_CONTROL_NOPWD_SET(x) \ 471 (((x) << WLAN_PLL_CONTROL_NOPWD_LSB) & WLAN_PLL_CONTROL_NOPWD_MASK) 472 #define WLAN_PLL_CONTROL_BYPASS_GET(x) \ 473 (((x) & WLAN_PLL_CONTROL_BYPASS_MASK) >> WLAN_PLL_CONTROL_BYPASS_LSB) 474 #define WLAN_PLL_CONTROL_BYPASS_SET(x) \ 475 (((x) << WLAN_PLL_CONTROL_BYPASS_LSB) & WLAN_PLL_CONTROL_BYPASS_MASK) 476 #define WLAN_PLL_CONTROL_CLK_SEL_GET(x) \ 477 (((x) & WLAN_PLL_CONTROL_CLK_SEL_MASK) >> WLAN_PLL_CONTROL_CLK_SEL_LSB) 478 #define WLAN_PLL_CONTROL_CLK_SEL_SET(x) \ 479 (((x) << WLAN_PLL_CONTROL_CLK_SEL_LSB) & WLAN_PLL_CONTROL_CLK_SEL_MASK) 480 #define WLAN_PLL_CONTROL_REFDIV_GET(x) \ 481 (((x) & WLAN_PLL_CONTROL_REFDIV_MASK) >> WLAN_PLL_CONTROL_REFDIV_LSB) 482 #define WLAN_PLL_CONTROL_REFDIV_SET(x) \ 483 (((x) << WLAN_PLL_CONTROL_REFDIV_LSB) & WLAN_PLL_CONTROL_REFDIV_MASK) 484 #define WLAN_PLL_CONTROL_DIV_GET(x) \ 485 (((x) & WLAN_PLL_CONTROL_DIV_MASK) >> WLAN_PLL_CONTROL_DIV_LSB) 486 #define WLAN_PLL_CONTROL_DIV_SET(x) \ 487 (((x) << WLAN_PLL_CONTROL_DIV_LSB) & WLAN_PLL_CONTROL_DIV_MASK) 488 #define SOC_CORE_CLK_CTRL_DIV_GET(x) \ 489 (((x) & SOC_CORE_CLK_CTRL_DIV_MASK) >> SOC_CORE_CLK_CTRL_DIV_LSB) 490 #define SOC_CORE_CLK_CTRL_DIV_SET(x) \ 491 (((x) << SOC_CORE_CLK_CTRL_DIV_LSB) & SOC_CORE_CLK_CTRL_DIV_MASK) 492 #define RTC_SYNC_STATUS_PLL_CHANGING_GET(x) \ 493 (((x) & RTC_SYNC_STATUS_PLL_CHANGING_MASK) >> \ 494 RTC_SYNC_STATUS_PLL_CHANGING_LSB) 495 #define RTC_SYNC_STATUS_PLL_CHANGING_SET(x) \ 496 (((x) << RTC_SYNC_STATUS_PLL_CHANGING_LSB) & \ 497 RTC_SYNC_STATUS_PLL_CHANGING_MASK) 498 #define SOC_CPU_CLOCK_STANDARD_GET(x) \ 499 (((x) & SOC_CPU_CLOCK_STANDARD_MASK) >> SOC_CPU_CLOCK_STANDARD_LSB) 500 #define SOC_CPU_CLOCK_STANDARD_SET(x) \ 501 (((x) << SOC_CPU_CLOCK_STANDARD_LSB) & SOC_CPU_CLOCK_STANDARD_MASK) 502 /* PLL end */ 503 #define WLAN_GPIO_PIN0_CONFIG_SET(x) \ 504 (((x) << GPIO_PIN0_CONFIG_LSB) & GPIO_PIN0_CONFIG_MASK) 505 #define WLAN_GPIO_PIN0_PAD_PULL_SET(x) \ 506 (((x) << GPIO_PIN0_PAD_PULL_LSB) & GPIO_PIN0_PAD_PULL_MASK) 507 #define SI_CONFIG_ERR_INT_SET(x) \ 508 (((x) << SI_CONFIG_ERR_INT_LSB) & SI_CONFIG_ERR_INT_MASK) 509 510 511 #ifdef QCA_WIFI_3_0_ADRASTEA 512 #define Q6_ENABLE_REGISTER_0 \ 513 (scn->targetdef->d_Q6_ENABLE_REGISTER_0) 514 #define Q6_ENABLE_REGISTER_1 \ 515 (scn->targetdef->d_Q6_ENABLE_REGISTER_1) 516 #define Q6_CAUSE_REGISTER_0 \ 517 (scn->targetdef->d_Q6_CAUSE_REGISTER_0) 518 #define Q6_CAUSE_REGISTER_1 \ 519 (scn->targetdef->d_Q6_CAUSE_REGISTER_1) 520 #define Q6_CLEAR_REGISTER_0 \ 521 (scn->targetdef->d_Q6_CLEAR_REGISTER_0) 522 #define Q6_CLEAR_REGISTER_1 \ 523 (scn->targetdef->d_Q6_CLEAR_REGISTER_1) 524 #endif 525 526 #ifdef CONFIG_BYPASS_QMI 527 #define BYPASS_QMI_TEMP_REGISTER \ 528 (scn->targetdef->d_BYPASS_QMI_TEMP_REGISTER) 529 #endif 530 531 #define A_SOC_PCIE_PCIE_BAR0_START (scn->hostdef->d_A_SOC_PCIE_PCIE_BAR0_START) 532 #define DESC_DATA_FLAG_MASK (scn->hostdef->d_DESC_DATA_FLAG_MASK) 533 #define MUX_ID_MASK (scn->hostdef->d_MUX_ID_MASK) 534 #define TRANSACTION_ID_MASK (scn->hostdef->d_TRANSACTION_ID_MASK) 535 #define HOST_CE_COUNT (scn->hostdef->d_HOST_CE_COUNT) 536 #define ENABLE_MSI (scn->hostdef->d_ENABLE_MSI) 537 #define INT_STATUS_ENABLE_ERROR_LSB \ 538 (scn->hostdef->d_INT_STATUS_ENABLE_ERROR_LSB) 539 #define INT_STATUS_ENABLE_ERROR_MASK \ 540 (scn->hostdef->d_INT_STATUS_ENABLE_ERROR_MASK) 541 #define INT_STATUS_ENABLE_CPU_LSB (scn->hostdef->d_INT_STATUS_ENABLE_CPU_LSB) 542 #define INT_STATUS_ENABLE_CPU_MASK (scn->hostdef->d_INT_STATUS_ENABLE_CPU_MASK) 543 #define INT_STATUS_ENABLE_COUNTER_LSB \ 544 (scn->hostdef->d_INT_STATUS_ENABLE_COUNTER_LSB) 545 #define INT_STATUS_ENABLE_COUNTER_MASK \ 546 (scn->hostdef->d_INT_STATUS_ENABLE_COUNTER_MASK) 547 #define INT_STATUS_ENABLE_MBOX_DATA_LSB \ 548 (scn->hostdef->d_INT_STATUS_ENABLE_MBOX_DATA_LSB) 549 #define INT_STATUS_ENABLE_MBOX_DATA_MASK \ 550 (scn->hostdef->d_INT_STATUS_ENABLE_MBOX_DATA_MASK) 551 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB \ 552 (scn->hostdef->d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) 553 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK \ 554 (scn->hostdef->d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) 555 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB \ 556 (scn->hostdef->d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) 557 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK \ 558 (scn->hostdef->d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) 559 #define COUNTER_INT_STATUS_ENABLE_BIT_LSB \ 560 (scn->hostdef->d_COUNTER_INT_STATUS_ENABLE_BIT_LSB) 561 #define COUNTER_INT_STATUS_ENABLE_BIT_MASK \ 562 (scn->hostdef->d_COUNTER_INT_STATUS_ENABLE_BIT_MASK) 563 #define INT_STATUS_ENABLE_ADDRESS \ 564 (scn->hostdef->d_INT_STATUS_ENABLE_ADDRESS) 565 #define CPU_INT_STATUS_ENABLE_BIT_LSB \ 566 (scn->hostdef->d_CPU_INT_STATUS_ENABLE_BIT_LSB) 567 #define CPU_INT_STATUS_ENABLE_BIT_MASK \ 568 (scn->hostdef->d_CPU_INT_STATUS_ENABLE_BIT_MASK) 569 #define HOST_INT_STATUS_ADDRESS (scn->hostdef->d_HOST_INT_STATUS_ADDRESS) 570 #define CPU_INT_STATUS_ADDRESS (scn->hostdef->d_CPU_INT_STATUS_ADDRESS) 571 #define ERROR_INT_STATUS_ADDRESS (scn->hostdef->d_ERROR_INT_STATUS_ADDRESS) 572 #define ERROR_INT_STATUS_WAKEUP_MASK \ 573 (scn->hostdef->d_ERROR_INT_STATUS_WAKEUP_MASK) 574 #define ERROR_INT_STATUS_WAKEUP_LSB \ 575 (scn->hostdef->d_ERROR_INT_STATUS_WAKEUP_LSB) 576 #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK \ 577 (scn->hostdef->d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK) 578 #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB \ 579 (scn->hostdef->d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB) 580 #define ERROR_INT_STATUS_TX_OVERFLOW_MASK \ 581 (scn->hostdef->d_ERROR_INT_STATUS_TX_OVERFLOW_MASK) 582 #define ERROR_INT_STATUS_TX_OVERFLOW_LSB \ 583 (scn->hostdef->d_ERROR_INT_STATUS_TX_OVERFLOW_LSB) 584 #define COUNT_DEC_ADDRESS (scn->hostdef->d_COUNT_DEC_ADDRESS) 585 #define HOST_INT_STATUS_CPU_MASK (scn->hostdef->d_HOST_INT_STATUS_CPU_MASK) 586 #define HOST_INT_STATUS_CPU_LSB (scn->hostdef->d_HOST_INT_STATUS_CPU_LSB) 587 #define HOST_INT_STATUS_ERROR_MASK (scn->hostdef->d_HOST_INT_STATUS_ERROR_MASK) 588 #define HOST_INT_STATUS_ERROR_LSB (scn->hostdef->d_HOST_INT_STATUS_ERROR_LSB) 589 #define HOST_INT_STATUS_COUNTER_MASK \ 590 (scn->hostdef->d_HOST_INT_STATUS_COUNTER_MASK) 591 #define HOST_INT_STATUS_COUNTER_LSB \ 592 (scn->hostdef->d_HOST_INT_STATUS_COUNTER_LSB) 593 #define RX_LOOKAHEAD_VALID_ADDRESS (scn->hostdef->d_RX_LOOKAHEAD_VALID_ADDRESS) 594 #define WINDOW_DATA_ADDRESS (scn->hostdef->d_WINDOW_DATA_ADDRESS) 595 #define WINDOW_READ_ADDR_ADDRESS (scn->hostdef->d_WINDOW_READ_ADDR_ADDRESS) 596 #define WINDOW_WRITE_ADDR_ADDRESS (scn->hostdef->d_WINDOW_WRITE_ADDR_ADDRESS) 597 #define SOC_GLOBAL_RESET_ADDRESS (scn->hostdef->d_SOC_GLOBAL_RESET_ADDRESS) 598 #define RTC_STATE_ADDRESS (scn->hostdef->d_RTC_STATE_ADDRESS) 599 #define RTC_STATE_COLD_RESET_MASK (scn->hostdef->d_RTC_STATE_COLD_RESET_MASK) 600 #define PCIE_LOCAL_BASE_ADDRESS (scn->hostdef->d_PCIE_LOCAL_BASE_ADDRESS) 601 #define PCIE_SOC_WAKE_RESET (scn->hostdef->d_PCIE_SOC_WAKE_RESET) 602 #define PCIE_SOC_WAKE_ADDRESS (scn->hostdef->d_PCIE_SOC_WAKE_ADDRESS) 603 #define PCIE_SOC_WAKE_V_MASK (scn->hostdef->d_PCIE_SOC_WAKE_V_MASK) 604 #define RTC_STATE_V_MASK (scn->hostdef->d_RTC_STATE_V_MASK) 605 #define RTC_STATE_V_LSB (scn->hostdef->d_RTC_STATE_V_LSB) 606 #define FW_IND_EVENT_PENDING (scn->hostdef->d_FW_IND_EVENT_PENDING) 607 #define FW_IND_INITIALIZED (scn->hostdef->d_FW_IND_INITIALIZED) 608 #define FW_IND_HELPER (scn->hostdef->d_FW_IND_HELPER) 609 #define RTC_STATE_V_ON (scn->hostdef->d_RTC_STATE_V_ON) 610 611 #define FW_IND_HOST_READY (scn->hostdef->d_FW_IND_HOST_READY) 612 613 #if defined(SDIO_3_0) 614 #define HOST_INT_STATUS_MBOX_DATA_MASK \ 615 (scn->hostdef->d_HOST_INT_STATUS_MBOX_DATA_MASK) 616 #define HOST_INT_STATUS_MBOX_DATA_LSB \ 617 (scn->hostdef->d_HOST_INT_STATUS_MBOX_DATA_LSB) 618 #endif 619 620 #if !defined(SOC_PCIE_BASE_ADDRESS) 621 #define SOC_PCIE_BASE_ADDRESS 0 622 #endif 623 624 #if !defined(PCIE_SOC_RDY_STATUS_ADDRESS) 625 #define PCIE_SOC_RDY_STATUS_ADDRESS 0 626 #define PCIE_SOC_RDY_STATUS_BAR_MASK 0 627 #endif 628 629 #if !defined(MSI_MAGIC_ADR_ADDRESS) 630 #define MSI_MAGIC_ADR_ADDRESS 0 631 #define MSI_MAGIC_ADDRESS 0 632 #endif 633 634 /* SET/GET macros */ 635 #define INT_STATUS_ENABLE_ERROR_SET(x) \ 636 (((x) << INT_STATUS_ENABLE_ERROR_LSB) & INT_STATUS_ENABLE_ERROR_MASK) 637 #define INT_STATUS_ENABLE_CPU_SET(x) \ 638 (((x) << INT_STATUS_ENABLE_CPU_LSB) & INT_STATUS_ENABLE_CPU_MASK) 639 #define INT_STATUS_ENABLE_COUNTER_SET(x) \ 640 (((x) << INT_STATUS_ENABLE_COUNTER_LSB) & \ 641 INT_STATUS_ENABLE_COUNTER_MASK) 642 #define INT_STATUS_ENABLE_MBOX_DATA_SET(x) \ 643 (((x) << INT_STATUS_ENABLE_MBOX_DATA_LSB) & \ 644 INT_STATUS_ENABLE_MBOX_DATA_MASK) 645 #define CPU_INT_STATUS_ENABLE_BIT_SET(x) \ 646 (((x) << CPU_INT_STATUS_ENABLE_BIT_LSB) & \ 647 CPU_INT_STATUS_ENABLE_BIT_MASK) 648 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(x) \ 649 (((x) << ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) & \ 650 ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) 651 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(x) \ 652 (((x) << ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) & \ 653 ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) 654 #define COUNTER_INT_STATUS_ENABLE_BIT_SET(x) \ 655 (((x) << COUNTER_INT_STATUS_ENABLE_BIT_LSB) & \ 656 COUNTER_INT_STATUS_ENABLE_BIT_MASK) 657 #define ERROR_INT_STATUS_WAKEUP_GET(x) \ 658 (((x) & ERROR_INT_STATUS_WAKEUP_MASK) >> \ 659 ERROR_INT_STATUS_WAKEUP_LSB) 660 #define ERROR_INT_STATUS_RX_UNDERFLOW_GET(x) \ 661 (((x) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) >> \ 662 ERROR_INT_STATUS_RX_UNDERFLOW_LSB) 663 #define ERROR_INT_STATUS_TX_OVERFLOW_GET(x) \ 664 (((x) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) >> \ 665 ERROR_INT_STATUS_TX_OVERFLOW_LSB) 666 #define HOST_INT_STATUS_CPU_GET(x) \ 667 (((x) & HOST_INT_STATUS_CPU_MASK) >> HOST_INT_STATUS_CPU_LSB) 668 #define HOST_INT_STATUS_ERROR_GET(x) \ 669 (((x) & HOST_INT_STATUS_ERROR_MASK) >> HOST_INT_STATUS_ERROR_LSB) 670 #define HOST_INT_STATUS_COUNTER_GET(x) \ 671 (((x) & HOST_INT_STATUS_COUNTER_MASK) >> HOST_INT_STATUS_COUNTER_LSB) 672 #define RTC_STATE_V_GET(x) \ 673 (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB) 674 #if defined(SDIO_3_0) 675 #define HOST_INT_STATUS_MBOX_DATA_GET(x) \ 676 (((x) & HOST_INT_STATUS_MBOX_DATA_MASK) >> \ 677 HOST_INT_STATUS_MBOX_DATA_LSB) 678 #endif 679 680 #define INVALID_REG_LOC_DUMMY_DATA 0xAA 681 682 #define AR6320_CORE_CLK_DIV_ADDR 0x403fa8 683 #define AR6320_CPU_PLL_INIT_DONE_ADDR 0x403fd0 684 #define AR6320_CPU_SPEED_ADDR 0x403fa4 685 #define AR6320V2_CORE_CLK_DIV_ADDR 0x403fd8 686 #define AR6320V2_CPU_PLL_INIT_DONE_ADDR 0x403fd0 687 #define AR6320V2_CPU_SPEED_ADDR 0x403fd4 688 #define AR6320V3_CORE_CLK_DIV_ADDR 0x404028 689 #define AR6320V3_CPU_PLL_INIT_DONE_ADDR 0x404020 690 #define AR6320V3_CPU_SPEED_ADDR 0x404024 691 692 enum a_refclk_speed_t { 693 SOC_REFCLK_UNKNOWN = -1, /* Unsupported ref clock -- use PLL Bypass */ 694 SOC_REFCLK_48_MHZ = 0, 695 SOC_REFCLK_19_2_MHZ = 1, 696 SOC_REFCLK_24_MHZ = 2, 697 SOC_REFCLK_26_MHZ = 3, 698 SOC_REFCLK_37_4_MHZ = 4, 699 SOC_REFCLK_38_4_MHZ = 5, 700 SOC_REFCLK_40_MHZ = 6, 701 SOC_REFCLK_52_MHZ = 7, 702 }; 703 704 #define A_REFCLK_UNKNOWN SOC_REFCLK_UNKNOWN 705 #define A_REFCLK_48_MHZ SOC_REFCLK_48_MHZ 706 #define A_REFCLK_19_2_MHZ SOC_REFCLK_19_2_MHZ 707 #define A_REFCLK_24_MHZ SOC_REFCLK_24_MHZ 708 #define A_REFCLK_26_MHZ SOC_REFCLK_26_MHZ 709 #define A_REFCLK_37_4_MHZ SOC_REFCLK_37_4_MHZ 710 #define A_REFCLK_38_4_MHZ SOC_REFCLK_38_4_MHZ 711 #define A_REFCLK_40_MHZ SOC_REFCLK_40_MHZ 712 #define A_REFCLK_52_MHZ SOC_REFCLK_52_MHZ 713 714 #define TARGET_CPU_FREQ 176000000 715 716 struct wlan_pll_s { 717 uint32_t refdiv; 718 uint32_t div; 719 uint32_t rnfrac; 720 uint32_t outdiv; 721 }; 722 723 struct cmnos_clock_s { 724 enum a_refclk_speed_t refclk_speed; 725 uint32_t refclk_hz; 726 uint32_t pll_settling_time; /* 50us */ 727 struct wlan_pll_s wlan_pll; 728 }; 729 730 struct tgt_reg_section { 731 uint32_t start_addr; 732 uint32_t end_addr; 733 }; 734 735 struct tgt_reg_table { 736 const struct tgt_reg_section *section; 737 uint32_t section_size; 738 }; 739 740 struct hif_softc; 741 void hif_target_register_tbl_attach(struct hif_softc *scn, u32 target_type); 742 void hif_register_tbl_attach(struct hif_softc *scn, u32 hif_type); 743 744 #endif /* _REGTABLE_PCIE_H_ */ 745