1 /* 2 * Copyright (c) 2015-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef REG_STRUCT_H 20 #define REG_STRUCT_H 21 22 #define MISSING_REGISTER 0 23 #define UNSUPPORTED_REGISTER_OFFSET 0xffffffff 24 25 /** 26 * is_register_supported() - return true if the register offset is valid 27 * @reg: register address being checked 28 * 29 * Return: true if the register offset is valid 30 */ 31 static inline bool is_register_supported(uint32_t reg) 32 { 33 return (reg != MISSING_REGISTER) && 34 (reg != UNSUPPORTED_REGISTER_OFFSET); 35 } 36 37 struct targetdef_s { 38 uint32_t d_RTC_SOC_BASE_ADDRESS; 39 uint32_t d_RTC_WMAC_BASE_ADDRESS; 40 uint32_t d_SYSTEM_SLEEP_OFFSET; 41 uint32_t d_WLAN_SYSTEM_SLEEP_OFFSET; 42 uint32_t d_WLAN_SYSTEM_SLEEP_DISABLE_LSB; 43 uint32_t d_WLAN_SYSTEM_SLEEP_DISABLE_MASK; 44 uint32_t d_CLOCK_CONTROL_OFFSET; 45 uint32_t d_CLOCK_CONTROL_SI0_CLK_MASK; 46 uint32_t d_RESET_CONTROL_OFFSET; 47 uint32_t d_RESET_CONTROL_MBOX_RST_MASK; 48 uint32_t d_RESET_CONTROL_SI0_RST_MASK; 49 uint32_t d_WLAN_RESET_CONTROL_OFFSET; 50 uint32_t d_WLAN_RESET_CONTROL_COLD_RST_MASK; 51 uint32_t d_WLAN_RESET_CONTROL_WARM_RST_MASK; 52 uint32_t d_GPIO_BASE_ADDRESS; 53 uint32_t d_GPIO_PIN0_OFFSET; 54 uint32_t d_GPIO_PIN1_OFFSET; 55 uint32_t d_GPIO_PIN0_CONFIG_MASK; 56 uint32_t d_GPIO_PIN1_CONFIG_MASK; 57 uint32_t d_SI_CONFIG_BIDIR_OD_DATA_LSB; 58 uint32_t d_SI_CONFIG_BIDIR_OD_DATA_MASK; 59 uint32_t d_SI_CONFIG_I2C_LSB; 60 uint32_t d_SI_CONFIG_I2C_MASK; 61 uint32_t d_SI_CONFIG_POS_SAMPLE_LSB; 62 uint32_t d_SI_CONFIG_POS_SAMPLE_MASK; 63 uint32_t d_SI_CONFIG_INACTIVE_CLK_LSB; 64 uint32_t d_SI_CONFIG_INACTIVE_CLK_MASK; 65 uint32_t d_SI_CONFIG_INACTIVE_DATA_LSB; 66 uint32_t d_SI_CONFIG_INACTIVE_DATA_MASK; 67 uint32_t d_SI_CONFIG_DIVIDER_LSB; 68 uint32_t d_SI_CONFIG_DIVIDER_MASK; 69 uint32_t d_SI_BASE_ADDRESS; 70 uint32_t d_SI_CONFIG_OFFSET; 71 uint32_t d_SI_TX_DATA0_OFFSET; 72 uint32_t d_SI_TX_DATA1_OFFSET; 73 uint32_t d_SI_RX_DATA0_OFFSET; 74 uint32_t d_SI_RX_DATA1_OFFSET; 75 uint32_t d_SI_CS_OFFSET; 76 uint32_t d_SI_CS_DONE_ERR_MASK; 77 uint32_t d_SI_CS_DONE_INT_MASK; 78 uint32_t d_SI_CS_START_LSB; 79 uint32_t d_SI_CS_START_MASK; 80 uint32_t d_SI_CS_RX_CNT_LSB; 81 uint32_t d_SI_CS_RX_CNT_MASK; 82 uint32_t d_SI_CS_TX_CNT_LSB; 83 uint32_t d_SI_CS_TX_CNT_MASK; 84 uint32_t d_BOARD_DATA_SZ; 85 uint32_t d_BOARD_EXT_DATA_SZ; 86 uint32_t d_MBOX_BASE_ADDRESS; 87 uint32_t d_LOCAL_SCRATCH_OFFSET; 88 uint32_t d_CPU_CLOCK_OFFSET; 89 uint32_t d_LPO_CAL_OFFSET; 90 uint32_t d_GPIO_PIN10_OFFSET; 91 uint32_t d_GPIO_PIN11_OFFSET; 92 uint32_t d_GPIO_PIN12_OFFSET; 93 uint32_t d_GPIO_PIN13_OFFSET; 94 uint32_t d_CLOCK_GPIO_OFFSET; 95 uint32_t d_CPU_CLOCK_STANDARD_LSB; 96 uint32_t d_CPU_CLOCK_STANDARD_MASK; 97 uint32_t d_LPO_CAL_ENABLE_LSB; 98 uint32_t d_LPO_CAL_ENABLE_MASK; 99 uint32_t d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB; 100 uint32_t d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK; 101 uint32_t d_ANALOG_INTF_BASE_ADDRESS; 102 uint32_t d_WLAN_MAC_BASE_ADDRESS; 103 uint32_t d_FW_INDICATOR_ADDRESS; 104 uint32_t d_FW_CPU_PLL_CONFIG; 105 uint32_t d_DRAM_BASE_ADDRESS; 106 uint32_t d_SOC_CORE_BASE_ADDRESS; 107 uint32_t d_CORE_CTRL_ADDRESS; 108 uint32_t d_CE_COUNT; 109 uint32_t d_MSI_NUM_REQUEST; 110 uint32_t d_MSI_ASSIGN_FW; 111 uint32_t d_MSI_ASSIGN_CE_INITIAL; 112 uint32_t d_PCIE_INTR_ENABLE_ADDRESS; 113 uint32_t d_PCIE_INTR_CLR_ADDRESS; 114 uint32_t d_PCIE_INTR_FIRMWARE_MASK; 115 uint32_t d_PCIE_INTR_CE_MASK_ALL; 116 uint32_t d_CORE_CTRL_CPU_INTR_MASK; 117 uint32_t d_WIFICMN_PCIE_BAR_REG_ADDRESS; 118 /* htt_rx.c */ 119 /* htt tx */ 120 uint32_t d_MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK; 121 uint32_t d_MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK; 122 uint32_t d_MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK; 123 uint32_t d_MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK; 124 uint32_t d_MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB; 125 uint32_t d_MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB; 126 uint32_t d_MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB; 127 uint32_t d_MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB; 128 /* copy_engine.c */ 129 uint32_t d_SR_WR_INDEX_ADDRESS; 130 uint32_t d_DST_WATERMARK_ADDRESS; 131 /* htt_rx.c */ 132 uint32_t d_RX_MSDU_END_4_FIRST_MSDU_MASK; 133 uint32_t d_RX_MSDU_END_4_FIRST_MSDU_LSB; 134 uint32_t d_RX_MPDU_START_0_RETRY_LSB; 135 uint32_t d_RX_MPDU_START_0_RETRY_MASK; 136 uint32_t d_RX_MPDU_START_0_SEQ_NUM_MASK; 137 uint32_t d_RX_MPDU_START_0_SEQ_NUM_LSB; 138 uint32_t d_RX_MPDU_START_2_PN_47_32_LSB; 139 uint32_t d_RX_MPDU_START_2_PN_47_32_MASK; 140 uint32_t d_RX_MPDU_START_2_TID_LSB; 141 uint32_t d_RX_MPDU_START_2_TID_MASK; 142 uint32_t d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK; 143 uint32_t d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB; 144 uint32_t d_RX_MSDU_END_1_KEY_ID_OCT_MASK; 145 uint32_t d_RX_MSDU_END_1_KEY_ID_OCT_LSB; 146 uint32_t d_RX_MSDU_END_4_LAST_MSDU_MASK; 147 uint32_t d_RX_MSDU_END_4_LAST_MSDU_LSB; 148 uint32_t d_RX_ATTENTION_0_MCAST_BCAST_MASK; 149 uint32_t d_RX_ATTENTION_0_MCAST_BCAST_LSB; 150 uint32_t d_RX_ATTENTION_0_FRAGMENT_MASK; 151 uint32_t d_RX_ATTENTION_0_FRAGMENT_LSB; 152 uint32_t d_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK; 153 uint32_t d_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK; 154 uint32_t d_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB; 155 uint32_t d_RX_MSDU_START_0_MSDU_LENGTH_MASK; 156 uint32_t d_RX_MSDU_START_0_MSDU_LENGTH_LSB; 157 uint32_t d_RX_MSDU_START_2_DECAP_FORMAT_OFFSET; 158 uint32_t d_RX_MSDU_START_2_DECAP_FORMAT_MASK; 159 uint32_t d_RX_MSDU_START_2_DECAP_FORMAT_LSB; 160 uint32_t d_RX_MPDU_START_0_ENCRYPTED_MASK; 161 uint32_t d_RX_MPDU_START_0_ENCRYPTED_LSB; 162 uint32_t d_RX_ATTENTION_0_MORE_DATA_MASK; 163 uint32_t d_RX_ATTENTION_0_MSDU_DONE_MASK; 164 uint32_t d_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK; 165 /* end */ 166 167 /* PLL start */ 168 uint32_t d_EFUSE_OFFSET; 169 uint32_t d_EFUSE_XTAL_SEL_MSB; 170 uint32_t d_EFUSE_XTAL_SEL_LSB; 171 uint32_t d_EFUSE_XTAL_SEL_MASK; 172 uint32_t d_BB_PLL_CONFIG_OFFSET; 173 uint32_t d_BB_PLL_CONFIG_OUTDIV_MSB; 174 uint32_t d_BB_PLL_CONFIG_OUTDIV_LSB; 175 uint32_t d_BB_PLL_CONFIG_OUTDIV_MASK; 176 uint32_t d_BB_PLL_CONFIG_FRAC_MSB; 177 uint32_t d_BB_PLL_CONFIG_FRAC_LSB; 178 uint32_t d_BB_PLL_CONFIG_FRAC_MASK; 179 uint32_t d_WLAN_PLL_SETTLE_TIME_MSB; 180 uint32_t d_WLAN_PLL_SETTLE_TIME_LSB; 181 uint32_t d_WLAN_PLL_SETTLE_TIME_MASK; 182 uint32_t d_WLAN_PLL_SETTLE_OFFSET; 183 uint32_t d_WLAN_PLL_SETTLE_SW_MASK; 184 uint32_t d_WLAN_PLL_SETTLE_RSTMASK; 185 uint32_t d_WLAN_PLL_SETTLE_RESET; 186 uint32_t d_WLAN_PLL_CONTROL_NOPWD_MSB; 187 uint32_t d_WLAN_PLL_CONTROL_NOPWD_LSB; 188 uint32_t d_WLAN_PLL_CONTROL_NOPWD_MASK; 189 uint32_t d_WLAN_PLL_CONTROL_BYPASS_MSB; 190 uint32_t d_WLAN_PLL_CONTROL_BYPASS_LSB; 191 uint32_t d_WLAN_PLL_CONTROL_BYPASS_MASK; 192 uint32_t d_WLAN_PLL_CONTROL_BYPASS_RESET; 193 uint32_t d_WLAN_PLL_CONTROL_CLK_SEL_MSB; 194 uint32_t d_WLAN_PLL_CONTROL_CLK_SEL_LSB; 195 uint32_t d_WLAN_PLL_CONTROL_CLK_SEL_MASK; 196 uint32_t d_WLAN_PLL_CONTROL_CLK_SEL_RESET; 197 uint32_t d_WLAN_PLL_CONTROL_REFDIV_MSB; 198 uint32_t d_WLAN_PLL_CONTROL_REFDIV_LSB; 199 uint32_t d_WLAN_PLL_CONTROL_REFDIV_MASK; 200 uint32_t d_WLAN_PLL_CONTROL_REFDIV_RESET; 201 uint32_t d_WLAN_PLL_CONTROL_DIV_MSB; 202 uint32_t d_WLAN_PLL_CONTROL_DIV_LSB; 203 uint32_t d_WLAN_PLL_CONTROL_DIV_MASK; 204 uint32_t d_WLAN_PLL_CONTROL_DIV_RESET; 205 uint32_t d_WLAN_PLL_CONTROL_OFFSET; 206 uint32_t d_WLAN_PLL_CONTROL_SW_MASK; 207 uint32_t d_WLAN_PLL_CONTROL_RSTMASK; 208 uint32_t d_WLAN_PLL_CONTROL_RESET; 209 uint32_t d_SOC_CORE_CLK_CTRL_OFFSET; 210 uint32_t d_SOC_CORE_CLK_CTRL_DIV_MSB; 211 uint32_t d_SOC_CORE_CLK_CTRL_DIV_LSB; 212 uint32_t d_SOC_CORE_CLK_CTRL_DIV_MASK; 213 uint32_t d_RTC_SYNC_STATUS_PLL_CHANGING_MSB; 214 uint32_t d_RTC_SYNC_STATUS_PLL_CHANGING_LSB; 215 uint32_t d_RTC_SYNC_STATUS_PLL_CHANGING_MASK; 216 uint32_t d_RTC_SYNC_STATUS_PLL_CHANGING_RESET; 217 uint32_t d_RTC_SYNC_STATUS_OFFSET; 218 uint32_t d_SOC_CPU_CLOCK_OFFSET; 219 uint32_t d_SOC_CPU_CLOCK_STANDARD_MSB; 220 uint32_t d_SOC_CPU_CLOCK_STANDARD_LSB; 221 uint32_t d_SOC_CPU_CLOCK_STANDARD_MASK; 222 /* PLL end */ 223 224 uint32_t d_SOC_POWER_REG_OFFSET; 225 uint32_t d_PCIE_INTR_CAUSE_ADDRESS; 226 uint32_t d_SOC_RESET_CONTROL_ADDRESS; 227 uint32_t d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK; 228 uint32_t d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB; 229 uint32_t d_SOC_RESET_CONTROL_CE_RST_MASK; 230 uint32_t d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK; 231 uint32_t d_CPU_INTR_ADDRESS; 232 uint32_t d_SOC_LF_TIMER_CONTROL0_ADDRESS; 233 uint32_t d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK; 234 uint32_t d_SOC_LF_TIMER_STATUS0_ADDRESS; 235 236 /* chip id start */ 237 uint32_t d_SI_CONFIG_ERR_INT_MASK; 238 uint32_t d_SI_CONFIG_ERR_INT_LSB; 239 uint32_t d_GPIO_ENABLE_W1TS_LOW_ADDRESS; 240 uint32_t d_GPIO_PIN0_CONFIG_LSB; 241 uint32_t d_GPIO_PIN0_PAD_PULL_LSB; 242 uint32_t d_GPIO_PIN0_PAD_PULL_MASK; 243 244 uint32_t d_SOC_CHIP_ID_ADDRESS; 245 uint32_t d_SOC_CHIP_ID_VERSION_MASK; 246 uint32_t d_SOC_CHIP_ID_VERSION_LSB; 247 uint32_t d_SOC_CHIP_ID_REVISION_MASK; 248 uint32_t d_SOC_CHIP_ID_REVISION_LSB; 249 uint32_t d_SOC_CHIP_ID_REVISION_MSB; 250 uint32_t d_FW_AXI_MSI_ADDR; 251 uint32_t d_FW_AXI_MSI_DATA; 252 uint32_t d_WLAN_SUBSYSTEM_CORE_ID_ADDRESS; 253 254 /* chip id end */ 255 256 uint32_t d_A_SOC_CORE_SCRATCH_0_ADDRESS; 257 uint32_t d_A_SOC_CORE_SCRATCH_1_ADDRESS; 258 uint32_t d_A_SOC_CORE_SCRATCH_2_ADDRESS; 259 uint32_t d_A_SOC_CORE_SCRATCH_3_ADDRESS; 260 uint32_t d_A_SOC_CORE_SCRATCH_4_ADDRESS; 261 uint32_t d_A_SOC_CORE_SCRATCH_5_ADDRESS; 262 uint32_t d_A_SOC_CORE_SCRATCH_6_ADDRESS; 263 uint32_t d_A_SOC_CORE_SCRATCH_7_ADDRESS; 264 uint32_t d_A_SOC_CORE_SPARE_0_REGISTER; 265 uint32_t d_PCIE_INTR_FIRMWARE_ROUTE_MASK; 266 uint32_t d_A_SOC_CORE_PCIE_INTR_CAUSE_GRP1; 267 uint32_t d_A_SOC_CORE_SPARE_1_REGISTER; 268 uint32_t d_A_SOC_CORE_PCIE_INTR_CLR_GRP1; 269 uint32_t d_A_SOC_CORE_PCIE_INTR_ENABLE_GRP1; 270 uint32_t d_A_SOC_PCIE_PCIE_SCRATCH_0; 271 uint32_t d_A_SOC_PCIE_PCIE_SCRATCH_1; 272 uint32_t d_A_WIFI_APB_1_A_WFSS_CE_TARGET_HOST_DELTA; 273 uint32_t d_A_SOC_PCIE_PCIE_SCRATCH_2; 274 uint32_t d_A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK; 275 276 uint32_t d_WLAN_DEBUG_INPUT_SEL_OFFSET; 277 uint32_t d_WLAN_DEBUG_INPUT_SEL_SRC_MSB; 278 uint32_t d_WLAN_DEBUG_INPUT_SEL_SRC_LSB; 279 uint32_t d_WLAN_DEBUG_INPUT_SEL_SRC_MASK; 280 uint32_t d_WLAN_DEBUG_CONTROL_OFFSET; 281 uint32_t d_WLAN_DEBUG_CONTROL_ENABLE_MSB; 282 uint32_t d_WLAN_DEBUG_CONTROL_ENABLE_LSB; 283 uint32_t d_WLAN_DEBUG_CONTROL_ENABLE_MASK; 284 uint32_t d_WLAN_DEBUG_OUT_OFFSET; 285 uint32_t d_WLAN_DEBUG_OUT_DATA_MSB; 286 uint32_t d_WLAN_DEBUG_OUT_DATA_LSB; 287 uint32_t d_WLAN_DEBUG_OUT_DATA_MASK; 288 uint32_t d_AMBA_DEBUG_BUS_OFFSET; 289 uint32_t d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB; 290 uint32_t d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB; 291 uint32_t d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK; 292 uint32_t d_AMBA_DEBUG_BUS_SEL_MSB; 293 uint32_t d_AMBA_DEBUG_BUS_SEL_LSB; 294 uint32_t d_AMBA_DEBUG_BUS_SEL_MASK; 295 296 #ifdef QCA_WIFI_3_0_ADRASTEA 297 uint32_t d_Q6_ENABLE_REGISTER_0; 298 uint32_t d_Q6_ENABLE_REGISTER_1; 299 uint32_t d_Q6_CAUSE_REGISTER_0; 300 uint32_t d_Q6_CAUSE_REGISTER_1; 301 uint32_t d_Q6_CLEAR_REGISTER_0; 302 uint32_t d_Q6_CLEAR_REGISTER_1; 303 #endif 304 #ifdef CONFIG_BYPASS_QMI 305 uint32_t d_BYPASS_QMI_TEMP_REGISTER; 306 #endif 307 uint32_t d_WIFICMN_INT_STATUS_ADDRESS; 308 }; 309 310 struct hostdef_s { 311 uint32_t d_INT_STATUS_ENABLE_ERROR_LSB; 312 uint32_t d_INT_STATUS_ENABLE_ERROR_MASK; 313 uint32_t d_INT_STATUS_ENABLE_CPU_LSB; 314 uint32_t d_INT_STATUS_ENABLE_CPU_MASK; 315 uint32_t d_INT_STATUS_ENABLE_COUNTER_LSB; 316 uint32_t d_INT_STATUS_ENABLE_COUNTER_MASK; 317 uint32_t d_INT_STATUS_ENABLE_MBOX_DATA_LSB; 318 uint32_t d_INT_STATUS_ENABLE_MBOX_DATA_MASK; 319 uint32_t d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB; 320 uint32_t d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK; 321 uint32_t d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB; 322 uint32_t d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK; 323 uint32_t d_COUNTER_INT_STATUS_ENABLE_BIT_LSB; 324 uint32_t d_COUNTER_INT_STATUS_ENABLE_BIT_MASK; 325 uint32_t d_INT_STATUS_ENABLE_ADDRESS; 326 uint32_t d_CPU_INT_STATUS_ENABLE_BIT_LSB; 327 uint32_t d_CPU_INT_STATUS_ENABLE_BIT_MASK; 328 uint32_t d_HOST_INT_STATUS_ADDRESS; 329 uint32_t d_CPU_INT_STATUS_ADDRESS; 330 uint32_t d_ERROR_INT_STATUS_ADDRESS; 331 uint32_t d_ERROR_INT_STATUS_WAKEUP_MASK; 332 uint32_t d_ERROR_INT_STATUS_WAKEUP_LSB; 333 uint32_t d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK; 334 uint32_t d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB; 335 uint32_t d_ERROR_INT_STATUS_TX_OVERFLOW_MASK; 336 uint32_t d_ERROR_INT_STATUS_TX_OVERFLOW_LSB; 337 uint32_t d_COUNT_DEC_ADDRESS; 338 uint32_t d_HOST_INT_STATUS_CPU_MASK; 339 uint32_t d_HOST_INT_STATUS_CPU_LSB; 340 uint32_t d_HOST_INT_STATUS_ERROR_MASK; 341 uint32_t d_HOST_INT_STATUS_ERROR_LSB; 342 uint32_t d_HOST_INT_STATUS_COUNTER_MASK; 343 uint32_t d_HOST_INT_STATUS_COUNTER_LSB; 344 uint32_t d_RX_LOOKAHEAD_VALID_ADDRESS; 345 uint32_t d_WINDOW_DATA_ADDRESS; 346 uint32_t d_WINDOW_READ_ADDR_ADDRESS; 347 uint32_t d_WINDOW_WRITE_ADDR_ADDRESS; 348 uint32_t d_SOC_GLOBAL_RESET_ADDRESS; 349 uint32_t d_RTC_STATE_ADDRESS; 350 uint32_t d_RTC_STATE_COLD_RESET_MASK; 351 uint32_t d_PCIE_LOCAL_BASE_ADDRESS; 352 uint32_t d_PCIE_SOC_WAKE_RESET; 353 uint32_t d_PCIE_SOC_WAKE_ADDRESS; 354 uint32_t d_PCIE_SOC_WAKE_V_MASK; 355 uint32_t d_RTC_STATE_V_MASK; 356 uint32_t d_RTC_STATE_V_LSB; 357 uint32_t d_FW_IND_EVENT_PENDING; 358 uint32_t d_FW_IND_INITIALIZED; 359 uint32_t d_FW_IND_HELPER; 360 uint32_t d_RTC_STATE_V_ON; 361 #if defined(SDIO_3_0) 362 uint32_t d_HOST_INT_STATUS_MBOX_DATA_MASK; 363 uint32_t d_HOST_INT_STATUS_MBOX_DATA_LSB; 364 #endif 365 uint32_t d_PCIE_SOC_RDY_STATUS_ADDRESS; 366 uint32_t d_PCIE_SOC_RDY_STATUS_BAR_MASK; 367 uint32_t d_SOC_PCIE_BASE_ADDRESS; 368 uint32_t d_MSI_MAGIC_ADR_ADDRESS; 369 uint32_t d_MSI_MAGIC_ADDRESS; 370 uint32_t d_HOST_CE_COUNT; 371 uint32_t d_ENABLE_MSI; 372 uint32_t d_MUX_ID_MASK; 373 uint32_t d_TRANSACTION_ID_MASK; 374 uint32_t d_DESC_DATA_FLAG_MASK; 375 uint32_t d_A_SOC_PCIE_PCIE_BAR0_START; 376 uint32_t d_FW_IND_HOST_READY; 377 }; 378 379 struct host_shadow_regs_s { 380 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_0; 381 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_1; 382 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_2; 383 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_3; 384 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_4; 385 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_5; 386 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_6; 387 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_7; 388 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_8; 389 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_9; 390 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_10; 391 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_11; 392 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_12; 393 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_13; 394 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_14; 395 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_15; 396 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_16; 397 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_17; 398 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_18; 399 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_19; 400 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_20; 401 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_21; 402 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_22; 403 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_23; 404 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_0; 405 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_1; 406 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_2; 407 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_3; 408 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_4; 409 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_5; 410 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_6; 411 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_7; 412 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_8; 413 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_9; 414 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_10; 415 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_11; 416 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_12; 417 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_13; 418 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_14; 419 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_15; 420 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_16; 421 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_17; 422 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_18; 423 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_19; 424 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_20; 425 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_21; 426 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_22; 427 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_23; 428 }; 429 430 431 /* 432 * @d_DST_WR_INDEX_ADDRESS: Destination ring write index 433 * 434 * @d_SRC_WATERMARK_ADDRESS: Source ring watermark 435 * 436 * @d_SRC_WATERMARK_LOW_MASK: Bits indicating low watermark from Source ring 437 * watermark 438 * 439 * @d_SRC_WATERMARK_HIGH_MASK: Bits indicating high watermark from Source ring 440 * watermark 441 * 442 * @d_DST_WATERMARK_LOW_MASK: Bits indicating low watermark from Destination 443 * ring watermark 444 * 445 * @d_DST_WATERMARK_HIGH_MASK: Bits indicating high watermark from Destination 446 * ring watermark 447 * 448 * @d_CURRENT_SRRI_ADDRESS: Current source ring read index.The Start Offset 449 * will be reflected after a CE transfer is completed. 450 * 451 * @d_CURRENT_DRRI_ADDRESS: Current Destination ring read index. The Start 452 * Offset will be reflected after a CE transfer 453 * is completed. 454 * 455 * @d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK: Source ring high watermark 456 * Interrupt Status 457 * 458 * @d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK: Source ring low watermark 459 * Interrupt Status 460 * 461 * @d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK: Destination ring high watermark 462 * Interrupt Status 463 * 464 * @d_HOST_IS_DST_RING_LOW_WATERMARK_MASK: Source ring low watermark 465 * Interrupt Status 466 * 467 * @d_HOST_IS_ADDRESS: Host Interrupt Status Register 468 * 469 * @d_MISC_IS_ADDRESS: Miscellaneous Interrupt Status Register 470 * 471 * @d_HOST_IS_COPY_COMPLETE_MASK: Bits indicating Copy complete interrupt 472 * status from the Host Interrupt Status 473 * register 474 * 475 * @d_CE_WRAPPER_BASE_ADDRESS: Copy Engine Wrapper Base Address 476 * 477 * @d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS: CE Wrapper summary for interrupts 478 * to host 479 * 480 * @d_CE_WRAPPER_INDEX_BASE_LOW: The LSB Base address to which source and 481 * destination read indices are written 482 * 483 * @d_CE_WRAPPER_INDEX_BASE_HIGH: The MSB Base address to which source and 484 * destination read indices are written 485 * 486 * @d_HOST_IE_ADDRESS: Host Line Interrupt Enable Register 487 * 488 * @d_HOST_IE_COPY_COMPLETE_MASK: Bits indicating Copy complete interrupt 489 * enable from the IE register 490 * 491 * @d_SR_BA_ADDRESS: LSB of Source Ring Base Address 492 * 493 * @d_SR_BA_ADDRESS_HIGH: MSB of Source Ring Base Address 494 * 495 * @d_SR_SIZE_ADDRESS: Source Ring size - number of entries and Start Offset 496 * 497 * @d_CE_CTRL1_ADDRESS: CE Control register 498 * 499 * @d_CE_CTRL1_DMAX_LENGTH_MASK: Destination buffer Max Length used for error 500 * check 501 * 502 * @d_DR_BA_ADDRESS: Destination Ring Base Address Low 503 * 504 * @d_DR_BA_ADDRESS_HIGH: Destination Ring Base Address High 505 * 506 * @d_DR_SIZE_ADDRESS: Destination Ring size - number of entries Start Offset 507 * 508 * @d_CE_CMD_REGISTER: Implements commands to all CE Halt Flush 509 * 510 * @d_CE_MSI_ADDRESS: CE MSI LOW Address register 511 * 512 * @d_CE_MSI_ADDRESS_HIGH: CE MSI High Address register 513 * 514 * @d_CE_MSI_DATA: CE MSI Data Register 515 * 516 * @d_CE_MSI_ENABLE_BIT: Bit in CTRL1 register indication the MSI enable 517 * 518 * @d_MISC_IE_ADDRESS: Miscellaneous Interrupt Enable Register 519 * 520 * @d_MISC_IS_AXI_ERR_MASK: 521 * Bit in Misc IS indicating AXI Timeout Interrupt status 522 * 523 * @d_MISC_IS_DST_ADDR_ERR_MASK: 524 * Bit in Misc IS indicating Destination Address Error 525 * 526 * @d_MISC_IS_SRC_LEN_ERR_MASK: Bit in Misc IS indicating Source Zero Length 527 * Error Interrupt status 528 * 529 * @d_MISC_IS_DST_MAX_LEN_VIO_MASK: Bit in Misc IS indicating Destination Max 530 * Length Violated Interrupt status 531 * 532 * @d_MISC_IS_DST_RING_OVERFLOW_MASK: Bit in Misc IS indicating Destination 533 * Ring Overflow Interrupt status 534 * 535 * @d_MISC_IS_SRC_RING_OVERFLOW_MASK: Bit in Misc IS indicating Source Ring 536 * Overflow Interrupt status 537 * 538 * @d_SRC_WATERMARK_LOW_LSB: Source Ring Low Watermark LSB 539 * 540 * @d_SRC_WATERMARK_HIGH_LSB: Source Ring Low Watermark MSB 541 * 542 * @d_DST_WATERMARK_LOW_LSB: Destination Ring Low Watermark LSB 543 * 544 * @d_DST_WATERMARK_HIGH_LSB: Destination Ring High Watermark LSB 545 * 546 * @d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK: 547 * Bits in d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDR 548 * indicating Copy engine miscellaneous interrupt summary 549 * 550 * @d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB: 551 * Bits in d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDR 552 * indicating Host interrupts summary 553 * 554 * @d_CE_CTRL1_DMAX_LENGTH_LSB: 555 * LSB of Destination buffer Max Length used for error check 556 * 557 * @d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK: 558 * Bits indicating Source ring Byte Swap enable. 559 * Treats source ring memory organisation as big-endian. 560 * 561 * @d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK: 562 * Bits indicating Destination ring byte swap enable. 563 * Treats destination ring memory organisation as big-endian 564 * 565 * @d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB: 566 * LSB of Source ring Byte Swap enable 567 * 568 * @d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB: 569 * LSB of Destination ring Byte Swap enable 570 * 571 * @d_CE_WRAPPER_DEBUG_OFFSET: Offset of CE OBS BUS Select register 572 * 573 * @d_CE_WRAPPER_DEBUG_SEL_MSB: 574 * MSB of Control register selecting inputs for trace/debug 575 * 576 * @d_CE_WRAPPER_DEBUG_SEL_LSB: 577 * LSB of Control register selecting inputs for trace/debug 578 * 579 * @d_CE_WRAPPER_DEBUG_SEL_MASK: 580 * Bit mask for trace/debug Control register 581 * 582 * @d_CE_DEBUG_OFFSET: Offset of Copy Engine FSM Debug Status 583 * 584 * @d_CE_DEBUG_SEL_MSB: MSB of Copy Engine FSM Debug Status 585 * 586 * @d_CE_DEBUG_SEL_LSB: LSB of Copy Engine FSM Debug Status 587 * 588 * @d_CE_DEBUG_SEL_MASK: Bits indicating Copy Engine FSM Debug Status 589 * 590 */ 591 struct ce_reg_def { 592 /* copy_engine.c */ 593 uint32_t d_DST_WR_INDEX_ADDRESS; 594 uint32_t d_SRC_WATERMARK_ADDRESS; 595 uint32_t d_SRC_WATERMARK_LOW_MASK; 596 uint32_t d_SRC_WATERMARK_HIGH_MASK; 597 uint32_t d_DST_WATERMARK_LOW_MASK; 598 uint32_t d_DST_WATERMARK_HIGH_MASK; 599 uint32_t d_CURRENT_SRRI_ADDRESS; 600 uint32_t d_CURRENT_DRRI_ADDRESS; 601 uint32_t d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK; 602 uint32_t d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK; 603 uint32_t d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK; 604 uint32_t d_HOST_IS_DST_RING_LOW_WATERMARK_MASK; 605 uint32_t d_HOST_IS_ADDRESS; 606 uint32_t d_MISC_IS_ADDRESS; 607 uint32_t d_HOST_IS_COPY_COMPLETE_MASK; 608 uint32_t d_CE_WRAPPER_BASE_ADDRESS; 609 uint32_t d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS; 610 uint32_t d_CE_DDR_ADDRESS_FOR_RRI_LOW; 611 uint32_t d_CE_DDR_ADDRESS_FOR_RRI_HIGH; 612 uint32_t d_HOST_IE_ADDRESS; 613 uint32_t d_HOST_IE_ADDRESS_2; 614 uint32_t d_HOST_IE_COPY_COMPLETE_MASK; 615 uint32_t d_SR_BA_ADDRESS; 616 uint32_t d_SR_BA_ADDRESS_HIGH; 617 uint32_t d_SR_SIZE_ADDRESS; 618 uint32_t d_CE_CTRL1_ADDRESS; 619 uint32_t d_CE_CTRL1_DMAX_LENGTH_MASK; 620 uint32_t d_DR_BA_ADDRESS; 621 uint32_t d_DR_BA_ADDRESS_HIGH; 622 uint32_t d_DR_SIZE_ADDRESS; 623 uint32_t d_CE_CMD_REGISTER; 624 uint32_t d_CE_MSI_ADDRESS; 625 uint32_t d_CE_MSI_ADDRESS_HIGH; 626 uint32_t d_CE_MSI_DATA; 627 uint32_t d_CE_MSI_ENABLE_BIT; 628 uint32_t d_MISC_IE_ADDRESS; 629 uint32_t d_MISC_IS_AXI_ERR_MASK; 630 uint32_t d_MISC_IS_DST_ADDR_ERR_MASK; 631 uint32_t d_MISC_IS_SRC_LEN_ERR_MASK; 632 uint32_t d_MISC_IS_DST_MAX_LEN_VIO_MASK; 633 uint32_t d_MISC_IS_DST_RING_OVERFLOW_MASK; 634 uint32_t d_MISC_IS_SRC_RING_OVERFLOW_MASK; 635 uint32_t d_SRC_WATERMARK_LOW_LSB; 636 uint32_t d_SRC_WATERMARK_HIGH_LSB; 637 uint32_t d_DST_WATERMARK_LOW_LSB; 638 uint32_t d_DST_WATERMARK_HIGH_LSB; 639 uint32_t d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK; 640 uint32_t d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB; 641 uint32_t d_CE_CTRL1_DMAX_LENGTH_LSB; 642 uint32_t d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK; 643 uint32_t d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK; 644 uint32_t d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB; 645 uint32_t d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB; 646 uint32_t d_CE_CTRL1_IDX_UPD_EN_MASK; 647 uint32_t d_CE_WRAPPER_DEBUG_OFFSET; 648 uint32_t d_CE_WRAPPER_DEBUG_SEL_MSB; 649 uint32_t d_CE_WRAPPER_DEBUG_SEL_LSB; 650 uint32_t d_CE_WRAPPER_DEBUG_SEL_MASK; 651 uint32_t d_CE_DEBUG_OFFSET; 652 uint32_t d_CE_DEBUG_SEL_MSB; 653 uint32_t d_CE_DEBUG_SEL_LSB; 654 uint32_t d_CE_DEBUG_SEL_MASK; 655 uint32_t d_CE0_BASE_ADDRESS; 656 uint32_t d_CE1_BASE_ADDRESS; 657 uint32_t d_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES; 658 uint32_t d_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_STATUS; 659 uint32_t d_HOST_IE_ADDRESS_3; 660 uint32_t d_HOST_IE_REG1_CE_LSB; 661 uint32_t d_HOST_IE_REG2_CE_LSB; 662 uint32_t d_HOST_IE_REG3_CE_LSB; 663 }; 664 665 #endif 666