1 /* 2 * Copyright (c) 2013-2018 The Linux Foundation. All rights reserved. 3 * 4 * Previously licensed under the ISC license by Qualcomm Atheros, Inc. 5 * 6 * 7 * Permission to use, copy, modify, and/or distribute this software for 8 * any purpose with or without fee is hereby granted, provided that the 9 * above copyright notice and this permission notice appear in all 10 * copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 13 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 14 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 15 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 16 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 17 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 18 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 19 * PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /* 23 * This file was originally distributed by Qualcomm Atheros, Inc. 24 * under proprietary terms before Copyright ownership was assigned 25 * to the Linux Foundation. 26 */ 27 28 #ifndef _HIF_H_ 29 #define _HIF_H_ 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif /* __cplusplus */ 34 35 /* Header files */ 36 #include <qdf_status.h> 37 #include "qdf_nbuf.h" 38 #include "qdf_lro.h" 39 #include "ol_if_athvar.h" 40 #include <linux/platform_device.h> 41 #ifdef HIF_PCI 42 #include <linux/pci.h> 43 #endif /* HIF_PCI */ 44 #ifdef HIF_USB 45 #include <linux/usb.h> 46 #endif /* HIF_USB */ 47 #ifdef IPA_OFFLOAD 48 #include <linux/ipa.h> 49 #endif 50 #define ENABLE_MBOX_DUMMY_SPACE_FEATURE 1 51 52 typedef void __iomem *A_target_id_t; 53 typedef void *hif_handle_t; 54 55 #define HIF_TYPE_AR6002 2 56 #define HIF_TYPE_AR6003 3 57 #define HIF_TYPE_AR6004 5 58 #define HIF_TYPE_AR9888 6 59 #define HIF_TYPE_AR6320 7 60 #define HIF_TYPE_AR6320V2 8 61 /* For attaching Peregrine 2.0 board host_reg_tbl only */ 62 #define HIF_TYPE_AR9888V2 9 63 #define HIF_TYPE_ADRASTEA 10 64 #define HIF_TYPE_AR900B 11 65 #define HIF_TYPE_QCA9984 12 66 #define HIF_TYPE_IPQ4019 13 67 #define HIF_TYPE_QCA9888 14 68 #define HIF_TYPE_QCA8074 15 69 #define HIF_TYPE_QCA6290 16 70 71 #ifdef IPA_OFFLOAD 72 #define DMA_COHERENT_MASK_IPA_VER_3_AND_ABOVE 37 73 #define DMA_COHERENT_MASK_BELOW_IPA_VER_3 32 74 #endif 75 76 /* enum hif_ic_irq - enum defining integrated chip irq numbers 77 * defining irq nubers that can be used by external modules like datapath 78 */ 79 enum hif_ic_irq { 80 host2wbm_desc_feed = 18, 81 host2reo_re_injection, 82 host2reo_command, 83 host2rxdma_monitor_ring3, 84 host2rxdma_monitor_ring2, 85 host2rxdma_monitor_ring1, 86 reo2host_exception, 87 wbm2host_rx_release, 88 reo2host_status, 89 reo2host_destination_ring4, 90 reo2host_destination_ring3, 91 reo2host_destination_ring2, 92 reo2host_destination_ring1, 93 rxdma2host_monitor_destination_mac3, 94 rxdma2host_monitor_destination_mac2, 95 rxdma2host_monitor_destination_mac1, 96 ppdu_end_interrupts_mac3, 97 ppdu_end_interrupts_mac2, 98 ppdu_end_interrupts_mac1, 99 rxdma2host_monitor_status_ring_mac3, 100 rxdma2host_monitor_status_ring_mac2, 101 rxdma2host_monitor_status_ring_mac1, 102 host2rxdma_host_buf_ring_mac3, 103 host2rxdma_host_buf_ring_mac2, 104 host2rxdma_host_buf_ring_mac1, 105 rxdma2host_destination_ring_mac3, 106 rxdma2host_destination_ring_mac2, 107 rxdma2host_destination_ring_mac1, 108 host2tcl_input_ring4, 109 host2tcl_input_ring3, 110 host2tcl_input_ring2, 111 host2tcl_input_ring1, 112 wbm2host_tx_completions_ring3, 113 wbm2host_tx_completions_ring2, 114 wbm2host_tx_completions_ring1, 115 tcl2host_status_ring, 116 }; 117 118 struct CE_state; 119 #define CE_COUNT_MAX 12 120 #define HIF_MAX_GRP_IRQ 16 121 #define HIF_MAX_GROUP 8 122 123 #ifdef CONFIG_SLUB_DEBUG_ON 124 #ifndef CONFIG_WIN 125 #define HIF_CONFIG_SLUB_DEBUG_ON 126 #endif 127 #endif 128 129 #ifndef NAPI_YIELD_BUDGET_BASED 130 #ifdef HIF_CONFIG_SLUB_DEBUG_ON 131 #define QCA_NAPI_DEF_SCALE_BIN_SHIFT 1 132 #else /* PERF build */ 133 #ifdef CONFIG_WIN 134 #define QCA_NAPI_DEF_SCALE_BIN_SHIFT 1 135 #else 136 #define QCA_NAPI_DEF_SCALE_BIN_SHIFT 4 137 #endif /* CONFIG_WIN */ 138 #endif /* SLUB_DEBUG_ON */ 139 #else /* NAPI_YIELD_BUDGET_BASED */ 140 #define QCA_NAPI_DEF_SCALE_BIN_SHIFT 2 141 #endif /* NAPI_YIELD_BUDGET_BASED */ 142 #define QCA_NAPI_BUDGET 64 143 #define QCA_NAPI_DEF_SCALE \ 144 (1 << QCA_NAPI_DEF_SCALE_BIN_SHIFT) 145 146 #define HIF_NAPI_MAX_RECEIVES (QCA_NAPI_BUDGET * QCA_NAPI_DEF_SCALE) 147 /* NOTE: "napi->scale" can be changed, 148 * but this does not change the number of buckets 149 */ 150 #define QCA_NAPI_NUM_BUCKETS 4 151 /** 152 * qca_napi_stat - stats structure for execution contexts 153 * @napi_schedules - number of times the schedule function is called 154 * @napi_polls - number of times the execution context runs 155 * @napi_completes - number of times that the generating interrupt is reenabled 156 * @napi_workdone - cumulative of all work done reported by handler 157 * @cpu_corrected - incremented when execution context runs on a different core 158 * than the one that its irq is affined to. 159 * @napi_budget_uses - histogram of work done per execution run 160 * @time_limit_reache - count of yields due to time limit threshholds 161 * @rxpkt_thresh_reached - count of yields due to a work limit 162 * 163 * needs to be renamed 164 */ 165 struct qca_napi_stat { 166 uint32_t napi_schedules; 167 uint32_t napi_polls; 168 uint32_t napi_completes; 169 uint32_t napi_workdone; 170 uint32_t cpu_corrected; 171 uint32_t napi_budget_uses[QCA_NAPI_NUM_BUCKETS]; 172 uint32_t time_limit_reached; 173 uint32_t rxpkt_thresh_reached; 174 }; 175 176 177 /** 178 * per NAPI instance data structure 179 * This data structure holds stuff per NAPI instance. 180 * Note that, in the current implementation, though scale is 181 * an instance variable, it is set to the same value for all 182 * instances. 183 */ 184 struct qca_napi_info { 185 struct net_device netdev; /* dummy net_dev */ 186 void *hif_ctx; 187 struct napi_struct napi; 188 uint8_t scale; /* currently same on all instances */ 189 uint8_t id; 190 uint8_t cpu; 191 int irq; 192 struct qca_napi_stat stats[NR_CPUS]; 193 /* will only be present for data rx CE's */ 194 void (*lro_flush_cb)(void *); 195 qdf_lro_ctx_t lro_ctx; 196 }; 197 198 enum qca_napi_tput_state { 199 QCA_NAPI_TPUT_UNINITIALIZED, 200 QCA_NAPI_TPUT_LO, 201 QCA_NAPI_TPUT_HI 202 }; 203 enum qca_napi_cpu_state { 204 QCA_NAPI_CPU_UNINITIALIZED, 205 QCA_NAPI_CPU_DOWN, 206 QCA_NAPI_CPU_UP }; 207 208 /** 209 * struct qca_napi_cpu - an entry of the napi cpu table 210 * @core_id: physical core id of the core 211 * @cluster_id: cluster this core belongs to 212 * @core_mask: mask to match all core of this cluster 213 * @thread_mask: mask for this core within the cluster 214 * @max_freq: maximum clock this core can be clocked at 215 * same for all cpus of the same core. 216 * @napis: bitmap of napi instances on this core 217 * @execs: bitmap of execution contexts on this core 218 * cluster_nxt: chain to link cores within the same cluster 219 * 220 * This structure represents a single entry in the napi cpu 221 * table. The table is part of struct qca_napi_data. 222 * This table is initialized by the init function, called while 223 * the first napi instance is being created, updated by hotplug 224 * notifier and when cpu affinity decisions are made (by throughput 225 * detection), and deleted when the last napi instance is removed. 226 */ 227 struct qca_napi_cpu { 228 enum qca_napi_cpu_state state; 229 int core_id; 230 int cluster_id; 231 cpumask_t core_mask; 232 cpumask_t thread_mask; 233 unsigned int max_freq; 234 uint32_t napis; 235 uint32_t execs; 236 int cluster_nxt; /* index, not pointer */ 237 }; 238 239 /** 240 * struct qca_napi_data - collection of napi data for a single hif context 241 * @hif_softc: pointer to the hif context 242 * @lock: spinlock used in the event state machine 243 * @state: state variable used in the napi stat machine 244 * @ce_map: bit map indicating which ce's have napis running 245 * @exec_map: bit map of instanciated exec contexts 246 * @napi_cpu: cpu info for irq affinty 247 * @lilcl_head: 248 * @bigcl_head: 249 * @napi_mode: irq affinity & clock voting mode 250 * @cpuhp_handler: CPU hotplug event registration handle 251 */ 252 struct qca_napi_data { 253 struct hif_softc *hif_softc; 254 qdf_spinlock_t lock; 255 uint32_t state; 256 257 /* bitmap of created/registered NAPI instances, indexed by pipe_id, 258 * not used by clients (clients use an id returned by create) 259 */ 260 uint32_t ce_map; 261 uint32_t exec_map; 262 struct qca_napi_info *napis[CE_COUNT_MAX]; 263 struct qca_napi_cpu napi_cpu[NR_CPUS]; 264 int lilcl_head, bigcl_head; 265 enum qca_napi_tput_state napi_mode; 266 struct qdf_cpuhp_handler *cpuhp_handler; 267 uint8_t flags; 268 }; 269 270 /** 271 * struct hif_config_info - Place Holder for hif confiruation 272 * @enable_self_recovery: Self Recovery 273 * 274 * Structure for holding hif ini parameters. 275 */ 276 struct hif_config_info { 277 bool enable_self_recovery; 278 #ifdef FEATURE_RUNTIME_PM 279 bool enable_runtime_pm; 280 u_int32_t runtime_pm_delay; 281 #endif 282 }; 283 284 /** 285 * struct hif_target_info - Target Information 286 * @target_version: Target Version 287 * @target_type: Target Type 288 * @target_revision: Target Revision 289 * @soc_version: SOC Version 290 * 291 * Structure to hold target information. 292 */ 293 struct hif_target_info { 294 uint32_t target_version; 295 uint32_t target_type; 296 uint32_t target_revision; 297 uint32_t soc_version; 298 char *hw_name; 299 }; 300 301 struct hif_opaque_softc { 302 }; 303 304 /** 305 * enum HIF_DEVICE_POWER_CHANGE_TYPE: Device Power change type 306 * 307 * @HIF_DEVICE_POWER_UP: HIF layer should power up interface and/or module 308 * @HIF_DEVICE_POWER_DOWN: HIF layer should initiate bus-specific measures to 309 * minimize power 310 * @HIF_DEVICE_POWER_CUT: HIF layer should initiate bus-specific AND/OR 311 * platform-specific measures to completely power-off 312 * the module and associated hardware (i.e. cut power 313 * supplies) 314 */ 315 enum HIF_DEVICE_POWER_CHANGE_TYPE { 316 HIF_DEVICE_POWER_UP, 317 HIF_DEVICE_POWER_DOWN, 318 HIF_DEVICE_POWER_CUT 319 }; 320 321 /** 322 * enum hif_enable_type: what triggered the enabling of hif 323 * 324 * @HIF_ENABLE_TYPE_PROBE: probe triggered enable 325 * @HIF_ENABLE_TYPE_REINIT: reinit triggered enable 326 */ 327 enum hif_enable_type { 328 HIF_ENABLE_TYPE_PROBE, 329 HIF_ENABLE_TYPE_REINIT, 330 HIF_ENABLE_TYPE_MAX 331 }; 332 333 /** 334 * enum hif_disable_type: what triggered the disabling of hif 335 * 336 * @HIF_DISABLE_TYPE_PROBE_ERROR: probe error triggered disable 337 * @HIF_DISABLE_TYPE_REINIT_ERROR: reinit error triggered disable 338 * @HIF_DISABLE_TYPE_REMOVE: remove triggered disable 339 * @HIF_DISABLE_TYPE_SHUTDOWN: shutdown triggered disable 340 */ 341 enum hif_disable_type { 342 HIF_DISABLE_TYPE_PROBE_ERROR, 343 HIF_DISABLE_TYPE_REINIT_ERROR, 344 HIF_DISABLE_TYPE_REMOVE, 345 HIF_DISABLE_TYPE_SHUTDOWN, 346 HIF_DISABLE_TYPE_MAX 347 }; 348 /** 349 * enum hif_device_config_opcode: configure mode 350 * 351 * @HIF_DEVICE_POWER_STATE: device power state 352 * @HIF_DEVICE_GET_MBOX_BLOCK_SIZE: get mbox block size 353 * @HIF_DEVICE_GET_MBOX_ADDR: get mbox block address 354 * @HIF_DEVICE_GET_PENDING_EVENTS_FUNC: get pending events functions 355 * @HIF_DEVICE_GET_IRQ_PROC_MODE: get irq proc mode 356 * @HIF_DEVICE_GET_RECV_EVENT_MASK_UNMASK_FUNC: receive event function 357 * @HIF_DEVICE_POWER_STATE_CHANGE: change power state 358 * @HIF_DEVICE_GET_IRQ_YIELD_PARAMS: get yield params 359 * @HIF_CONFIGURE_QUERY_SCATTER_REQUEST_SUPPORT: configure scatter request 360 * @HIF_DEVICE_GET_OS_DEVICE: get OS device 361 * @HIF_DEVICE_DEBUG_BUS_STATE: debug bus state 362 * @HIF_BMI_DONE: bmi done 363 * @HIF_DEVICE_SET_TARGET_TYPE: set target type 364 * @HIF_DEVICE_SET_HTC_CONTEXT: set htc context 365 * @HIF_DEVICE_GET_HTC_CONTEXT: get htc context 366 */ 367 enum hif_device_config_opcode { 368 HIF_DEVICE_POWER_STATE = 0, 369 HIF_DEVICE_GET_MBOX_BLOCK_SIZE, 370 HIF_DEVICE_GET_MBOX_ADDR, 371 HIF_DEVICE_GET_PENDING_EVENTS_FUNC, 372 HIF_DEVICE_GET_IRQ_PROC_MODE, 373 HIF_DEVICE_GET_RECV_EVENT_MASK_UNMASK_FUNC, 374 HIF_DEVICE_POWER_STATE_CHANGE, 375 HIF_DEVICE_GET_IRQ_YIELD_PARAMS, 376 HIF_CONFIGURE_QUERY_SCATTER_REQUEST_SUPPORT, 377 HIF_DEVICE_GET_OS_DEVICE, 378 HIF_DEVICE_DEBUG_BUS_STATE, 379 HIF_BMI_DONE, 380 HIF_DEVICE_SET_TARGET_TYPE, 381 HIF_DEVICE_SET_HTC_CONTEXT, 382 HIF_DEVICE_GET_HTC_CONTEXT, 383 }; 384 385 #ifdef CONFIG_ATH_PCIE_ACCESS_DEBUG 386 struct HID_ACCESS_LOG { 387 uint32_t seqnum; 388 bool is_write; 389 void *addr; 390 uint32_t value; 391 }; 392 #endif 393 394 void hif_reg_write(struct hif_opaque_softc *hif_ctx, uint32_t offset, 395 uint32_t value); 396 uint32_t hif_reg_read(struct hif_opaque_softc *hif_ctx, uint32_t offset); 397 398 #define HIF_MAX_DEVICES 1 399 /** 400 * struct htc_callbacks - Structure for HTC Callbacks methods 401 * @context: context to pass to the dsrhandler 402 * note : rwCompletionHandler is provided the context 403 * passed to hif_read_write 404 * @rwCompletionHandler: Read / write completion handler 405 * @dsrHandler: DSR Handler 406 */ 407 struct htc_callbacks { 408 void *context; 409 QDF_STATUS(*rwCompletionHandler)(void *rwContext, QDF_STATUS status); 410 QDF_STATUS(*dsrHandler)(void *context); 411 }; 412 413 /** 414 * struct hif_driver_state_callbacks - Callbacks for HIF to query Driver state 415 * @context: Private data context 416 * @set_recovery_in_progress: To Set Driver state for recovery in progress 417 * @is_recovery_in_progress: Query if driver state is recovery in progress 418 * @is_load_unload_in_progress: Query if driver state Load/Unload in Progress 419 * @is_driver_unloading: Query if driver is unloading. 420 * 421 * This Structure provides callback pointer for HIF to query hdd for driver 422 * states. 423 */ 424 struct hif_driver_state_callbacks { 425 void *context; 426 void (*set_recovery_in_progress)(void *context, uint8_t val); 427 bool (*is_recovery_in_progress)(void *context); 428 bool (*is_load_unload_in_progress)(void *context); 429 bool (*is_driver_unloading)(void *context); 430 bool (*is_target_ready)(void *context); 431 }; 432 433 /* This API detaches the HTC layer from the HIF device */ 434 void hif_detach_htc(struct hif_opaque_softc *hif_ctx); 435 436 /****************************************************************/ 437 /* BMI and Diag window abstraction */ 438 /****************************************************************/ 439 440 #define HIF_BMI_EXCHANGE_NO_TIMEOUT ((uint32_t)(0)) 441 442 #define DIAG_TRANSFER_LIMIT 2048U /* maximum number of bytes that can be 443 * handled atomically by 444 * DiagRead/DiagWrite 445 */ 446 447 /* 448 * API to handle HIF-specific BMI message exchanges, this API is synchronous 449 * and only allowed to be called from a context that can block (sleep) 450 */ 451 QDF_STATUS hif_exchange_bmi_msg(struct hif_opaque_softc *hif_ctx, 452 qdf_dma_addr_t cmd, qdf_dma_addr_t rsp, 453 uint8_t *pSendMessage, uint32_t Length, 454 uint8_t *pResponseMessage, 455 uint32_t *pResponseLength, uint32_t TimeoutMS); 456 void hif_register_bmi_callbacks(struct hif_softc *hif_sc); 457 /* 458 * APIs to handle HIF specific diagnostic read accesses. These APIs are 459 * synchronous and only allowed to be called from a context that 460 * can block (sleep). They are not high performance APIs. 461 * 462 * hif_diag_read_access reads a 4 Byte aligned/length value from a 463 * Target register or memory word. 464 * 465 * hif_diag_read_mem reads an arbitrary length of arbitrarily aligned memory. 466 */ 467 QDF_STATUS hif_diag_read_access(struct hif_opaque_softc *hif_ctx, 468 uint32_t address, uint32_t *data); 469 QDF_STATUS hif_diag_read_mem(struct hif_opaque_softc *hif_ctx, uint32_t address, 470 uint8_t *data, int nbytes); 471 void hif_dump_target_memory(struct hif_opaque_softc *hif_ctx, 472 void *ramdump_base, uint32_t address, uint32_t size); 473 /* 474 * APIs to handle HIF specific diagnostic write accesses. These APIs are 475 * synchronous and only allowed to be called from a context that 476 * can block (sleep). 477 * They are not high performance APIs. 478 * 479 * hif_diag_write_access writes a 4 Byte aligned/length value to a 480 * Target register or memory word. 481 * 482 * hif_diag_write_mem writes an arbitrary length of arbitrarily aligned memory. 483 */ 484 QDF_STATUS hif_diag_write_access(struct hif_opaque_softc *hif_ctx, 485 uint32_t address, uint32_t data); 486 QDF_STATUS hif_diag_write_mem(struct hif_opaque_softc *hif_ctx, 487 uint32_t address, uint8_t *data, int nbytes); 488 489 typedef void (*fastpath_msg_handler)(void *, qdf_nbuf_t *, uint32_t); 490 491 void hif_enable_polled_mode(struct hif_opaque_softc *hif_ctx); 492 bool hif_is_polled_mode_enabled(struct hif_opaque_softc *hif_ctx); 493 494 /* 495 * Set the FASTPATH_mode_on flag in sc, for use by data path 496 */ 497 #ifdef WLAN_FEATURE_FASTPATH 498 void hif_enable_fastpath(struct hif_opaque_softc *hif_ctx); 499 bool hif_is_fastpath_mode_enabled(struct hif_opaque_softc *hif_ctx); 500 void *hif_get_ce_handle(struct hif_opaque_softc *hif_ctx, int ret); 501 int hif_ce_fastpath_cb_register(struct hif_opaque_softc *hif_ctx, 502 fastpath_msg_handler handler, void *context); 503 #else 504 static inline int hif_ce_fastpath_cb_register(struct hif_opaque_softc *hif_ctx, 505 fastpath_msg_handler handler, 506 void *context) 507 { 508 return QDF_STATUS_E_FAILURE; 509 } 510 static inline void *hif_get_ce_handle(struct hif_opaque_softc *hif_ctx, int ret) 511 { 512 return NULL; 513 } 514 515 #endif 516 517 /* 518 * Enable/disable CDC max performance workaround 519 * For max-performace set this to 0 520 * To allow SoC to enter sleep set this to 1 521 */ 522 #define CONFIG_DISABLE_CDC_MAX_PERF_WAR 0 523 524 void hif_ipa_get_ce_resource(struct hif_opaque_softc *hif_ctx, 525 qdf_shared_mem_t **ce_sr, 526 uint32_t *ce_sr_ring_size, 527 qdf_dma_addr_t *ce_reg_paddr); 528 529 /** 530 * @brief List of callbacks - filled in by HTC. 531 */ 532 struct hif_msg_callbacks { 533 void *Context; 534 /**< context meaningful to HTC */ 535 QDF_STATUS (*txCompletionHandler)(void *Context, qdf_nbuf_t wbuf, 536 uint32_t transferID, 537 uint32_t toeplitz_hash_result); 538 QDF_STATUS (*rxCompletionHandler)(void *Context, qdf_nbuf_t wbuf, 539 uint8_t pipeID); 540 void (*txResourceAvailHandler)(void *context, uint8_t pipe); 541 void (*fwEventHandler)(void *context, QDF_STATUS status); 542 }; 543 544 enum hif_target_status { 545 TARGET_STATUS_CONNECTED = 0, /* target connected */ 546 TARGET_STATUS_RESET, /* target got reset */ 547 TARGET_STATUS_EJECT, /* target got ejected */ 548 TARGET_STATUS_SUSPEND /*target got suspend */ 549 }; 550 551 /** 552 * enum hif_attribute_flags: configure hif 553 * 554 * @HIF_LOWDESC_CE_CFG: Configure HIF with Low descriptor CE 555 * @HIF_LOWDESC_CE_NO_PKTLOG_CFG: Configure HIF with Low descriptor 556 * + No pktlog CE 557 */ 558 enum hif_attribute_flags { 559 HIF_LOWDESC_CE_CFG = 1, 560 HIF_LOWDESC_CE_NO_PKTLOG_CFG 561 }; 562 563 #define HIF_DATA_ATTR_SET_TX_CLASSIFY(attr, v) \ 564 (attr |= (v & 0x01) << 5) 565 #define HIF_DATA_ATTR_SET_ENCAPSULATION_TYPE(attr, v) \ 566 (attr |= (v & 0x03) << 6) 567 #define HIF_DATA_ATTR_SET_ADDR_X_SEARCH_DISABLE(attr, v) \ 568 (attr |= (v & 0x01) << 13) 569 #define HIF_DATA_ATTR_SET_ADDR_Y_SEARCH_DISABLE(attr, v) \ 570 (attr |= (v & 0x01) << 14) 571 #define HIF_DATA_ATTR_SET_TOEPLITZ_HASH_ENABLE(attr, v) \ 572 (attr |= (v & 0x01) << 15) 573 #define HIF_DATA_ATTR_SET_PACKET_OR_RESULT_OFFSET(attr, v) \ 574 (attr |= (v & 0x0FFF) << 16) 575 #define HIF_DATA_ATTR_SET_ENABLE_11H(attr, v) \ 576 (attr |= (v & 0x01) << 30) 577 578 struct hif_ul_pipe_info { 579 unsigned int nentries; 580 unsigned int nentries_mask; 581 unsigned int sw_index; 582 unsigned int write_index; /* cached copy */ 583 unsigned int hw_index; /* cached copy */ 584 void *base_addr_owner_space; /* Host address space */ 585 qdf_dma_addr_t base_addr_CE_space; /* CE address space */ 586 }; 587 588 struct hif_dl_pipe_info { 589 unsigned int nentries; 590 unsigned int nentries_mask; 591 unsigned int sw_index; 592 unsigned int write_index; /* cached copy */ 593 unsigned int hw_index; /* cached copy */ 594 void *base_addr_owner_space; /* Host address space */ 595 qdf_dma_addr_t base_addr_CE_space; /* CE address space */ 596 }; 597 598 struct hif_pipe_addl_info { 599 uint32_t pci_mem; 600 uint32_t ctrl_addr; 601 struct hif_ul_pipe_info ul_pipe; 602 struct hif_dl_pipe_info dl_pipe; 603 }; 604 605 struct hif_bus_id; 606 607 void hif_claim_device(struct hif_opaque_softc *hif_ctx); 608 QDF_STATUS hif_get_config_item(struct hif_opaque_softc *hif_ctx, 609 int opcode, void *config, uint32_t config_len); 610 void hif_set_mailbox_swap(struct hif_opaque_softc *hif_ctx); 611 void hif_mask_interrupt_call(struct hif_opaque_softc *hif_ctx); 612 void hif_post_init(struct hif_opaque_softc *hif_ctx, void *hHTC, 613 struct hif_msg_callbacks *callbacks); 614 QDF_STATUS hif_start(struct hif_opaque_softc *hif_ctx); 615 void hif_stop(struct hif_opaque_softc *hif_ctx); 616 void hif_flush_surprise_remove(struct hif_opaque_softc *hif_ctx); 617 void hif_dump(struct hif_opaque_softc *hif_ctx, uint8_t CmdId, bool start); 618 void hif_trigger_dump(struct hif_opaque_softc *hif_ctx, 619 uint8_t cmd_id, bool start); 620 621 QDF_STATUS hif_send_head(struct hif_opaque_softc *hif_ctx, uint8_t PipeID, 622 uint32_t transferID, uint32_t nbytes, 623 qdf_nbuf_t wbuf, uint32_t data_attr); 624 void hif_send_complete_check(struct hif_opaque_softc *hif_ctx, uint8_t PipeID, 625 int force); 626 void hif_shut_down_device(struct hif_opaque_softc *hif_ctx); 627 void hif_get_default_pipe(struct hif_opaque_softc *hif_ctx, uint8_t *ULPipe, 628 uint8_t *DLPipe); 629 int hif_map_service_to_pipe(struct hif_opaque_softc *hif_ctx, uint16_t svc_id, 630 uint8_t *ul_pipe, uint8_t *dl_pipe, int *ul_is_polled, 631 int *dl_is_polled); 632 uint16_t 633 hif_get_free_queue_number(struct hif_opaque_softc *hif_ctx, uint8_t PipeID); 634 void *hif_get_targetdef(struct hif_opaque_softc *hif_ctx); 635 uint32_t hif_hia_item_address(uint32_t target_type, uint32_t item_offset); 636 void hif_set_target_sleep(struct hif_opaque_softc *hif_ctx, bool sleep_ok, 637 bool wait_for_it); 638 int hif_check_fw_reg(struct hif_opaque_softc *hif_ctx); 639 #ifndef HIF_PCI 640 static inline int hif_check_soc_status(struct hif_opaque_softc *hif_ctx) 641 { 642 return 0; 643 } 644 #else 645 int hif_check_soc_status(struct hif_opaque_softc *hif_ctx); 646 #endif 647 void hif_get_hw_info(struct hif_opaque_softc *hif_ctx, u32 *version, 648 u32 *revision, const char **target_name); 649 void hif_disable_isr(struct hif_opaque_softc *hif_ctx); 650 void hif_reset_soc(struct hif_opaque_softc *hif_ctx); 651 void hif_save_htc_htt_config_endpoint(struct hif_opaque_softc *hif_ctx, 652 int htc_htt_tx_endpoint); 653 struct hif_opaque_softc *hif_open(qdf_device_t qdf_ctx, uint32_t mode, 654 enum qdf_bus_type bus_type, 655 struct hif_driver_state_callbacks *cbk); 656 void hif_close(struct hif_opaque_softc *hif_ctx); 657 QDF_STATUS hif_enable(struct hif_opaque_softc *hif_ctx, struct device *dev, 658 void *bdev, const struct hif_bus_id *bid, 659 enum qdf_bus_type bus_type, 660 enum hif_enable_type type); 661 void hif_disable(struct hif_opaque_softc *hif_ctx, enum hif_disable_type type); 662 void hif_display_stats(struct hif_opaque_softc *hif_ctx); 663 void hif_clear_stats(struct hif_opaque_softc *hif_ctx); 664 #ifdef FEATURE_RUNTIME_PM 665 struct hif_pm_runtime_lock; 666 void hif_fastpath_resume(struct hif_opaque_softc *hif_ctx); 667 int hif_pm_runtime_get(struct hif_opaque_softc *hif_ctx); 668 void hif_pm_runtime_get_noresume(struct hif_opaque_softc *hif_ctx); 669 int hif_pm_runtime_put(struct hif_opaque_softc *hif_ctx); 670 int hif_runtime_lock_init(qdf_runtime_lock_t *lock, const char *name); 671 void hif_runtime_lock_deinit(struct hif_opaque_softc *hif_ctx, 672 struct hif_pm_runtime_lock *lock); 673 int hif_pm_runtime_prevent_suspend(struct hif_opaque_softc *ol_sc, 674 struct hif_pm_runtime_lock *lock); 675 int hif_pm_runtime_allow_suspend(struct hif_opaque_softc *ol_sc, 676 struct hif_pm_runtime_lock *lock); 677 int hif_pm_runtime_prevent_suspend_timeout(struct hif_opaque_softc *ol_sc, 678 struct hif_pm_runtime_lock *lock, unsigned int delay); 679 #else 680 struct hif_pm_runtime_lock { 681 const char *name; 682 }; 683 static inline void hif_fastpath_resume(struct hif_opaque_softc *hif_ctx) {} 684 static inline void hif_pm_runtime_get_noresume(struct hif_opaque_softc *hif_ctx) 685 {} 686 687 static inline int hif_pm_runtime_get(struct hif_opaque_softc *hif_ctx) 688 { return 0; } 689 static inline int hif_pm_runtime_put(struct hif_opaque_softc *hif_ctx) 690 { return 0; } 691 static inline int hif_runtime_lock_init(qdf_runtime_lock_t *lock, 692 const char *name) 693 { return 0; } 694 static inline void 695 hif_runtime_lock_deinit(struct hif_opaque_softc *hif_ctx, 696 struct hif_pm_runtime_lock *lock) {} 697 698 static inline int hif_pm_runtime_prevent_suspend(struct hif_opaque_softc *ol_sc, 699 struct hif_pm_runtime_lock *lock) 700 { return 0; } 701 static inline int hif_pm_runtime_allow_suspend(struct hif_opaque_softc *ol_sc, 702 struct hif_pm_runtime_lock *lock) 703 { return 0; } 704 static inline int 705 hif_pm_runtime_prevent_suspend_timeout(struct hif_opaque_softc *ol_sc, 706 struct hif_pm_runtime_lock *lock, unsigned int delay) 707 { return 0; } 708 #endif 709 710 void hif_enable_power_management(struct hif_opaque_softc *hif_ctx, 711 bool is_packet_log_enabled); 712 void hif_disable_power_management(struct hif_opaque_softc *hif_ctx); 713 714 void hif_vote_link_down(struct hif_opaque_softc *hif_ctx); 715 void hif_vote_link_up(struct hif_opaque_softc *hif_ctx); 716 bool hif_can_suspend_link(struct hif_opaque_softc *hif_ctx); 717 718 #ifdef IPA_OFFLOAD 719 /** 720 * hif_get_ipa_hw_type() - get IPA hw type 721 * 722 * This API return the IPA hw type. 723 * 724 * Return: IPA hw type 725 */ 726 static inline 727 enum ipa_hw_type hif_get_ipa_hw_type(void) 728 { 729 return ipa_get_hw_type(); 730 } 731 732 /** 733 * hif_get_ipa_present() - get IPA hw status 734 * 735 * This API return the IPA hw status. 736 * 737 * Return: true if IPA is present or false otherwise 738 */ 739 static inline 740 bool hif_get_ipa_present(void) 741 { 742 if (ipa_uc_reg_rdyCB(NULL) != -EPERM) 743 return true; 744 else 745 return false; 746 } 747 #endif 748 int hif_bus_resume(struct hif_opaque_softc *hif_ctx); 749 /** 750 * hif_bus_ealry_suspend() - stop non wmi tx traffic 751 * @context: hif context 752 */ 753 int hif_bus_early_suspend(struct hif_opaque_softc *hif_ctx); 754 755 /** 756 * hif_bus_late_resume() - resume non wmi traffic 757 * @context: hif context 758 */ 759 int hif_bus_late_resume(struct hif_opaque_softc *hif_ctx); 760 int hif_bus_suspend(struct hif_opaque_softc *hif_ctx); 761 int hif_bus_resume_noirq(struct hif_opaque_softc *hif_ctx); 762 int hif_bus_suspend_noirq(struct hif_opaque_softc *hif_ctx); 763 764 /** 765 * hif_apps_irqs_enable() - Enables all irqs from the APPS side 766 * @hif_ctx: an opaque HIF handle to use 767 * 768 * As opposed to the standard hif_irq_enable, this function always applies to 769 * the APPS side kernel interrupt handling. 770 * 771 * Return: errno 772 */ 773 int hif_apps_irqs_enable(struct hif_opaque_softc *hif_ctx); 774 775 /** 776 * hif_apps_irqs_disable() - Disables all irqs from the APPS side 777 * @hif_ctx: an opaque HIF handle to use 778 * 779 * As opposed to the standard hif_irq_disable, this function always applies to 780 * the APPS side kernel interrupt handling. 781 * 782 * Return: errno 783 */ 784 int hif_apps_irqs_disable(struct hif_opaque_softc *hif_ctx); 785 786 /** 787 * hif_apps_wake_irq_enable() - Enables the wake irq from the APPS side 788 * @hif_ctx: an opaque HIF handle to use 789 * 790 * As opposed to the standard hif_irq_enable, this function always applies to 791 * the APPS side kernel interrupt handling. 792 * 793 * Return: errno 794 */ 795 int hif_apps_wake_irq_enable(struct hif_opaque_softc *hif_ctx); 796 797 /** 798 * hif_apps_wake_irq_disable() - Disables the wake irq from the APPS side 799 * @hif_ctx: an opaque HIF handle to use 800 * 801 * As opposed to the standard hif_irq_disable, this function always applies to 802 * the APPS side kernel interrupt handling. 803 * 804 * Return: errno 805 */ 806 int hif_apps_wake_irq_disable(struct hif_opaque_softc *hif_ctx); 807 808 #ifdef FEATURE_RUNTIME_PM 809 int hif_pre_runtime_suspend(struct hif_opaque_softc *hif_ctx); 810 void hif_pre_runtime_resume(struct hif_opaque_softc *hif_ctx); 811 int hif_runtime_suspend(struct hif_opaque_softc *hif_ctx); 812 int hif_runtime_resume(struct hif_opaque_softc *hif_ctx); 813 void hif_process_runtime_suspend_success(struct hif_opaque_softc *hif_ctx); 814 void hif_process_runtime_suspend_failure(struct hif_opaque_softc *hif_ctx); 815 void hif_process_runtime_resume_success(struct hif_opaque_softc *hif_ctx); 816 #endif 817 818 int hif_get_irq_num(struct hif_opaque_softc *scn, int *irq, uint32_t size); 819 int hif_dump_registers(struct hif_opaque_softc *scn); 820 int ol_copy_ramdump(struct hif_opaque_softc *scn); 821 void hif_crash_shutdown(struct hif_opaque_softc *hif_ctx); 822 void hif_get_hw_info(struct hif_opaque_softc *hif_ctx, u32 *version, 823 u32 *revision, const char **target_name); 824 void hif_lro_flush_cb_register(struct hif_opaque_softc *hif_ctx, 825 void (lro_flush_handler)(void *arg), 826 void *(lro_init_handler)(void)); 827 void hif_lro_flush_cb_deregister(struct hif_opaque_softc *hif_ctx, 828 void (lro_deinit_cb)(void *arg)); 829 bool hif_needs_bmi(struct hif_opaque_softc *hif_ctx); 830 enum qdf_bus_type hif_get_bus_type(struct hif_opaque_softc *hif_hdl); 831 struct hif_target_info *hif_get_target_info_handle(struct hif_opaque_softc * 832 scn); 833 struct hif_config_info *hif_get_ini_handle(struct hif_opaque_softc *hif_ctx); 834 struct ramdump_info *hif_get_ramdump_ctx(struct hif_opaque_softc *hif_ctx); 835 enum hif_target_status hif_get_target_status(struct hif_opaque_softc *hif_ctx); 836 void hif_set_target_status(struct hif_opaque_softc *hif_ctx, enum 837 hif_target_status); 838 void hif_init_ini_config(struct hif_opaque_softc *hif_ctx, 839 struct hif_config_info *cfg); 840 void hif_update_tx_ring(struct hif_opaque_softc *osc, u_int32_t num_htt_cmpls); 841 qdf_nbuf_t hif_batch_send(struct hif_opaque_softc *osc, qdf_nbuf_t msdu, 842 uint32_t transfer_id, u_int32_t len, uint32_t sendhead); 843 int hif_send_single(struct hif_opaque_softc *osc, qdf_nbuf_t msdu, uint32_t 844 transfer_id, u_int32_t len); 845 int hif_send_fast(struct hif_opaque_softc *osc, qdf_nbuf_t nbuf, 846 uint32_t transfer_id, uint32_t download_len); 847 void hif_pkt_dl_len_set(void *hif_sc, unsigned int pkt_download_len); 848 void hif_ce_war_disable(void); 849 void hif_ce_war_enable(void); 850 void hif_disable_interrupt(struct hif_opaque_softc *osc, uint32_t pipe_num); 851 #ifdef QCA_NSS_WIFI_OFFLOAD_SUPPORT 852 struct hif_pipe_addl_info *hif_get_addl_pipe_info(struct hif_opaque_softc *osc, 853 struct hif_pipe_addl_info *hif_info, uint32_t pipe_number); 854 uint32_t hif_set_nss_wifiol_mode(struct hif_opaque_softc *osc, 855 uint32_t pipe_num); 856 int32_t hif_get_nss_wifiol_bypass_nw_process(struct hif_opaque_softc *osc); 857 #endif /* QCA_NSS_WIFI_OFFLOAD_SUPPORT */ 858 859 void hif_set_bundle_mode(struct hif_opaque_softc *hif_ctx, bool enabled, 860 int rx_bundle_cnt); 861 int hif_bus_reset_resume(struct hif_opaque_softc *hif_ctx); 862 863 void hif_set_attribute(struct hif_opaque_softc *osc, uint8_t hif_attrib); 864 865 void *hif_get_lro_info(int ctx_id, struct hif_opaque_softc *hif_hdl); 866 867 enum hif_exec_type { 868 HIF_EXEC_NAPI_TYPE, 869 HIF_EXEC_TASKLET_TYPE, 870 }; 871 872 typedef uint32_t (*ext_intr_handler)(void *, uint32_t); 873 uint32_t hif_configure_ext_group_interrupts(struct hif_opaque_softc *hif_ctx); 874 uint32_t hif_register_ext_group(struct hif_opaque_softc *hif_ctx, 875 uint32_t numirq, uint32_t irq[], ext_intr_handler handler, 876 void *cb_ctx, const char *context_name, 877 enum hif_exec_type type, uint32_t scale); 878 879 void hif_deregister_exec_group(struct hif_opaque_softc *hif_ctx, 880 const char *context_name); 881 882 void hif_update_pipe_callback(struct hif_opaque_softc *osc, 883 u_int8_t pipeid, 884 struct hif_msg_callbacks *callbacks); 885 886 void hif_print_napi_stats(struct hif_opaque_softc *hif_ctx); 887 #ifdef __cplusplus 888 } 889 #endif 890 891 void *hif_get_dev_ba(struct hif_opaque_softc *hif_handle); 892 893 /** 894 * hif_set_initial_wakeup_cb() - set the initial wakeup event handler function 895 * @hif_ctx - the HIF context to assign the callback to 896 * @callback - the callback to assign 897 * @priv - the private data to pass to the callback when invoked 898 * 899 * Return: None 900 */ 901 void hif_set_initial_wakeup_cb(struct hif_opaque_softc *hif_ctx, 902 void (*callback)(void *), 903 void *priv); 904 #ifndef CONFIG_WIN 905 #ifndef HIF_CE_DEBUG_DATA_BUF 906 #define HIF_CE_DEBUG_DATA_BUF 0 907 #endif 908 #endif 909 /* 910 * Note: For MCL, #if defined (HIF_CONFIG_SLUB_DEBUG_ON) needs to be checked 911 * for defined here 912 */ 913 #if HIF_CE_DEBUG_DATA_BUF 914 ssize_t hif_dump_desc_trace_buf(struct device *dev, 915 struct device_attribute *attr, char *buf); 916 ssize_t hif_input_desc_trace_buf_index(struct hif_softc *scn, 917 const char *buf, size_t size); 918 ssize_t hif_ce_en_desc_hist(struct hif_softc *scn, 919 const char *buf, size_t size); 920 ssize_t hif_disp_ce_enable_desc_data_hist(struct hif_softc *scn, char *buf); 921 ssize_t hif_dump_desc_event(struct hif_softc *scn, char *buf); 922 #endif /* Note: for MCL, #if defined(HIF_CONFIG_SLUB_DEBUG_ON) || HIF_CE_DEBUG_DATA_BUF */ 923 #endif /* _HIF_H_ */ 924