1 /* 2 * Copyright (c) 2013-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _HIF_H_ 20 #define _HIF_H_ 21 22 #ifdef __cplusplus 23 extern "C" { 24 #endif /* __cplusplus */ 25 26 /* Header files */ 27 #include <qdf_status.h> 28 #include "qdf_nbuf.h" 29 #include "qdf_lro.h" 30 #include "ol_if_athvar.h" 31 #include <linux/platform_device.h> 32 #ifdef HIF_PCI 33 #include <linux/pci.h> 34 #endif /* HIF_PCI */ 35 #ifdef HIF_USB 36 #include <linux/usb.h> 37 #endif /* HIF_USB */ 38 #ifdef IPA_OFFLOAD 39 #include <linux/ipa.h> 40 #endif 41 #include "cfg_ucfg_api.h" 42 #include "qdf_dev.h" 43 #define ENABLE_MBOX_DUMMY_SPACE_FEATURE 1 44 45 typedef void __iomem *A_target_id_t; 46 typedef void *hif_handle_t; 47 48 #define HIF_TYPE_AR6002 2 49 #define HIF_TYPE_AR6003 3 50 #define HIF_TYPE_AR6004 5 51 #define HIF_TYPE_AR9888 6 52 #define HIF_TYPE_AR6320 7 53 #define HIF_TYPE_AR6320V2 8 54 /* For attaching Peregrine 2.0 board host_reg_tbl only */ 55 #define HIF_TYPE_AR9888V2 9 56 #define HIF_TYPE_ADRASTEA 10 57 #define HIF_TYPE_AR900B 11 58 #define HIF_TYPE_QCA9984 12 59 #define HIF_TYPE_IPQ4019 13 60 #define HIF_TYPE_QCA9888 14 61 #define HIF_TYPE_QCA8074 15 62 #define HIF_TYPE_QCA6290 16 63 #define HIF_TYPE_QCN7605 17 64 #define HIF_TYPE_QCA6390 18 65 #define HIF_TYPE_QCA8074V2 19 66 #define HIF_TYPE_QCA6018 20 67 #define HIF_TYPE_QCN9000 21 68 #define HIF_TYPE_QCA6490 22 69 #define HIF_TYPE_QCA6750 23 70 #define HIF_TYPE_QCA5018 24 71 72 #define DMA_COHERENT_MASK_DEFAULT 37 73 74 #ifdef IPA_OFFLOAD 75 #define DMA_COHERENT_MASK_BELOW_IPA_VER_3 32 76 #endif 77 78 /* enum hif_ic_irq - enum defining integrated chip irq numbers 79 * defining irq nubers that can be used by external modules like datapath 80 */ 81 enum hif_ic_irq { 82 host2wbm_desc_feed = 16, 83 host2reo_re_injection, 84 host2reo_command, 85 host2rxdma_monitor_ring3, 86 host2rxdma_monitor_ring2, 87 host2rxdma_monitor_ring1, 88 reo2host_exception, 89 wbm2host_rx_release, 90 reo2host_status, 91 reo2host_destination_ring4, 92 reo2host_destination_ring3, 93 reo2host_destination_ring2, 94 reo2host_destination_ring1, 95 rxdma2host_monitor_destination_mac3, 96 rxdma2host_monitor_destination_mac2, 97 rxdma2host_monitor_destination_mac1, 98 ppdu_end_interrupts_mac3, 99 ppdu_end_interrupts_mac2, 100 ppdu_end_interrupts_mac1, 101 rxdma2host_monitor_status_ring_mac3, 102 rxdma2host_monitor_status_ring_mac2, 103 rxdma2host_monitor_status_ring_mac1, 104 host2rxdma_host_buf_ring_mac3, 105 host2rxdma_host_buf_ring_mac2, 106 host2rxdma_host_buf_ring_mac1, 107 rxdma2host_destination_ring_mac3, 108 rxdma2host_destination_ring_mac2, 109 rxdma2host_destination_ring_mac1, 110 host2tcl_input_ring4, 111 host2tcl_input_ring3, 112 host2tcl_input_ring2, 113 host2tcl_input_ring1, 114 wbm2host_tx_completions_ring3, 115 wbm2host_tx_completions_ring2, 116 wbm2host_tx_completions_ring1, 117 tcl2host_status_ring, 118 }; 119 120 struct CE_state; 121 #define CE_COUNT_MAX 12 122 #define HIF_MAX_GRP_IRQ 16 123 124 #ifndef HIF_MAX_GROUP 125 #define HIF_MAX_GROUP 7 126 #endif 127 128 #ifndef NAPI_YIELD_BUDGET_BASED 129 #ifndef QCA_NAPI_DEF_SCALE_BIN_SHIFT 130 #define QCA_NAPI_DEF_SCALE_BIN_SHIFT 4 131 #endif 132 #else /* NAPI_YIELD_BUDGET_BASED */ 133 #define QCA_NAPI_DEF_SCALE_BIN_SHIFT 2 134 #endif /* NAPI_YIELD_BUDGET_BASED */ 135 136 #define QCA_NAPI_BUDGET 64 137 #define QCA_NAPI_DEF_SCALE \ 138 (1 << QCA_NAPI_DEF_SCALE_BIN_SHIFT) 139 140 #define HIF_NAPI_MAX_RECEIVES (QCA_NAPI_BUDGET * QCA_NAPI_DEF_SCALE) 141 /* NOTE: "napi->scale" can be changed, 142 * but this does not change the number of buckets 143 */ 144 #define QCA_NAPI_NUM_BUCKETS 4 145 146 /** 147 * qca_napi_stat - stats structure for execution contexts 148 * @napi_schedules - number of times the schedule function is called 149 * @napi_polls - number of times the execution context runs 150 * @napi_completes - number of times that the generating interrupt is reenabled 151 * @napi_workdone - cumulative of all work done reported by handler 152 * @cpu_corrected - incremented when execution context runs on a different core 153 * than the one that its irq is affined to. 154 * @napi_budget_uses - histogram of work done per execution run 155 * @time_limit_reache - count of yields due to time limit threshholds 156 * @rxpkt_thresh_reached - count of yields due to a work limit 157 * @poll_time_buckets - histogram of poll times for the napi 158 * 159 */ 160 struct qca_napi_stat { 161 uint32_t napi_schedules; 162 uint32_t napi_polls; 163 uint32_t napi_completes; 164 uint32_t napi_workdone; 165 uint32_t cpu_corrected; 166 uint32_t napi_budget_uses[QCA_NAPI_NUM_BUCKETS]; 167 uint32_t time_limit_reached; 168 uint32_t rxpkt_thresh_reached; 169 unsigned long long napi_max_poll_time; 170 #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT 171 uint32_t poll_time_buckets[QCA_NAPI_NUM_BUCKETS]; 172 #endif 173 }; 174 175 176 /** 177 * per NAPI instance data structure 178 * This data structure holds stuff per NAPI instance. 179 * Note that, in the current implementation, though scale is 180 * an instance variable, it is set to the same value for all 181 * instances. 182 */ 183 struct qca_napi_info { 184 struct net_device netdev; /* dummy net_dev */ 185 void *hif_ctx; 186 struct napi_struct napi; 187 uint8_t scale; /* currently same on all instances */ 188 uint8_t id; 189 uint8_t cpu; 190 int irq; 191 cpumask_t cpumask; 192 struct qca_napi_stat stats[NR_CPUS]; 193 #ifdef RECEIVE_OFFLOAD 194 /* will only be present for data rx CE's */ 195 void (*offld_flush_cb)(void *); 196 struct napi_struct rx_thread_napi; 197 struct net_device rx_thread_netdev; 198 #endif /* RECEIVE_OFFLOAD */ 199 qdf_lro_ctx_t lro_ctx; 200 }; 201 202 enum qca_napi_tput_state { 203 QCA_NAPI_TPUT_UNINITIALIZED, 204 QCA_NAPI_TPUT_LO, 205 QCA_NAPI_TPUT_HI 206 }; 207 enum qca_napi_cpu_state { 208 QCA_NAPI_CPU_UNINITIALIZED, 209 QCA_NAPI_CPU_DOWN, 210 QCA_NAPI_CPU_UP }; 211 212 /** 213 * struct qca_napi_cpu - an entry of the napi cpu table 214 * @core_id: physical core id of the core 215 * @cluster_id: cluster this core belongs to 216 * @core_mask: mask to match all core of this cluster 217 * @thread_mask: mask for this core within the cluster 218 * @max_freq: maximum clock this core can be clocked at 219 * same for all cpus of the same core. 220 * @napis: bitmap of napi instances on this core 221 * @execs: bitmap of execution contexts on this core 222 * cluster_nxt: chain to link cores within the same cluster 223 * 224 * This structure represents a single entry in the napi cpu 225 * table. The table is part of struct qca_napi_data. 226 * This table is initialized by the init function, called while 227 * the first napi instance is being created, updated by hotplug 228 * notifier and when cpu affinity decisions are made (by throughput 229 * detection), and deleted when the last napi instance is removed. 230 */ 231 struct qca_napi_cpu { 232 enum qca_napi_cpu_state state; 233 int core_id; 234 int cluster_id; 235 cpumask_t core_mask; 236 cpumask_t thread_mask; 237 unsigned int max_freq; 238 uint32_t napis; 239 uint32_t execs; 240 int cluster_nxt; /* index, not pointer */ 241 }; 242 243 /** 244 * struct qca_napi_data - collection of napi data for a single hif context 245 * @hif_softc: pointer to the hif context 246 * @lock: spinlock used in the event state machine 247 * @state: state variable used in the napi stat machine 248 * @ce_map: bit map indicating which ce's have napis running 249 * @exec_map: bit map of instanciated exec contexts 250 * @user_cpu_affin_map: CPU affinity map from INI config. 251 * @napi_cpu: cpu info for irq affinty 252 * @lilcl_head: 253 * @bigcl_head: 254 * @napi_mode: irq affinity & clock voting mode 255 * @cpuhp_handler: CPU hotplug event registration handle 256 */ 257 struct qca_napi_data { 258 struct hif_softc *hif_softc; 259 qdf_spinlock_t lock; 260 uint32_t state; 261 262 /* bitmap of created/registered NAPI instances, indexed by pipe_id, 263 * not used by clients (clients use an id returned by create) 264 */ 265 uint32_t ce_map; 266 uint32_t exec_map; 267 uint32_t user_cpu_affin_mask; 268 struct qca_napi_info *napis[CE_COUNT_MAX]; 269 struct qca_napi_cpu napi_cpu[NR_CPUS]; 270 int lilcl_head, bigcl_head; 271 enum qca_napi_tput_state napi_mode; 272 struct qdf_cpuhp_handler *cpuhp_handler; 273 uint8_t flags; 274 }; 275 276 /** 277 * struct hif_config_info - Place Holder for HIF configuration 278 * @enable_self_recovery: Self Recovery 279 * @enable_runtime_pm: Enable Runtime PM 280 * @runtime_pm_delay: Runtime PM Delay 281 * @rx_softirq_max_yield_duration_ns: Max Yield time duration for RX Softirq 282 * 283 * Structure for holding HIF ini parameters. 284 */ 285 struct hif_config_info { 286 bool enable_self_recovery; 287 #ifdef FEATURE_RUNTIME_PM 288 uint8_t enable_runtime_pm; 289 u_int32_t runtime_pm_delay; 290 #endif 291 uint64_t rx_softirq_max_yield_duration_ns; 292 }; 293 294 /** 295 * struct hif_target_info - Target Information 296 * @target_version: Target Version 297 * @target_type: Target Type 298 * @target_revision: Target Revision 299 * @soc_version: SOC Version 300 * @hw_name: pointer to hardware name 301 * 302 * Structure to hold target information. 303 */ 304 struct hif_target_info { 305 uint32_t target_version; 306 uint32_t target_type; 307 uint32_t target_revision; 308 uint32_t soc_version; 309 char *hw_name; 310 }; 311 312 struct hif_opaque_softc { 313 }; 314 315 /** 316 * enum hif_event_type - Type of DP events to be recorded 317 * @HIF_EVENT_IRQ_TRIGGER: IRQ trigger event 318 * @HIF_EVENT_BH_SCHED: NAPI POLL scheduled event 319 * @HIF_EVENT_SRNG_ACCESS_START: hal ring access start event 320 * @HIF_EVENT_SRNG_ACCESS_END: hal ring access end event 321 */ 322 enum hif_event_type { 323 HIF_EVENT_IRQ_TRIGGER, 324 HIF_EVENT_BH_SCHED, 325 HIF_EVENT_SRNG_ACCESS_START, 326 HIF_EVENT_SRNG_ACCESS_END, 327 }; 328 329 #ifdef WLAN_FEATURE_DP_EVENT_HISTORY 330 331 /* HIF_EVENT_HIST_MAX should always be power of 2 */ 332 #define HIF_EVENT_HIST_MAX 512 333 #define HIF_NUM_INT_CONTEXTS HIF_MAX_GROUP 334 #define HIF_EVENT_HIST_DISABLE_MASK 0 335 336 /** 337 * struct hif_event_record - an entry of the DP event history 338 * @hal_ring_id: ring id for which event is recorded 339 * @hp: head pointer of the ring (may not be applicable for all events) 340 * @tp: tail pointer of the ring (may not be applicable for all events) 341 * @cpu_id: cpu id on which the event occurred 342 * @timestamp: timestamp when event occurred 343 * @type: type of the event 344 * 345 * This structure represents the information stored for every datapath 346 * event which is logged in the history. 347 */ 348 struct hif_event_record { 349 uint8_t hal_ring_id; 350 uint32_t hp; 351 uint32_t tp; 352 int cpu_id; 353 uint64_t timestamp; 354 enum hif_event_type type; 355 }; 356 357 /** 358 * struct hif_event_history - history for one interrupt group 359 * @index: index to store new event 360 * @event: event entry 361 * 362 * This structure represents the datapath history for one 363 * interrupt group. 364 */ 365 struct hif_event_history { 366 qdf_atomic_t index; 367 struct hif_event_record event[HIF_EVENT_HIST_MAX]; 368 }; 369 370 /** 371 * hif_hist_record_event() - Record one datapath event in history 372 * @hif_ctx: HIF opaque context 373 * @event: DP event entry 374 * @intr_grp_id: interrupt group ID registered with hif 375 * 376 * Return: None 377 */ 378 void hif_hist_record_event(struct hif_opaque_softc *hif_ctx, 379 struct hif_event_record *event, 380 uint8_t intr_grp_id); 381 382 /** 383 * hif_record_event() - Wrapper function to form and record DP event 384 * @hif_ctx: HIF opaque context 385 * @intr_grp_id: interrupt group ID registered with hif 386 * @hal_ring_id: ring id for which event is recorded 387 * @hp: head pointer index of the srng 388 * @tp: tail pointer index of the srng 389 * @type: type of the event to be logged in history 390 * 391 * Return: None 392 */ 393 static inline void hif_record_event(struct hif_opaque_softc *hif_ctx, 394 uint8_t intr_grp_id, 395 uint8_t hal_ring_id, 396 uint32_t hp, 397 uint32_t tp, 398 enum hif_event_type type) 399 { 400 struct hif_event_record event; 401 402 event.hal_ring_id = hal_ring_id; 403 event.hp = hp; 404 event.tp = tp; 405 event.type = type; 406 407 return hif_hist_record_event(hif_ctx, &event, 408 intr_grp_id); 409 } 410 411 #else 412 413 static inline void hif_record_event(struct hif_opaque_softc *hif_ctx, 414 uint8_t intr_grp_id, 415 uint8_t hal_ring_id, 416 uint32_t hp, 417 uint32_t tp, 418 enum hif_event_type type) 419 { 420 } 421 #endif /* WLAN_FEATURE_DP_EVENT_HISTORY */ 422 423 /** 424 * enum HIF_DEVICE_POWER_CHANGE_TYPE: Device Power change type 425 * 426 * @HIF_DEVICE_POWER_UP: HIF layer should power up interface and/or module 427 * @HIF_DEVICE_POWER_DOWN: HIF layer should initiate bus-specific measures to 428 * minimize power 429 * @HIF_DEVICE_POWER_CUT: HIF layer should initiate bus-specific AND/OR 430 * platform-specific measures to completely power-off 431 * the module and associated hardware (i.e. cut power 432 * supplies) 433 */ 434 enum HIF_DEVICE_POWER_CHANGE_TYPE { 435 HIF_DEVICE_POWER_UP, 436 HIF_DEVICE_POWER_DOWN, 437 HIF_DEVICE_POWER_CUT 438 }; 439 440 /** 441 * enum hif_enable_type: what triggered the enabling of hif 442 * 443 * @HIF_ENABLE_TYPE_PROBE: probe triggered enable 444 * @HIF_ENABLE_TYPE_REINIT: reinit triggered enable 445 */ 446 enum hif_enable_type { 447 HIF_ENABLE_TYPE_PROBE, 448 HIF_ENABLE_TYPE_REINIT, 449 HIF_ENABLE_TYPE_MAX 450 }; 451 452 /** 453 * enum hif_disable_type: what triggered the disabling of hif 454 * 455 * @HIF_DISABLE_TYPE_PROBE_ERROR: probe error triggered disable 456 * @HIF_DISABLE_TYPE_REINIT_ERROR: reinit error triggered disable 457 * @HIF_DISABLE_TYPE_REMOVE: remove triggered disable 458 * @HIF_DISABLE_TYPE_SHUTDOWN: shutdown triggered disable 459 */ 460 enum hif_disable_type { 461 HIF_DISABLE_TYPE_PROBE_ERROR, 462 HIF_DISABLE_TYPE_REINIT_ERROR, 463 HIF_DISABLE_TYPE_REMOVE, 464 HIF_DISABLE_TYPE_SHUTDOWN, 465 HIF_DISABLE_TYPE_MAX 466 }; 467 /** 468 * enum hif_device_config_opcode: configure mode 469 * 470 * @HIF_DEVICE_POWER_STATE: device power state 471 * @HIF_DEVICE_GET_BLOCK_SIZE: get block size 472 * @HIF_DEVICE_GET_ADDR: get block address 473 * @HIF_DEVICE_GET_PENDING_EVENTS_FUNC: get pending events functions 474 * @HIF_DEVICE_GET_IRQ_PROC_MODE: get irq proc mode 475 * @HIF_DEVICE_GET_RECV_EVENT_MASK_UNMASK_FUNC: receive event function 476 * @HIF_DEVICE_POWER_STATE_CHANGE: change power state 477 * @HIF_DEVICE_GET_IRQ_YIELD_PARAMS: get yield params 478 * @HIF_CONFIGURE_QUERY_SCATTER_REQUEST_SUPPORT: configure scatter request 479 * @HIF_DEVICE_GET_OS_DEVICE: get OS device 480 * @HIF_DEVICE_DEBUG_BUS_STATE: debug bus state 481 * @HIF_BMI_DONE: bmi done 482 * @HIF_DEVICE_SET_TARGET_TYPE: set target type 483 * @HIF_DEVICE_SET_HTC_CONTEXT: set htc context 484 * @HIF_DEVICE_GET_HTC_CONTEXT: get htc context 485 */ 486 enum hif_device_config_opcode { 487 HIF_DEVICE_POWER_STATE = 0, 488 HIF_DEVICE_GET_BLOCK_SIZE, 489 HIF_DEVICE_GET_FIFO_ADDR, 490 HIF_DEVICE_GET_PENDING_EVENTS_FUNC, 491 HIF_DEVICE_GET_IRQ_PROC_MODE, 492 HIF_DEVICE_GET_RECV_EVENT_MASK_UNMASK_FUNC, 493 HIF_DEVICE_POWER_STATE_CHANGE, 494 HIF_DEVICE_GET_IRQ_YIELD_PARAMS, 495 HIF_CONFIGURE_QUERY_SCATTER_REQUEST_SUPPORT, 496 HIF_DEVICE_GET_OS_DEVICE, 497 HIF_DEVICE_DEBUG_BUS_STATE, 498 HIF_BMI_DONE, 499 HIF_DEVICE_SET_TARGET_TYPE, 500 HIF_DEVICE_SET_HTC_CONTEXT, 501 HIF_DEVICE_GET_HTC_CONTEXT, 502 }; 503 504 #ifdef CONFIG_ATH_PCIE_ACCESS_DEBUG 505 struct HID_ACCESS_LOG { 506 uint32_t seqnum; 507 bool is_write; 508 void *addr; 509 uint32_t value; 510 }; 511 #endif 512 513 void hif_reg_write(struct hif_opaque_softc *hif_ctx, uint32_t offset, 514 uint32_t value); 515 uint32_t hif_reg_read(struct hif_opaque_softc *hif_ctx, uint32_t offset); 516 517 #define HIF_MAX_DEVICES 1 518 /** 519 * struct htc_callbacks - Structure for HTC Callbacks methods 520 * @context: context to pass to the dsrhandler 521 * note : rwCompletionHandler is provided the context 522 * passed to hif_read_write 523 * @rwCompletionHandler: Read / write completion handler 524 * @dsrHandler: DSR Handler 525 */ 526 struct htc_callbacks { 527 void *context; 528 QDF_STATUS(*rw_compl_handler)(void *rw_ctx, QDF_STATUS status); 529 QDF_STATUS(*dsr_handler)(void *context); 530 }; 531 532 /** 533 * struct hif_driver_state_callbacks - Callbacks for HIF to query Driver state 534 * @context: Private data context 535 * @set_recovery_in_progress: To Set Driver state for recovery in progress 536 * @is_recovery_in_progress: Query if driver state is recovery in progress 537 * @is_load_unload_in_progress: Query if driver state Load/Unload in Progress 538 * @is_driver_unloading: Query if driver is unloading. 539 * @get_bandwidth_level: Query current bandwidth level for the driver 540 * This Structure provides callback pointer for HIF to query hdd for driver 541 * states. 542 */ 543 struct hif_driver_state_callbacks { 544 void *context; 545 void (*set_recovery_in_progress)(void *context, uint8_t val); 546 bool (*is_recovery_in_progress)(void *context); 547 bool (*is_load_unload_in_progress)(void *context); 548 bool (*is_driver_unloading)(void *context); 549 bool (*is_target_ready)(void *context); 550 int (*get_bandwidth_level)(void *context); 551 }; 552 553 /* This API detaches the HTC layer from the HIF device */ 554 void hif_detach_htc(struct hif_opaque_softc *hif_ctx); 555 556 /****************************************************************/ 557 /* BMI and Diag window abstraction */ 558 /****************************************************************/ 559 560 #define HIF_BMI_EXCHANGE_NO_TIMEOUT ((uint32_t)(0)) 561 562 #define DIAG_TRANSFER_LIMIT 2048U /* maximum number of bytes that can be 563 * handled atomically by 564 * DiagRead/DiagWrite 565 */ 566 567 #ifdef WLAN_FEATURE_BMI 568 /* 569 * API to handle HIF-specific BMI message exchanges, this API is synchronous 570 * and only allowed to be called from a context that can block (sleep) 571 */ 572 QDF_STATUS hif_exchange_bmi_msg(struct hif_opaque_softc *hif_ctx, 573 qdf_dma_addr_t cmd, qdf_dma_addr_t rsp, 574 uint8_t *pSendMessage, uint32_t Length, 575 uint8_t *pResponseMessage, 576 uint32_t *pResponseLength, uint32_t TimeoutMS); 577 void hif_register_bmi_callbacks(struct hif_opaque_softc *hif_ctx); 578 bool hif_needs_bmi(struct hif_opaque_softc *hif_ctx); 579 #else /* WLAN_FEATURE_BMI */ 580 static inline void 581 hif_register_bmi_callbacks(struct hif_opaque_softc *hif_ctx) 582 { 583 } 584 585 static inline bool 586 hif_needs_bmi(struct hif_opaque_softc *hif_ctx) 587 { 588 return false; 589 } 590 #endif /* WLAN_FEATURE_BMI */ 591 592 /* 593 * APIs to handle HIF specific diagnostic read accesses. These APIs are 594 * synchronous and only allowed to be called from a context that 595 * can block (sleep). They are not high performance APIs. 596 * 597 * hif_diag_read_access reads a 4 Byte aligned/length value from a 598 * Target register or memory word. 599 * 600 * hif_diag_read_mem reads an arbitrary length of arbitrarily aligned memory. 601 */ 602 QDF_STATUS hif_diag_read_access(struct hif_opaque_softc *hif_ctx, 603 uint32_t address, uint32_t *data); 604 QDF_STATUS hif_diag_read_mem(struct hif_opaque_softc *hif_ctx, uint32_t address, 605 uint8_t *data, int nbytes); 606 void hif_dump_target_memory(struct hif_opaque_softc *hif_ctx, 607 void *ramdump_base, uint32_t address, uint32_t size); 608 /* 609 * APIs to handle HIF specific diagnostic write accesses. These APIs are 610 * synchronous and only allowed to be called from a context that 611 * can block (sleep). 612 * They are not high performance APIs. 613 * 614 * hif_diag_write_access writes a 4 Byte aligned/length value to a 615 * Target register or memory word. 616 * 617 * hif_diag_write_mem writes an arbitrary length of arbitrarily aligned memory. 618 */ 619 QDF_STATUS hif_diag_write_access(struct hif_opaque_softc *hif_ctx, 620 uint32_t address, uint32_t data); 621 QDF_STATUS hif_diag_write_mem(struct hif_opaque_softc *hif_ctx, 622 uint32_t address, uint8_t *data, int nbytes); 623 624 typedef void (*fastpath_msg_handler)(void *, qdf_nbuf_t *, uint32_t); 625 626 void hif_enable_polled_mode(struct hif_opaque_softc *hif_ctx); 627 bool hif_is_polled_mode_enabled(struct hif_opaque_softc *hif_ctx); 628 629 /* 630 * Set the FASTPATH_mode_on flag in sc, for use by data path 631 */ 632 #ifdef WLAN_FEATURE_FASTPATH 633 void hif_enable_fastpath(struct hif_opaque_softc *hif_ctx); 634 bool hif_is_fastpath_mode_enabled(struct hif_opaque_softc *hif_ctx); 635 void *hif_get_ce_handle(struct hif_opaque_softc *hif_ctx, int ret); 636 int hif_ce_fastpath_cb_register(struct hif_opaque_softc *hif_ctx, 637 fastpath_msg_handler handler, void *context); 638 #else 639 static inline int hif_ce_fastpath_cb_register(struct hif_opaque_softc *hif_ctx, 640 fastpath_msg_handler handler, 641 void *context) 642 { 643 return QDF_STATUS_E_FAILURE; 644 } 645 static inline void *hif_get_ce_handle(struct hif_opaque_softc *hif_ctx, int ret) 646 { 647 return NULL; 648 } 649 650 #endif 651 652 /* 653 * Enable/disable CDC max performance workaround 654 * For max-performace set this to 0 655 * To allow SoC to enter sleep set this to 1 656 */ 657 #define CONFIG_DISABLE_CDC_MAX_PERF_WAR 0 658 659 void hif_ipa_get_ce_resource(struct hif_opaque_softc *hif_ctx, 660 qdf_shared_mem_t **ce_sr, 661 uint32_t *ce_sr_ring_size, 662 qdf_dma_addr_t *ce_reg_paddr); 663 664 /** 665 * @brief List of callbacks - filled in by HTC. 666 */ 667 struct hif_msg_callbacks { 668 void *Context; 669 /**< context meaningful to HTC */ 670 QDF_STATUS (*txCompletionHandler)(void *Context, qdf_nbuf_t wbuf, 671 uint32_t transferID, 672 uint32_t toeplitz_hash_result); 673 QDF_STATUS (*rxCompletionHandler)(void *Context, qdf_nbuf_t wbuf, 674 uint8_t pipeID); 675 void (*txResourceAvailHandler)(void *context, uint8_t pipe); 676 void (*fwEventHandler)(void *context, QDF_STATUS status); 677 void (*update_bundle_stats)(void *context, uint8_t no_of_pkt_in_bundle); 678 }; 679 680 enum hif_target_status { 681 TARGET_STATUS_CONNECTED = 0, /* target connected */ 682 TARGET_STATUS_RESET, /* target got reset */ 683 TARGET_STATUS_EJECT, /* target got ejected */ 684 TARGET_STATUS_SUSPEND /*target got suspend */ 685 }; 686 687 /** 688 * enum hif_attribute_flags: configure hif 689 * 690 * @HIF_LOWDESC_CE_CFG: Configure HIF with Low descriptor CE 691 * @HIF_LOWDESC_CE_NO_PKTLOG_CFG: Configure HIF with Low descriptor 692 * + No pktlog CE 693 */ 694 enum hif_attribute_flags { 695 HIF_LOWDESC_CE_CFG = 1, 696 HIF_LOWDESC_CE_NO_PKTLOG_CFG 697 }; 698 699 #define HIF_DATA_ATTR_SET_TX_CLASSIFY(attr, v) \ 700 (attr |= (v & 0x01) << 5) 701 #define HIF_DATA_ATTR_SET_ENCAPSULATION_TYPE(attr, v) \ 702 (attr |= (v & 0x03) << 6) 703 #define HIF_DATA_ATTR_SET_ADDR_X_SEARCH_DISABLE(attr, v) \ 704 (attr |= (v & 0x01) << 13) 705 #define HIF_DATA_ATTR_SET_ADDR_Y_SEARCH_DISABLE(attr, v) \ 706 (attr |= (v & 0x01) << 14) 707 #define HIF_DATA_ATTR_SET_TOEPLITZ_HASH_ENABLE(attr, v) \ 708 (attr |= (v & 0x01) << 15) 709 #define HIF_DATA_ATTR_SET_PACKET_OR_RESULT_OFFSET(attr, v) \ 710 (attr |= (v & 0x0FFF) << 16) 711 #define HIF_DATA_ATTR_SET_ENABLE_11H(attr, v) \ 712 (attr |= (v & 0x01) << 30) 713 714 struct hif_ul_pipe_info { 715 unsigned int nentries; 716 unsigned int nentries_mask; 717 unsigned int sw_index; 718 unsigned int write_index; /* cached copy */ 719 unsigned int hw_index; /* cached copy */ 720 void *base_addr_owner_space; /* Host address space */ 721 qdf_dma_addr_t base_addr_CE_space; /* CE address space */ 722 }; 723 724 struct hif_dl_pipe_info { 725 unsigned int nentries; 726 unsigned int nentries_mask; 727 unsigned int sw_index; 728 unsigned int write_index; /* cached copy */ 729 unsigned int hw_index; /* cached copy */ 730 void *base_addr_owner_space; /* Host address space */ 731 qdf_dma_addr_t base_addr_CE_space; /* CE address space */ 732 }; 733 734 struct hif_pipe_addl_info { 735 uint32_t pci_mem; 736 uint32_t ctrl_addr; 737 struct hif_ul_pipe_info ul_pipe; 738 struct hif_dl_pipe_info dl_pipe; 739 }; 740 741 #ifdef CONFIG_SLUB_DEBUG_ON 742 #define MSG_FLUSH_NUM 16 743 #else /* PERF build */ 744 #define MSG_FLUSH_NUM 32 745 #endif /* SLUB_DEBUG_ON */ 746 747 struct hif_bus_id; 748 749 void hif_claim_device(struct hif_opaque_softc *hif_ctx); 750 QDF_STATUS hif_get_config_item(struct hif_opaque_softc *hif_ctx, 751 int opcode, void *config, uint32_t config_len); 752 void hif_set_mailbox_swap(struct hif_opaque_softc *hif_ctx); 753 void hif_mask_interrupt_call(struct hif_opaque_softc *hif_ctx); 754 void hif_post_init(struct hif_opaque_softc *hif_ctx, void *hHTC, 755 struct hif_msg_callbacks *callbacks); 756 QDF_STATUS hif_start(struct hif_opaque_softc *hif_ctx); 757 void hif_stop(struct hif_opaque_softc *hif_ctx); 758 void hif_flush_surprise_remove(struct hif_opaque_softc *hif_ctx); 759 void hif_dump(struct hif_opaque_softc *hif_ctx, uint8_t CmdId, bool start); 760 void hif_trigger_dump(struct hif_opaque_softc *hif_ctx, 761 uint8_t cmd_id, bool start); 762 763 QDF_STATUS hif_send_head(struct hif_opaque_softc *hif_ctx, uint8_t PipeID, 764 uint32_t transferID, uint32_t nbytes, 765 qdf_nbuf_t wbuf, uint32_t data_attr); 766 void hif_send_complete_check(struct hif_opaque_softc *hif_ctx, uint8_t PipeID, 767 int force); 768 void hif_shut_down_device(struct hif_opaque_softc *hif_ctx); 769 void hif_get_default_pipe(struct hif_opaque_softc *hif_ctx, uint8_t *ULPipe, 770 uint8_t *DLPipe); 771 int hif_map_service_to_pipe(struct hif_opaque_softc *hif_ctx, uint16_t svc_id, 772 uint8_t *ul_pipe, uint8_t *dl_pipe, int *ul_is_polled, 773 int *dl_is_polled); 774 uint16_t 775 hif_get_free_queue_number(struct hif_opaque_softc *hif_ctx, uint8_t PipeID); 776 void *hif_get_targetdef(struct hif_opaque_softc *hif_ctx); 777 uint32_t hif_hia_item_address(uint32_t target_type, uint32_t item_offset); 778 void hif_set_target_sleep(struct hif_opaque_softc *hif_ctx, bool sleep_ok, 779 bool wait_for_it); 780 int hif_check_fw_reg(struct hif_opaque_softc *hif_ctx); 781 #ifndef HIF_PCI 782 static inline int hif_check_soc_status(struct hif_opaque_softc *hif_ctx) 783 { 784 return 0; 785 } 786 #else 787 int hif_check_soc_status(struct hif_opaque_softc *hif_ctx); 788 #endif 789 void hif_get_hw_info(struct hif_opaque_softc *hif_ctx, u32 *version, 790 u32 *revision, const char **target_name); 791 792 #ifdef RECEIVE_OFFLOAD 793 /** 794 * hif_offld_flush_cb_register() - Register the offld flush callback 795 * @scn: HIF opaque context 796 * @offld_flush_handler: Flush callback is either ol_flush, incase of rx_thread 797 * Or GRO/LRO flush when RxThread is not enabled. Called 798 * with corresponding context for flush. 799 * Return: None 800 */ 801 void hif_offld_flush_cb_register(struct hif_opaque_softc *scn, 802 void (offld_flush_handler)(void *ol_ctx)); 803 804 /** 805 * hif_offld_flush_cb_deregister() - deRegister the offld flush callback 806 * @scn: HIF opaque context 807 * 808 * Return: None 809 */ 810 void hif_offld_flush_cb_deregister(struct hif_opaque_softc *scn); 811 #endif 812 813 #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT 814 /** 815 * hif_exec_should_yield() - Check if hif napi context should yield 816 * @hif_ctx - HIF opaque context 817 * @grp_id - grp_id of the napi for which check needs to be done 818 * 819 * The function uses grp_id to look for NAPI and checks if NAPI needs to 820 * yield. HIF_EXT_GROUP_MAX_YIELD_DURATION_NS is the duration used for 821 * yield decision. 822 * 823 * Return: true if NAPI needs to yield, else false 824 */ 825 bool hif_exec_should_yield(struct hif_opaque_softc *hif_ctx, uint grp_id); 826 #else 827 static inline bool hif_exec_should_yield(struct hif_opaque_softc *hif_ctx, 828 uint grp_id) 829 { 830 return false; 831 } 832 #endif 833 834 void hif_disable_isr(struct hif_opaque_softc *hif_ctx); 835 void hif_reset_soc(struct hif_opaque_softc *hif_ctx); 836 void hif_save_htc_htt_config_endpoint(struct hif_opaque_softc *hif_ctx, 837 int htc_htt_tx_endpoint); 838 839 /** 840 * hif_open() - Create hif handle 841 * @qdf_ctx: qdf context 842 * @mode: Driver Mode 843 * @bus_type: Bus Type 844 * @cbk: CDS Callbacks 845 * @psoc: psoc object manager 846 * 847 * API to open HIF Context 848 * 849 * Return: HIF Opaque Pointer 850 */ 851 struct hif_opaque_softc *hif_open(qdf_device_t qdf_ctx, 852 uint32_t mode, 853 enum qdf_bus_type bus_type, 854 struct hif_driver_state_callbacks *cbk, 855 struct wlan_objmgr_psoc *psoc); 856 857 void hif_close(struct hif_opaque_softc *hif_ctx); 858 QDF_STATUS hif_enable(struct hif_opaque_softc *hif_ctx, struct device *dev, 859 void *bdev, const struct hif_bus_id *bid, 860 enum qdf_bus_type bus_type, 861 enum hif_enable_type type); 862 void hif_disable(struct hif_opaque_softc *hif_ctx, enum hif_disable_type type); 863 #ifdef CE_TASKLET_DEBUG_ENABLE 864 void hif_enable_ce_latency_stats(struct hif_opaque_softc *hif_ctx, 865 uint8_t value); 866 #endif 867 void hif_display_stats(struct hif_opaque_softc *hif_ctx); 868 void hif_clear_stats(struct hif_opaque_softc *hif_ctx); 869 870 /** 871 * enum wlan_rtpm_dbgid - runtime pm put/get debug id 872 * @RTPM_ID_RESVERD: Reserved 873 * @RTPM_ID_WMI: WMI sending msg, expect put happen at 874 * tx completion from CE level directly. 875 * @RTPM_ID_HTC: pkt sending by HTT_DATA_MSG_SVC, expect 876 * put from fw response or just in 877 * htc_issue_packets 878 * @RTPM_ID_QOS_NOTIFY: pm qos notifer 879 * @RTPM_ID_DP_TX_DESC_ALLOC_FREE: tx desc alloc/free 880 * @RTPM_ID_CE_SEND_FAST: operation in ce_send_fast, not include 881 * the pkt put happens outside this function 882 * @RTPM_ID_SUSPEND_RESUME: suspend/resume in hdd 883 * @RTPM_ID_DW_TX_HW_ENQUEUE: operation in functin dp_tx_hw_enqueue 884 * @RTPM_ID_HAL_REO_CMD: HAL_REO_CMD operation 885 * @RTPM_ID_DP_PRINT_RING_STATS: operation in dp_print_ring_stats 886 */ 887 /* New value added to the enum must also be reflected in function 888 * rtpm_string_from_dbgid() 889 */ 890 typedef enum { 891 RTPM_ID_RESVERD = 0, 892 RTPM_ID_WMI = 1, 893 RTPM_ID_HTC = 2, 894 RTPM_ID_QOS_NOTIFY = 3, 895 RTPM_ID_DP_TX_DESC_ALLOC_FREE = 4, 896 RTPM_ID_CE_SEND_FAST = 5, 897 RTPM_ID_SUSPEND_RESUME = 6, 898 RTPM_ID_DW_TX_HW_ENQUEUE = 7, 899 RTPM_ID_HAL_REO_CMD = 8, 900 RTPM_ID_DP_PRINT_RING_STATS = 9, 901 902 RTPM_ID_MAX, 903 } wlan_rtpm_dbgid; 904 905 /** 906 * rtpm_string_from_dbgid() - Convert dbgid to respective string 907 * @id - debug id 908 * 909 * Debug support function to convert dbgid to string. 910 * Please note to add new string in the array at index equal to 911 * its enum value in wlan_rtpm_dbgid. 912 */ 913 static inline char *rtpm_string_from_dbgid(wlan_rtpm_dbgid id) 914 { 915 static const char *strings[] = { "RTPM_ID_RESVERD", 916 "RTPM_ID_WMI", 917 "RTPM_ID_HTC", 918 "RTPM_ID_QOS_NOTIFY", 919 "RTPM_ID_DP_TX_DESC_ALLOC_FREE", 920 "RTPM_ID_CE_SEND_FAST", 921 "RTPM_ID_SUSPEND_RESUME", 922 "RTPM_ID_DW_TX_HW_ENQUEUE", 923 "RTPM_ID_HAL_REO_CMD", 924 "RTPM_ID_DP_PRINT_RING_STATS", 925 "RTPM_ID_MAX"}; 926 927 return (char *)strings[id]; 928 } 929 930 #ifdef FEATURE_RUNTIME_PM 931 struct hif_pm_runtime_lock; 932 void hif_fastpath_resume(struct hif_opaque_softc *hif_ctx); 933 int hif_pm_runtime_get_sync(struct hif_opaque_softc *hif_ctx, 934 wlan_rtpm_dbgid rtpm_dbgid); 935 int hif_pm_runtime_put_sync_suspend(struct hif_opaque_softc *hif_ctx, 936 wlan_rtpm_dbgid rtpm_dbgid); 937 int hif_pm_runtime_request_resume(struct hif_opaque_softc *hif_ctx); 938 int hif_pm_runtime_get(struct hif_opaque_softc *hif_ctx, 939 wlan_rtpm_dbgid rtpm_dbgid); 940 void hif_pm_runtime_get_noresume(struct hif_opaque_softc *hif_ctx, 941 wlan_rtpm_dbgid rtpm_dbgid); 942 int hif_pm_runtime_put(struct hif_opaque_softc *hif_ctx, 943 wlan_rtpm_dbgid rtpm_dbgid); 944 int hif_pm_runtime_put_noidle(struct hif_opaque_softc *hif_ctx, 945 wlan_rtpm_dbgid rtpm_dbgid); 946 void hif_pm_runtime_mark_last_busy(struct hif_opaque_softc *hif_ctx); 947 int hif_runtime_lock_init(qdf_runtime_lock_t *lock, const char *name); 948 void hif_runtime_lock_deinit(struct hif_opaque_softc *hif_ctx, 949 struct hif_pm_runtime_lock *lock); 950 int hif_pm_runtime_prevent_suspend(struct hif_opaque_softc *ol_sc, 951 struct hif_pm_runtime_lock *lock); 952 int hif_pm_runtime_allow_suspend(struct hif_opaque_softc *ol_sc, 953 struct hif_pm_runtime_lock *lock); 954 int hif_pm_runtime_prevent_suspend_timeout(struct hif_opaque_softc *ol_sc, 955 struct hif_pm_runtime_lock *lock, unsigned int delay); 956 bool hif_pm_runtime_is_suspended(struct hif_opaque_softc *hif_ctx); 957 int hif_pm_runtime_get_monitor_wake_intr(struct hif_opaque_softc *hif_ctx); 958 void hif_pm_runtime_set_monitor_wake_intr(struct hif_opaque_softc *hif_ctx, 959 int val); 960 void hif_pm_runtime_mark_dp_rx_busy(struct hif_opaque_softc *hif_ctx); 961 int hif_pm_runtime_is_dp_rx_busy(struct hif_opaque_softc *hif_ctx); 962 qdf_time_t hif_pm_runtime_get_dp_rx_busy_mark(struct hif_opaque_softc *hif_ctx); 963 int hif_pm_runtime_sync_resume(struct hif_opaque_softc *hif_ctx); 964 #else 965 struct hif_pm_runtime_lock { 966 const char *name; 967 }; 968 static inline void hif_fastpath_resume(struct hif_opaque_softc *hif_ctx) {} 969 static inline int 970 hif_pm_runtime_get_sync(struct hif_opaque_softc *hif_ctx, 971 wlan_rtpm_dbgid rtpm_dbgid) 972 { return 0; } 973 static inline int 974 hif_pm_runtime_put_sync_suspend(struct hif_opaque_softc *hif_ctx, 975 wlan_rtpm_dbgid rtpm_dbgid) 976 { return 0; } 977 static inline int 978 hif_pm_runtime_request_resume(struct hif_opaque_softc *hif_ctx) 979 { return 0; } 980 static inline void 981 hif_pm_runtime_get_noresume(struct hif_opaque_softc *hif_ctx, 982 wlan_rtpm_dbgid rtpm_dbgid) 983 {} 984 985 static inline int 986 hif_pm_runtime_get(struct hif_opaque_softc *hif_ctx, wlan_rtpm_dbgid rtpm_dbgid) 987 { return 0; } 988 static inline int 989 hif_pm_runtime_put(struct hif_opaque_softc *hif_ctx, wlan_rtpm_dbgid rtpm_dbgid) 990 { return 0; } 991 static inline int 992 hif_pm_runtime_put_noidle(struct hif_opaque_softc *hif_ctx, 993 wlan_rtpm_dbgid rtpm_dbgid) 994 { return 0; } 995 static inline void 996 hif_pm_runtime_mark_last_busy(struct hif_opaque_softc *hif_ctx) {}; 997 static inline int hif_runtime_lock_init(qdf_runtime_lock_t *lock, 998 const char *name) 999 { return 0; } 1000 static inline void 1001 hif_runtime_lock_deinit(struct hif_opaque_softc *hif_ctx, 1002 struct hif_pm_runtime_lock *lock) {} 1003 1004 static inline int hif_pm_runtime_prevent_suspend(struct hif_opaque_softc *ol_sc, 1005 struct hif_pm_runtime_lock *lock) 1006 { return 0; } 1007 static inline int hif_pm_runtime_allow_suspend(struct hif_opaque_softc *ol_sc, 1008 struct hif_pm_runtime_lock *lock) 1009 { return 0; } 1010 static inline int 1011 hif_pm_runtime_prevent_suspend_timeout(struct hif_opaque_softc *ol_sc, 1012 struct hif_pm_runtime_lock *lock, unsigned int delay) 1013 { return 0; } 1014 static inline bool hif_pm_runtime_is_suspended(struct hif_opaque_softc *hif_ctx) 1015 { return false; } 1016 static inline int 1017 hif_pm_runtime_get_monitor_wake_intr(struct hif_opaque_softc *hif_ctx) 1018 { return 0; } 1019 static inline void 1020 hif_pm_runtime_set_monitor_wake_intr(struct hif_opaque_softc *hif_ctx, int val) 1021 { return; } 1022 static inline void 1023 hif_pm_runtime_mark_dp_rx_busy(struct hif_opaque_softc *hif_ctx) {}; 1024 static inline int 1025 hif_pm_runtime_is_dp_rx_busy(struct hif_opaque_softc *hif_ctx) 1026 { return 0; } 1027 static inline qdf_time_t 1028 hif_pm_runtime_get_dp_rx_busy_mark(struct hif_opaque_softc *hif_ctx) 1029 { return 0; } 1030 static inline int hif_pm_runtime_sync_resume(struct hif_opaque_softc *hif_ctx) 1031 { return 0; } 1032 #endif 1033 1034 void hif_enable_power_management(struct hif_opaque_softc *hif_ctx, 1035 bool is_packet_log_enabled); 1036 void hif_disable_power_management(struct hif_opaque_softc *hif_ctx); 1037 1038 void hif_vote_link_down(struct hif_opaque_softc *hif_ctx); 1039 void hif_vote_link_up(struct hif_opaque_softc *hif_ctx); 1040 bool hif_can_suspend_link(struct hif_opaque_softc *hif_ctx); 1041 1042 #ifdef IPA_OFFLOAD 1043 /** 1044 * hif_get_ipa_hw_type() - get IPA hw type 1045 * 1046 * This API return the IPA hw type. 1047 * 1048 * Return: IPA hw type 1049 */ 1050 static inline 1051 enum ipa_hw_type hif_get_ipa_hw_type(void) 1052 { 1053 return ipa_get_hw_type(); 1054 } 1055 1056 /** 1057 * hif_get_ipa_present() - get IPA hw status 1058 * 1059 * This API return the IPA hw status. 1060 * 1061 * Return: true if IPA is present or false otherwise 1062 */ 1063 static inline 1064 bool hif_get_ipa_present(void) 1065 { 1066 if (ipa_uc_reg_rdyCB(NULL) != -EPERM) 1067 return true; 1068 else 1069 return false; 1070 } 1071 #endif 1072 int hif_bus_resume(struct hif_opaque_softc *hif_ctx); 1073 /** 1074 * hif_bus_ealry_suspend() - stop non wmi tx traffic 1075 * @context: hif context 1076 */ 1077 int hif_bus_early_suspend(struct hif_opaque_softc *hif_ctx); 1078 1079 /** 1080 * hif_bus_late_resume() - resume non wmi traffic 1081 * @context: hif context 1082 */ 1083 int hif_bus_late_resume(struct hif_opaque_softc *hif_ctx); 1084 int hif_bus_suspend(struct hif_opaque_softc *hif_ctx); 1085 int hif_bus_resume_noirq(struct hif_opaque_softc *hif_ctx); 1086 int hif_bus_suspend_noirq(struct hif_opaque_softc *hif_ctx); 1087 1088 /** 1089 * hif_apps_irqs_enable() - Enables all irqs from the APPS side 1090 * @hif_ctx: an opaque HIF handle to use 1091 * 1092 * As opposed to the standard hif_irq_enable, this function always applies to 1093 * the APPS side kernel interrupt handling. 1094 * 1095 * Return: errno 1096 */ 1097 int hif_apps_irqs_enable(struct hif_opaque_softc *hif_ctx); 1098 1099 /** 1100 * hif_apps_irqs_disable() - Disables all irqs from the APPS side 1101 * @hif_ctx: an opaque HIF handle to use 1102 * 1103 * As opposed to the standard hif_irq_disable, this function always applies to 1104 * the APPS side kernel interrupt handling. 1105 * 1106 * Return: errno 1107 */ 1108 int hif_apps_irqs_disable(struct hif_opaque_softc *hif_ctx); 1109 1110 /** 1111 * hif_apps_wake_irq_enable() - Enables the wake irq from the APPS side 1112 * @hif_ctx: an opaque HIF handle to use 1113 * 1114 * As opposed to the standard hif_irq_enable, this function always applies to 1115 * the APPS side kernel interrupt handling. 1116 * 1117 * Return: errno 1118 */ 1119 int hif_apps_wake_irq_enable(struct hif_opaque_softc *hif_ctx); 1120 1121 /** 1122 * hif_apps_wake_irq_disable() - Disables the wake irq from the APPS side 1123 * @hif_ctx: an opaque HIF handle to use 1124 * 1125 * As opposed to the standard hif_irq_disable, this function always applies to 1126 * the APPS side kernel interrupt handling. 1127 * 1128 * Return: errno 1129 */ 1130 int hif_apps_wake_irq_disable(struct hif_opaque_softc *hif_ctx); 1131 1132 #ifdef FEATURE_RUNTIME_PM 1133 int hif_pre_runtime_suspend(struct hif_opaque_softc *hif_ctx); 1134 void hif_pre_runtime_resume(struct hif_opaque_softc *hif_ctx); 1135 int hif_runtime_suspend(struct hif_opaque_softc *hif_ctx); 1136 int hif_runtime_resume(struct hif_opaque_softc *hif_ctx); 1137 void hif_process_runtime_suspend_success(struct hif_opaque_softc *hif_ctx); 1138 void hif_process_runtime_suspend_failure(struct hif_opaque_softc *hif_ctx); 1139 void hif_process_runtime_resume_success(struct hif_opaque_softc *hif_ctx); 1140 #endif 1141 1142 int hif_get_irq_num(struct hif_opaque_softc *scn, int *irq, uint32_t size); 1143 int hif_dump_registers(struct hif_opaque_softc *scn); 1144 int ol_copy_ramdump(struct hif_opaque_softc *scn); 1145 void hif_crash_shutdown(struct hif_opaque_softc *hif_ctx); 1146 void hif_get_hw_info(struct hif_opaque_softc *hif_ctx, u32 *version, 1147 u32 *revision, const char **target_name); 1148 enum qdf_bus_type hif_get_bus_type(struct hif_opaque_softc *hif_hdl); 1149 struct hif_target_info *hif_get_target_info_handle(struct hif_opaque_softc * 1150 scn); 1151 struct hif_config_info *hif_get_ini_handle(struct hif_opaque_softc *hif_ctx); 1152 struct ramdump_info *hif_get_ramdump_ctx(struct hif_opaque_softc *hif_ctx); 1153 enum hif_target_status hif_get_target_status(struct hif_opaque_softc *hif_ctx); 1154 void hif_set_target_status(struct hif_opaque_softc *hif_ctx, enum 1155 hif_target_status); 1156 void hif_init_ini_config(struct hif_opaque_softc *hif_ctx, 1157 struct hif_config_info *cfg); 1158 void hif_update_tx_ring(struct hif_opaque_softc *osc, u_int32_t num_htt_cmpls); 1159 qdf_nbuf_t hif_batch_send(struct hif_opaque_softc *osc, qdf_nbuf_t msdu, 1160 uint32_t transfer_id, u_int32_t len, uint32_t sendhead); 1161 QDF_STATUS hif_send_single(struct hif_opaque_softc *osc, qdf_nbuf_t msdu, 1162 uint32_t transfer_id, u_int32_t len); 1163 int hif_send_fast(struct hif_opaque_softc *osc, qdf_nbuf_t nbuf, 1164 uint32_t transfer_id, uint32_t download_len); 1165 void hif_pkt_dl_len_set(void *hif_sc, unsigned int pkt_download_len); 1166 void hif_ce_war_disable(void); 1167 void hif_ce_war_enable(void); 1168 void hif_disable_interrupt(struct hif_opaque_softc *osc, uint32_t pipe_num); 1169 #ifdef QCA_NSS_WIFI_OFFLOAD_SUPPORT 1170 struct hif_pipe_addl_info *hif_get_addl_pipe_info(struct hif_opaque_softc *osc, 1171 struct hif_pipe_addl_info *hif_info, uint32_t pipe_number); 1172 uint32_t hif_set_nss_wifiol_mode(struct hif_opaque_softc *osc, 1173 uint32_t pipe_num); 1174 int32_t hif_get_nss_wifiol_bypass_nw_process(struct hif_opaque_softc *osc); 1175 #endif /* QCA_NSS_WIFI_OFFLOAD_SUPPORT */ 1176 1177 void hif_set_bundle_mode(struct hif_opaque_softc *hif_ctx, bool enabled, 1178 int rx_bundle_cnt); 1179 int hif_bus_reset_resume(struct hif_opaque_softc *hif_ctx); 1180 1181 void hif_set_attribute(struct hif_opaque_softc *osc, uint8_t hif_attrib); 1182 1183 void *hif_get_lro_info(int ctx_id, struct hif_opaque_softc *hif_hdl); 1184 1185 enum hif_exec_type { 1186 HIF_EXEC_NAPI_TYPE, 1187 HIF_EXEC_TASKLET_TYPE, 1188 }; 1189 1190 typedef uint32_t (*ext_intr_handler)(void *, uint32_t); 1191 1192 /** 1193 * hif_get_int_ctx_irq_num() - retrieve an irq num for an interrupt context id 1194 * @softc: hif opaque context owning the exec context 1195 * @id: the id of the interrupt context 1196 * 1197 * Return: IRQ number of the first (zero'th) IRQ within the interrupt context ID 1198 * 'id' registered with the OS 1199 */ 1200 int32_t hif_get_int_ctx_irq_num(struct hif_opaque_softc *softc, 1201 uint8_t id); 1202 1203 uint32_t hif_configure_ext_group_interrupts(struct hif_opaque_softc *hif_ctx); 1204 uint32_t hif_register_ext_group(struct hif_opaque_softc *hif_ctx, 1205 uint32_t numirq, uint32_t irq[], ext_intr_handler handler, 1206 void *cb_ctx, const char *context_name, 1207 enum hif_exec_type type, uint32_t scale); 1208 1209 void hif_deregister_exec_group(struct hif_opaque_softc *hif_ctx, 1210 const char *context_name); 1211 1212 void hif_update_pipe_callback(struct hif_opaque_softc *osc, 1213 u_int8_t pipeid, 1214 struct hif_msg_callbacks *callbacks); 1215 1216 /** 1217 * hif_print_napi_stats() - Display HIF NAPI stats 1218 * @hif_ctx - HIF opaque context 1219 * 1220 * Return: None 1221 */ 1222 void hif_print_napi_stats(struct hif_opaque_softc *hif_ctx); 1223 1224 /* hif_clear_napi_stats() - function clears the stats of the 1225 * latency when called. 1226 * @hif_ctx - the HIF context to assign the callback to 1227 * 1228 * Return: None 1229 */ 1230 void hif_clear_napi_stats(struct hif_opaque_softc *hif_ctx); 1231 1232 #ifdef __cplusplus 1233 } 1234 #endif 1235 1236 #ifdef FORCE_WAKE 1237 /** 1238 * hif_force_wake_request() - Function to wake from power collapse 1239 * @handle: HIF opaque handle 1240 * 1241 * Description: API to check if the device is awake or not before 1242 * read/write to BAR + 4K registers. If device is awake return 1243 * success otherwise write '1' to 1244 * PCIE_PCIE_LOCAL_REG_PCIE_SOC_WAKE_PCIE_LOCAL_REG which will interrupt 1245 * the device and does wakeup the PCI and MHI within 50ms 1246 * and then the device writes a value to 1247 * PCIE_SOC_PCIE_REG_PCIE_SCRATCH_0_SOC_PCIE_REG to complete the 1248 * handshake process to let the host know the device is awake. 1249 * 1250 * Return: zero - success/non-zero - failure 1251 */ 1252 int hif_force_wake_request(struct hif_opaque_softc *handle); 1253 1254 /** 1255 * hif_force_wake_release() - API to release/reset the SOC wake register 1256 * from interrupting the device. 1257 * @handle: HIF opaque handle 1258 * 1259 * Description: API to set the 1260 * PCIE_PCIE_LOCAL_REG_PCIE_SOC_WAKE_PCIE_LOCAL_REG to '0' 1261 * to release the interrupt line. 1262 * 1263 * Return: zero - success/non-zero - failure 1264 */ 1265 int hif_force_wake_release(struct hif_opaque_softc *handle); 1266 #else 1267 static inline 1268 int hif_force_wake_request(struct hif_opaque_softc *handle) 1269 { 1270 return 0; 1271 } 1272 1273 static inline 1274 int hif_force_wake_release(struct hif_opaque_softc *handle) 1275 { 1276 return 0; 1277 } 1278 #endif /* FORCE_WAKE */ 1279 1280 #ifdef FEATURE_HAL_DELAYED_REG_WRITE 1281 /** 1282 * hif_prevent_link_low_power_states() - Prevent from going to low power states 1283 * @hif - HIF opaque context 1284 * 1285 * Return: 0 on success. Error code on failure. 1286 */ 1287 int hif_prevent_link_low_power_states(struct hif_opaque_softc *hif); 1288 1289 /** 1290 * hif_allow_link_low_power_states() - Allow link to go to low power states 1291 * @hif - HIF opaque context 1292 * 1293 * Return: None 1294 */ 1295 void hif_allow_link_low_power_states(struct hif_opaque_softc *hif); 1296 1297 #else 1298 1299 static inline 1300 int hif_prevent_link_low_power_states(struct hif_opaque_softc *hif) 1301 { 1302 return 0; 1303 } 1304 1305 static inline 1306 void hif_allow_link_low_power_states(struct hif_opaque_softc *hif) 1307 { 1308 } 1309 #endif 1310 1311 void *hif_get_dev_ba(struct hif_opaque_softc *hif_handle); 1312 void *hif_get_dev_ba_ce(struct hif_opaque_softc *hif_handle); 1313 1314 /** 1315 * hif_set_initial_wakeup_cb() - set the initial wakeup event handler function 1316 * @hif_ctx - the HIF context to assign the callback to 1317 * @callback - the callback to assign 1318 * @priv - the private data to pass to the callback when invoked 1319 * 1320 * Return: None 1321 */ 1322 void hif_set_initial_wakeup_cb(struct hif_opaque_softc *hif_ctx, 1323 void (*callback)(void *), 1324 void *priv); 1325 /* 1326 * Note: For MCL, #if defined (HIF_CONFIG_SLUB_DEBUG_ON) needs to be checked 1327 * for defined here 1328 */ 1329 #if defined(HIF_CONFIG_SLUB_DEBUG_ON) || defined(HIF_CE_DEBUG_DATA_BUF) 1330 ssize_t hif_dump_desc_trace_buf(struct device *dev, 1331 struct device_attribute *attr, char *buf); 1332 ssize_t hif_input_desc_trace_buf_index(struct hif_softc *scn, 1333 const char *buf, size_t size); 1334 ssize_t hif_ce_en_desc_hist(struct hif_softc *scn, 1335 const char *buf, size_t size); 1336 ssize_t hif_disp_ce_enable_desc_data_hist(struct hif_softc *scn, char *buf); 1337 ssize_t hif_dump_desc_event(struct hif_softc *scn, char *buf); 1338 #endif/*#if defined(HIF_CONFIG_SLUB_DEBUG_ON)||defined(HIF_CE_DEBUG_DATA_BUF)*/ 1339 1340 /** 1341 * hif_set_ce_service_max_yield_time() - sets CE service max yield time 1342 * @hif: hif context 1343 * @ce_service_max_yield_time: CE service max yield time to set 1344 * 1345 * This API storess CE service max yield time in hif context based 1346 * on ini value. 1347 * 1348 * Return: void 1349 */ 1350 void hif_set_ce_service_max_yield_time(struct hif_opaque_softc *hif, 1351 uint32_t ce_service_max_yield_time); 1352 1353 /** 1354 * hif_get_ce_service_max_yield_time() - get CE service max yield time 1355 * @hif: hif context 1356 * 1357 * This API returns CE service max yield time. 1358 * 1359 * Return: CE service max yield time 1360 */ 1361 unsigned long long 1362 hif_get_ce_service_max_yield_time(struct hif_opaque_softc *hif); 1363 1364 /** 1365 * hif_set_ce_service_max_rx_ind_flush() - sets CE service max rx ind flush 1366 * @hif: hif context 1367 * @ce_service_max_rx_ind_flush: CE service max rx ind flush to set 1368 * 1369 * This API stores CE service max rx ind flush in hif context based 1370 * on ini value. 1371 * 1372 * Return: void 1373 */ 1374 void hif_set_ce_service_max_rx_ind_flush(struct hif_opaque_softc *hif, 1375 uint8_t ce_service_max_rx_ind_flush); 1376 1377 #ifdef OL_ATH_SMART_LOGGING 1378 /* 1379 * hif_log_ce_dump() - Copy all the CE DEST ring to buf 1380 * @scn : HIF handler 1381 * @buf_cur: Current pointer in ring buffer 1382 * @buf_init:Start of the ring buffer 1383 * @buf_sz: Size of the ring buffer 1384 * @ce: Copy Engine id 1385 * @skb_sz: Max size of the SKB buffer to be copied 1386 * 1387 * Calls the respective function to dump all the CE SRC/DEST ring descriptors 1388 * and buffers pointed by them in to the given buf 1389 * 1390 * Return: Current pointer in ring buffer 1391 */ 1392 uint8_t *hif_log_dump_ce(struct hif_softc *scn, uint8_t *buf_cur, 1393 uint8_t *buf_init, uint32_t buf_sz, 1394 uint32_t ce, uint32_t skb_sz); 1395 #endif /* OL_ATH_SMART_LOGGING */ 1396 1397 /* 1398 * hif_softc_to_hif_opaque_softc - API to convert hif_softc handle 1399 * to hif_opaque_softc handle 1400 * @hif_handle - hif_softc type 1401 * 1402 * Return: hif_opaque_softc type 1403 */ 1404 static inline struct hif_opaque_softc * 1405 hif_softc_to_hif_opaque_softc(struct hif_softc *hif_handle) 1406 { 1407 return (struct hif_opaque_softc *)hif_handle; 1408 } 1409 1410 #ifdef FORCE_WAKE 1411 /** 1412 * hif_srng_init_phase(): Indicate srng initialization phase 1413 * to avoid force wake as UMAC power collapse is not yet 1414 * enabled 1415 * @hif_ctx: hif opaque handle 1416 * @init_phase: initialization phase 1417 * 1418 * Return: None 1419 */ 1420 void hif_srng_init_phase(struct hif_opaque_softc *hif_ctx, 1421 bool init_phase); 1422 #else 1423 static inline 1424 void hif_srng_init_phase(struct hif_opaque_softc *hif_ctx, 1425 bool init_phase) 1426 { 1427 } 1428 #endif /* FORCE_WAKE */ 1429 1430 #ifdef HIF_CE_LOG_INFO 1431 /** 1432 * hif_log_ce_info() - API to log ce info 1433 * @scn: hif handle 1434 * @data: hang event data buffer 1435 * @offset: offset at which data needs to be written 1436 * 1437 * Return: None 1438 */ 1439 void hif_log_ce_info(struct hif_softc *scn, uint8_t *data, 1440 unsigned int *offset); 1441 #else 1442 static inline 1443 void hif_log_ce_info(struct hif_softc *scn, uint8_t *data, 1444 unsigned int *offset) 1445 { 1446 } 1447 #endif 1448 1449 #ifdef HIF_CPU_PERF_AFFINE_MASK 1450 /** 1451 * hif_config_irq_set_perf_affinity_hint() - API to set affinity 1452 * @hif_ctx: hif opaque handle 1453 * 1454 * This function is used to move the WLAN IRQs to perf cores in 1455 * case of defconfig builds. 1456 * 1457 * Return: None 1458 */ 1459 void hif_config_irq_set_perf_affinity_hint( 1460 struct hif_opaque_softc *hif_ctx); 1461 1462 #else 1463 static inline void hif_config_irq_set_perf_affinity_hint( 1464 struct hif_opaque_softc *hif_ctx) 1465 { 1466 } 1467 #endif 1468 #endif /* _HIF_H_ */ 1469