1 /* 2 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include "qdf_types.h" 21 #include "qdf_util.h" 22 #include "qdf_types.h" 23 #include "qdf_lock.h" 24 #include "qdf_mem.h" 25 #include "qdf_nbuf.h" 26 #include "hal_internal.h" 27 #include "hal_api.h" 28 #include "target_type.h" 29 #include "wcss_version.h" 30 #include "qdf_module.h" 31 #include "hal_flow.h" 32 #include "rx_flow_search_entry.h" 33 #include "hal_rx_flow_info.h" 34 35 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 36 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET 37 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 38 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK 39 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 40 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB 41 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 42 PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 43 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 44 PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 45 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 46 PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 47 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 48 PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 49 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 50 PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 51 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 52 PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 53 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 54 PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 55 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 56 PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 57 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 58 PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 59 60 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 61 PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET 62 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 63 PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 64 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 65 RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 66 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 67 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 68 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 69 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 70 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 71 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 72 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 73 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 74 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 75 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER 76 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 77 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 78 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 79 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 80 81 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 82 TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 83 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 84 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 85 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 86 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 87 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 88 TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 89 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 90 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 91 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 92 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 93 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 94 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 95 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 96 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 97 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 98 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 99 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 100 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 101 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 102 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 103 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 104 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 105 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 106 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 107 108 #include "hal_wcn6450_tx.h" 109 #include "hal_wcn6450_rx.h" 110 #include <hal_generic_api.h> 111 #include "hal_rh_rx.h" 112 #include "hal_rh_api.h" 113 #include "hal_api_mon.h" 114 #include "hal_rh_generic_api.h" 115 116 struct hal_hw_srng_config hw_srng_table_wcn6450[] = { 117 /* TODO: max_rings can populated by querying HW capabilities */ 118 {/* REO_DST */ 0}, 119 {/* REO_EXCEPTION */ 0}, 120 {/* REO_REINJECT */ 0}, 121 {/* REO_CMD */ 0}, 122 {/* REO_STATUS */ 0}, 123 {/* TCL_DATA */ 0}, 124 {/* TCL_CMD */ 0}, 125 {/* TCL_STATUS */ 0}, 126 {/* CE_SRC */ 0}, 127 {/* CE_DST */ 0}, 128 {/* CE_DST_STATUS */ 0}, 129 {/* WBM_IDLE_LINK */ 0}, 130 {/* SW2WBM_RELEASE */ 0}, 131 {/* WBM2SW_RELEASE */ 0}, 132 { /* RXDMA_BUF */ 133 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 134 #ifdef IPA_OFFLOAD 135 .max_rings = 3, 136 #else 137 .max_rings = 2, 138 #endif 139 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 140 .lmac_ring = TRUE, 141 .ring_dir = HAL_SRNG_SRC_RING, 142 /* reg_start is not set because LMAC rings are not accessed 143 * from host 144 */ 145 .reg_start = {}, 146 .reg_size = {}, 147 .max_size = HAL_RXDMA_MAX_RING_SIZE, 148 }, 149 { /* RXDMA_DST */ 150 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 151 .max_rings = 1, 152 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 153 .lmac_ring = TRUE, 154 .ring_dir = HAL_SRNG_DST_RING, 155 /* reg_start is not set because LMAC rings are not accessed 156 * from host 157 */ 158 .reg_start = {}, 159 .reg_size = {}, 160 .max_size = HAL_RXDMA_MAX_RING_SIZE, 161 }, 162 {/* RXDMA_MONITOR_BUF */ 0}, 163 { /* RXDMA_MONITOR_STATUS */ 164 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 165 .max_rings = 1, 166 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 167 .lmac_ring = TRUE, 168 .ring_dir = HAL_SRNG_SRC_RING, 169 /* reg_start is not set because LMAC rings are not accessed 170 * from host 171 */ 172 .reg_start = {}, 173 .reg_size = {}, 174 .max_size = HAL_RXDMA_MAX_RING_SIZE, 175 }, 176 {/* RXDMA_MONITOR_DST */ 0}, 177 {/* RXDMA_MONITOR_DESC */ 0}, 178 {/* DIR_BUF_RX_DMA_SRC */ 179 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 180 /* 181 * one ring is for spectral scan 182 * the other is for cfr 183 */ 184 .max_rings = 2, 185 .entry_size = 2, 186 .lmac_ring = TRUE, 187 .ring_dir = HAL_SRNG_SRC_RING, 188 /* reg_start is not set because LMAC rings are not accessed 189 * from host 190 */ 191 .reg_start = {}, 192 .reg_size = {}, 193 .max_size = HAL_RXDMA_MAX_RING_SIZE, 194 }, 195 #ifdef WLAN_FEATURE_CIF_CFR 196 {/* WIFI_POS_SRC */ 197 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 198 .max_rings = 1, 199 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 200 .lmac_ring = TRUE, 201 .ring_dir = HAL_SRNG_SRC_RING, 202 /* reg_start is not set because LMAC rings are not accessed 203 * from host 204 */ 205 .reg_start = {}, 206 .reg_size = {}, 207 .max_size = HAL_RXDMA_MAX_RING_SIZE, 208 }, 209 #endif 210 { /* REO2PPE */ 0}, 211 { /* PPE2TCL */ 0}, 212 { /* PPE_RELEASE */ 0}, 213 { /* TX_MONITOR_BUF */ 0}, 214 { /* TX_MONITOR_DST */ 0}, 215 { /* SW2RXDMA_NEW */ 0}, 216 { /* SW2RXDMA_LINK_RELEASE */ 217 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA_LINK_RING, 218 .max_rings = 1, 219 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 220 .lmac_ring = TRUE, 221 .ring_dir = HAL_SRNG_SRC_RING, 222 /* reg_start is not set because LMAC rings are not accessed 223 * from host 224 */ 225 .reg_start = {}, 226 .reg_size = {}, 227 .max_size = HAL_RXDMA_MAX_RING_SIZE, 228 }, 229 230 }; 231 232 static void hal_get_hw_hptp_6450(struct hal_soc *hal_soc, 233 hal_ring_handle_t hal_ring_hdl, 234 uint32_t *headp, uint32_t *tailp, 235 uint8_t ring) 236 { 237 } 238 239 static void hal_reo_setup_6450(struct hal_soc *soc, void *reoparams, 240 int qref_reset) 241 { 242 } 243 244 static void hal_reo_set_err_dst_remap_6450(void *hal_soc) 245 { 246 } 247 248 static void hal_tx_desc_set_dscp_tid_table_id_6450(void *desc, uint8_t id) 249 { 250 } 251 252 static void hal_tx_set_dscp_tid_map_6450(struct hal_soc *hal_soc, 253 uint8_t *map, uint8_t id) 254 { 255 } 256 257 static void hal_tx_update_dscp_tid_6450(struct hal_soc *hal_soc, uint8_t tid, 258 uint8_t id, uint8_t dscp) 259 { 260 } 261 262 static uint8_t hal_tx_comp_get_release_reason_6450(void *hal_desc) 263 { 264 return 0; 265 } 266 267 static uint8_t hal_get_wbm_internal_error_6450(void *hal_desc) 268 { 269 return 0; 270 } 271 272 static void hal_tx_init_cmd_credit_ring_6450(hal_soc_handle_t hal_soc_hdl, 273 hal_ring_handle_t hal_ring_hdl) 274 { 275 } 276 277 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 278 static uint32_t hal_get_link_desc_size_6450(void) 279 { 280 return LINK_DESC_SIZE; 281 } 282 283 static void hal_reo_status_get_header_6450(hal_ring_desc_t ring_desc, 284 int b, void *h1) 285 { 286 } 287 288 static void hal_rx_wbm_err_info_get_6450(void *wbm_desc, 289 void *wbm_er_info1) 290 { 291 } 292 293 static bool hal_rx_is_unicast_6450(uint8_t *buf) 294 { 295 return true; 296 } 297 298 static uint32_t hal_rx_tid_get_6450(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 299 { 300 return 0; 301 } 302 303 static void *hal_rx_msdu0_buffer_addr_lsb_6450(void *link_desc_va) 304 { 305 return NULL; 306 } 307 308 static void *hal_rx_msdu_desc_info_ptr_get_6450(void *msdu0) 309 { 310 return NULL; 311 } 312 313 static void *hal_ent_mpdu_desc_info_6450(void *ent_ring_desc) 314 { 315 return NULL; 316 } 317 318 static void *hal_dst_mpdu_desc_info_6450(void *dst_ring_desc) 319 { 320 return NULL; 321 } 322 323 static uint8_t hal_rx_get_fc_valid_6450(uint8_t *buf) 324 { 325 return HAL_RX_GET_FC_VALID(buf); 326 } 327 328 static uint8_t hal_rx_get_to_ds_flag_6450(uint8_t *buf) 329 { 330 return HAL_RX_GET_TO_DS_FLAG(buf); 331 } 332 333 static uint8_t hal_rx_get_mac_addr2_valid_6450(uint8_t *buf) 334 { 335 return HAL_RX_GET_MAC_ADDR2_VALID(buf); 336 } 337 338 static uint8_t hal_rx_get_filter_category_6450(uint8_t *buf) 339 { 340 return HAL_RX_GET_FILTER_CATEGORY(buf); 341 } 342 343 static void hal_reo_config_6450(struct hal_soc *soc, 344 uint32_t reg_val, 345 struct hal_reo_params *reo_params) 346 { 347 } 348 349 /** 350 * hal_rx_msdu_flow_idx_get_6450: API to get flow index 351 * from rx_msdu_end TLV 352 * @buf: pointer to the start of RX PKT TLV headers 353 * 354 * Return: flow index value from MSDU END TLV 355 */ 356 static inline uint32_t hal_rx_msdu_flow_idx_get_6450(uint8_t *buf) 357 { 358 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 359 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 360 361 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 362 } 363 364 static void hal_compute_reo_remap_ix2_ix3_6450(uint32_t *ring, 365 uint32_t num_rings, 366 uint32_t *remap1, 367 uint32_t *remap2) 368 { 369 } 370 371 static void 372 hal_setup_link_idle_list_6450(struct hal_soc *soc, 373 qdf_dma_addr_t scatter_bufs_base_paddr[], 374 void *scatter_bufs_base_vaddr[], 375 uint32_t num_scatter_bufs, 376 uint32_t scatter_buf_size, 377 uint32_t last_buf_end_offset, 378 uint32_t num_entries) 379 { 380 } 381 382 static void hal_compute_reo_remap_ix0_6450(uint32_t *remap0) 383 { 384 } 385 386 #define UMAC_WINDOW_REMAP_RANGE 0x14 387 #define CE_WINDOW_REMAP_RANGE 0X37 388 #define CMEM_WINDOW_REMAP_RANGE 0x2 389 390 /** 391 * hal_get_window_address_6450(): Function to get the ioremap address 392 * @hal_soc: Pointer to hal_soc 393 * @addr: address offset of register 394 * 395 * Return: modified address offset of register 396 */ 397 static inline qdf_iomem_t hal_get_window_address_6450(struct hal_soc *hal_soc, 398 qdf_iomem_t addr) 399 { 400 uint32_t offset; 401 uint32_t window; 402 uint8_t scale; 403 404 offset = addr - hal_soc->dev_base_addr; 405 window = (offset >> WINDOW_SHIFT) & WINDOW_VALUE_MASK; 406 407 /* UMAC: 2nd window(unused) CE: 3rd window, CMEM: 4th window */ 408 switch (window) { 409 case UMAC_WINDOW_REMAP_RANGE: 410 scale = 1; 411 break; 412 case CE_WINDOW_REMAP_RANGE: 413 scale = 2; 414 break; 415 case CMEM_WINDOW_REMAP_RANGE: 416 scale = 3; 417 break; 418 default: 419 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 420 "%s: ERROR: Accessing Wrong register\n", __func__); 421 qdf_assert_always(0); 422 return 0; 423 } 424 425 return hal_soc->dev_base_addr + (scale * WINDOW_START) + 426 (offset & WINDOW_RANGE_MASK); 427 } 428 429 /* 430 * hal_rx_msdu_start_nss_get_6450(): API to get the NSS 431 * Interval from rx_msdu_start 432 * 433 * @buf: pointer to the start of RX PKT TLV header 434 * Return: uint32_t(nss) 435 */ 436 static uint32_t hal_rx_msdu_start_nss_get_6450(uint8_t *buf) 437 { 438 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 439 struct rx_msdu_start *msdu_start = 440 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 441 uint8_t mimo_ss_bitmap; 442 443 mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start); 444 445 return qdf_get_hweight8(mimo_ss_bitmap); 446 } 447 448 /** 449 * hal_rx_mon_hw_desc_get_mpdu_status_6450(): Retrieve MPDU status 450 * 451 * @hw_desc_addr: Start address of Rx HW TLVs 452 * @rs: Status for monitor mode 453 * 454 * Return: void 455 */ 456 static void hal_rx_mon_hw_desc_get_mpdu_status_6450(void *hw_desc_addr, 457 struct mon_rx_status *rs) 458 { 459 struct rx_msdu_start *rx_msdu_start; 460 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 461 uint32_t reg_value; 462 const uint32_t sgi_hw_to_cdp[] = { 463 CDP_SGI_0_8_US, 464 CDP_SGI_0_4_US, 465 CDP_SGI_1_6_US, 466 CDP_SGI_3_2_US, 467 }; 468 469 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 470 471 HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs); 472 473 rs->ant_signal_db = HAL_RX_GET(rx_msdu_start, 474 RX_MSDU_START_5, USER_RSSI); 475 rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC); 476 477 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI); 478 rs->sgi = sgi_hw_to_cdp[reg_value]; 479 480 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE); 481 rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0; 482 /* TODO: rs->beamformed should be set for SU beamforming also */ 483 } 484 485 /* 486 * hal_rx_get_tlv_6450(): API to get the tlv 487 * 488 * @rx_tlv: TLV data extracted from the rx packet 489 * Return: uint8_t 490 */ 491 static uint8_t hal_rx_get_tlv_6450(void *rx_tlv) 492 { 493 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH); 494 } 495 496 /** 497 * hal_rx_proc_phyrx_other_receive_info_tlv_6450() 498 * - process other receive info TLV 499 * @rx_tlv_hdr: pointer to TLV header 500 * @ppdu_info_handle: pointer to ppdu_info 501 * 502 * Return: None 503 */ 504 static 505 void hal_rx_proc_phyrx_other_receive_info_tlv_6450(void *rx_tlv_hdr, 506 void *ppdu_info_handle) 507 { 508 uint32_t tlv_tag, tlv_len; 509 uint32_t temp_len, other_tlv_len, other_tlv_tag; 510 void *rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 511 void *other_tlv_hdr = NULL; 512 void *other_tlv = NULL; 513 514 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 515 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 516 temp_len = 0; 517 518 other_tlv_hdr = rx_tlv + HAL_RX_TLV32_HDR_SIZE; 519 520 other_tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(other_tlv_hdr); 521 other_tlv_len = HAL_RX_GET_USER_TLV32_LEN(other_tlv_hdr); 522 temp_len += other_tlv_len; 523 other_tlv = other_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 524 525 switch (other_tlv_tag) { 526 default: 527 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 528 "%s unhandled TLV type: %d, TLV len:%d", 529 __func__, other_tlv_tag, other_tlv_len); 530 break; 531 } 532 } 533 534 /** 535 * hal_rx_dump_msdu_start_tlv_6450() : dump RX msdu_start TLV in structured 536 * human readable format. 537 * @msdustart: pointer the msdu_start TLV in pkt. 538 * @dbg_level: log level. 539 * 540 * Return: void 541 */ 542 static void hal_rx_dump_msdu_start_tlv_6450(void *msdustart, uint8_t dbg_level) 543 { 544 struct rx_msdu_start *msdu_start = (struct rx_msdu_start *)msdustart; 545 546 hal_verbose_debug( 547 "rx_msdu_start tlv (1/2) - " 548 "rxpcu_mpdu_filter_in_category: %x " 549 "sw_frame_group_id: %x " 550 "phy_ppdu_id: %x " 551 "msdu_length: %x " 552 "ipsec_esp: %x " 553 "l3_offset: %x " 554 "ipsec_ah: %x " 555 "l4_offset: %x " 556 "msdu_number: %x " 557 "decap_format: %x " 558 "ipv4_proto: %x " 559 "ipv6_proto: %x " 560 "tcp_proto: %x " 561 "udp_proto: %x " 562 "ip_frag: %x " 563 "tcp_only_ack: %x " 564 "da_is_bcast_mcast: %x " 565 "ip4_protocol_ip6_next_header: %x " 566 "toeplitz_hash_2_or_4: %x " 567 "flow_id_toeplitz: %x " 568 "user_rssi: %x " 569 "pkt_type: %x " 570 "stbc: %x " 571 "sgi: %x " 572 "rate_mcs: %x " 573 "receive_bandwidth: %x " 574 "reception_type: %x " 575 "ppdu_start_timestamp: %u ", 576 msdu_start->rxpcu_mpdu_filter_in_category, 577 msdu_start->sw_frame_group_id, 578 msdu_start->phy_ppdu_id, 579 msdu_start->msdu_length, 580 msdu_start->ipsec_esp, 581 msdu_start->l3_offset, 582 msdu_start->ipsec_ah, 583 msdu_start->l4_offset, 584 msdu_start->msdu_number, 585 msdu_start->decap_format, 586 msdu_start->ipv4_proto, 587 msdu_start->ipv6_proto, 588 msdu_start->tcp_proto, 589 msdu_start->udp_proto, 590 msdu_start->ip_frag, 591 msdu_start->tcp_only_ack, 592 msdu_start->da_is_bcast_mcast, 593 msdu_start->ip4_protocol_ip6_next_header, 594 msdu_start->toeplitz_hash_2_or_4, 595 msdu_start->flow_id_toeplitz, 596 msdu_start->user_rssi, 597 msdu_start->pkt_type, 598 msdu_start->stbc, 599 msdu_start->sgi, 600 msdu_start->rate_mcs, 601 msdu_start->receive_bandwidth, 602 msdu_start->reception_type, 603 msdu_start->ppdu_start_timestamp); 604 605 hal_verbose_debug( 606 "rx_msdu_start tlv (2/2) - " 607 "sw_phy_meta_data: %x ", 608 msdu_start->sw_phy_meta_data); 609 } 610 611 /** 612 * hal_rx_dump_msdu_end_tlv_6450: dump RX msdu_end TLV in structured 613 * human readable format. 614 * @msduend: pointer the msdu_end TLV in pkt. 615 * @dbg_level: log level. 616 * 617 * Return: void 618 */ 619 static void hal_rx_dump_msdu_end_tlv_6450(void *msduend, 620 uint8_t dbg_level) 621 { 622 struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend; 623 624 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_DP, 625 "rx_msdu_end tlv (1/3) - " 626 "rxpcu_mpdu_filter_in_category: %x " 627 "sw_frame_group_id: %x " 628 "phy_ppdu_id: %x " 629 "ip_hdr_chksum: %x " 630 "tcp_udp_chksum: %x " 631 "key_id_octet: %x " 632 "cce_super_rule: %x " 633 "cce_classify_not_done_truncat: %x " 634 "cce_classify_not_done_cce_dis: %x " 635 "reported_mpdu_length: %x " 636 "first_msdu: %x " 637 "last_msdu: %x " 638 "sa_idx_timeout: %x " 639 "da_idx_timeout: %x " 640 "msdu_limit_error: %x " 641 "flow_idx_timeout: %x " 642 "flow_idx_invalid: %x " 643 "wifi_parser_error: %x " 644 "amsdu_parser_error: %x", 645 msdu_end->rxpcu_mpdu_filter_in_category, 646 msdu_end->sw_frame_group_id, 647 msdu_end->phy_ppdu_id, 648 msdu_end->ip_hdr_chksum, 649 msdu_end->tcp_udp_chksum, 650 msdu_end->key_id_octet, 651 msdu_end->cce_super_rule, 652 msdu_end->cce_classify_not_done_truncate, 653 msdu_end->cce_classify_not_done_cce_dis, 654 msdu_end->reported_mpdu_length, 655 msdu_end->first_msdu, 656 msdu_end->last_msdu, 657 msdu_end->sa_idx_timeout, 658 msdu_end->da_idx_timeout, 659 msdu_end->msdu_limit_error, 660 msdu_end->flow_idx_timeout, 661 msdu_end->flow_idx_invalid, 662 msdu_end->wifi_parser_error, 663 msdu_end->amsdu_parser_error); 664 665 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_DP, 666 "rx_msdu_end tlv (2/3)- " 667 "sa_is_valid: %x " 668 "da_is_valid: %x " 669 "da_is_mcbc: %x " 670 "l3_header_padding: %x " 671 "ipv6_options_crc: %x " 672 "tcp_seq_number: %x " 673 "tcp_ack_number: %x " 674 "tcp_flag: %x " 675 "lro_eligible: %x " 676 "window_size: %x " 677 "da_offset: %x " 678 "sa_offset: %x " 679 "da_offset_valid: %x " 680 "sa_offset_valid: %x " 681 "rule_indication_31_0: %x " 682 "rule_indication_63_32: %x " 683 "sa_idx: %x " 684 "da_idx: %x " 685 "msdu_drop: %x " 686 "reo_destination_indication: %x " 687 "flow_idx: %x " 688 "fse_metadata: %x " 689 "cce_metadata: %x " 690 "sa_sw_peer_id: %x ", 691 msdu_end->sa_is_valid, 692 msdu_end->da_is_valid, 693 msdu_end->da_is_mcbc, 694 msdu_end->l3_header_padding, 695 msdu_end->ipv6_options_crc, 696 msdu_end->tcp_seq_number, 697 msdu_end->tcp_ack_number, 698 msdu_end->tcp_flag, 699 msdu_end->lro_eligible, 700 msdu_end->window_size, 701 msdu_end->da_offset, 702 msdu_end->sa_offset, 703 msdu_end->da_offset_valid, 704 msdu_end->sa_offset_valid, 705 msdu_end->rule_indication_31_0, 706 msdu_end->rule_indication_63_32, 707 msdu_end->sa_idx, 708 msdu_end->da_idx_or_sw_peer_id, 709 msdu_end->msdu_drop, 710 msdu_end->reo_destination_indication, 711 msdu_end->flow_idx, 712 msdu_end->fse_metadata, 713 msdu_end->cce_metadata, 714 msdu_end->sa_sw_peer_id); 715 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_DP, 716 "rx_msdu_end tlv (3/3)" 717 "aggregation_count %x " 718 "flow_aggregation_continuation %x " 719 "fisa_timeout %x " 720 "cumulative_l4_checksum %x " 721 "cumulative_ip_length %x", 722 msdu_end->aggregation_count, 723 msdu_end->flow_aggregation_continuation, 724 msdu_end->fisa_timeout, 725 msdu_end->cumulative_l4_checksum, 726 msdu_end->cumulative_ip_length); 727 } 728 729 /* 730 * Get tid from RX_MPDU_START 731 */ 732 #define HAL_RX_MPDU_INFO_TID_GET(_rx_mpdu_info) \ 733 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 734 RX_MPDU_INFO_7_TID_OFFSET)), \ 735 RX_MPDU_INFO_7_TID_MASK, \ 736 RX_MPDU_INFO_7_TID_LSB)) 737 738 static uint32_t hal_rx_mpdu_start_tid_get_6450(uint8_t *buf) 739 { 740 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 741 struct rx_mpdu_start *mpdu_start = 742 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 743 uint32_t tid; 744 745 tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details); 746 747 return tid; 748 } 749 750 #define HAL_RX_MSDU_START_RECEPTION_TYPE_GET(_rx_msdu_start) \ 751 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \ 752 RX_MSDU_START_5_RECEPTION_TYPE_OFFSET)), \ 753 RX_MSDU_START_5_RECEPTION_TYPE_MASK, \ 754 RX_MSDU_START_5_RECEPTION_TYPE_LSB)) 755 756 /* 757 * hal_rx_msdu_start_reception_type_get(): API to get the reception type 758 * Interval from rx_msdu_start 759 * 760 * @buf: pointer to the start of RX PKT TLV header 761 * Return: uint32_t(reception_type) 762 */ 763 static 764 uint32_t hal_rx_msdu_start_reception_type_get_6450(uint8_t *buf) 765 { 766 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 767 struct rx_msdu_start *msdu_start = 768 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 769 uint32_t reception_type; 770 771 reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start); 772 773 return reception_type; 774 } 775 776 /** 777 * hal_rx_msdu_end_da_idx_get_6450: API to get da_idx 778 * from rx_msdu_end TLV 779 * 780 * @buf: pointer to the start of RX PKT TLV headers 781 * Return: da index 782 */ 783 static uint16_t hal_rx_msdu_end_da_idx_get_6450(uint8_t *buf) 784 { 785 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 786 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 787 uint16_t da_idx; 788 789 da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 790 791 return da_idx; 792 } 793 794 /** 795 * hal_rx_msdu_desc_info_get_ptr_6450() - Get msdu desc info ptr 796 * @msdu_details_ptr: Pointer to msdu_details_ptr 797 * 798 * Return - Pointer to rx_msdu_desc_info structure. 799 * 800 */ 801 static void *hal_rx_msdu_desc_info_get_ptr_6450(void *msdu_details_ptr) 802 { 803 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 804 } 805 806 /** 807 * hal_rx_link_desc_msdu0_ptr_6450 - Get pointer to rx_msdu details 808 * @link_desc: Pointer to link desc 809 * 810 * Return - Pointer to rx_msdu_details structure 811 * 812 */ 813 static void *hal_rx_link_desc_msdu0_ptr_6450(void *link_desc) 814 { 815 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 816 } 817 818 /** 819 * hal_rx_get_rx_fragment_number_6450(): Function to retrieve rx fragment number 820 * 821 * @buf: Network buffer 822 * Returns: rx fragment number 823 */ 824 static 825 uint8_t hal_rx_get_rx_fragment_number_6450(uint8_t *buf) 826 { 827 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 828 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 829 830 /* Return first 4 bits as fragment number */ 831 return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & 832 DOT11_SEQ_FRAG_MASK); 833 } 834 835 /** 836 * hal_rx_msdu_end_da_is_mcbc_get_6450(): API to check if pkt is MCBC 837 * from rx_msdu_end TLV 838 * 839 * @buf: pointer to the start of RX PKT TLV headers 840 * Return: da_is_mcbc 841 */ 842 static uint8_t 843 hal_rx_msdu_end_da_is_mcbc_get_6450(uint8_t *buf) 844 { 845 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 846 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 847 848 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); 849 } 850 851 /** 852 * hal_rx_msdu_end_sa_is_valid_get_6450(): API to get_6450 the 853 * sa_is_valid bit from rx_msdu_end TLV 854 * 855 * @buf: pointer to the start of RX PKT TLV headers 856 * Return: sa_is_valid bit 857 */ 858 static uint8_t 859 hal_rx_msdu_end_sa_is_valid_get_6450(uint8_t *buf) 860 { 861 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 862 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 863 uint8_t sa_is_valid; 864 865 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); 866 867 return sa_is_valid; 868 } 869 870 /** 871 * hal_rx_msdu_end_sa_idx_get_6450(): API to get_6450 the 872 * sa_idx from rx_msdu_end TLV 873 * 874 * @buf: pointer to the start of RX PKT TLV headers 875 * Return: sa_idx (SA AST index) 876 */ 877 static 878 uint16_t hal_rx_msdu_end_sa_idx_get_6450(uint8_t *buf) 879 { 880 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 881 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 882 uint16_t sa_idx; 883 884 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 885 886 return sa_idx; 887 } 888 889 /** 890 * hal_rx_desc_is_first_msdu_6450() - Check if first msdu 891 * 892 * @hw_desc_addr: hardware descriptor address 893 * 894 * Return: 0 - success/ non-zero failure 895 */ 896 static uint32_t hal_rx_desc_is_first_msdu_6450(void *hw_desc_addr) 897 { 898 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; 899 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; 900 901 return HAL_RX_GET(msdu_end, RX_MSDU_END_10, FIRST_MSDU); 902 } 903 904 /** 905 * hal_rx_msdu_end_l3_hdr_padding_get_6450(): API to get_6450 the 906 * l3_header padding from rx_msdu_end TLV 907 * 908 * @buf: pointer to the start of RX PKT TLV headers 909 * Return: number of l3 header padding bytes 910 */ 911 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_6450(uint8_t *buf) 912 { 913 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 914 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 915 uint32_t l3_header_padding; 916 917 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 918 919 return l3_header_padding; 920 } 921 922 /* 923 * @ hal_rx_encryption_info_valid_6450: Returns encryption type. 924 * 925 * @ buf: rx_tlv_hdr of the received packet 926 * @ Return: encryption type 927 */ 928 static uint32_t hal_rx_encryption_info_valid_6450(uint8_t *buf) 929 { 930 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 931 struct rx_mpdu_start *mpdu_start = 932 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 933 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 934 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); 935 936 return encryption_info; 937 } 938 939 /* 940 * @ hal_rx_print_pn_6450: Prints the PN of rx packet. 941 * 942 * @ buf: rx_tlv_hdr of the received packet 943 * @ Return: void 944 */ 945 static void hal_rx_print_pn_6450(uint8_t *buf) 946 { 947 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 948 struct rx_mpdu_start *mpdu_start = 949 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 950 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 951 952 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); 953 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); 954 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); 955 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); 956 957 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x", 958 pn_127_96, pn_95_64, pn_63_32, pn_31_0); 959 } 960 961 /** 962 * hal_rx_msdu_end_first_msdu_get_6450: API to get first msdu status 963 * from rx_msdu_end TLV 964 * 965 * @buf: pointer to the start of RX PKT TLV headers 966 * Return: first_msdu 967 */ 968 static uint8_t hal_rx_msdu_end_first_msdu_get_6450(uint8_t *buf) 969 { 970 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 971 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 972 uint8_t first_msdu; 973 974 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); 975 976 return first_msdu; 977 } 978 979 /** 980 * hal_rx_msdu_end_da_is_valid_get_6450: API to check if da is valid 981 * from rx_msdu_end TLV 982 * 983 * @buf: pointer to the start of RX PKT TLV headers 984 * Return: da_is_valid 985 */ 986 static uint8_t hal_rx_msdu_end_da_is_valid_get_6450(uint8_t *buf) 987 { 988 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 989 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 990 uint8_t da_is_valid; 991 992 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); 993 994 return da_is_valid; 995 } 996 997 /** 998 * hal_rx_msdu_end_last_msdu_get_6450: API to get last msdu status 999 * from rx_msdu_end TLV 1000 * 1001 * @buf: pointer to the start of RX PKT TLV headers 1002 * Return: last_msdu 1003 */ 1004 static uint8_t hal_rx_msdu_end_last_msdu_get_6450(uint8_t *buf) 1005 { 1006 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1007 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1008 uint8_t last_msdu; 1009 1010 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); 1011 1012 return last_msdu; 1013 } 1014 1015 /* 1016 * hal_rx_get_mpdu_mac_ad4_valid_6450(): Retrieves if mpdu 4th addr is valid 1017 * 1018 * @nbuf: Network buffer 1019 * Returns: value of mpdu 4th address valid field 1020 */ 1021 static bool hal_rx_get_mpdu_mac_ad4_valid_6450(uint8_t *buf) 1022 { 1023 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 1024 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 1025 bool ad4_valid = 0; 1026 1027 ad4_valid = HAL_RX_MPDU_GET_MAC_AD4_VALID(rx_mpdu_info); 1028 1029 return ad4_valid; 1030 } 1031 1032 /** 1033 * hal_rx_mpdu_start_sw_peer_id_get_6450: Retrieve sw peer_id 1034 * @buf: network buffer 1035 * 1036 * Return: sw peer_id 1037 */ 1038 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_6450(uint8_t *buf) 1039 { 1040 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1041 struct rx_mpdu_start *mpdu_start = 1042 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1043 1044 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET( 1045 &mpdu_start->rx_mpdu_info_details); 1046 } 1047 1048 /** 1049 * hal_rx_mpdu_get_to_ds_6450(): API to get the tods info 1050 * from rx_mpdu_start 1051 * 1052 * @buf: pointer to the start of RX PKT TLV header 1053 * Return: uint32_t(to_ds) 1054 */ 1055 static uint32_t hal_rx_mpdu_get_to_ds_6450(uint8_t *buf) 1056 { 1057 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1058 struct rx_mpdu_start *mpdu_start = 1059 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1060 1061 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 1062 1063 return HAL_RX_MPDU_GET_TODS(mpdu_info); 1064 } 1065 1066 /* 1067 * hal_rx_mpdu_get_fr_ds_6450(): API to get the from ds info 1068 * from rx_mpdu_start 1069 * 1070 * @buf: pointer to the start of RX PKT TLV header 1071 * Return: uint32_t(fr_ds) 1072 */ 1073 static uint32_t hal_rx_mpdu_get_fr_ds_6450(uint8_t *buf) 1074 { 1075 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1076 struct rx_mpdu_start *mpdu_start = 1077 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1078 1079 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 1080 1081 return HAL_RX_MPDU_GET_FROMDS(mpdu_info); 1082 } 1083 1084 /* 1085 * hal_rx_get_mpdu_frame_control_valid_6450(): Retrieves mpdu 1086 * frame control valid 1087 * 1088 * @nbuf: Network buffer 1089 * Returns: value of frame control valid field 1090 */ 1091 static uint8_t hal_rx_get_mpdu_frame_control_valid_6450(uint8_t *buf) 1092 { 1093 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 1094 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 1095 1096 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); 1097 } 1098 1099 /* 1100 * hal_rx_mpdu_get_addr1_6450(): API to check get address1 of the mpdu 1101 * 1102 * @buf: pointer to the start of RX PKT TLV headera 1103 * @mac_addr: pointer to mac address 1104 * Return: success/failure 1105 */ 1106 static QDF_STATUS hal_rx_mpdu_get_addr1_6450(uint8_t *buf, uint8_t *mac_addr) 1107 { 1108 struct __attribute__((__packed__)) hal_addr1 { 1109 uint32_t ad1_31_0; 1110 uint16_t ad1_47_32; 1111 }; 1112 1113 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1114 struct rx_mpdu_start *mpdu_start = 1115 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1116 1117 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 1118 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; 1119 uint32_t mac_addr_ad1_valid; 1120 1121 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); 1122 1123 if (mac_addr_ad1_valid) { 1124 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); 1125 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); 1126 return QDF_STATUS_SUCCESS; 1127 } 1128 1129 return QDF_STATUS_E_FAILURE; 1130 } 1131 1132 /* 1133 * hal_rx_mpdu_get_addr2_6450(): API to check get address2 of the mpdu 1134 * in the packet 1135 * 1136 * @buf: pointer to the start of RX PKT TLV header 1137 * @mac_addr: pointer to mac address 1138 * Return: success/failure 1139 */ 1140 static QDF_STATUS hal_rx_mpdu_get_addr2_6450(uint8_t *buf, 1141 uint8_t *mac_addr) 1142 { 1143 struct __attribute__((__packed__)) hal_addr2 { 1144 uint16_t ad2_15_0; 1145 uint32_t ad2_47_16; 1146 }; 1147 1148 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1149 struct rx_mpdu_start *mpdu_start = 1150 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1151 1152 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 1153 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; 1154 uint32_t mac_addr_ad2_valid; 1155 1156 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); 1157 1158 if (mac_addr_ad2_valid) { 1159 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); 1160 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); 1161 return QDF_STATUS_SUCCESS; 1162 } 1163 1164 return QDF_STATUS_E_FAILURE; 1165 } 1166 1167 /* 1168 * hal_rx_mpdu_get_addr3_6450(): API to get address3 of the mpdu 1169 * in the packet 1170 * 1171 * @buf: pointer to the start of RX PKT TLV header 1172 * @mac_addr: pointer to mac address 1173 * Return: success/failure 1174 */ 1175 static QDF_STATUS hal_rx_mpdu_get_addr3_6450(uint8_t *buf, uint8_t *mac_addr) 1176 { 1177 struct __attribute__((__packed__)) hal_addr3 { 1178 uint32_t ad3_31_0; 1179 uint16_t ad3_47_32; 1180 }; 1181 1182 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1183 struct rx_mpdu_start *mpdu_start = 1184 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1185 1186 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 1187 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; 1188 uint32_t mac_addr_ad3_valid; 1189 1190 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); 1191 1192 if (mac_addr_ad3_valid) { 1193 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); 1194 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); 1195 return QDF_STATUS_SUCCESS; 1196 } 1197 1198 return QDF_STATUS_E_FAILURE; 1199 } 1200 1201 /* 1202 * hal_rx_mpdu_get_addr4_6450(): API to get address4 of the mpdu 1203 * in the packet 1204 * 1205 * @buf: pointer to the start of RX PKT TLV header 1206 * @mac_addr: pointer to mac address 1207 * Return: success/failure 1208 */ 1209 static QDF_STATUS hal_rx_mpdu_get_addr4_6450(uint8_t *buf, uint8_t *mac_addr) 1210 { 1211 struct __attribute__((__packed__)) hal_addr4 { 1212 uint32_t ad4_31_0; 1213 uint16_t ad4_47_32; 1214 }; 1215 1216 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1217 struct rx_mpdu_start *mpdu_start = 1218 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1219 1220 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 1221 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; 1222 uint32_t mac_addr_ad4_valid; 1223 1224 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); 1225 1226 if (mac_addr_ad4_valid) { 1227 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); 1228 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); 1229 return QDF_STATUS_SUCCESS; 1230 } 1231 1232 return QDF_STATUS_E_FAILURE; 1233 } 1234 1235 /* 1236 * hal_rx_get_mpdu_sequence_control_valid_6450(): Get mpdu 1237 * sequence control valid 1238 * 1239 * @nbuf: Network buffer 1240 * Returns: value of sequence control valid field 1241 */ 1242 static uint8_t hal_rx_get_mpdu_sequence_control_valid_6450(uint8_t *buf) 1243 { 1244 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 1245 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 1246 1247 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); 1248 } 1249 1250 /** 1251 * hal_rx_hw_desc_get_ppduid_get_6450(): retrieve ppdu id 1252 * @rx_tlv_hdr: rx tlv header 1253 * @rxdma_dst_ring_desc: rxdma HW descriptor 1254 * 1255 * Return: ppdu id 1256 */ 1257 static uint32_t hal_rx_hw_desc_get_ppduid_get_6450(void *rx_tlv_hdr, 1258 void *rxdma_dst_ring_desc) 1259 { 1260 struct rx_mpdu_info *rx_mpdu_info; 1261 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 1262 1263 rx_mpdu_info = 1264 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 1265 1266 return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_9, PHY_PPDU_ID); 1267 } 1268 1269 static uint32_t 1270 hal_rx_get_ppdu_id_6450(uint8_t *buf) 1271 { 1272 return HAL_RX_GET_PPDU_ID(buf); 1273 } 1274 1275 /** 1276 * hal_rx_msdu_flow_idx_invalid_6450: API to get flow index invalid 1277 * from rx_msdu_end TLV 1278 * @buf: pointer to the start of RX PKT TLV headers 1279 * 1280 * Return: flow index invalid value from MSDU END TLV 1281 */ 1282 static bool hal_rx_msdu_flow_idx_invalid_6450(uint8_t *buf) 1283 { 1284 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1285 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1286 1287 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 1288 } 1289 1290 /** 1291 * hal_rx_msdu_flow_idx_timeout_6450: API to get flow index timeout 1292 * from rx_msdu_end TLV 1293 * @buf: pointer to the start of RX PKT TLV headers 1294 * 1295 * Return: flow index timeout value from MSDU END TLV 1296 */ 1297 static bool hal_rx_msdu_flow_idx_timeout_6450(uint8_t *buf) 1298 { 1299 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1300 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1301 1302 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 1303 } 1304 1305 /** 1306 * hal_rx_msdu_fse_metadata_get_6450: API to get FSE metadata 1307 * from rx_msdu_end TLV 1308 * @buf: pointer to the start of RX PKT TLV headers 1309 * 1310 * Return: fse metadata value from MSDU END TLV 1311 */ 1312 static uint32_t hal_rx_msdu_fse_metadata_get_6450(uint8_t *buf) 1313 { 1314 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1315 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1316 1317 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end); 1318 } 1319 1320 /** 1321 * hal_rx_msdu_cce_metadata_get_6450: API to get CCE metadata 1322 * from rx_msdu_end TLV 1323 * @buf: pointer to the start of RX PKT TLV headers 1324 * 1325 * Return: cce_metadata 1326 */ 1327 static uint16_t 1328 hal_rx_msdu_cce_metadata_get_6450(uint8_t *buf) 1329 { 1330 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1331 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1332 1333 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end); 1334 } 1335 1336 /** 1337 * hal_rx_msdu_get_flow_params_6450: API to get flow index, flow index invalid 1338 * and flow index timeout from rx_msdu_end TLV 1339 * @buf: pointer to the start of RX PKT TLV headers 1340 * @flow_invalid: pointer to return value of flow_idx_valid 1341 * @flow_timeout: pointer to return value of flow_idx_timeout 1342 * @flow_index: pointer to return value of flow_idx 1343 * 1344 * Return: none 1345 */ 1346 static inline void 1347 hal_rx_msdu_get_flow_params_6450(uint8_t *buf, 1348 bool *flow_invalid, 1349 bool *flow_timeout, 1350 uint32_t *flow_index) 1351 { 1352 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1353 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1354 1355 *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 1356 *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 1357 *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 1358 } 1359 1360 /** 1361 * hal_rx_tlv_get_tcp_chksum_6450() - API to get tcp checksum 1362 * @buf: rx_tlv_hdr 1363 * 1364 * Return: tcp checksum 1365 */ 1366 static uint16_t 1367 hal_rx_tlv_get_tcp_chksum_6450(uint8_t *buf) 1368 { 1369 return HAL_RX_TLV_GET_TCP_CHKSUM(buf); 1370 } 1371 1372 /** 1373 * hal_rx_get_rx_sequence_6450(): Function to retrieve rx sequence number 1374 * 1375 * @buf: Network buffer 1376 * Returns: rx sequence number 1377 */ 1378 static 1379 uint16_t hal_rx_get_rx_sequence_6450(uint8_t *buf) 1380 { 1381 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 1382 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 1383 1384 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info); 1385 } 1386 1387 /** 1388 * hal_rx_get_fisa_cumulative_l4_checksum_6450() - Retrieve cumulative 1389 * checksum 1390 * @buf: buffer pointer 1391 * 1392 * Return: cumulative checksum 1393 */ 1394 static inline 1395 uint16_t hal_rx_get_fisa_cumulative_l4_checksum_6450(uint8_t *buf) 1396 { 1397 return HAL_RX_TLV_GET_FISA_CUMULATIVE_L4_CHECKSUM(buf); 1398 } 1399 1400 /** 1401 * hal_rx_get_fisa_cumulative_ip_length_6450() - Retrieve cumulative 1402 * ip length 1403 * @buf: buffer pointer 1404 * 1405 * Return: cumulative length 1406 */ 1407 static inline 1408 uint16_t hal_rx_get_fisa_cumulative_ip_length_6450(uint8_t *buf) 1409 { 1410 return HAL_RX_TLV_GET_FISA_CUMULATIVE_IP_LENGTH(buf); 1411 } 1412 1413 /** 1414 * hal_rx_get_udp_proto_6450() - Retrieve udp proto value 1415 * @buf: buffer 1416 * 1417 * Return: udp proto bit 1418 */ 1419 static inline 1420 bool hal_rx_get_udp_proto_6450(uint8_t *buf) 1421 { 1422 return HAL_RX_TLV_GET_UDP_PROTO(buf); 1423 } 1424 1425 /** 1426 * hal_rx_get_flow_agg_continuation_6450() - retrieve flow agg 1427 * continuation 1428 * @buf: buffer 1429 * 1430 * Return: flow agg 1431 */ 1432 static inline 1433 bool hal_rx_get_flow_agg_continuation_6450(uint8_t *buf) 1434 { 1435 return HAL_RX_TLV_GET_FLOW_AGGR_CONT(buf); 1436 } 1437 1438 /** 1439 * hal_rx_get_flow_agg_count_6450()- Retrieve flow agg count 1440 * @buf: buffer 1441 * 1442 * Return: flow agg count 1443 */ 1444 static inline 1445 uint8_t hal_rx_get_flow_agg_count_6450(uint8_t *buf) 1446 { 1447 return HAL_RX_TLV_GET_FLOW_AGGR_COUNT(buf); 1448 } 1449 1450 /** 1451 * hal_rx_get_fisa_timeout_6450() - Retrieve fisa timeout 1452 * @buf: buffer 1453 * 1454 * Return: fisa timeout 1455 */ 1456 static inline 1457 bool hal_rx_get_fisa_timeout_6450(uint8_t *buf) 1458 { 1459 return HAL_RX_TLV_GET_FISA_TIMEOUT(buf); 1460 } 1461 1462 /** 1463 * hal_rx_mpdu_start_tlv_tag_valid_6450 () - API to check if RX_MPDU_START 1464 * tlv tag is valid 1465 * 1466 *@rx_tlv_hdr: start address of rx_pkt_tlvs 1467 * 1468 * Return: true if RX_MPDU_START is valid, else false. 1469 */ 1470 static uint8_t hal_rx_mpdu_start_tlv_tag_valid_6450(void *rx_tlv_hdr) 1471 { 1472 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 1473 uint32_t tlv_tag; 1474 1475 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(&rx_desc->mpdu_start_tlv); 1476 1477 return tlv_tag == WIFIRX_MPDU_START_E ? true : false; 1478 } 1479 1480 /* 1481 * hal_rx_flow_setup_fse_6450() - Setup a flow search entry in HW FST 1482 * @fst: Pointer to the Rx Flow Search Table 1483 * @table_offset: offset into the table where the flow is to be setup 1484 * @flow: Flow Parameters 1485 * 1486 * Flow table entry fields are updated in host byte order, little endian order. 1487 * 1488 * Return: Success/Failure 1489 */ 1490 static void * 1491 hal_rx_flow_setup_fse_6450(uint8_t *rx_fst, uint32_t table_offset, 1492 uint8_t *rx_flow) 1493 { 1494 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 1495 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 1496 uint8_t *fse; 1497 bool fse_valid; 1498 1499 if (table_offset >= fst->max_entries) { 1500 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 1501 "HAL FSE table offset %u exceeds max entries %u", 1502 table_offset, fst->max_entries); 1503 return NULL; 1504 } 1505 1506 fse = (uint8_t *)fst->base_vaddr + 1507 (table_offset * HAL_RX_FST_ENTRY_SIZE); 1508 1509 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1510 1511 if (fse_valid) { 1512 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 1513 "HAL FSE %pK already valid", fse); 1514 return NULL; 1515 } 1516 1517 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96) = 1518 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96, 1519 (flow->tuple_info.src_ip_127_96)); 1520 1521 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64) = 1522 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64, 1523 (flow->tuple_info.src_ip_95_64)); 1524 1525 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32) = 1526 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32, 1527 (flow->tuple_info.src_ip_63_32)); 1528 1529 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0) = 1530 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0, 1531 (flow->tuple_info.src_ip_31_0)); 1532 1533 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96) = 1534 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96, 1535 (flow->tuple_info.dest_ip_127_96)); 1536 1537 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64) = 1538 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64, 1539 (flow->tuple_info.dest_ip_95_64)); 1540 1541 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32) = 1542 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32, 1543 (flow->tuple_info.dest_ip_63_32)); 1544 1545 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0) = 1546 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0, 1547 (flow->tuple_info.dest_ip_31_0)); 1548 1549 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT); 1550 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT) |= 1551 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, DEST_PORT, 1552 (flow->tuple_info.dest_port)); 1553 1554 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT); 1555 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT) |= 1556 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, SRC_PORT, 1557 (flow->tuple_info.src_port)); 1558 1559 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL); 1560 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL) |= 1561 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL, 1562 flow->tuple_info.l4_protocol); 1563 1564 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER); 1565 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER) |= 1566 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER, 1567 flow->reo_destination_handler); 1568 1569 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1570 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID) |= 1571 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, VALID, 1); 1572 1573 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA); 1574 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA) = 1575 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_10, METADATA, 1576 (flow->fse_metadata)); 1577 1578 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION); 1579 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION) |= 1580 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, 1581 REO_DESTINATION_INDICATION, 1582 flow->reo_destination_indication); 1583 1584 /* Reset all the other fields in FSE */ 1585 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, RESERVED_9); 1586 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, MSDU_DROP); 1587 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_COUNT); 1588 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_12, MSDU_BYTE_COUNT); 1589 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_13, TIMESTAMP); 1590 1591 return fse; 1592 } 1593 1594 /* 1595 * hal_rx_flow_setup_cmem_fse_6450() - Setup a flow search entry in HW CMEM FST 1596 * @hal_soc: hal_soc reference 1597 * @cmem_ba: CMEM base address 1598 * @table_offset: offset into the table where the flow is to be setup 1599 * @flow: Flow Parameters 1600 * 1601 * Return: Success/Failure 1602 */ 1603 static uint32_t 1604 hal_rx_flow_setup_cmem_fse_6450(struct hal_soc *hal_soc, uint32_t cmem_ba, 1605 uint32_t table_offset, uint8_t *rx_flow) 1606 { 1607 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 1608 uint32_t fse_offset; 1609 uint32_t value; 1610 1611 fse_offset = cmem_ba + (table_offset * HAL_RX_FST_ENTRY_SIZE); 1612 1613 /* Reset the Valid bit */ 1614 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_9, 1615 VALID), 0); 1616 1617 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96, 1618 (flow->tuple_info.src_ip_127_96)); 1619 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_0, 1620 SRC_IP_127_96), value); 1621 1622 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64, 1623 (flow->tuple_info.src_ip_95_64)); 1624 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_1, 1625 SRC_IP_95_64), value); 1626 1627 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32, 1628 (flow->tuple_info.src_ip_63_32)); 1629 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_2, 1630 SRC_IP_63_32), value); 1631 1632 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0, 1633 (flow->tuple_info.src_ip_31_0)); 1634 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_3, 1635 SRC_IP_31_0), value); 1636 1637 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96, 1638 (flow->tuple_info.dest_ip_127_96)); 1639 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_4, 1640 DEST_IP_127_96), value); 1641 1642 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64, 1643 (flow->tuple_info.dest_ip_95_64)); 1644 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_5, 1645 DEST_IP_95_64), value); 1646 1647 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32, 1648 (flow->tuple_info.dest_ip_63_32)); 1649 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_6, 1650 DEST_IP_63_32), value); 1651 1652 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0, 1653 (flow->tuple_info.dest_ip_31_0)); 1654 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_7, 1655 DEST_IP_31_0), value); 1656 1657 value = 0 | HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, DEST_PORT, 1658 (flow->tuple_info.dest_port)); 1659 value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, SRC_PORT, 1660 (flow->tuple_info.src_port)); 1661 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_8, 1662 SRC_PORT), value); 1663 1664 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_10, METADATA, 1665 (flow->fse_metadata)); 1666 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_10, 1667 METADATA), value); 1668 1669 /* Reset all the other fields in FSE */ 1670 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_11, 1671 MSDU_COUNT), 0); 1672 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_12, 1673 MSDU_BYTE_COUNT), 0); 1674 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_13, 1675 TIMESTAMP), 0); 1676 1677 value = 0 | HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL, 1678 flow->tuple_info.l4_protocol); 1679 value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER, 1680 flow->reo_destination_handler); 1681 value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, 1682 REO_DESTINATION_INDICATION, 1683 flow->reo_destination_indication); 1684 value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, VALID, 1); 1685 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_9, 1686 L4_PROTOCOL), value); 1687 1688 return fse_offset; 1689 } 1690 1691 /** 1692 * hal_rx_flow_get_cmem_fse_ts_6450() - Get timestamp field from CMEM FSE 1693 * @hal_soc: hal_soc reference 1694 * @fse_offset: CMEM FSE offset 1695 * 1696 * Return: Timestamp 1697 */ 1698 static uint32_t hal_rx_flow_get_cmem_fse_ts_6450(struct hal_soc *hal_soc, 1699 uint32_t fse_offset) 1700 { 1701 return HAL_CMEM_READ(hal_soc, fse_offset + 1702 HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_13, TIMESTAMP)); 1703 } 1704 1705 /** 1706 * hal_rx_flow_get_cmem_fse_6450() - Get FSE from CMEM 1707 * @hal_soc: hal_soc reference 1708 * @fse_offset: CMEM FSE offset 1709 * @fse: reference where FSE will be copied 1710 * @len: length of FSE 1711 * 1712 * Return: If read is successful or not 1713 */ 1714 static void 1715 hal_rx_flow_get_cmem_fse_6450(struct hal_soc *hal_soc, uint32_t fse_offset, 1716 uint32_t *fse, qdf_size_t len) 1717 { 1718 int i; 1719 1720 if (len != HAL_RX_FST_ENTRY_SIZE) 1721 return; 1722 1723 for (i = 0; i < NUM_OF_DWORDS_RX_FLOW_SEARCH_ENTRY; i++) 1724 fse[i] = HAL_CMEM_READ(hal_soc, fse_offset + i * 4); 1725 } 1726 1727 /** 1728 * hal_rx_msdu_get_reo_destination_indication_6450: API to get 1729 * reo_destination_indication from rx_msdu_end TLV 1730 * @buf: pointer to the start of RX PKT TLV headers 1731 * @reo_destination_ind: pointer to return value 1732 * of reo_destination_indication 1733 * 1734 * Return: none 1735 */ 1736 static void 1737 hal_rx_msdu_get_reo_destination_indication_6450(uint8_t *buf, 1738 uint32_t *reo_destination_ind) 1739 { 1740 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1741 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1742 1743 *reo_destination_ind = 1744 HAL_RX_MSDU_END_REO_DEST_IND_GET(msdu_end); 1745 } 1746 1747 #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET 1748 static inline uint8_t hal_get_first_wow_wakeup_packet_6450(uint8_t *buf) 1749 { 1750 return 0; 1751 } 1752 #endif 1753 1754 /** 1755 * hal_rx_msdu_start_get_len_6450(): API to get the MSDU length 1756 * from rx_msdu_start TLV 1757 * 1758 * @buf: pointer to the start of RX PKT TLV headers 1759 * Return: (uint32_t)msdu length 1760 */ 1761 static uint32_t hal_rx_msdu_start_get_len_6450(uint8_t *buf) 1762 { 1763 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1764 struct rx_msdu_start *msdu_start = 1765 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 1766 uint32_t msdu_len; 1767 1768 msdu_len = HAL_RX_MSDU_START_MSDU_LEN_GET(msdu_start); 1769 1770 return msdu_len; 1771 } 1772 1773 static void hal_hw_txrx_ops_attach_wcn6450(struct hal_soc *hal_soc) 1774 { 1775 /* Initialize setup tx/rx ops here */ 1776 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic; 1777 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic; 1778 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_6450; 1779 hal_soc->ops->hal_reo_setup = hal_reo_setup_6450; 1780 hal_soc->ops->hal_get_window_address = hal_get_window_address_6450; 1781 hal_soc->ops->hal_reo_set_err_dst_remap = 1782 hal_reo_set_err_dst_remap_6450; 1783 1784 /* tx */ 1785 hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id = 1786 hal_tx_desc_set_dscp_tid_table_id_6450; 1787 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_6450; 1788 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_6450; 1789 hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_6450; 1790 hal_soc->ops->hal_tx_desc_set_buf_addr = 1791 hal_tx_desc_set_buf_addr_generic_rh; 1792 hal_soc->ops->hal_tx_desc_set_search_type = 1793 hal_tx_desc_set_search_type_generic_rh; 1794 hal_soc->ops->hal_tx_desc_set_search_index = 1795 hal_tx_desc_set_search_index_generic_rh; 1796 hal_soc->ops->hal_tx_desc_set_cache_set_num = 1797 hal_tx_desc_set_cache_set_num_generic_rh; 1798 hal_soc->ops->hal_tx_comp_get_status = 1799 hal_tx_comp_get_status_generic_rh; 1800 hal_soc->ops->hal_tx_comp_get_release_reason = 1801 hal_tx_comp_get_release_reason_6450; 1802 hal_soc->ops->hal_get_wbm_internal_error = 1803 hal_get_wbm_internal_error_6450; 1804 hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_6450; 1805 hal_soc->ops->hal_tx_init_cmd_credit_ring = 1806 hal_tx_init_cmd_credit_ring_6450; 1807 1808 /* rx */ 1809 hal_soc->ops->hal_rx_msdu_start_nss_get = 1810 hal_rx_msdu_start_nss_get_6450; 1811 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status = 1812 hal_rx_mon_hw_desc_get_mpdu_status_6450; 1813 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_6450; 1814 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv = 1815 hal_rx_proc_phyrx_other_receive_info_tlv_6450; 1816 hal_soc->ops->hal_rx_dump_msdu_start_tlv = 1817 hal_rx_dump_msdu_start_tlv_6450; 1818 hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_6450; 1819 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_6450; 1820 hal_soc->ops->hal_rx_mpdu_start_tid_get = 1821 hal_rx_mpdu_start_tid_get_6450; 1822 hal_soc->ops->hal_rx_msdu_start_reception_type_get = 1823 hal_rx_msdu_start_reception_type_get_6450; 1824 hal_soc->ops->hal_rx_msdu_end_da_idx_get = 1825 hal_rx_msdu_end_da_idx_get_6450; 1826 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = 1827 hal_rx_msdu_desc_info_get_ptr_6450; 1828 hal_soc->ops->hal_rx_link_desc_msdu0_ptr = 1829 hal_rx_link_desc_msdu0_ptr_6450; 1830 hal_soc->ops->hal_reo_status_get_header = 1831 hal_reo_status_get_header_6450; 1832 hal_soc->ops->hal_rx_status_get_tlv_info = 1833 hal_rx_status_get_tlv_info_generic_rh; 1834 hal_soc->ops->hal_rx_wbm_err_info_get = 1835 hal_rx_wbm_err_info_get_6450; 1836 hal_soc->ops->hal_rx_dump_mpdu_start_tlv = 1837 hal_rx_dump_mpdu_start_tlv_generic_rh; 1838 hal_soc->ops->hal_tx_set_pcp_tid_map = 1839 hal_tx_set_pcp_tid_map_generic_rh; 1840 hal_soc->ops->hal_tx_update_pcp_tid_map = 1841 hal_tx_update_pcp_tid_generic_rh; 1842 hal_soc->ops->hal_tx_set_tidmap_prty = 1843 hal_tx_update_tidmap_prty_generic_rh; 1844 hal_soc->ops->hal_rx_get_rx_fragment_number = 1845 hal_rx_get_rx_fragment_number_6450; 1846 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = 1847 hal_rx_msdu_end_da_is_mcbc_get_6450; 1848 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = 1849 hal_rx_msdu_end_sa_is_valid_get_6450; 1850 hal_soc->ops->hal_rx_msdu_end_sa_idx_get = 1851 hal_rx_msdu_end_sa_idx_get_6450; 1852 hal_soc->ops->hal_rx_desc_is_first_msdu = 1853 hal_rx_desc_is_first_msdu_6450; 1854 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get = 1855 hal_rx_msdu_end_l3_hdr_padding_get_6450; 1856 hal_soc->ops->hal_rx_encryption_info_valid = 1857 hal_rx_encryption_info_valid_6450; 1858 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_6450; 1859 hal_soc->ops->hal_rx_msdu_end_first_msdu_get = 1860 hal_rx_msdu_end_first_msdu_get_6450; 1861 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = 1862 hal_rx_msdu_end_da_is_valid_get_6450; 1863 hal_soc->ops->hal_rx_msdu_end_last_msdu_get = 1864 hal_rx_msdu_end_last_msdu_get_6450; 1865 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = 1866 hal_rx_get_mpdu_mac_ad4_valid_6450; 1867 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get = 1868 hal_rx_mpdu_start_sw_peer_id_get_6450; 1869 hal_soc->ops->hal_rx_tlv_peer_meta_data_get = 1870 hal_rx_mpdu_peer_meta_data_get_rh; 1871 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_6450; 1872 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_6450; 1873 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid = 1874 hal_rx_get_mpdu_frame_control_valid_6450; 1875 hal_soc->ops->hal_rx_get_frame_ctrl_field = 1876 hal_rx_get_frame_ctrl_field_rh; 1877 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_6450; 1878 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_6450; 1879 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_6450; 1880 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_6450; 1881 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid = 1882 hal_rx_get_mpdu_sequence_control_valid_6450; 1883 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_6450; 1884 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_6450; 1885 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = 1886 hal_rx_hw_desc_get_ppduid_get_6450; 1887 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = 1888 hal_rx_msdu0_buffer_addr_lsb_6450; 1889 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = 1890 hal_rx_msdu_desc_info_ptr_get_6450; 1891 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_6450; 1892 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_6450; 1893 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_6450; 1894 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_6450; 1895 hal_soc->ops->hal_rx_get_mac_addr2_valid = 1896 hal_rx_get_mac_addr2_valid_6450; 1897 hal_soc->ops->hal_rx_get_filter_category = 1898 hal_rx_get_filter_category_6450; 1899 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_6450; 1900 hal_soc->ops->hal_reo_config = hal_reo_config_6450; 1901 hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_6450; 1902 hal_soc->ops->hal_rx_msdu_flow_idx_invalid = 1903 hal_rx_msdu_flow_idx_invalid_6450; 1904 hal_soc->ops->hal_rx_msdu_flow_idx_timeout = 1905 hal_rx_msdu_flow_idx_timeout_6450; 1906 hal_soc->ops->hal_rx_msdu_fse_metadata_get = 1907 hal_rx_msdu_fse_metadata_get_6450; 1908 hal_soc->ops->hal_rx_msdu_cce_match_get = 1909 hal_rx_msdu_cce_match_get_rh; 1910 hal_soc->ops->hal_rx_msdu_cce_metadata_get = 1911 hal_rx_msdu_cce_metadata_get_6450; 1912 hal_soc->ops->hal_rx_msdu_get_flow_params = 1913 hal_rx_msdu_get_flow_params_6450; 1914 hal_soc->ops->hal_rx_tlv_get_tcp_chksum = 1915 hal_rx_tlv_get_tcp_chksum_6450; 1916 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_6450; 1917 #if defined(QCA_WIFI_WCN6450) && defined(WLAN_CFR_ENABLE) && \ 1918 defined(WLAN_ENH_CFR_ENABLE) 1919 hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_6450; 1920 hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_6450; 1921 #endif 1922 1923 /* rx - msdu end fast path info fields */ 1924 hal_soc->ops->hal_rx_msdu_packet_metadata_get = 1925 hal_rx_msdu_packet_metadata_get_generic_rh; 1926 hal_soc->ops->hal_rx_get_fisa_cumulative_l4_checksum = 1927 hal_rx_get_fisa_cumulative_l4_checksum_6450; 1928 hal_soc->ops->hal_rx_get_fisa_cumulative_ip_length = 1929 hal_rx_get_fisa_cumulative_ip_length_6450; 1930 hal_soc->ops->hal_rx_get_udp_proto = hal_rx_get_udp_proto_6450; 1931 hal_soc->ops->hal_rx_get_fisa_flow_agg_continuation = 1932 hal_rx_get_flow_agg_continuation_6450; 1933 hal_soc->ops->hal_rx_get_fisa_flow_agg_count = 1934 hal_rx_get_flow_agg_count_6450; 1935 hal_soc->ops->hal_rx_get_fisa_timeout = hal_rx_get_fisa_timeout_6450; 1936 hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid = 1937 hal_rx_mpdu_start_tlv_tag_valid_6450; 1938 1939 /* rx - TLV struct offsets */ 1940 hal_soc->ops->hal_rx_msdu_end_offset_get = 1941 hal_rx_msdu_end_offset_get_generic; 1942 hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic; 1943 hal_soc->ops->hal_rx_msdu_start_offset_get = 1944 hal_rx_msdu_start_offset_get_generic; 1945 hal_soc->ops->hal_rx_mpdu_start_offset_get = 1946 hal_rx_mpdu_start_offset_get_generic; 1947 hal_soc->ops->hal_rx_mpdu_end_offset_get = 1948 hal_rx_mpdu_end_offset_get_generic; 1949 #ifndef NO_RX_PKT_HDR_TLV 1950 hal_soc->ops->hal_rx_pkt_tlv_offset_get = 1951 hal_rx_pkt_tlv_offset_get_generic; 1952 #endif 1953 hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_6450; 1954 hal_soc->ops->hal_rx_flow_get_tuple_info = 1955 hal_rx_flow_get_tuple_info_rh; 1956 hal_soc->ops->hal_rx_flow_delete_entry = 1957 hal_rx_flow_delete_entry_rh; 1958 hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_rh; 1959 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = 1960 hal_compute_reo_remap_ix2_ix3_6450; 1961 1962 /* CMEM FSE */ 1963 hal_soc->ops->hal_rx_flow_setup_cmem_fse = 1964 hal_rx_flow_setup_cmem_fse_6450; 1965 hal_soc->ops->hal_rx_flow_get_cmem_fse_ts = 1966 hal_rx_flow_get_cmem_fse_ts_6450; 1967 hal_soc->ops->hal_rx_flow_get_cmem_fse = hal_rx_flow_get_cmem_fse_6450; 1968 hal_soc->ops->hal_rx_msdu_get_reo_destination_indication = 1969 hal_rx_msdu_get_reo_destination_indication_6450; 1970 hal_soc->ops->hal_setup_link_idle_list = 1971 hal_setup_link_idle_list_6450; 1972 #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET 1973 hal_soc->ops->hal_get_first_wow_wakeup_packet = 1974 hal_get_first_wow_wakeup_packet_6450; 1975 #endif 1976 hal_soc->ops->hal_compute_reo_remap_ix0 = 1977 hal_compute_reo_remap_ix0_6450; 1978 hal_soc->ops->hal_rx_tlv_msdu_len_get = 1979 hal_rx_msdu_start_get_len_6450; 1980 } 1981 1982 /** 1983 * hal_wcn6450_attach() - Attach 6450 target specific hal_soc ops, 1984 * offset and srng table 1985 * @hal_soc: HAL Soc handle 1986 * 1987 * Return: None 1988 */ 1989 void hal_wcn6450_attach(struct hal_soc *hal_soc) 1990 { 1991 hal_soc->hw_srng_table = hw_srng_table_wcn6450; 1992 hal_hw_txrx_default_ops_attach_rh(hal_soc); 1993 hal_hw_txrx_ops_attach_wcn6450(hal_soc); 1994 } 1995