1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _HAL_RH_TX_H_ 21 #define _HAL_RH_TX_H_ 22 23 enum hal_rh_tx_ret_buf_manager { 24 HAL_RH_WBM_SW0_BM_ID = 3, 25 HAL_RH_WBM_SW1_BM_ID = 4, 26 HAL_RH_WBM_SW2_BM_ID = 5, 27 HAL_RH_WBM_SW3_BM_ID = 6, 28 HAL_RH_WBM_SW4_BM_ID = 7, 29 }; 30 31 /*--------------------------------------------------------------------------- 32 * Function declarations and documentation 33 * --------------------------------------------------------------------------- 34 */ 35 36 /*--------------------------------------------------------------------------- 37 * TCL Descriptor accessor APIs 38 * --------------------------------------------------------------------------- 39 */ 40 41 /** 42 * hal_tx_desc_set_buf_addr - Fill Buffer Address information in Tx Descriptor 43 * @hal_soc_hdl: HAL SOC handle 44 * @desc: Handle to Tx Descriptor 45 * @paddr: Physical Address 46 * @pool_id: Return Buffer Manager ID 47 * @desc_id: Descriptor ID 48 * @type: 0 - Address points to a MSDU buffer 49 * 1 - Address points to MSDU extension descriptor 50 * 51 * Return: void 52 */ 53 static inline 54 void hal_tx_desc_set_buf_addr(hal_soc_handle_t hal_soc_hdl, void *desc, 55 dma_addr_t paddr, 56 uint8_t pool_id, uint32_t desc_id, 57 uint8_t type) 58 { 59 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 60 61 hal_soc->ops->hal_tx_desc_set_buf_addr(desc, paddr, pool_id, 62 desc_id, type); 63 } 64 65 /** 66 * hal_tx_desc_set_lmac_id - Set the lmac_id value 67 * @hal_soc_hdl: HAL SOC handle 68 * @desc: Handle to Tx Descriptor 69 * @lmac_id: mac Id to ast matching 70 * b00 – mac 0 71 * b01 – mac 1 72 * b10 – mac 2 73 * b11 – all macs (legacy HK way) 74 * 75 * Return: void 76 */ 77 static inline void hal_tx_desc_set_lmac_id(hal_soc_handle_t hal_soc_hdl, 78 void *desc, uint8_t lmac_id) 79 { 80 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 81 82 hal_soc->ops->hal_tx_desc_set_lmac_id(desc, lmac_id); 83 } 84 85 /** 86 * hal_tx_desc_set_search_type - Set the search type value 87 * @hal_soc_hdl: HAL SOC handle 88 * @desc: Handle to Tx Descriptor 89 * @search_type: search type 90 * 0 – Normal search 91 * 1 – Index based address search 92 * 2 – Index based flow search 93 * 94 * Return: void 95 */ 96 static inline void hal_tx_desc_set_search_type(hal_soc_handle_t hal_soc_hdl, 97 void *desc, 98 uint8_t search_type) 99 { 100 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 101 102 hal_soc->ops->hal_tx_desc_set_search_type(desc, search_type); 103 } 104 105 /** 106 * hal_tx_desc_set_search_index - Set the search index value 107 * @hal_soc_hdl: HAL SOC handle 108 * @desc: Handle to Tx Descriptor 109 * @search_index: The index that will be used for index based address or 110 * flow search. The field is valid when 'search_type' is 111 * 1 0r 2 112 * 113 * Return: void 114 */ 115 static inline void hal_tx_desc_set_search_index(hal_soc_handle_t hal_soc_hdl, 116 void *desc, 117 uint32_t search_index) 118 { 119 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 120 121 hal_soc->ops->hal_tx_desc_set_search_index(desc, search_index); 122 } 123 124 /** 125 * hal_tx_desc_set_cache_set_num - Set the cache-set-num value 126 * @hal_soc_hdl: HAL SOC handle 127 * @desc: Handle to Tx Descriptor 128 * @cache_num: Cache set number that should be used to cache the index 129 * based search results, for address and flow search. 130 * This value should be equal to LSB four bits of the hash value 131 * of match data, in case of search index points to an entry 132 * which may be used in content based search also. The value can 133 * be anything when the entry pointed by search index will not be 134 * used for content based search. 135 * 136 * Return: void 137 */ 138 static inline void hal_tx_desc_set_cache_set_num(hal_soc_handle_t hal_soc_hdl, 139 void *desc, 140 uint8_t cache_num) 141 { 142 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 143 144 hal_soc->ops->hal_tx_desc_set_cache_set_num(desc, cache_num); 145 } 146 147 /** 148 * hal_tx_desc_set_buf_length - Set Data length in bytes in Tx Descriptor 149 * @desc: Handle to Tx Descriptor 150 * @data_length: MSDU length in case of direct descriptor. 151 * Length of link extension descriptor in case of Link extension 152 * descriptor.Includes the length of Metadata 153 * Return: None 154 */ 155 static inline void hal_tx_desc_set_buf_length(void *desc, 156 uint16_t data_length) 157 { 158 HAL_SET_FLD(desc, TCL_DATA_CMD_3, DATA_LENGTH) |= 159 HAL_TX_SM(TCL_DATA_CMD_3, DATA_LENGTH, data_length); 160 } 161 162 /** 163 * hal_tx_desc_set_buf_offset - Sets Packet Offset field in Tx descriptor 164 * @desc: Handle to Tx Descriptor 165 * @offset: Packet offset from Metadata in case of direct buffer descriptor. 166 * 167 * Return: void 168 */ 169 static inline void hal_tx_desc_set_buf_offset(void *desc, 170 uint8_t offset) 171 { 172 HAL_SET_FLD(desc, TCL_DATA_CMD_3, PACKET_OFFSET) |= 173 HAL_TX_SM(TCL_DATA_CMD_3, PACKET_OFFSET, offset); 174 } 175 176 /** 177 * hal_tx_desc_set_encap_type - Set encapsulation type in Tx Descriptor 178 * @desc: Handle to Tx Descriptor 179 * @encap_type: Encapsulation that HW will perform 180 * 181 * Return: void 182 * 183 */ 184 static inline void hal_tx_desc_set_encap_type(void *desc, 185 enum hal_tx_encap_type encap_type) 186 { 187 HAL_SET_FLD(desc, TCL_DATA_CMD_2, ENCAP_TYPE) |= 188 HAL_TX_SM(TCL_DATA_CMD_2, ENCAP_TYPE, encap_type); 189 } 190 191 /** 192 * hal_tx_desc_set_encrypt_type - Sets the Encrypt Type in Tx Descriptor 193 * @desc: Handle to Tx Descriptor 194 * @type: Encrypt Type 195 * 196 * Return: void 197 */ 198 static inline void hal_tx_desc_set_encrypt_type(void *desc, 199 enum hal_tx_encrypt_type type) 200 { 201 HAL_SET_FLD(desc, TCL_DATA_CMD_2, ENCRYPT_TYPE) |= 202 HAL_TX_SM(TCL_DATA_CMD_2, ENCRYPT_TYPE, type); 203 } 204 205 /** 206 * hal_tx_desc_set_addr_search_flags - Enable AddrX and AddrY search flags 207 * @desc: Handle to Tx Descriptor 208 * @flags: Bit 0 - AddrY search enable, Bit 1 - AddrX search enable 209 * 210 * Return: void 211 */ 212 static inline void hal_tx_desc_set_addr_search_flags(void *desc, 213 uint8_t flags) 214 { 215 HAL_SET_FLD(desc, TCL_DATA_CMD_2, ADDRX_EN) |= 216 HAL_TX_SM(TCL_DATA_CMD_2, ADDRX_EN, (flags & 0x1)); 217 218 HAL_SET_FLD(desc, TCL_DATA_CMD_2, ADDRY_EN) |= 219 HAL_TX_SM(TCL_DATA_CMD_2, ADDRY_EN, (flags >> 1)); 220 } 221 222 /** 223 * hal_tx_desc_set_l4_checksum_en - Set TCP/IP checksum enable flags 224 * Tx Descriptor for MSDU_buffer type 225 * @desc: Handle to Tx Descriptor 226 * @en: UDP/TCP over ipv4/ipv6 checksum enable flags (5 bits) 227 * 228 * Return: void 229 */ 230 static inline void hal_tx_desc_set_l4_checksum_en(void *desc, 231 uint8_t en) 232 { 233 HAL_SET_FLD(desc, TCL_DATA_CMD_3, IPV4_CHECKSUM_EN) |= 234 (HAL_TX_SM(TCL_DATA_CMD_3, UDP_OVER_IPV4_CHECKSUM_EN, en) | 235 HAL_TX_SM(TCL_DATA_CMD_3, UDP_OVER_IPV6_CHECKSUM_EN, en) | 236 HAL_TX_SM(TCL_DATA_CMD_3, TCP_OVER_IPV4_CHECKSUM_EN, en) | 237 HAL_TX_SM(TCL_DATA_CMD_3, TCP_OVER_IPV6_CHECKSUM_EN, en)); 238 } 239 240 /** 241 * hal_tx_desc_set_l3_checksum_en - Set IPv4 checksum enable flag in 242 * Tx Descriptor for MSDU_buffer type 243 * @desc: Handle to Tx Descriptor 244 * @en: ipv4 checksum enable flags 245 * 246 * Return: void 247 */ 248 static inline void hal_tx_desc_set_l3_checksum_en(void *desc, 249 uint8_t en) 250 { 251 HAL_SET_FLD(desc, TCL_DATA_CMD_3, IPV4_CHECKSUM_EN) |= 252 HAL_TX_SM(TCL_DATA_CMD_3, IPV4_CHECKSUM_EN, en); 253 } 254 255 /** 256 * hal_tx_desc_set_fw_metadata- Sets the metadata that is part of TCL descriptor 257 * @desc:Handle to Tx Descriptor 258 * @metadata: Metadata to be sent to Firmware 259 * 260 * Return: void 261 */ 262 static inline void hal_tx_desc_set_fw_metadata(void *desc, 263 uint16_t metadata) 264 { 265 HAL_SET_FLD(desc, TCL_DATA_CMD_2, TCL_CMD_NUMBER) |= 266 HAL_TX_SM(TCL_DATA_CMD_2, TCL_CMD_NUMBER, metadata); 267 } 268 269 /** 270 * hal_tx_desc_set_to_fw - Set To_FW bit in Tx Descriptor. 271 * @desc:Handle to Tx Descriptor 272 * @to_fw: if set, Forward packet to FW along with classification result 273 * 274 * Return: void 275 */ 276 static inline void hal_tx_desc_set_to_fw(void *desc, uint8_t to_fw) 277 { 278 HAL_SET_FLD(desc, TCL_DATA_CMD_3, TO_FW) |= 279 HAL_TX_SM(TCL_DATA_CMD_3, TO_FW, to_fw); 280 } 281 282 /** 283 * hal_tx_desc_set_mesh_en - Set mesh_enable flag in Tx descriptor 284 * @hal_soc_hdl: hal soc handle 285 * @desc: Handle to Tx Descriptor 286 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 287 * enabling the interpretation of the 'Mesh Control Present' bit 288 * (bit 8) of QoS Control (otherwise this bit is ignored), 289 * For native WiFi frames, this indicates that a 'Mesh Control' field 290 * is present between the header and the LLC. 291 * 292 * Return: void 293 */ 294 static inline void hal_tx_desc_set_mesh_en(hal_soc_handle_t hal_soc_hdl, 295 void *desc, uint8_t en) 296 { 297 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 298 299 hal_soc->ops->hal_tx_desc_set_mesh_en(desc, en); 300 } 301 302 /** 303 * hal_tx_desc_set_hlos_tid - Set the TID value (override DSCP/PCP fields in 304 * frame) to be used for Tx Frame 305 * @desc: Handle to Tx Descriptor 306 * @hlos_tid: HLOS TID 307 * 308 * Return: void 309 */ 310 static inline void hal_tx_desc_set_hlos_tid(void *desc, 311 uint8_t hlos_tid) 312 { 313 HAL_SET_FLD(desc, TCL_DATA_CMD_4, HLOS_TID) |= 314 HAL_TX_SM(TCL_DATA_CMD_4, HLOS_TID, hlos_tid); 315 316 HAL_SET_FLD(desc, TCL_DATA_CMD_4, HLOS_TID_OVERWRITE) |= 317 HAL_TX_SM(TCL_DATA_CMD_4, HLOS_TID_OVERWRITE, 1); 318 } 319 320 /** 321 * hal_tx_desc_clear - Clear the HW descriptor entry 322 * @hw_desc: Hardware descriptor to be cleared 323 * 324 * Return: void 325 */ 326 static inline void hal_tx_desc_clear(void *hw_desc) 327 { 328 qdf_mem_set(hw_desc + sizeof(struct tlv_32_hdr), 329 HAL_TX_DESC_LEN_BYTES, 0); 330 } 331 332 /** 333 * hal_tx_desc_sync - Commit the descriptor to Hardware 334 * @hal_tx_desc_cached: Cached descriptor that software maintains 335 * @hw_desc: Hardware descriptor to be updated 336 */ 337 static inline void hal_tx_desc_sync(void *hal_tx_desc_cached, 338 void *hw_desc) 339 { 340 qdf_mem_copy((hw_desc + sizeof(struct tlv_32_hdr)), 341 hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES); 342 } 343 344 /*--------------------------------------------------------------------------- 345 * WBM Descriptor accessor APIs for Tx completions 346 *--------------------------------------------------------------------------- 347 */ 348 349 /** 350 * hal_tx_get_wbm_sw0_bm_id() - Get the BM ID for first tx completion ring 351 * 352 * Return: BM ID for first tx completion ring 353 */ 354 static inline uint32_t hal_tx_get_wbm_sw0_bm_id(void) 355 { 356 return HAL_RH_WBM_SW0_BM_ID; 357 } 358 #endif /* _HAL_RH_TX_H_ */ 359