1 /* 2 * Copyright (c) 2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 #include "hal_9224.h" 18 19 struct hal_hw_srng_config hw_srng_table_9224v2[] = { 20 /* TODO: max_rings can populated by querying HW capabilities */ 21 { /* REO_DST */ 22 .start_ring_id = HAL_SRNG_REO2SW1, 23 .max_rings = 8, 24 .entry_size = sizeof(struct reo_destination_ring) >> 2, 25 .lmac_ring = FALSE, 26 .ring_dir = HAL_SRNG_DST_RING, 27 .reg_start = { 28 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 29 REO_REG_REG_BASE), 30 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 31 REO_REG_REG_BASE) 32 }, 33 .reg_size = { 34 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 35 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 36 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 37 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 38 }, 39 .max_size = 40 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 41 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 42 }, 43 { /* REO_EXCEPTION */ 44 /* Designating REO2SW0 ring as exception ring. This ring is 45 * similar to other REO2SW rings though it is named as REO2SW0. 46 * Any of theREO2SW rings can be used as exception ring. 47 */ 48 .start_ring_id = HAL_SRNG_REO2SW0, 49 .max_rings = 1, 50 .entry_size = sizeof(struct reo_destination_ring) >> 2, 51 .lmac_ring = FALSE, 52 .ring_dir = HAL_SRNG_DST_RING, 53 .reg_start = { 54 HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR( 55 REO_REG_REG_BASE), 56 HWIO_REO_R2_REO2SW0_RING_HP_ADDR( 57 REO_REG_REG_BASE) 58 }, 59 /* Single ring - provide ring size if multiple rings of this 60 * type are supported 61 */ 62 .reg_size = {}, 63 .max_size = 64 HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_BMSK >> 65 HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_SHFT, 66 }, 67 { /* REO_REINJECT */ 68 .start_ring_id = HAL_SRNG_SW2REO, 69 .max_rings = 4, 70 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 71 .lmac_ring = FALSE, 72 .ring_dir = HAL_SRNG_SRC_RING, 73 .reg_start = { 74 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 75 REO_REG_REG_BASE), 76 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 77 REO_REG_REG_BASE) 78 }, 79 /* Single ring - provide ring size if multiple rings of this 80 * type are supported 81 */ 82 .reg_size = { 83 HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(0) - 84 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(0), 85 HWIO_REO_R2_SW2REO1_RING_HP_ADDR(0) - 86 HWIO_REO_R2_SW2REO_RING_HP_ADDR(0) 87 }, 88 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 89 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 90 }, 91 { /* REO_CMD */ 92 .start_ring_id = HAL_SRNG_REO_CMD, 93 .max_rings = 1, 94 .entry_size = (sizeof(struct tlv_32_hdr) + 95 sizeof(struct reo_get_queue_stats)) >> 2, 96 .lmac_ring = FALSE, 97 .ring_dir = HAL_SRNG_SRC_RING, 98 .reg_start = { 99 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 100 REO_REG_REG_BASE), 101 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 102 REO_REG_REG_BASE), 103 }, 104 /* Single ring - provide ring size if multiple rings of this 105 * type are supported 106 */ 107 .reg_size = {}, 108 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 109 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 110 }, 111 { /* REO_STATUS */ 112 .start_ring_id = HAL_SRNG_REO_STATUS, 113 .max_rings = 1, 114 .entry_size = (sizeof(struct tlv_32_hdr) + 115 sizeof(struct reo_get_queue_stats_status)) >> 2, 116 .lmac_ring = FALSE, 117 .ring_dir = HAL_SRNG_DST_RING, 118 .reg_start = { 119 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 120 REO_REG_REG_BASE), 121 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 122 REO_REG_REG_BASE), 123 }, 124 /* Single ring - provide ring size if multiple rings of this 125 * type are supported 126 */ 127 .reg_size = {}, 128 .max_size = 129 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 130 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 131 }, 132 { /* TCL_DATA */ 133 .start_ring_id = HAL_SRNG_SW2TCL1, 134 .max_rings = 6, 135 .entry_size = sizeof(struct tcl_data_cmd) >> 2, 136 .lmac_ring = FALSE, 137 .ring_dir = HAL_SRNG_SRC_RING, 138 .reg_start = { 139 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 140 MAC_TCL_REG_REG_BASE), 141 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 142 MAC_TCL_REG_REG_BASE), 143 }, 144 .reg_size = { 145 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 146 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 147 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 148 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 149 }, 150 .max_size = 151 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 152 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 153 }, 154 { /* TCL_CMD/CREDIT */ 155 /* qca8074v2 and qcn9224 uses this ring for data commands */ 156 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 157 .max_rings = 1, 158 .entry_size = sizeof(struct tcl_data_cmd) >> 2, 159 .lmac_ring = FALSE, 160 .ring_dir = HAL_SRNG_SRC_RING, 161 .reg_start = { 162 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR( 163 MAC_TCL_REG_REG_BASE), 164 HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR( 165 MAC_TCL_REG_REG_BASE), 166 }, 167 /* Single ring - provide ring size if multiple rings of this 168 * type are supported 169 */ 170 .reg_size = {}, 171 .max_size = 172 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >> 173 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT, 174 }, 175 { /* TCL_STATUS */ 176 .start_ring_id = HAL_SRNG_TCL_STATUS, 177 .max_rings = 1, 178 .entry_size = (sizeof(struct tlv_32_hdr) + 179 sizeof(struct tcl_status_ring)) >> 2, 180 .lmac_ring = FALSE, 181 .ring_dir = HAL_SRNG_DST_RING, 182 .reg_start = { 183 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 184 MAC_TCL_REG_REG_BASE), 185 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 186 MAC_TCL_REG_REG_BASE), 187 }, 188 /* Single ring - provide ring size if multiple rings of this 189 * type are supported 190 */ 191 .reg_size = {}, 192 .max_size = 193 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 194 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 195 }, 196 { /* CE_SRC */ 197 .start_ring_id = HAL_SRNG_CE_0_SRC, 198 .max_rings = 16, 199 .entry_size = sizeof(struct ce_src_desc) >> 2, 200 .lmac_ring = FALSE, 201 .ring_dir = HAL_SRNG_SRC_RING, 202 .reg_start = { 203 HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR( 204 WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE), 205 HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR( 206 WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE), 207 }, 208 .reg_size = { 209 WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE - 210 WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE, 211 WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE - 212 WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE, 213 }, 214 .max_size = 215 HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK >> 216 HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT, 217 }, 218 { /* CE_DST */ 219 .start_ring_id = HAL_SRNG_CE_0_DST, 220 .max_rings = 16, 221 .entry_size = 8 >> 2, 222 /*TODO: entry_size above should actually be 223 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 224 * of struct ce_dst_desc in HW header files 225 */ 226 .lmac_ring = FALSE, 227 .ring_dir = HAL_SRNG_SRC_RING, 228 .reg_start = { 229 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 230 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE), 231 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 232 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE), 233 }, 234 .reg_size = { 235 WFSS_CE_1_CHANNEL_DST_REG_REG_BASE - 236 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE, 237 WFSS_CE_1_CHANNEL_DST_REG_REG_BASE - 238 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE, 239 }, 240 .max_size = 241 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 242 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 243 }, 244 { /* CE_DST_STATUS */ 245 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 246 .max_rings = 16, 247 .entry_size = sizeof(struct ce_stat_desc) >> 2, 248 .lmac_ring = FALSE, 249 .ring_dir = HAL_SRNG_DST_RING, 250 .reg_start = { 251 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 252 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE), 253 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 254 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE), 255 }, 256 /* TODO: check destination status ring registers */ 257 .reg_size = { 258 WFSS_CE_1_CHANNEL_DST_REG_REG_BASE - 259 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE, 260 WFSS_CE_1_CHANNEL_DST_REG_REG_BASE - 261 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE, 262 }, 263 .max_size = 264 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 265 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 266 }, 267 { /* WBM_IDLE_LINK */ 268 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 269 .max_rings = 1, 270 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 271 .lmac_ring = FALSE, 272 .ring_dir = HAL_SRNG_SRC_RING, 273 .reg_start = { 274 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE), 275 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(WBM_REG_REG_BASE), 276 }, 277 /* Single ring - provide ring size if multiple rings of this 278 * type are supported 279 */ 280 .reg_size = {}, 281 .max_size = 282 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 283 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 284 }, 285 { /* SW2WBM_RELEASE */ 286 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 287 .max_rings = 2, 288 .entry_size = sizeof(struct wbm_release_ring) >> 2, 289 .lmac_ring = FALSE, 290 .ring_dir = HAL_SRNG_SRC_RING, 291 .reg_start = { 292 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE), 293 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE), 294 }, 295 .reg_size = { 296 HWIO_WBM_R0_SW1_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE) - 297 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE), 298 HWIO_WBM_R2_SW1_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE) - 299 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE) 300 }, 301 .max_size = 302 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 303 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 304 }, 305 { /* WBM2SW_RELEASE */ 306 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 307 .max_rings = 8, 308 .entry_size = sizeof(struct wbm_release_ring) >> 2, 309 .lmac_ring = FALSE, 310 .ring_dir = HAL_SRNG_DST_RING, 311 .reg_start = { 312 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR( 313 WBM_REG_REG_BASE), 314 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR( 315 WBM_REG_REG_BASE), 316 }, 317 .reg_size = { 318 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR( 319 WBM_REG_REG_BASE) - 320 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR( 321 WBM_REG_REG_BASE), 322 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR( 323 WBM_REG_REG_BASE) - 324 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR( 325 WBM_REG_REG_BASE), 326 }, 327 .max_size = 328 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 329 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 330 }, 331 { /* RXDMA_BUF */ 332 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 333 #ifdef IPA_OFFLOAD 334 .max_rings = 3, 335 #else 336 .max_rings = 3, 337 #endif 338 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 339 .lmac_ring = TRUE, 340 .ring_dir = HAL_SRNG_SRC_RING, 341 /* reg_start is not set because LMAC rings are not accessed 342 * from host 343 */ 344 .reg_start = {}, 345 .reg_size = {}, 346 .max_size = HAL_RXDMA_MAX_RING_SIZE, 347 }, 348 { /* RXDMA_DST */ 349 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 350 .max_rings = 0, 351 .entry_size = 0/*sizeof(struct reo_entrance_ring) >> 2*/, 352 .lmac_ring = TRUE, 353 .ring_dir = HAL_SRNG_DST_RING, 354 /* reg_start is not set because LMAC rings are not accessed 355 * from host 356 */ 357 .reg_start = {}, 358 .reg_size = {}, 359 .max_size = HAL_RXDMA_MAX_RING_SIZE, 360 }, 361 #ifdef QCA_MONITOR_2_0_SUPPORT 362 { /* RXDMA_MONITOR_BUF */ 363 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 364 .max_rings = 1, 365 .entry_size = sizeof(struct mon_ingress_ring) >> 2, 366 .lmac_ring = TRUE, 367 .ring_dir = HAL_SRNG_SRC_RING, 368 /* reg_start is not set because LMAC rings are not accessed 369 * from host 370 */ 371 .reg_start = {}, 372 .reg_size = {}, 373 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 374 }, 375 #else 376 {}, 377 #endif 378 { /* RXDMA_MONITOR_STATUS */ 379 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 380 .max_rings = 0, 381 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 382 .lmac_ring = TRUE, 383 .ring_dir = HAL_SRNG_SRC_RING, 384 /* reg_start is not set because LMAC rings are not accessed 385 * from host 386 */ 387 .reg_start = {}, 388 .reg_size = {}, 389 .max_size = HAL_RXDMA_MAX_RING_SIZE, 390 }, 391 #ifdef QCA_MONITOR_2_0_SUPPORT 392 { /* RXDMA_MONITOR_DST */ 393 .start_ring_id = HAL_SRNG_WMAC1_RXMON2SW0, 394 .max_rings = 2, 395 .entry_size = sizeof(struct mon_destination_ring) >> 2, 396 .lmac_ring = TRUE, 397 .ring_dir = HAL_SRNG_DST_RING, 398 /* reg_start is not set because LMAC rings are not accessed 399 * from host 400 */ 401 .reg_start = {}, 402 .reg_size = {}, 403 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 404 }, 405 #else 406 {}, 407 #endif 408 { /* RXDMA_MONITOR_DESC */ 409 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 410 .max_rings = 0, 411 .entry_size = 0/*sizeof(struct sw_monitor_ring) >> 2*/, 412 .lmac_ring = TRUE, 413 .ring_dir = HAL_SRNG_DST_RING, 414 /* reg_start is not set because LMAC rings are not accessed 415 * from host 416 */ 417 .reg_start = {}, 418 .reg_size = {}, 419 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 420 }, 421 422 { /* DIR_BUF_RX_DMA_SRC */ 423 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 424 /* one ring for spectral, one ring for cfr and 425 * another one ring for txbf cv upload 426 */ 427 .max_rings = 3, 428 .entry_size = 2, 429 .lmac_ring = TRUE, 430 .ring_dir = HAL_SRNG_SRC_RING, 431 /* reg_start is not set because LMAC rings are not accessed 432 * from host 433 */ 434 .reg_start = {}, 435 .reg_size = {}, 436 .max_size = HAL_RXDMA_MAX_RING_SIZE, 437 }, 438 #ifdef WLAN_FEATURE_CIF_CFR 439 { /* WIFI_POS_SRC */ 440 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 441 .max_rings = 1, 442 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 443 .lmac_ring = TRUE, 444 .ring_dir = HAL_SRNG_SRC_RING, 445 /* reg_start is not set because LMAC rings are not accessed 446 * from host 447 */ 448 .reg_start = {}, 449 .reg_size = {}, 450 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 451 }, 452 #endif 453 { /* REO2PPE */ 454 .start_ring_id = HAL_SRNG_REO2PPE, 455 .max_rings = 1, 456 .entry_size = sizeof(struct reo_destination_ring) >> 2, 457 .lmac_ring = FALSE, 458 .ring_dir = HAL_SRNG_DST_RING, 459 .reg_start = { 460 HWIO_REO_R0_REO2PPE_RING_BASE_LSB_ADDR( 461 REO_REG_REG_BASE), 462 HWIO_REO_R2_REO2PPE_RING_HP_ADDR( 463 REO_REG_REG_BASE), 464 }, 465 /* Single ring - provide ring size if multiple rings of this 466 * type are supported 467 */ 468 .reg_size = {}, 469 .max_size = 470 HWIO_REO_R0_REO2PPE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK >> 471 HWIO_REO_R0_REO2PPE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT, 472 }, 473 { /* PPE2TCL */ 474 .start_ring_id = HAL_SRNG_PPE2TCL1, 475 .max_rings = 1, 476 .entry_size = sizeof(struct tcl_entrance_from_ppe_ring) >> 2, 477 .lmac_ring = FALSE, 478 .ring_dir = HAL_SRNG_SRC_RING, 479 .reg_start = { 480 HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_ADDR( 481 MAC_TCL_REG_REG_BASE), 482 HWIO_TCL_R2_PPE2TCL1_RING_HP_ADDR( 483 MAC_TCL_REG_REG_BASE), 484 }, 485 .reg_size = {}, 486 .max_size = 487 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 488 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 489 }, 490 { /* PPE_RELEASE */ 491 .start_ring_id = HAL_SRNG_WBM_PPE_RELEASE, 492 .max_rings = 1, 493 .entry_size = sizeof(struct wbm_release_ring) >> 2, 494 .lmac_ring = FALSE, 495 .ring_dir = HAL_SRNG_SRC_RING, 496 .reg_start = { 497 HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE), 498 HWIO_WBM_R2_PPE_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE), 499 }, 500 .reg_size = {}, 501 .max_size = 502 HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 503 HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 504 }, 505 #ifdef QCA_MONITOR_2_0_SUPPORT 506 { /* TX_MONITOR_BUF */ 507 .start_ring_id = HAL_SRNG_SW2TXMON_BUF0, 508 .max_rings = 1, 509 .entry_size = sizeof(struct mon_ingress_ring) >> 2, 510 .lmac_ring = TRUE, 511 .ring_dir = HAL_SRNG_SRC_RING, 512 /* reg_start is not set because LMAC rings are not accessed 513 * from host 514 */ 515 .reg_start = {}, 516 .reg_size = {}, 517 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 518 }, 519 { /* TX_MONITOR_DST */ 520 .start_ring_id = HAL_SRNG_WMAC1_TXMON2SW0, 521 .max_rings = 2, 522 .entry_size = sizeof(struct mon_destination_ring) >> 2, 523 .lmac_ring = TRUE, 524 .ring_dir = HAL_SRNG_DST_RING, 525 /* reg_start is not set because LMAC rings are not accessed 526 * from host 527 */ 528 .reg_start = {}, 529 .reg_size = {}, 530 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 531 }, 532 #else 533 {}, 534 {}, 535 #endif 536 { /* SW2RXDMA */ 537 .start_ring_id = HAL_SRNG_SW2RXDMA_BUF0, 538 .max_rings = 3, 539 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 540 .lmac_ring = TRUE, 541 .ring_dir = HAL_SRNG_SRC_RING, 542 /* reg_start is not set because LMAC rings are not accessed 543 * from host 544 */ 545 .reg_start = {}, 546 .reg_size = {}, 547 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 548 .dmac_cmn_ring = TRUE, 549 }, 550 }; 551 552 /** 553 * hal_reo_config_reo2ppe_dest_info_9224() - Configure reo2ppe dest info 554 * @hal_soc_hdl: HAL SoC Context 555 * 556 * Return: None. 557 */ 558 static inline 559 void hal_reo_config_reo2ppe_dest_info_9224(hal_soc_handle_t hal_soc_hdl) 560 { 561 HAL_REG_WRITE((struct hal_soc *)hal_soc_hdl, 562 HWIO_REO_R0_REO2PPE_DEST_INFO_ADDR(REO_REG_REG_BASE), 563 REO2PPE_RULE_FAIL_FB); 564 } 565 566 #define PMM_REG_BASE_QCN9224_V2 0xB500FC 567 568 /** 569 * hal_get_tsf2_scratch_reg_qcn9224_v2() - API to read tsf2 scratch register 570 * @hal_soc_hdl: HAL soc context 571 * @mac_id: mac id 572 * @value: Pointer to update tsf2 value 573 * 574 * Return: void 575 */ 576 static void hal_get_tsf2_scratch_reg_qcn9224_v2(hal_soc_handle_t hal_soc_hdl, 577 uint8_t mac_id, uint64_t *value) 578 { 579 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; 580 uint32_t offset_lo, offset_hi; 581 enum hal_scratch_reg_enum enum_lo, enum_hi; 582 583 hal_get_tsf_enum(DEFAULT_TSF_ID, mac_id, &enum_lo, &enum_hi); 584 585 offset_lo = hal_read_pmm_scratch_reg(soc, 586 PMM_REG_BASE_QCN9224_V2, 587 enum_lo); 588 589 offset_hi = hal_read_pmm_scratch_reg(soc, 590 PMM_REG_BASE_QCN9224_V2, 591 enum_hi); 592 593 *value = ((uint64_t)(offset_hi) << 32 | offset_lo); 594 } 595 596 /** 597 * hal_get_tqm_scratch_reg_qcn9224_v2() - API to read tqm scratch register 598 * @hal_soc_hdl: HAL soc context 599 * @value: Pointer to update tqm value 600 * 601 * Return: void 602 */ 603 static void hal_get_tqm_scratch_reg_qcn9224_v2(hal_soc_handle_t hal_soc_hdl, 604 uint64_t *value) 605 { 606 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; 607 uint32_t offset_lo, offset_hi; 608 609 offset_lo = hal_read_pmm_scratch_reg(soc, 610 PMM_REG_BASE_QCN9224_V2, 611 PMM_TQM_CLOCK_OFFSET_LO_US); 612 613 offset_hi = hal_read_pmm_scratch_reg(soc, 614 PMM_REG_BASE_QCN9224_V2, 615 PMM_TQM_CLOCK_OFFSET_HI_US); 616 617 *value = ((uint64_t)(offset_hi) << 32 | offset_lo); 618 } 619 620 static void hal_hw_txrx_ops_override_qcn9224_v2(struct hal_soc *hal_soc) 621 { 622 hal_soc->ops->hal_reo_config_reo2ppe_dest_info = 623 hal_reo_config_reo2ppe_dest_info_9224; 624 625 hal_soc->ops->hal_get_tsf2_scratch_reg = 626 hal_get_tsf2_scratch_reg_qcn9224_v2; 627 hal_soc->ops->hal_get_tqm_scratch_reg = 628 hal_get_tqm_scratch_reg_qcn9224_v2; 629 } 630 /** 631 * hal_qcn9224v2_attach() - Attach 9224v2 target specific hal_soc ops, 632 * offset and srng table 633 * @hal_soc: HAL SoC context 634 * 635 * Return: void 636 */ 637 void hal_qcn9224v2_attach(struct hal_soc *hal_soc) 638 { 639 hal_soc->hw_srng_table = hw_srng_table_9224v2; 640 641 hal_srng_hw_reg_offset_init_generic(hal_soc); 642 hal_srng_hw_reg_offset_init_qcn9224(hal_soc); 643 644 hal_hw_txrx_default_ops_attach_be(hal_soc); 645 hal_hw_txrx_ops_attach_qcn9224(hal_soc); 646 if (hal_soc->static_window_map) 647 hal_write_window_register(hal_soc); 648 hal_soc->dmac_cmn_src_rxbuf_ring = true; 649 650 hal_hw_txrx_ops_override_qcn9224_v2(hal_soc); 651 } 652