1 /* 2 * Copyright (c) 2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 #ifndef _HAL_9224_TX_H_ 20 #define _HAL_9224_TX_H_ 21 22 #include "tcl_data_cmd.h" 23 #include "phyrx_rssi_legacy.h" 24 #include "hal_internal.h" 25 #include "qdf_trace.h" 26 #include "hal_rx.h" 27 #include "hal_tx.h" 28 #include "hal_api_mon.h" 29 #include <hal_be_tx.h> 30 31 #define DSCP_TID_TABLE_SIZE 24 32 #define NUM_WORDS_PER_DSCP_TID_TABLE (DSCP_TID_TABLE_SIZE / 4) 33 #define HAL_TX_NUM_DSCP_REGISTER_SIZE 32 34 35 /** 36 * hal_tx_set_dscp_tid_map_9224() - Configure default DSCP to TID map table 37 * @soc: HAL SoC context 38 * @map: DSCP-TID mapping table 39 * @id: mapping table ID - 0-31 40 * 41 * DSCP are mapped to 8 TID values using TID values programmed 42 * in any of the 32 DSCP_TID_MAPS (id = 0-31). 43 * 44 * Return: none 45 */ 46 static void hal_tx_set_dscp_tid_map_9224(struct hal_soc *hal_soc, uint8_t *map, 47 uint8_t id) 48 { 49 int i; 50 uint32_t addr, cmn_reg_addr; 51 uint32_t value = 0, regval; 52 uint8_t val[DSCP_TID_TABLE_SIZE], cnt = 0; 53 54 struct hal_soc *soc = (struct hal_soc *)hal_soc; 55 56 if (id >= HAL_MAX_HW_DSCP_TID_V2_MAPS) 57 return; 58 59 cmn_reg_addr = HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR( 60 MAC_TCL_REG_REG_BASE); 61 62 addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR( 63 MAC_TCL_REG_REG_BASE, 64 id * NUM_WORDS_PER_DSCP_TID_TABLE); 65 66 /* Enable read/write access */ 67 regval = HAL_REG_READ(soc, cmn_reg_addr); 68 regval |= 69 (1 << 70 HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT); 71 72 HAL_REG_WRITE(soc, cmn_reg_addr, regval); 73 74 /* Write 8 (24 bits) DSCP-TID mappings in each interation */ 75 for (i = 0; i < 64; i += 8) { 76 value = (map[i] | 77 (map[i + 1] << 0x3) | 78 (map[i + 2] << 0x6) | 79 (map[i + 3] << 0x9) | 80 (map[i + 4] << 0xc) | 81 (map[i + 5] << 0xf) | 82 (map[i + 6] << 0x12) | 83 (map[i + 7] << 0x15)); 84 85 qdf_mem_copy(&val[cnt], (void *)&value, 3); 86 cnt += 3; 87 } 88 89 for (i = 0; i < DSCP_TID_TABLE_SIZE; i += 4) { 90 regval = *(uint32_t *)(val + i); 91 HAL_REG_WRITE(soc, addr, 92 (regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK)); 93 addr += 4; 94 } 95 96 /* Diasble read/write access */ 97 regval = HAL_REG_READ(soc, cmn_reg_addr); 98 regval &= 99 ~(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK); 100 101 HAL_REG_WRITE(soc, cmn_reg_addr, regval); 102 } 103 104 /** 105 * hal_tx_update_dscp_tid_9224() - Update the dscp tid map table as updated 106 * by the user 107 * @soc: HAL SoC context 108 * @map: DSCP-TID mapping table 109 * @id : MAP ID 110 * @dscp: DSCP_TID map index 111 * 112 * Return: void 113 */ 114 static void hal_tx_update_dscp_tid_9224(struct hal_soc *soc, uint8_t tid, 115 uint8_t id, uint8_t dscp) 116 { 117 uint32_t addr, addr1, cmn_reg_addr; 118 uint32_t start_value = 0, end_value = 0; 119 uint32_t regval; 120 uint8_t end_bits = 0; 121 uint8_t start_bits = 0; 122 uint32_t start_index, end_index; 123 124 cmn_reg_addr = HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR( 125 MAC_TCL_REG_REG_BASE); 126 127 addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR( 128 MAC_TCL_REG_REG_BASE, 129 id * NUM_WORDS_PER_DSCP_TID_TABLE); 130 131 start_index = dscp * HAL_TX_BITS_PER_TID; 132 end_index = (start_index + (HAL_TX_BITS_PER_TID - 1)) 133 % HAL_TX_NUM_DSCP_REGISTER_SIZE; 134 start_index = start_index % HAL_TX_NUM_DSCP_REGISTER_SIZE; 135 addr += (4 * ((dscp * HAL_TX_BITS_PER_TID) / 136 HAL_TX_NUM_DSCP_REGISTER_SIZE)); 137 138 if (end_index < start_index) { 139 end_bits = end_index + 1; 140 start_bits = HAL_TX_BITS_PER_TID - end_bits; 141 start_value = tid << start_index; 142 end_value = tid >> start_bits; 143 addr1 = addr + 4; 144 } else { 145 start_bits = HAL_TX_BITS_PER_TID - end_bits; 146 start_value = tid << start_index; 147 addr1 = 0; 148 } 149 150 /* Enable read/write access */ 151 regval = HAL_REG_READ(soc, cmn_reg_addr); 152 regval |= 153 (1 << HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT); 154 155 HAL_REG_WRITE(soc, cmn_reg_addr, regval); 156 157 regval = HAL_REG_READ(soc, addr); 158 159 if (end_index < start_index) 160 regval &= (~0) >> start_bits; 161 else 162 regval &= ~(7 << start_index); 163 164 regval |= start_value; 165 166 HAL_REG_WRITE(soc, addr, (regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK)); 167 168 if (addr1) { 169 regval = HAL_REG_READ(soc, addr1); 170 regval &= (~0) << end_bits; 171 regval |= end_value; 172 173 HAL_REG_WRITE(soc, addr1, (regval & 174 HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK)); 175 } 176 177 /* Diasble read/write access */ 178 regval = HAL_REG_READ(soc, cmn_reg_addr); 179 regval &= 180 ~(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK); 181 HAL_REG_WRITE(soc, cmn_reg_addr, regval); 182 } 183 184 #ifdef DP_TX_IMPLICIT_RBM_MAPPING 185 186 #define RBM_MAPPING_BMSK HWIO_TCL_R0_RBM_MAPPING0_SW2TCL1_RING_BMSK 187 #define RBM_MAPPING_SHFT HWIO_TCL_R0_RBM_MAPPING0_SW2TCL2_RING_SHFT 188 189 #define RBM_PPE2TCL_OFFSET \ 190 (HWIO_TCL_R0_RBM_MAPPING0_PPE2TCL1_RING_SHFT >> 2) 191 #define RBM_TCL_CMD_CREDIT_OFFSET \ 192 (HWIO_TCL_R0_RBM_MAPPING0_SW2TCL_CREDIT_RING_SHFT >> 2) 193 194 /** 195 * hal_tx_config_rbm_mapping_be() - Update return buffer manager ring id 196 * @hal_soc: HAL SoC context 197 * @hal_ring_hdl: Source ring pointer 198 * @rbm_id: return buffer manager ring id 199 * 200 * Return: void 201 */ 202 static inline void 203 hal_tx_config_rbm_mapping_be_9224(hal_soc_handle_t hal_soc_hdl, 204 hal_ring_handle_t hal_ring_hdl, 205 uint8_t rbm_id) 206 { 207 struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl; 208 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 209 uint32_t reg_addr = 0; 210 uint32_t reg_val = 0; 211 uint32_t val = 0; 212 uint8_t ring_num; 213 enum hal_ring_type ring_type; 214 215 ring_type = srng->ring_type; 216 ring_num = hal_soc->hw_srng_table[ring_type].start_ring_id; 217 ring_num = srng->ring_id - ring_num; 218 219 reg_addr = HWIO_TCL_R0_RBM_MAPPING0_ADDR(MAC_TCL_REG_REG_BASE); 220 221 if (ring_type == PPE2TCL) 222 ring_num = ring_num + RBM_PPE2TCL_OFFSET; 223 else if (ring_type == TCL_CMD_CREDIT) 224 ring_num = ring_num + RBM_TCL_CMD_CREDIT_OFFSET; 225 226 /* get current value stored in register address */ 227 val = HAL_REG_READ(hal_soc, reg_addr); 228 229 /* mask out other stored value */ 230 val &= (~(RBM_MAPPING_BMSK << (RBM_MAPPING_SHFT * ring_num))); 231 232 reg_val = val | ((RBM_MAPPING_BMSK & rbm_id) << 233 (RBM_MAPPING_SHFT * ring_num)); 234 235 /* write rbm mapped value to register address */ 236 HAL_REG_WRITE(hal_soc, reg_addr, reg_val); 237 } 238 #else 239 static inline void 240 hal_tx_config_rbm_mapping_be_9224(hal_soc_handle_t hal_soc_hdl, 241 hal_ring_handle_t hal_ring_hdl, 242 uint8_t rbm_id) 243 { 244 } 245 #endif 246 247 /** 248 * hal_tx_init_cmd_credit_ring_9224() - Initialize command/credit SRNG 249 * @hal_soc_hdl: Handle to HAL SoC structure 250 * @hal_srng: Handle to HAL SRNG structure 251 * 252 * Return: none 253 */ 254 static inline void 255 hal_tx_init_cmd_credit_ring_9224(hal_soc_handle_t hal_soc_hdl, 256 hal_ring_handle_t hal_ring_hdl) 257 { 258 } 259 260 /* TX MONITOR */ 261 #ifdef QCA_MONITOR_2_0_SUPPORT 262 263 #if defined(TX_MONITOR_WORD_MASK) 264 typedef struct tx_fes_setup_compact_9224 hal_tx_fes_setup_t; 265 struct tx_fes_setup_compact_9224 { 266 /* DWORD - 0 */ 267 uint32_t schedule_id; 268 /* DWORD - 1 */ 269 uint32_t reserved_1a : 7, // [0: 6] 270 transmit_start_reason : 3, // [7: 9] 271 reserved_1b : 13, // [10: 22] 272 number_of_users : 6, // [28: 23] 273 MU_type : 1, // [29] 274 reserved_1c : 2; // [30] 275 /* DWORD - 2 */ 276 uint32_t reserved_2a : 4, // [0: 3] 277 ndp_frame : 2, // [4: 5] 278 txbf : 1, // [6] 279 reserved_2b : 3, // [7: 9] 280 static_bandwidth : 3, // [12: 10] 281 reserved_2c : 1, // [13] 282 transmission_contains_MU_RTS : 1, // [14] 283 reserved_2d : 17; // [15: 31] 284 /* DWORD - 3 */ 285 uint32_t reserved_3a : 15, // [0: 14] 286 mu_ndp : 1, // [15] 287 reserved_3b : 11, // [16: 26] 288 ndpa : 1, // [27] 289 reserved_3c : 4; // [28: 31] 290 }; 291 #endif 292 #endif /* QCA_MONITOR_2_0_SUPPORT */ 293 /** 294 * hal_tx_set_ppe_cmn_config_9224() - Set the PPE common config register 295 * @hal_soc_hdl: HAL SoC handle 296 * @cmn_cfg: Common PPE config 297 * 298 * Based on the PPE2TCL descriptor below errors, if the below register 299 * values are set then the packets are forward to Tx rule handler if 1'0b 300 * or to TCL exit base if 1'1b. 301 * 302 * Return: void 303 */ 304 static inline 305 void hal_tx_set_ppe_cmn_config_9224(hal_soc_handle_t hal_soc_hdl, 306 union hal_tx_cmn_config_ppe *cmn_cfg) 307 { 308 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; 309 union hal_tx_cmn_config_ppe *cfg = 310 (union hal_tx_cmn_config_ppe *)cmn_cfg; 311 uint32_t reg_addr, reg_val = 0; 312 313 reg_addr = HWIO_TCL_R0_CMN_CONFIG_PPE_ADDR(MAC_TCL_REG_REG_BASE); 314 315 reg_val = HAL_REG_READ(soc, reg_addr); 316 317 reg_val &= ~HWIO_TCL_R0_CMN_CONFIG_PPE_DROP_PREC_ERR_EXCEPTION_BMSK; 318 reg_val |= 319 (cfg->drop_prec_err & 320 HWIO_TCL_R0_CMN_CONFIG_PPE_DROP_PREC_ERR_EXCEPTION_BMSK) << 321 HWIO_TCL_R0_CMN_CONFIG_PPE_DROP_PREC_ERR_EXCEPTION_SHFT; 322 323 reg_val &= ~HWIO_TCL_R0_CMN_CONFIG_PPE_FAKE_MAC_HDR_EXCEPTION_BMSK; 324 reg_val |= 325 (cfg->fake_mac_hdr & 326 HWIO_TCL_R0_CMN_CONFIG_PPE_FAKE_MAC_HDR_EXCEPTION_BMSK) << 327 HWIO_TCL_R0_CMN_CONFIG_PPE_FAKE_MAC_HDR_EXCEPTION_SHFT; 328 329 reg_val &= ~HWIO_TCL_R0_CMN_CONFIG_PPE_CPU_CODE_VALID_EXCEPTION_BMSK; 330 reg_val |= 331 (cfg->cpu_code_inv & 332 HWIO_TCL_R0_CMN_CONFIG_PPE_CPU_CODE_VALID_EXCEPTION_BMSK) << 333 HWIO_TCL_R0_CMN_CONFIG_PPE_CPU_CODE_VALID_EXCEPTION_SHFT; 334 335 reg_val &= ~HWIO_TCL_R0_CMN_CONFIG_PPE_L3_L4_CSUM_ERR_EXCEPTION_BMSK; 336 reg_val |= 337 (cfg->l3_l4_err & 338 HWIO_TCL_R0_CMN_CONFIG_PPE_L3_L4_CSUM_ERR_EXCEPTION_BMSK) << 339 HWIO_TCL_R0_CMN_CONFIG_PPE_L3_L4_CSUM_ERR_EXCEPTION_SHFT; 340 341 HAL_REG_WRITE(soc, reg_addr, reg_val); 342 } 343 344 /** 345 * hal_tx_set_ppe_vp_entry_9224() - Set the PPE VP entry 346 * @hal_soc_hdl: HAL SoC handle 347 * @vp_cfg: PPE VP config 348 * @ppe_vp_idx : PPE VP index to the table 349 * 350 * Return: void 351 */ 352 static inline 353 void hal_tx_set_ppe_vp_entry_9224(hal_soc_handle_t hal_soc_hdl, 354 union hal_tx_ppe_vp_config *cfg, 355 int ppe_vp_idx) 356 { 357 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; 358 uint32_t reg_addr, reg_val = 0; 359 360 reg_addr = HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_ADDR(MAC_TCL_REG_REG_BASE, 361 ppe_vp_idx); 362 363 /* 364 * Drop precedence is enabled by default. 365 */ 366 reg_val = HAL_REG_READ(soc, reg_addr); 367 368 reg_val &= ~HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_VP_NUM_BMSK; 369 reg_val |= (cfg->vp_num & 370 HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_VP_NUM_BMSK) << 371 HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_VP_NUM_SHFT; 372 373 reg_val &= ~HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_PMAC_ID_BMSK; 374 reg_val |= (cfg->pmac_id & 375 HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_PMAC_ID_BMSK) << 376 HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_PMAC_ID_SHFT; 377 378 reg_val &= ~HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_BANK_ID_BMSK; 379 reg_val |= (cfg->bank_id & 380 HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_BANK_ID_BMSK) << 381 HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_BANK_ID_SHFT; 382 383 reg_val &= ~HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_VDEV_ID_BMSK; 384 reg_val |= (cfg->vdev_id & 385 HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_VDEV_ID_BMSK) << 386 HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_VDEV_ID_SHFT; 387 388 reg_val &= ~HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_SEARCH_INDEX_REG_NUM_BMSK; 389 reg_val |= 390 (cfg->search_idx_reg_num & 391 HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_SEARCH_INDEX_REG_NUM_BMSK) << 392 HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_SEARCH_INDEX_REG_NUM_SHFT; 393 394 reg_val &= 395 ~HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_USE_PPE_INT_PRI_FOR_TID_BMSK; 396 reg_val |= 397 (cfg->use_ppe_int_pri & 398 HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_USE_PPE_INT_PRI_FOR_TID_BMSK) << 399 HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_USE_PPE_INT_PRI_FOR_TID_SHFT; 400 401 reg_val &= ~HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_TO_FW_BMSK; 402 reg_val |= (cfg->to_fw & 403 HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_TO_FW_BMSK) << 404 HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_TO_FW_SHFT; 405 406 reg_val &= ~HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_DROP_PREC_ENABLE_BMSK; 407 reg_val |= (cfg->drop_prec_enable & 408 HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_DROP_PREC_ENABLE_BMSK) << 409 HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_DROP_PREC_ENABLE_SHFT; 410 411 HAL_REG_WRITE(soc, reg_addr, reg_val); 412 } 413 414 /** 415 * hal_tx_set_ppe_pri2tid_map1_9224() 416 * @hal_soc_hdl: HAL SoC handle 417 * @val : PRI to TID value 418 * @map_no: Map number 419 * 420 * Return: void 421 */ 422 static inline 423 void hal_tx_set_ppe_pri2tid_map_9224(hal_soc_handle_t hal_soc_hdl, 424 uint32_t val, uint8_t map_no) 425 { 426 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; 427 uint32_t reg_addr, reg_val = 0; 428 429 if (map_no == 0) 430 reg_addr = 431 HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_ADDR(MAC_TCL_REG_REG_BASE); 432 else 433 reg_addr = 434 HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_ADDR(MAC_TCL_REG_REG_BASE); 435 436 reg_val |= val; 437 HAL_REG_WRITE(soc, reg_addr, reg_val); 438 } 439 440 /** 441 * hal_tx_set_ppe_pri2tid_map1_9224() 442 * @hal_soc_hdl: HAL SoC handle 443 * @val : PRI to TID value 444 * @map_no: Map number 445 * 446 * Return: void 447 */ 448 static inline 449 void hal_tx_enable_pri2tid_map_9224(hal_soc_handle_t hal_soc_hdl, 450 bool val, uint8_t ppe_vp_idx) 451 { 452 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; 453 uint32_t reg_addr, reg_val = 0; 454 455 reg_addr = HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_ADDR(MAC_TCL_REG_REG_BASE, 456 ppe_vp_idx); 457 458 /* 459 * Drop precedence is enabled by default. 460 */ 461 reg_val = HAL_REG_READ(soc, reg_addr); 462 463 reg_val &= 464 ~HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_USE_PPE_INT_PRI_FOR_TID_BMSK; 465 466 reg_val |= 467 (val & 468 HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_USE_PPE_INT_PRI_FOR_TID_BMSK) << 469 HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_USE_PPE_INT_PRI_FOR_TID_SHFT; 470 471 HAL_REG_WRITE(soc, reg_addr, reg_val); 472 } 473 474 /** 475 * hal_tx_update_ppe_pri2tid_9224() 476 * @hal_soc_hdl: HAL SoC handle 477 * @pri: INT_PRI 478 * @tid: Wi-Fi TID 479 * 480 * Return: void 481 */ 482 static inline 483 void hal_tx_update_ppe_pri2tid_9224(hal_soc_handle_t hal_soc_hdl, 484 uint8_t pri, uint8_t tid) 485 { 486 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; 487 uint32_t reg_addr, reg_val = 0, mask, shift; 488 489 /* 490 * INT_PRI 0..9 is in MAP0 register and INT_PRI 10..15 491 * is in MAP1 register. 492 */ 493 switch (pri) { 494 case 0 ... 9: 495 reg_addr = 496 HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_ADDR(MAC_TCL_REG_REG_BASE); 497 mask = 498 (HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_0_BMSK << (0x3 * pri)); 499 shift = HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_0_SHFT + (pri * 0x3); 500 break; 501 case 10 ... 15: 502 pri = pri - 10; 503 reg_addr = 504 HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_ADDR(MAC_TCL_REG_REG_BASE); 505 mask = 506 (HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_10_BMSK << (0x3 * pri)); 507 shift = 508 HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_10_SHFT + (pri * 0x3); 509 break; 510 default: 511 return; 512 } 513 514 reg_val = HAL_REG_READ(soc, reg_addr); 515 reg_val &= ~mask; 516 reg_val |= (pri << shift) & mask; 517 518 HAL_REG_WRITE(soc, reg_addr, reg_val); 519 } 520 #endif /* _HAL_9224_TX_H_ */ 521