1 /* 2 * Copyright (c) 2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 #ifndef _HAL_9224_TX_H_ 20 #define _HAL_9224_TX_H_ 21 22 #include "tcl_data_cmd.h" 23 #include "phyrx_rssi_legacy.h" 24 #include "hal_internal.h" 25 #include "qdf_trace.h" 26 #include "hal_rx.h" 27 #include "hal_tx.h" 28 #include "hal_api_mon.h" 29 #include <hal_be_tx.h> 30 31 #define DSCP_TID_TABLE_SIZE 24 32 #define NUM_WORDS_PER_DSCP_TID_TABLE (DSCP_TID_TABLE_SIZE / 4) 33 #define HAL_TX_NUM_DSCP_REGISTER_SIZE 32 34 35 /** 36 * hal_tx_ppe2tcl_ring_halt_set() - Enable ring halt for the ppe2tcl ring 37 * @hal_soc: HAL SoC context 38 * 39 * Return: none 40 */ 41 static void hal_tx_ppe2tcl_ring_halt_set_9224(hal_soc_handle_t hal_soc) 42 { 43 uint32_t cmn_reg_addr; 44 uint32_t regval; 45 struct hal_soc *soc = (struct hal_soc *)hal_soc; 46 47 cmn_reg_addr = 48 HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(MAC_TCL_REG_REG_BASE); 49 50 /* Enable RING_HALT */ 51 regval = HAL_REG_READ(soc, cmn_reg_addr); 52 regval |= 53 (1 << 54 HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PPE2TCL1_RNG_HALT_SHFT); 55 56 HAL_REG_WRITE(soc, cmn_reg_addr, regval); 57 } 58 59 /** 60 * hal_tx_ppe2tcl_ring_halt_reset() - Disable ring halt for the ppe2tcl ring 61 * @hal_soc: HAL SoC context 62 * 63 * Return: none 64 */ 65 static void hal_tx_ppe2tcl_ring_halt_reset_9224(hal_soc_handle_t hal_soc) 66 { 67 uint32_t cmn_reg_addr; 68 uint32_t regval; 69 struct hal_soc *soc = (struct hal_soc *)hal_soc; 70 71 cmn_reg_addr = 72 HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(MAC_TCL_REG_REG_BASE); 73 74 /* Disable RING_HALT */ 75 regval = HAL_REG_READ(soc, cmn_reg_addr); 76 regval &= ~(1 << 77 HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PPE2TCL1_RNG_HALT_SHFT); 78 79 HAL_REG_WRITE(soc, cmn_reg_addr, regval); 80 } 81 82 /** 83 * hal_tx_ppe2tcl_ring_halt_done() - Check if ring halt is done for ppe2tcl ring 84 * @hal_soc: HAL SoC context 85 * 86 * Return: true if halt done 87 */ 88 static bool hal_tx_ppe2tcl_ring_halt_done_9224(hal_soc_handle_t hal_soc) 89 { 90 uint32_t cmn_reg_addr; 91 uint32_t regval; 92 struct hal_soc *soc = (struct hal_soc *)hal_soc; 93 94 cmn_reg_addr = 95 HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(MAC_TCL_REG_REG_BASE); 96 97 regval = HAL_REG_READ(soc, cmn_reg_addr); 98 regval &= (1 << HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PPE2TCL1_RNG_HALT_STAT_SHFT); 99 100 return(!!regval); 101 } 102 103 /** 104 * hal_tx_set_dscp_tid_map_9224() - Configure default DSCP to TID map table 105 * @soc: HAL SoC context 106 * @map: DSCP-TID mapping table 107 * @id: mapping table ID - 0-31 108 * 109 * DSCP are mapped to 8 TID values using TID values programmed 110 * in any of the 32 DSCP_TID_MAPS (id = 0-31). 111 * 112 * Return: none 113 */ 114 static void hal_tx_set_dscp_tid_map_9224(struct hal_soc *hal_soc, uint8_t *map, 115 uint8_t id) 116 { 117 int i; 118 uint32_t addr, cmn_reg_addr; 119 uint32_t value = 0, regval; 120 uint8_t val[DSCP_TID_TABLE_SIZE], cnt = 0; 121 122 struct hal_soc *soc = (struct hal_soc *)hal_soc; 123 124 if (id >= HAL_MAX_HW_DSCP_TID_V2_MAPS) 125 return; 126 127 cmn_reg_addr = HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR( 128 MAC_TCL_REG_REG_BASE); 129 130 addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR( 131 MAC_TCL_REG_REG_BASE, 132 id * NUM_WORDS_PER_DSCP_TID_TABLE); 133 134 /* Enable read/write access */ 135 regval = HAL_REG_READ(soc, cmn_reg_addr); 136 regval |= 137 (1 << 138 HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT); 139 140 HAL_REG_WRITE(soc, cmn_reg_addr, regval); 141 142 /* Write 8 (24 bits) DSCP-TID mappings in each iteration */ 143 for (i = 0; i < 64; i += 8) { 144 value = (map[i] | 145 (map[i + 1] << 0x3) | 146 (map[i + 2] << 0x6) | 147 (map[i + 3] << 0x9) | 148 (map[i + 4] << 0xc) | 149 (map[i + 5] << 0xf) | 150 (map[i + 6] << 0x12) | 151 (map[i + 7] << 0x15)); 152 153 qdf_mem_copy(&val[cnt], (void *)&value, 3); 154 cnt += 3; 155 } 156 157 for (i = 0; i < DSCP_TID_TABLE_SIZE; i += 4) { 158 regval = *(uint32_t *)(val + i); 159 HAL_REG_WRITE(soc, addr, 160 (regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK)); 161 addr += 4; 162 } 163 164 /* Diasble read/write access */ 165 regval = HAL_REG_READ(soc, cmn_reg_addr); 166 regval &= 167 ~(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK); 168 169 HAL_REG_WRITE(soc, cmn_reg_addr, regval); 170 } 171 172 /** 173 * hal_tx_update_dscp_tid_9224() - Update the dscp tid map table as updated 174 * by the user 175 * @soc: HAL SoC context 176 * @map: DSCP-TID mapping table 177 * @id : MAP ID 178 * @dscp: DSCP_TID map index 179 * 180 * Return: void 181 */ 182 static void hal_tx_update_dscp_tid_9224(struct hal_soc *soc, uint8_t tid, 183 uint8_t id, uint8_t dscp) 184 { 185 uint32_t addr, addr1, cmn_reg_addr; 186 uint32_t start_value = 0, end_value = 0; 187 uint32_t regval; 188 uint8_t end_bits = 0; 189 uint8_t start_bits = 0; 190 uint32_t start_index, end_index; 191 192 cmn_reg_addr = HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR( 193 MAC_TCL_REG_REG_BASE); 194 195 addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR( 196 MAC_TCL_REG_REG_BASE, 197 id * NUM_WORDS_PER_DSCP_TID_TABLE); 198 199 start_index = dscp * HAL_TX_BITS_PER_TID; 200 end_index = (start_index + (HAL_TX_BITS_PER_TID - 1)) 201 % HAL_TX_NUM_DSCP_REGISTER_SIZE; 202 start_index = start_index % HAL_TX_NUM_DSCP_REGISTER_SIZE; 203 addr += (4 * ((dscp * HAL_TX_BITS_PER_TID) / 204 HAL_TX_NUM_DSCP_REGISTER_SIZE)); 205 206 if (end_index < start_index) { 207 end_bits = end_index + 1; 208 start_bits = HAL_TX_BITS_PER_TID - end_bits; 209 start_value = tid << start_index; 210 end_value = tid >> start_bits; 211 addr1 = addr + 4; 212 } else { 213 start_bits = HAL_TX_BITS_PER_TID - end_bits; 214 start_value = tid << start_index; 215 addr1 = 0; 216 } 217 218 /* Enable read/write access */ 219 regval = HAL_REG_READ(soc, cmn_reg_addr); 220 regval |= 221 (1 << HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT); 222 223 HAL_REG_WRITE(soc, cmn_reg_addr, regval); 224 225 regval = HAL_REG_READ(soc, addr); 226 227 if (end_index < start_index) 228 regval &= (~0) >> start_bits; 229 else 230 regval &= ~(7 << start_index); 231 232 regval |= start_value; 233 234 HAL_REG_WRITE(soc, addr, (regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK)); 235 236 if (addr1) { 237 regval = HAL_REG_READ(soc, addr1); 238 regval &= (~0) << end_bits; 239 regval |= end_value; 240 241 HAL_REG_WRITE(soc, addr1, (regval & 242 HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK)); 243 } 244 245 /* Diasble read/write access */ 246 regval = HAL_REG_READ(soc, cmn_reg_addr); 247 regval &= 248 ~(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK); 249 HAL_REG_WRITE(soc, cmn_reg_addr, regval); 250 } 251 252 #ifdef DP_TX_IMPLICIT_RBM_MAPPING 253 254 #define RBM_MAPPING_BMSK HWIO_TCL_R0_RBM_MAPPING0_SW2TCL1_RING_BMSK 255 #define RBM_MAPPING_SHFT HWIO_TCL_R0_RBM_MAPPING0_SW2TCL2_RING_SHFT 256 257 #define RBM_PPE2TCL_OFFSET \ 258 (HWIO_TCL_R0_RBM_MAPPING0_PPE2TCL1_RING_SHFT >> 2) 259 #define RBM_TCL_CMD_CREDIT_OFFSET \ 260 (HWIO_TCL_R0_RBM_MAPPING0_SW2TCL_CREDIT_RING_SHFT >> 2) 261 262 /** 263 * hal_tx_config_rbm_mapping_be() - Update return buffer manager ring id 264 * @hal_soc: HAL SoC context 265 * @hal_ring_hdl: Source ring pointer 266 * @rbm_id: return buffer manager ring id 267 * 268 * Return: void 269 */ 270 static inline void 271 hal_tx_config_rbm_mapping_be_9224(hal_soc_handle_t hal_soc_hdl, 272 hal_ring_handle_t hal_ring_hdl, 273 uint8_t rbm_id) 274 { 275 struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl; 276 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 277 uint32_t reg_addr = 0; 278 uint32_t reg_val = 0; 279 uint32_t val = 0; 280 uint8_t ring_num; 281 enum hal_ring_type ring_type; 282 283 ring_type = srng->ring_type; 284 ring_num = hal_soc->hw_srng_table[ring_type].start_ring_id; 285 ring_num = srng->ring_id - ring_num; 286 287 reg_addr = HWIO_TCL_R0_RBM_MAPPING0_ADDR(MAC_TCL_REG_REG_BASE); 288 289 if (ring_type == PPE2TCL) 290 ring_num = ring_num + RBM_PPE2TCL_OFFSET; 291 else if (ring_type == TCL_CMD_CREDIT) 292 ring_num = ring_num + RBM_TCL_CMD_CREDIT_OFFSET; 293 294 /* get current value stored in register address */ 295 val = HAL_REG_READ(hal_soc, reg_addr); 296 297 /* mask out other stored value */ 298 val &= (~(RBM_MAPPING_BMSK << (RBM_MAPPING_SHFT * ring_num))); 299 300 reg_val = val | ((RBM_MAPPING_BMSK & rbm_id) << 301 (RBM_MAPPING_SHFT * ring_num)); 302 303 /* write rbm mapped value to register address */ 304 HAL_REG_WRITE(hal_soc, reg_addr, reg_val); 305 } 306 #else 307 static inline void 308 hal_tx_config_rbm_mapping_be_9224(hal_soc_handle_t hal_soc_hdl, 309 hal_ring_handle_t hal_ring_hdl, 310 uint8_t rbm_id) 311 { 312 } 313 #endif 314 315 /** 316 * hal_tx_init_cmd_credit_ring_9224() - Initialize command/credit SRNG 317 * @hal_soc_hdl: Handle to HAL SoC structure 318 * @hal_srng: Handle to HAL SRNG structure 319 * 320 * Return: none 321 */ 322 static inline void 323 hal_tx_init_cmd_credit_ring_9224(hal_soc_handle_t hal_soc_hdl, 324 hal_ring_handle_t hal_ring_hdl) 325 { 326 } 327 328 /* TX MONITOR */ 329 #ifdef QCA_MONITOR_2_0_SUPPORT 330 331 #if defined(TX_MONITOR_WORD_MASK) 332 typedef struct tx_fes_setup_compact_9224 hal_tx_fes_setup_t; 333 struct tx_fes_setup_compact_9224 { 334 /* DWORD - 0 */ 335 uint32_t schedule_id; 336 /* DWORD - 1 */ 337 uint32_t reserved_1a : 7, // [0: 6] 338 transmit_start_reason : 3, // [7: 9] 339 reserved_1b : 13, // [10: 22] 340 number_of_users : 6, // [28: 23] 341 MU_type : 1, // [29] 342 reserved_1c : 2; // [30] 343 /* DWORD - 2 */ 344 uint32_t reserved_2a : 4, // [0: 3] 345 ndp_frame : 2, // [4: 5] 346 txbf : 1, // [6] 347 reserved_2b : 3, // [7: 9] 348 static_bandwidth : 3, // [12: 10] 349 reserved_2c : 1, // [13] 350 transmission_contains_MU_RTS : 1, // [14] 351 reserved_2d : 17; // [15: 31] 352 /* DWORD - 3 */ 353 uint32_t reserved_3a : 15, // [0: 14] 354 mu_ndp : 1, // [15] 355 reserved_3b : 11, // [16: 26] 356 ndpa : 1, // [27] 357 reserved_3c : 4; // [28: 31] 358 }; 359 #endif 360 #endif /* QCA_MONITOR_2_0_SUPPORT */ 361 /** 362 * hal_tx_set_ppe_cmn_config_9224() - Set the PPE common config register 363 * @hal_soc_hdl: HAL SoC handle 364 * @cmn_cfg: Common PPE config 365 * 366 * Based on the PPE2TCL descriptor below errors, if the below register 367 * values are set then the packets are forward to Tx rule handler if 1'0b 368 * or to TCL exit base if 1'1b. 369 * 370 * Return: void 371 */ 372 static inline 373 void hal_tx_set_ppe_cmn_config_9224(hal_soc_handle_t hal_soc_hdl, 374 union hal_tx_cmn_config_ppe *cmn_cfg) 375 { 376 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; 377 union hal_tx_cmn_config_ppe *cfg = 378 (union hal_tx_cmn_config_ppe *)cmn_cfg; 379 uint32_t reg_addr, reg_val = 0; 380 381 reg_addr = HWIO_TCL_R0_CMN_CONFIG_PPE_ADDR(MAC_TCL_REG_REG_BASE); 382 383 reg_val = HAL_REG_READ(soc, reg_addr); 384 385 reg_val &= ~HWIO_TCL_R0_CMN_CONFIG_PPE_DROP_PREC_ERR_EXCEPTION_BMSK; 386 reg_val |= 387 (cfg->drop_prec_err & 388 HWIO_TCL_R0_CMN_CONFIG_PPE_DROP_PREC_ERR_EXCEPTION_BMSK) << 389 HWIO_TCL_R0_CMN_CONFIG_PPE_DROP_PREC_ERR_EXCEPTION_SHFT; 390 391 reg_val &= ~HWIO_TCL_R0_CMN_CONFIG_PPE_FAKE_MAC_HDR_EXCEPTION_BMSK; 392 reg_val |= 393 (cfg->fake_mac_hdr & 394 HWIO_TCL_R0_CMN_CONFIG_PPE_FAKE_MAC_HDR_EXCEPTION_BMSK) << 395 HWIO_TCL_R0_CMN_CONFIG_PPE_FAKE_MAC_HDR_EXCEPTION_SHFT; 396 397 reg_val &= ~HWIO_TCL_R0_CMN_CONFIG_PPE_CPU_CODE_VALID_EXCEPTION_BMSK; 398 reg_val |= 399 (cfg->cpu_code_inv & 400 HWIO_TCL_R0_CMN_CONFIG_PPE_CPU_CODE_VALID_EXCEPTION_BMSK) << 401 HWIO_TCL_R0_CMN_CONFIG_PPE_CPU_CODE_VALID_EXCEPTION_SHFT; 402 403 reg_val &= ~HWIO_TCL_R0_CMN_CONFIG_PPE_L3_L4_CSUM_ERR_EXCEPTION_BMSK; 404 reg_val |= 405 (cfg->l3_l4_err & 406 HWIO_TCL_R0_CMN_CONFIG_PPE_L3_L4_CSUM_ERR_EXCEPTION_BMSK) << 407 HWIO_TCL_R0_CMN_CONFIG_PPE_L3_L4_CSUM_ERR_EXCEPTION_SHFT; 408 409 HAL_REG_WRITE(soc, reg_addr, reg_val); 410 } 411 412 /** 413 * hal_tx_set_ppe_vp_entry_9224() - Set the PPE VP entry 414 * @hal_soc_hdl: HAL SoC handle 415 * @vp_cfg: PPE VP config 416 * @ppe_vp_idx : PPE VP index to the table 417 * 418 * Return: void 419 */ 420 static inline 421 void hal_tx_set_ppe_vp_entry_9224(hal_soc_handle_t hal_soc_hdl, 422 union hal_tx_ppe_vp_config *cfg, 423 int ppe_vp_idx) 424 { 425 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; 426 uint32_t reg_addr; 427 428 reg_addr = HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_ADDR(MAC_TCL_REG_REG_BASE, 429 ppe_vp_idx); 430 431 HAL_REG_WRITE(soc, reg_addr, cfg->val); 432 } 433 434 /** 435 * hal_ppeds_cfg_ast_override_map_reg_9224() - Set the PPE index mapping table 436 * @hal_soc_hdl: HAL SoC context 437 * @idx: index into the table 438 * @idx_map: HAL PPE INDESX MAPPING config 439 * 440 * Return: void 441 */ 442 static inline void 443 hal_ppeds_cfg_ast_override_map_reg_9224(hal_soc_handle_t hal_soc_hdl, 444 uint8_t idx, 445 union hal_tx_ppe_idx_map_config *idx_map) 446 { 447 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; 448 uint32_t reg_addr; 449 450 reg_addr = 451 HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_ADDR(MAC_TCL_REG_REG_BASE, 452 idx); 453 454 HAL_REG_WRITE(soc, reg_addr, idx_map->val); 455 } 456 457 /** 458 * hal_tx_set_ppe_pri2tid_map1_9224() 459 * @hal_soc_hdl: HAL SoC handle 460 * @val : PRI to TID value 461 * @map_no: Map number 462 * 463 * Return: void 464 */ 465 static inline 466 void hal_tx_set_ppe_pri2tid_map_9224(hal_soc_handle_t hal_soc_hdl, 467 uint32_t val, uint8_t map_no) 468 { 469 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; 470 uint32_t reg_addr, reg_val = 0; 471 472 if (map_no == 0) 473 reg_addr = 474 HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_ADDR(MAC_TCL_REG_REG_BASE); 475 else 476 reg_addr = 477 HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_ADDR(MAC_TCL_REG_REG_BASE); 478 479 reg_val |= val; 480 HAL_REG_WRITE(soc, reg_addr, reg_val); 481 } 482 483 /** 484 * hal_tx_set_ppe_pri2tid_map1_9224() 485 * @hal_soc_hdl: HAL SoC handle 486 * @val : PRI to TID value 487 * @map_no: Map number 488 * 489 * Return: void 490 */ 491 static inline 492 void hal_tx_enable_pri2tid_map_9224(hal_soc_handle_t hal_soc_hdl, 493 bool val, uint8_t ppe_vp_idx) 494 { 495 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; 496 uint32_t reg_addr, reg_val = 0; 497 498 reg_addr = HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_ADDR(MAC_TCL_REG_REG_BASE, 499 ppe_vp_idx); 500 501 /* 502 * Drop precedence is enabled by default. 503 */ 504 reg_val = HAL_REG_READ(soc, reg_addr); 505 506 reg_val &= 507 ~HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_USE_PPE_INT_PRI_FOR_TID_BMSK; 508 509 reg_val |= 510 (val & 511 HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_USE_PPE_INT_PRI_FOR_TID_BMSK) << 512 HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_USE_PPE_INT_PRI_FOR_TID_SHFT; 513 514 HAL_REG_WRITE(soc, reg_addr, reg_val); 515 } 516 517 /** 518 * hal_tx_update_ppe_pri2tid_9224() 519 * @hal_soc_hdl: HAL SoC handle 520 * @pri: INT_PRI 521 * @tid: Wi-Fi TID 522 * 523 * Return: void 524 */ 525 static inline 526 void hal_tx_update_ppe_pri2tid_9224(hal_soc_handle_t hal_soc_hdl, 527 uint8_t pri, uint8_t tid) 528 { 529 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; 530 uint32_t reg_addr, reg_val = 0, mask, shift; 531 532 /* 533 * INT_PRI 0..9 is in MAP0 register and INT_PRI 10..15 534 * is in MAP1 register. 535 */ 536 switch (pri) { 537 case 0 ... 9: 538 reg_addr = 539 HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_ADDR(MAC_TCL_REG_REG_BASE); 540 mask = 541 (HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_0_BMSK << (0x3 * pri)); 542 shift = HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_0_SHFT + (pri * 0x3); 543 break; 544 case 10 ... 15: 545 pri = pri - 10; 546 reg_addr = 547 HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_ADDR(MAC_TCL_REG_REG_BASE); 548 mask = 549 (HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_10_BMSK << (0x3 * pri)); 550 shift = 551 HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_10_SHFT + (pri * 0x3); 552 break; 553 default: 554 return; 555 } 556 557 reg_val = HAL_REG_READ(soc, reg_addr); 558 reg_val &= ~mask; 559 reg_val |= (pri << shift) & mask; 560 561 HAL_REG_WRITE(soc, reg_addr, reg_val); 562 } 563 #endif /* _HAL_9224_TX_H_ */ 564