1 /* 2 * Copyright (c) 2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _HAL_9224_RX_H_ 21 #define _HAL_9224_RX_H_ 22 #include "qdf_util.h" 23 #include "qdf_types.h" 24 #include "qdf_lock.h" 25 #include "qdf_mem.h" 26 #include "qdf_nbuf.h" 27 #include "tcl_data_cmd.h" 28 #include "phyrx_rssi_legacy.h" 29 #include "rx_msdu_start.h" 30 #include "tlv_tag_def.h" 31 #include "hal_hw_headers.h" 32 #include "hal_internal.h" 33 #include "cdp_txrx_mon_struct.h" 34 #include "qdf_trace.h" 35 #include "hal_rx.h" 36 #include "hal_tx.h" 37 #include "dp_types.h" 38 #include "hal_api_mon.h" 39 #include "phyrx_other_receive_info_ru_details.h" 40 #if (defined(WLAN_SA_API_ENABLE)) && (defined(QCA_WIFI_QCA9574)) 41 #include "phyrx_other_receive_info_su_evm_details.h" 42 #endif /* WLAN_SA_API_ENABLE && QCA_WIFI_QCA9574 */ 43 44 #define HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va) \ 45 (uint8_t *)(link_desc_va) + \ 46 RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 47 48 #define HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0) \ 49 (uint8_t *)(msdu0) + \ 50 RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 51 52 #define HAL_ENT_MPDU_DESC_INFO(ent_ring_desc) \ 53 (uint8_t *)(ent_ring_desc) + \ 54 RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 55 56 #define HAL_DST_MPDU_DESC_INFO(dst_ring_desc) \ 57 (uint8_t *)(dst_ring_desc) + \ 58 REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 59 60 #define HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start) \ 61 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO, MAC_ADDR_AD1_VALID) 62 63 #define HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start) \ 64 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO, SW_FRAME_GROUP_ID) 65 66 /* 67 * In Beryllium chipset msdu_start was removed and merged in msdu_end. 68 * Due to this valid contents will be present only in last msdu. 69 * After setting the 5th bit of spare control field, REO will copy the contents 70 * from last buffer to all the other buffers of MSDU. 71 */ 72 #define HAL_REO_MSDU_END_COPY 0x20 73 #define HAL_REO_R0_MISC_CTL_SPARE_CONTROL_SHFT 0 74 75 #define HAL_REO_R0_CONFIG(soc, reg_val, reo_params) \ 76 do { \ 77 reg_val &= \ 78 ~(HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK |\ 79 HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK); \ 80 reg_val |= \ 81 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 82 AGING_LIST_ENABLE, 1) | \ 83 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 84 AGING_FLUSH_ENABLE, 1); \ 85 HAL_REG_WRITE(soc, \ 86 HWIO_REO_R0_GENERAL_ENABLE_ADDR( \ 87 REO_REG_REG_BASE), \ 88 reg_val); \ 89 reg_val = HAL_REG_READ(soc, \ 90 HWIO_REO_R0_MISC_CTL_ADDR( \ 91 REO_REG_REG_BASE)); \ 92 reg_val &= ~(HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_BMSK); \ 93 reg_val |= HAL_SM(HWIO_REO_R0_MISC_CTL, \ 94 FRAGMENT_DEST_RING, \ 95 (reo_params)->frag_dst_ring); \ 96 reg_val |= ((HAL_REO_MSDU_END_COPY) << \ 97 HAL_REO_R0_MISC_CTL_SPARE_CONTROL_SHFT); \ 98 HAL_REG_WRITE(soc, \ 99 HWIO_REO_R0_MISC_CTL_ADDR( \ 100 REO_REG_REG_BASE), \ 101 reg_val); \ 102 } while (0) 103 104 #define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \ 105 ((struct rx_msdu_desc_info *) \ 106 _OFFSET_TO_BYTE_PTR(msdu_details_ptr, \ 107 UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET)) 108 109 #define HAL_RX_TLV_MSDU_DONE_COPY_GET(_rx_pkt_tlv) \ 110 HAL_RX_MSDU_END(_rx_pkt_tlv).msdu_done_copy 111 112 #define HAL_RX_LINK_DESC_MSDU0_PTR(link_desc) \ 113 ((struct rx_msdu_details *) \ 114 _OFFSET_TO_BYTE_PTR((link_desc),\ 115 RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET)) 116 117 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) 118 #define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_CHAN_CAPTURE_STATUS_BMASK 0x00000006 119 #define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_CHAN_CAPTURE_STATUS_LSB 1 120 #define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_CHAN_CAPTURE_STATUS_MSB 2 121 122 #define HAL_GET_RX_LOCATION_INFO_CHAN_CAPTURE_STATUS(rx_tlv) \ 123 ((HAL_RX_GET_64((rx_tlv), \ 124 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, \ 125 RTT_CFR_STATUS) & \ 126 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_CHAN_CAPTURE_STATUS_BMASK) >> \ 127 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_CHAN_CAPTURE_STATUS_LSB) 128 #endif 129 #endif 130