1 /* 2 * Copyright (c) 2021 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _HAL_9224_RX_H_ 20 #define _HAL_9224_RX_H_ 21 #include "qdf_util.h" 22 #include "qdf_types.h" 23 #include "qdf_lock.h" 24 #include "qdf_mem.h" 25 #include "qdf_nbuf.h" 26 #include "tcl_data_cmd.h" 27 #include "phyrx_rssi_legacy.h" 28 #include "rx_msdu_start.h" 29 #include "tlv_tag_def.h" 30 #include "hal_hw_headers.h" 31 #include "hal_internal.h" 32 #include "cdp_txrx_mon_struct.h" 33 #include "qdf_trace.h" 34 #include "hal_rx.h" 35 #include "hal_tx.h" 36 #include "dp_types.h" 37 #include "hal_api_mon.h" 38 #include "phyrx_other_receive_info_ru_details.h" 39 40 #define HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va) \ 41 (uint8_t *)(link_desc_va) + \ 42 RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 43 44 #define HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0) \ 45 (uint8_t *)(msdu0) + \ 46 RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 47 48 #define HAL_ENT_MPDU_DESC_INFO(ent_ring_desc) \ 49 (uint8_t *)(ent_ring_desc) + \ 50 RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 51 52 #define HAL_DST_MPDU_DESC_INFO(dst_ring_desc) \ 53 (uint8_t *)(dst_ring_desc) + \ 54 REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 55 56 #define HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start) \ 57 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO, MAC_ADDR_AD1_VALID) 58 59 #define HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start) \ 60 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO, SW_FRAME_GROUP_ID) 61 62 #define HAL_REO_R0_CONFIG(soc, reg_val, reo_params) \ 63 do { \ 64 reg_val &= \ 65 ~(HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK |\ 66 HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK); \ 67 reg_val |= \ 68 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 69 AGING_LIST_ENABLE, 1) | \ 70 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 71 AGING_FLUSH_ENABLE, 1); \ 72 HAL_REG_WRITE(soc, \ 73 HWIO_REO_R0_GENERAL_ENABLE_ADDR( \ 74 REO_REG_REG_BASE), \ 75 reg_val); \ 76 reg_val = HAL_REG_READ(soc, \ 77 HWIO_REO_R0_MISC_CTL_ADDR( \ 78 REO_REG_REG_BASE)); \ 79 reg_val &= ~(HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_BMSK); \ 80 reg_val |= HAL_SM(HWIO_REO_R0_MISC_CTL, \ 81 FRAGMENT_DEST_RING, \ 82 (reo_params)->frag_dst_ring); \ 83 reg_val &= (~HWIO_REO_R0_MISC_CTL_BAR_DEST_RING_BMSK | \ 84 (REO_REMAP_TCL << \ 85 HWIO_REO_R0_MISC_CTL_BAR_DEST_RING_SHFT)); \ 86 HAL_REG_WRITE(soc, \ 87 HWIO_REO_R0_MISC_CTL_ADDR(REO_REG_REG_BASE), \ 88 reg_val); \ 89 } while (0) 90 91 #define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \ 92 ((struct rx_msdu_desc_info *) \ 93 _OFFSET_TO_BYTE_PTR(msdu_details_ptr, \ 94 RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET)) 95 96 #define HAL_RX_LINK_DESC_MSDU0_PTR(link_desc) \ 97 ((struct rx_msdu_details *) \ 98 _OFFSET_TO_BYTE_PTR((link_desc),\ 99 RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET)) 100 101 #if defined(QCA_WIFI_WCN9224) && defined(WLAN_CFR_ENABLE) && \ 102 defined(WLAN_ENH_CFR_ENABLE) 103 104 static inline 105 void hal_rx_get_bb_info_9224(void *rx_tlv, 106 void *ppdu_info_hdl) 107 { 108 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 109 110 ppdu_info->cfr_info.bb_captured_channel = 111 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_CHANNEL); 112 113 ppdu_info->cfr_info.bb_captured_timeout = 114 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_TIMEOUT); 115 116 ppdu_info->cfr_info.bb_captured_reason = 117 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_REASON); 118 } 119 120 static inline 121 void hal_rx_get_rtt_info_9224(void *rx_tlv, 122 void *ppdu_info_hdl) 123 { 124 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 125 126 ppdu_info->cfr_info.rx_location_info_valid = 127 HAL_RX_GET(rx_tlv, PHYRX_LOCATION, 128 RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID); 129 130 ppdu_info->cfr_info.rtt_che_buffer_pointer_low32 = 131 HAL_RX_GET(rx_tlv, 132 RX_LOCATION_INFO, 133 RTT_CHE_BUFFER_POINTER_LOW32); 134 135 ppdu_info->cfr_info.rtt_che_buffer_pointer_high8 = 136 HAL_RX_GET(rx_tlv, 137 RX_LOCATION_INFO, 138 RTT_CHE_BUFFER_POINTER_HIGH8); 139 140 ppdu_info->cfr_info.chan_capture_status = 141 HAL_RX_GET(rx_tlv, 142 RX_LOCATION_INFO, 143 RESERVED_3); 144 } 145 #endif 146 #endif 147