1 /* 2 * Copyright (c) 2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 #include "qdf_types.h" 20 #include "qdf_util.h" 21 #include "qdf_mem.h" 22 #include "qdf_nbuf.h" 23 #include "qdf_module.h" 24 25 #include "target_type.h" 26 #include "wcss_version.h" 27 28 #include "hal_be_hw_headers.h" 29 #include "hal_internal.h" 30 #include "hal_api.h" 31 #include "hal_flow.h" 32 #include "rx_flow_search_entry.h" 33 #include "hal_rx_flow_info.h" 34 #include "hal_be_api.h" 35 #include "tcl_entrance_from_ppe_ring.h" 36 #include "sw_monitor_ring.h" 37 #include "wcss_seq_hwioreg_umac.h" 38 #include "wfss_ce_reg_seq_hwioreg.h" 39 #include <uniform_reo_status_header.h> 40 #include <wbm_release_ring_tx.h> 41 #include <phyrx_location.h> 42 #ifdef QCA_MONITOR_2_0_SUPPORT 43 #include <mon_ingress_ring.h> 44 #include <mon_destination_ring.h> 45 #endif 46 #include "rx_reo_queue_1k.h" 47 48 #include <hal_be_rx.h> 49 50 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 51 RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 52 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 53 RX_MSDU_LINK_MSDU_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 54 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 55 RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 56 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 57 RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 58 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 59 REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 60 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER \ 61 STATUS_HEADER_REO_STATUS_NUMBER 62 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 63 STATUS_HEADER_TIMESTAMP 64 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 65 RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 66 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 67 RX_MSDU_LINK_MSDU_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 68 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 69 TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 70 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 71 TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 72 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 73 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_OFFSET 74 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 75 BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 76 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 77 BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 78 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 79 BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB 80 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 81 BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK 82 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 83 BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 84 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 85 BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 86 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 87 BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB 88 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 89 BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK 90 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 91 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_LSB 92 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 93 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MASK 94 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 95 WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 96 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 97 WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 98 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 99 WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 100 101 #include "hal_be_api_mon.h" 102 103 #ifdef CONFIG_WIFI_EMULATION_WIFI_3_0 104 #define CMEM_REG_BASE 0x0010e000 105 106 #define CMEM_WINDOW_ADDRESS_9224 \ 107 ((CMEM_REG_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) 108 #endif 109 110 #define CE_WINDOW_ADDRESS_9224 \ 111 ((CE_WFSS_CE_REG_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) 112 113 #define UMAC_WINDOW_ADDRESS_9224 \ 114 ((UMAC_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) 115 116 #ifdef CONFIG_WIFI_EMULATION_WIFI_3_0 117 #define WINDOW_CONFIGURATION_VALUE_9224 \ 118 ((CE_WINDOW_ADDRESS_9224 << 6) |\ 119 (UMAC_WINDOW_ADDRESS_9224 << 12) | \ 120 CMEM_WINDOW_ADDRESS_9224 | \ 121 WINDOW_ENABLE_BIT) 122 #else 123 #define WINDOW_CONFIGURATION_VALUE_9224 \ 124 ((CE_WINDOW_ADDRESS_9224 << 6) |\ 125 (UMAC_WINDOW_ADDRESS_9224 << 12) | \ 126 WINDOW_ENABLE_BIT) 127 #endif 128 129 /* For Berryllium sw2rxdma ring size increased to 20 bits */ 130 #define HAL_RXDMA_MAX_RING_SIZE_BE 0xFFFFF 131 132 #ifdef CONFIG_WORD_BASED_TLV 133 #ifndef BIG_ENDIAN_HOST 134 struct rx_msdu_end_compact_qca9224 { 135 uint32_t rxpcu_mpdu_filter_in_category : 2, // [1:0] 136 sw_frame_group_id : 7, // [8:2] 137 reserved_0 : 7, // [15:9] 138 phy_ppdu_id : 16; // [31:16] 139 uint32_t ip_hdr_chksum : 16, // [15:0] 140 reported_mpdu_length : 14, // [29:16] 141 reserved_1a : 2; // [31:30] 142 uint32_t key_id_octet : 8, // [7:0] 143 cce_super_rule : 6, // [13:8] 144 cce_classify_not_done_truncate : 1, // [14:14] 145 cce_classify_not_done_cce_dis : 1, // [15:15] 146 cumulative_l3_checksum : 16; // [31:16] 147 uint32_t rule_indication_31_0 : 32; // [31:0] 148 uint32_t rule_indication_63_32 : 32; // [31:0] 149 uint32_t da_offset : 6, // [5:0] 150 sa_offset : 6, // [11:6] 151 da_offset_valid : 1, // [12:12] 152 sa_offset_valid : 1, // [13:13] 153 reserved_5a : 2, // [15:14] 154 l3_type : 16; // [31:16] 155 uint32_t ipv6_options_crc : 32; // [31:0] 156 uint32_t tcp_seq_number : 32; // [31:0] 157 uint32_t tcp_ack_number : 32; // [31:0] 158 uint32_t tcp_flag : 9, // [8:0] 159 lro_eligible : 1, // [9:9] 160 reserved_9a : 6, // [15:10] 161 window_size : 16; // [31:16] 162 uint32_t tcp_udp_chksum : 16, // [15:0] 163 sa_idx_timeout : 1, // [16:16] 164 da_idx_timeout : 1, // [17:17] 165 msdu_limit_error : 1, // [18:18] 166 flow_idx_timeout : 1, // [19:19] 167 flow_idx_invalid : 1, // [20:20] 168 wifi_parser_error : 1, // [21:21] 169 amsdu_parser_error : 1, // [22:22] 170 sa_is_valid : 1, // [23:23] 171 da_is_valid : 1, // [24:24] 172 da_is_mcbc : 1, // [25:25] 173 l3_header_padding : 2, // [27:26] 174 first_msdu : 1, // [28:28] 175 last_msdu : 1, // [29:29] 176 tcp_udp_chksum_fail_copy : 1, // [30:30] 177 ip_chksum_fail_copy : 1; // [31:31] 178 uint32_t sa_idx : 16, // [15:0] 179 da_idx_or_sw_peer_id : 16; // [31:16] 180 uint32_t msdu_drop : 1, // [0:0] 181 reo_destination_indication : 5, // [5:1] 182 flow_idx : 20, // [25:6] 183 use_ppe : 1, // [26:26] 184 reserved_12a : 5; // [31:27] 185 uint32_t fse_metadata : 32; // [31:0] 186 uint32_t cce_metadata : 16, // [15:0] 187 sa_sw_peer_id : 16; // [31:16] 188 uint32_t aggregation_count : 8, // [7:0] 189 flow_aggregation_continuation : 1, // [8:8] 190 fisa_timeout : 1, // [9:9] 191 reserved_15a : 22; // [31:10] 192 uint32_t cumulative_l4_checksum : 16, // [15:0] 193 cumulative_ip_length : 16; // [31:16] 194 uint32_t reserved_17a : 6, // [5:0] 195 service_code : 9, // [14:6] 196 priority_valid : 1, // [15:15] 197 intra_bss : 1, // [16:16] 198 dest_chip_id : 2, // [18:17] 199 multicast_echo : 1, // [19:19] 200 wds_learning_event : 1, // [20:20] 201 wds_roaming_event : 1, // [21:21] 202 wds_keep_alive_event : 1, // [22:22] 203 reserved_17b : 9; // [31:23] 204 uint32_t msdu_length : 14, // [13:0] 205 stbc : 1, // [14:14] 206 ipsec_esp : 1, // [15:15] 207 l3_offset : 7, // [22:16] 208 ipsec_ah : 1, // [23:23] 209 l4_offset : 8; // [31:24] 210 uint32_t msdu_number : 8, // [7:0] 211 decap_format : 2, // [9:8] 212 ipv4_proto : 1, // [10:10] 213 ipv6_proto : 1, // [11:11] 214 tcp_proto : 1, // [12:12] 215 udp_proto : 1, // [13:13] 216 ip_frag : 1, // [14:14] 217 tcp_only_ack : 1, // [15:15] 218 da_is_bcast_mcast : 1, // [16:16] 219 toeplitz_hash_sel : 2, // [18:17] 220 ip_fixed_header_valid : 1, // [19:19] 221 ip_extn_header_valid : 1, // [20:20] 222 tcp_udp_header_valid : 1, // [21:21] 223 mesh_control_present : 1, // [22:22] 224 ldpc : 1, // [23:23] 225 ip4_protocol_ip6_next_header : 8; // [31:24] 226 uint32_t toeplitz_hash_2_or_4 : 32; // [31:0] 227 uint32_t flow_id_toeplitz : 32; // [31:0] 228 uint32_t user_rssi : 8, // [7:0] 229 pkt_type : 4, // [11:8] 230 sgi : 2, // [13:12] 231 rate_mcs : 4, // [17:14] 232 receive_bandwidth : 3, // [20:18] 233 reception_type : 3, // [23:21] 234 mimo_ss_bitmap : 8; // [31:24] 235 uint32_t ppdu_start_timestamp_31_0 : 32; // [31:0] 236 uint32_t ppdu_start_timestamp_63_32 : 32; // [31:0] 237 uint32_t sw_phy_meta_data : 32; // [31:0] 238 uint32_t vlan_ctag_ci : 16, // [15:0] 239 vlan_stag_ci : 16; // [31:16] 240 uint32_t reserved_27a : 32; // [31:0] 241 uint32_t reserved_28a : 32; // [31:0] 242 uint32_t reserved_29a : 32; // [31:0] 243 uint32_t first_mpdu : 1, // [0:0] 244 reserved_30a : 1, // [1:1] 245 mcast_bcast : 1, // [2:2] 246 ast_index_not_found : 1, // [3:3] 247 ast_index_timeout : 1, // [4:4] 248 power_mgmt : 1, // [5:5] 249 non_qos : 1, // [6:6] 250 null_data : 1, // [7:7] 251 mgmt_type : 1, // [8:8] 252 ctrl_type : 1, // [9:9] 253 more_data : 1, // [10:10] 254 eosp : 1, // [11:11] 255 a_msdu_error : 1, // [12:12] 256 fragment_flag : 1, // [13:13] 257 order : 1, // [14:14] 258 cce_match : 1, // [15:15] 259 overflow_err : 1, // [16:16] 260 msdu_length_err : 1, // [17:17] 261 tcp_udp_chksum_fail : 1, // [18:18] 262 ip_chksum_fail : 1, // [19:19] 263 sa_idx_invalid : 1, // [20:20] 264 da_idx_invalid : 1, // [21:21] 265 reserved_30b : 1, // [22:22] 266 rx_in_tx_decrypt_byp : 1, // [23:23] 267 encrypt_required : 1, // [24:24] 268 directed : 1, // [25:25] 269 buffer_fragment : 1, // [26:26] 270 mpdu_length_err : 1, // [27:27] 271 tkip_mic_err : 1, // [28:28] 272 decrypt_err : 1, // [29:29] 273 unencrypted_frame_err : 1, // [30:30] 274 fcs_err : 1; // [31:31] 275 uint32_t reserved_31a : 10, // [9:0] 276 decrypt_status_code : 3, // [12:10] 277 rx_bitmap_not_updated : 1, // [13:13] 278 reserved_31b : 17, // [30:14] 279 msdu_done : 1; // [31:31] 280 281 }; 282 283 struct rx_mpdu_start_compact_qca9224 { 284 struct rxpt_classify_info rxpt_classify_info_details; 285 uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0] 286 uint32_t rx_reo_queue_desc_addr_39_32 : 8, // [7:0] 287 receive_queue_number : 16, // [23:8] 288 pre_delim_err_warning : 1, // [24:24] 289 first_delim_err : 1, // [25:25] 290 reserved_2a : 6; // [31:26] 291 uint32_t pn_31_0 : 32; // [31:0] 292 uint32_t pn_63_32 : 32; // [31:0] 293 uint32_t pn_95_64 : 32; // [31:0] 294 uint32_t pn_127_96 : 32; // [31:0] 295 uint32_t epd_en : 1, // [0:0] 296 all_frames_shall_be_encrypted : 1, // [1:1] 297 encrypt_type : 4, // [5:2] 298 wep_key_width_for_variable_key : 2, // [7:6] 299 mesh_sta : 2, // [9:8] 300 bssid_hit : 1, // [10:10] 301 bssid_number : 4, // [14:11] 302 tid : 4, // [18:15] 303 reserved_7a : 13; // [31:19] 304 uint32_t peer_meta_data : 32; // [31:0] 305 uint32_t rxpcu_mpdu_filter_in_category : 2, // [1:0] 306 sw_frame_group_id : 7, // [8:2] 307 ndp_frame : 1, // [9:9] 308 phy_err : 1, // [10:10] 309 phy_err_during_mpdu_header : 1, // [11:11] 310 protocol_version_err : 1, // [12:12] 311 ast_based_lookup_valid : 1, // [13:13] 312 ranging : 1, // [14:14] 313 reserved_9a : 1, // [15:15] 314 phy_ppdu_id : 16; // [31:16] 315 uint32_t ast_index : 16, // [15:0] 316 sw_peer_id : 16; // [31:16] 317 uint32_t mpdu_frame_control_valid : 1, // [0:0] 318 mpdu_duration_valid : 1, // [1:1] 319 mac_addr_ad1_valid : 1, // [2:2] 320 mac_addr_ad2_valid : 1, // [3:3] 321 mac_addr_ad3_valid : 1, // [4:4] 322 mac_addr_ad4_valid : 1, // [5:5] 323 mpdu_sequence_control_valid : 1, // [6:6] 324 mpdu_qos_control_valid : 1, // [7:7] 325 mpdu_ht_control_valid : 1, // [8:8] 326 frame_encryption_info_valid : 1, // [9:9] 327 mpdu_fragment_number : 4, // [13:10] 328 more_fragment_flag : 1, // [14:14] 329 reserved_11a : 1, // [15:15] 330 fr_ds : 1, // [16:16] 331 to_ds : 1, // [17:17] 332 encrypted : 1, // [18:18] 333 mpdu_retry : 1, // [19:19] 334 mpdu_sequence_number : 12; // [31:20] 335 uint32_t key_id_octet : 8, // [7:0] 336 new_peer_entry : 1, // [8:8] 337 decrypt_needed : 1, // [9:9] 338 decap_type : 2, // [11:10] 339 rx_insert_vlan_c_tag_padding : 1, // [12:12] 340 rx_insert_vlan_s_tag_padding : 1, // [13:13] 341 strip_vlan_c_tag_decap : 1, // [14:14] 342 strip_vlan_s_tag_decap : 1, // [15:15] 343 pre_delim_count : 12, // [27:16] 344 ampdu_flag : 1, // [28:28] 345 bar_frame : 1, // [29:29] 346 raw_mpdu : 1, // [30:30] 347 reserved_12 : 1; // [31:31] 348 uint32_t mpdu_length : 14, // [13:0] 349 first_mpdu : 1, // [14:14] 350 mcast_bcast : 1, // [15:15] 351 ast_index_not_found : 1, // [16:16] 352 ast_index_timeout : 1, // [17:17] 353 power_mgmt : 1, // [18:18] 354 non_qos : 1, // [19:19] 355 null_data : 1, // [20:20] 356 mgmt_type : 1, // [21:21] 357 ctrl_type : 1, // [22:22] 358 more_data : 1, // [23:23] 359 eosp : 1, // [24:24] 360 fragment_flag : 1, // [25:25] 361 order : 1, // [26:26] 362 u_apsd_trigger : 1, // [27:27] 363 encrypt_required : 1, // [28:28] 364 directed : 1, // [29:29] 365 amsdu_present : 1, // [30:30] 366 reserved_13 : 1; // [31:31] 367 uint32_t mpdu_frame_control_field : 16, // [15:0] 368 mpdu_duration_field : 16; // [31:16] 369 uint32_t mac_addr_ad1_31_0 : 32; // [31:0] 370 uint32_t mac_addr_ad1_47_32 : 16, // [15:0] 371 mac_addr_ad2_15_0 : 16; // [31:16] 372 uint32_t mac_addr_ad2_47_16 : 32; // [31:0] 373 uint32_t mac_addr_ad3_31_0 : 32; // [31:0] 374 uint32_t mac_addr_ad3_47_32 : 16, // [15:0] 375 mpdu_sequence_control_field : 16; // [31:16] 376 uint32_t mac_addr_ad4_31_0 : 32; // [31:0] 377 uint32_t mac_addr_ad4_47_32 : 16, // [15:0] 378 mpdu_qos_control_field : 16; // [31:16] 379 uint32_t mpdu_ht_control_field : 32; // [31:0] 380 uint32_t vdev_id : 8, // [7:0] 381 service_code : 9, // [16:8] 382 priority_valid : 1, // [17:17] 383 src_info : 12, // [29:18] 384 reserved_23a : 1, // [30:30] 385 multi_link_addr_ad1_ad2_valid : 1; // [31:31] 386 uint32_t multi_link_addr_ad1_31_0 : 32; // [31:0] 387 uint32_t multi_link_addr_ad1_47_32 : 16, // [15:0] 388 multi_link_addr_ad2_15_0 : 16; // [31:16] 389 uint32_t multi_link_addr_ad2_47_16 : 32; // [31:0] 390 uint32_t reserved_27a : 32; // [31:0] 391 uint32_t reserved_28a : 32; // [31:0] 392 uint32_t reserved_29a : 32; // [31:0] 393 }; 394 #else 395 struct rx_msdu_end_compact_qca9224 { 396 uint32_t phy_ppdu_id : 16, // [31:16] 397 reserved_0 : 7, // [15:9] 398 sw_frame_group_id : 7, // [8:2] 399 rxpcu_mpdu_filter_in_category : 2; // [1:0] 400 uint32_t reserved_1a : 2, // [31:30] 401 reported_mpdu_length : 14, // [29:16] 402 ip_hdr_chksum : 16; // [15:0] 403 uint32_t cumulative_l3_checksum : 16, // [31:16] 404 cce_classify_not_done_cce_dis : 1, // [15:15] 405 cce_classify_not_done_truncate : 1, // [14:14] 406 cce_super_rule : 6, // [13:8] 407 key_id_octet : 8; // [7:0] 408 uint32_t rule_indication_31_0 : 32; // [31:0] 409 uint32_t rule_indication_63_32 : 32; // [31:0] 410 uint32_t l3_type : 16, // [31:16] 411 reserved_5a : 2, // [15:14] 412 sa_offset_valid : 1, // [13:13] 413 da_offset_valid : 1, // [12:12] 414 sa_offset : 6, // [11:6] 415 da_offset : 6; // [5:0] 416 uint32_t ipv6_options_crc : 32; // [31:0] 417 uint32_t tcp_seq_number : 32; // [31:0] 418 uint32_t tcp_ack_number : 32; // [31:0] 419 uint32_t window_size : 16, // [31:16] 420 reserved_9a : 6, // [15:10] 421 lro_eligible : 1, // [9:9] 422 tcp_flag : 9; // [8:0] 423 uint32_t ip_chksum_fail_copy : 1, // [31:31] 424 tcp_udp_chksum_fail_copy : 1, // [30:30] 425 last_msdu : 1, // [29:29] 426 first_msdu : 1, // [28:28] 427 l3_header_padding : 2, // [27:26] 428 da_is_mcbc : 1, // [25:25] 429 da_is_valid : 1, // [24:24] 430 sa_is_valid : 1, // [23:23] 431 amsdu_parser_error : 1, // [22:22] 432 wifi_parser_error : 1, // [21:21] 433 flow_idx_invalid : 1, // [20:20] 434 flow_idx_timeout : 1, // [19:19] 435 msdu_limit_error : 1, // [18:18] 436 da_idx_timeout : 1, // [17:17] 437 sa_idx_timeout : 1, // [16:16] 438 tcp_udp_chksum : 16; // [15:0] 439 uint32_t da_idx_or_sw_peer_id : 16, // [31:16] 440 sa_idx : 16; // [15:0] 441 uint32_t reserved_12a : 5, // [31:27] 442 use_ppe : 1, // [26:26] 443 flow_idx : 20, // [25:6] 444 reo_destination_indication : 5, // [5:1] 445 msdu_drop : 1; // [0:0] 446 uint32_t fse_metadata : 32; // [31:0] 447 uint32_t sa_sw_peer_id : 16, // [31:16] 448 cce_metadata : 16; // [15:0] 449 uint32_t reserved_15a : 22, // [31:10] 450 fisa_timeout : 1, // [9:9] 451 flow_aggregation_continuation : 1, // [8:8] 452 aggregation_count : 8; // [7:0] 453 uint32_t cumulative_ip_length : 16, // [31:16] 454 cumulative_l4_checksum : 16; // [15:0] 455 uint32_t reserved_17b : 9, // [31:23] 456 wds_keep_alive_event : 1, // [22:22] 457 wds_roaming_event : 1, // [21:21] 458 wds_learning_event : 1, // [20:20] 459 multicast_echo : 1, // [19:19] 460 dest_chip_id : 2, // [18:17] 461 intra_bss : 1, // [16:16] 462 priority_valid : 1, // [15:15] 463 service_code : 9, // [14:6] 464 reserved_17a : 6; // [5:0] 465 uint32_t l4_offset : 8, // [31:24] 466 ipsec_ah : 1, // [23:23] 467 l3_offset : 7, // [22:16] 468 ipsec_esp : 1, // [15:15] 469 stbc : 1, // [14:14] 470 msdu_length : 14; // [13:0] 471 uint32_t ip4_protocol_ip6_next_header : 8, // [31:24] 472 ldpc : 1, // [23:23] 473 mesh_control_present : 1, // [22:22] 474 tcp_udp_header_valid : 1, // [21:21] 475 ip_extn_header_valid : 1, // [20:20] 476 ip_fixed_header_valid : 1, // [19:19] 477 toeplitz_hash_sel : 2, // [18:17] 478 da_is_bcast_mcast : 1, // [16:16] 479 tcp_only_ack : 1, // [15:15] 480 ip_frag : 1, // [14:14] 481 udp_proto : 1, // [13:13] 482 tcp_proto : 1, // [12:12] 483 ipv6_proto : 1, // [11:11] 484 ipv4_proto : 1, // [10:10] 485 decap_format : 2, // [9:8] 486 msdu_number : 8; // [7:0] 487 uint32_t toeplitz_hash_2_or_4 : 32; // [31:0] 488 uint32_t flow_id_toeplitz : 32; // [31:0] 489 uint32_t mimo_ss_bitmap : 8, // [31:24] 490 reception_type : 3, // [23:21] 491 receive_bandwidth : 3, // [20:18] 492 rate_mcs : 4, // [17:14] 493 sgi : 2, // [13:12] 494 pkt_type : 4, // [11:8] 495 user_rssi : 8; // [7:0] 496 uint32_t ppdu_start_timestamp_31_0 : 32; // [31:0] 497 uint32_t ppdu_start_timestamp_63_32 : 32; // [31:0] 498 uint32_t sw_phy_meta_data : 32; // [31:0] 499 uint32_t vlan_stag_ci : 16, // [31:16] 500 vlan_ctag_ci : 16; // [15:0] 501 uint32_t reserved_27a : 32; // [31:0] 502 uint32_t reserved_28a : 32; // [31:0] 503 uint32_t reserved_29a : 32; // [31:0] 504 uint32_t fcs_err : 1, // [31:31] 505 unencrypted_frame_err : 1, // [30:30] 506 decrypt_err : 1, // [29:29] 507 tkip_mic_err : 1, // [28:28] 508 mpdu_length_err : 1, // [27:27] 509 buffer_fragment : 1, // [26:26] 510 directed : 1, // [25:25] 511 encrypt_required : 1, // [24:24] 512 rx_in_tx_decrypt_byp : 1, // [23:23] 513 reserved_30b : 1, // [22:22] 514 da_idx_invalid : 1, // [21:21] 515 sa_idx_invalid : 1, // [20:20] 516 ip_chksum_fail : 1, // [19:19] 517 tcp_udp_chksum_fail : 1, // [18:18] 518 msdu_length_err : 1, // [17:17] 519 overflow_err : 1, // [16:16] 520 cce_match : 1, // [15:15] 521 order : 1, // [14:14] 522 fragment_flag : 1, // [13:13] 523 a_msdu_error : 1, // [12:12] 524 eosp : 1, // [11:11] 525 more_data : 1, // [10:10] 526 ctrl_type : 1, // [9:9] 527 mgmt_type : 1, // [8:8] 528 null_data : 1, // [7:7] 529 non_qos : 1, // [6:6] 530 power_mgmt : 1, // [5:5] 531 ast_index_timeout : 1, // [4:4] 532 ast_index_not_found : 1, // [3:3] 533 mcast_bcast : 1, // [2:2] 534 reserved_30a : 1, // [1:1] 535 first_mpdu : 1; // [0:0] 536 uint32_t msdu_done : 1, // [31:31] 537 reserved_31b : 17, // [30:14] 538 rx_bitmap_not_updated : 1, // [13:13] 539 decrypt_status_code : 3, // [12:10] 540 reserved_31a : 10; // [9:0] 541 }; 542 543 struct rx_mpdu_start_compact_qca9224 { 544 struct rxpt_classify_info rxpt_classify_info_details; 545 uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0] 546 uint32_t reserved_2a : 6, // [31:26] 547 first_delim_err : 1, // [25:25] 548 pre_delim_err_warning : 1, // [24:24] 549 receive_queue_number : 16, // [23:8] 550 rx_reo_queue_desc_addr_39_32 : 8; // [7:0] 551 uint32_t pn_31_0 : 32; // [31:0] 552 uint32_t pn_63_32 : 32; // [31:0] 553 uint32_t pn_95_64 : 32; // [31:0] 554 uint32_t pn_127_96 : 32; // [31:0] 555 uint32_t reserved_7a : 13, // [31:19] 556 tid : 4, // [18:15] 557 bssid_number : 4, // [14:11] 558 bssid_hit : 1, // [10:10] 559 mesh_sta : 2, // [9:8] 560 wep_key_width_for_variable_key : 2, // [7:6] 561 encrypt_type : 4, // [5:2] 562 all_frames_shall_be_encrypted : 1, // [1:1] 563 epd_en : 1; // [0:0] 564 uint32_t peer_meta_data : 32; // [31:0] 565 uint32_t phy_ppdu_id : 16, // [31:16] 566 reserved_9a : 1, // [15:15] 567 ranging : 1, // [14:14] 568 ast_based_lookup_valid : 1, // [13:13] 569 protocol_version_err : 1, // [12:12] 570 phy_err_during_mpdu_header : 1, // [11:11] 571 phy_err : 1, // [10:10] 572 ndp_frame : 1, // [9:9] 573 sw_frame_group_id : 7, // [8:2] 574 rxpcu_mpdu_filter_in_category : 2; // [1:0] 575 uint32_t sw_peer_id : 16, // [31:16] 576 ast_index : 16; // [15:0] 577 uint32_t mpdu_sequence_number : 12, // [31:20] 578 mpdu_retry : 1, // [19:19] 579 encrypted : 1, // [18:18] 580 to_ds : 1, // [17:17] 581 fr_ds : 1, // [16:16] 582 reserved_11a : 1, // [15:15] 583 more_fragment_flag : 1, // [14:14] 584 mpdu_fragment_number : 4, // [13:10] 585 frame_encryption_info_valid : 1, // [9:9] 586 mpdu_ht_control_valid : 1, // [8:8] 587 mpdu_qos_control_valid : 1, // [7:7] 588 mpdu_sequence_control_valid : 1, // [6:6] 589 mac_addr_ad4_valid : 1, // [5:5] 590 mac_addr_ad3_valid : 1, // [4:4] 591 mac_addr_ad2_valid : 1, // [3:3] 592 mac_addr_ad1_valid : 1, // [2:2] 593 mpdu_duration_valid : 1, // [1:1] 594 mpdu_frame_control_valid : 1; // [0:0] 595 uint32_t reserved_12 : 1, // [31:31] 596 raw_mpdu : 1, // [30:30] 597 bar_frame : 1, // [29:29] 598 ampdu_flag : 1, // [28:28] 599 pre_delim_count : 12, // [27:16] 600 strip_vlan_s_tag_decap : 1, // [15:15] 601 strip_vlan_c_tag_decap : 1, // [14:14] 602 rx_insert_vlan_s_tag_padding : 1, // [13:13] 603 rx_insert_vlan_c_tag_padding : 1, // [12:12] 604 decap_type : 2, // [11:10] 605 decrypt_needed : 1, // [9:9] 606 new_peer_entry : 1, // [8:8] 607 key_id_octet : 8; // [7:0] 608 uint32_t reserved_13 : 1, // [31:31] 609 amsdu_present : 1, // [30:30] 610 directed : 1, // [29:29] 611 encrypt_required : 1, // [28:28] 612 u_apsd_trigger : 1, // [27:27] 613 order : 1, // [26:26] 614 fragment_flag : 1, // [25:25] 615 eosp : 1, // [24:24] 616 more_data : 1, // [23:23] 617 ctrl_type : 1, // [22:22] 618 mgmt_type : 1, // [21:21] 619 null_data : 1, // [20:20] 620 non_qos : 1, // [19:19] 621 power_mgmt : 1, // [18:18] 622 ast_index_timeout : 1, // [17:17] 623 ast_index_not_found : 1, // [16:16] 624 mcast_bcast : 1, // [15:15] 625 first_mpdu : 1, // [14:14] 626 mpdu_length : 14; // [13:0] 627 uint32_t mpdu_duration_field : 16, // [31:16] 628 mpdu_frame_control_field : 16; // [15:0] 629 uint32_t mac_addr_ad1_31_0 : 32; // [31:0] 630 uint32_t mac_addr_ad2_15_0 : 16, // [31:16] 631 mac_addr_ad1_47_32 : 16; // [15:0] 632 uint32_t mac_addr_ad2_47_16 : 32; // [31:0] 633 uint32_t mac_addr_ad3_31_0 : 32; // [31:0] 634 uint32_t mpdu_sequence_control_field : 16, // [31:16] 635 mac_addr_ad3_47_32 : 16; // [15:0] 636 uint32_t mac_addr_ad4_31_0 : 32; // [31:0] 637 uint32_t mpdu_qos_control_field : 16, // [31:16] 638 mac_addr_ad4_47_32 : 16; // [15:0] 639 uint32_t mpdu_ht_control_field : 32; // [31:0] 640 uint32_t multi_link_addr_ad1_ad2_valid : 1, // [31:31] 641 reserved_23a : 1, // [30:30] 642 src_info : 12, // [29:18] 643 priority_valid : 1, // [17:17] 644 service_code : 9, // [16:8] 645 vdev_id : 8; // [7:0] 646 uint32_t multi_link_addr_ad1_31_0 : 32; // [31:0] 647 uint32_t multi_link_addr_ad2_15_0 : 16, // [31:16] 648 multi_link_addr_ad1_47_32 : 16; // [15:0] 649 uint32_t multi_link_addr_ad2_47_16 : 32; // [31:0] 650 uint32_t reserved_27a : 32; // [31:0] 651 uint32_t reserved_28a : 32; // [31:0] 652 uint32_t reserved_29a : 32; // [31:0] 653 }; 654 #endif /* BIG_ENDIAN_HOST */ 655 656 /* TLV struct for word based Tlv */ 657 typedef struct rx_mpdu_start_compact_qca9224 hal_rx_mpdu_start_t; 658 typedef struct rx_msdu_end_compact_qca9224 hal_rx_msdu_end_t; 659 #endif /* CONFIG_WORD_BASED_TLV */ 660 661 #include "hal_9224_rx.h" 662 #include "hal_9224_tx.h" 663 #include "hal_be_rx_tlv.h" 664 #include <hal_be_generic_api.h> 665 666 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 667 #define HAL_PPE_VP_ENTRIES_MAX 32 668 /** 669 * hal_get_link_desc_size_9224(): API to get the link desc size 670 * 671 * Return: uint32_t 672 */ 673 static uint32_t hal_get_link_desc_size_9224(void) 674 { 675 return LINK_DESC_SIZE; 676 } 677 678 /** 679 * hal_rx_get_tlv_9224(): API to get the tlv 680 * 681 * @rx_tlv: TLV data extracted from the rx packet 682 * Return: uint8_t 683 */ 684 static uint8_t hal_rx_get_tlv_9224(void *rx_tlv) 685 { 686 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY, RECEIVE_BANDWIDTH); 687 } 688 689 /** 690 * hal_rx_wbm_err_msdu_continuation_get_9224 () - API to check if WBM 691 * msdu continuation bit is set 692 * 693 *@wbm_desc: wbm release ring descriptor 694 * 695 * Return: true if msdu continuation bit is set. 696 */ 697 static inline 698 uint8_t hal_rx_wbm_err_msdu_continuation_get_9224(void *wbm_desc) 699 { 700 uint32_t comp_desc = *(uint32_t *)(((uint8_t *)wbm_desc) + 701 WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET); 702 703 return (comp_desc & 704 WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK) >> 705 WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB; 706 } 707 708 /** 709 * hal_rx_proc_phyrx_other_receive_info_tlv_9224(): API to get tlv info 710 * 711 * Return: uint32_t 712 */ 713 static inline 714 void hal_rx_proc_phyrx_other_receive_info_tlv_9224(void *rx_tlv_hdr, 715 void *ppdu_info_hdl) 716 { 717 uint32_t tlv_tag, tlv_len; 718 uint32_t temp_len, other_tlv_len, other_tlv_tag; 719 void *rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 720 void *other_tlv_hdr = NULL; 721 void *other_tlv = NULL; 722 723 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 724 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 725 temp_len = 0; 726 727 other_tlv_hdr = rx_tlv + HAL_RX_TLV32_HDR_SIZE; 728 other_tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(other_tlv_hdr); 729 other_tlv_len = HAL_RX_GET_USER_TLV32_LEN(other_tlv_hdr); 730 731 temp_len += other_tlv_len; 732 other_tlv = other_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 733 734 switch (other_tlv_tag) { 735 default: 736 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 737 "%s unhandled TLV type: %d, TLV len:%d", 738 __func__, other_tlv_tag, other_tlv_len); 739 break; 740 } 741 } 742 743 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) 744 static inline 745 void hal_rx_get_bb_info_9224(void *rx_tlv, void *ppdu_info_hdl) 746 { 747 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 748 749 ppdu_info->cfr_info.bb_captured_channel = 750 HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_CHANNEL); 751 752 ppdu_info->cfr_info.bb_captured_timeout = 753 HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_TIMEOUT); 754 755 ppdu_info->cfr_info.bb_captured_reason = 756 HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_REASON); 757 } 758 759 static inline 760 void hal_rx_get_rtt_info_9224(void *rx_tlv, void *ppdu_info_hdl) 761 { 762 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 763 764 ppdu_info->cfr_info.rx_location_info_valid = 765 HAL_RX_GET_64(rx_tlv, PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 766 RX_LOCATION_INFO_VALID); 767 768 ppdu_info->cfr_info.rtt_che_buffer_pointer_low32 = 769 HAL_RX_GET_64(rx_tlv, 770 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 771 RTT_CHE_BUFFER_POINTER_LOW32); 772 773 ppdu_info->cfr_info.rtt_che_buffer_pointer_high8 = 774 HAL_RX_GET_64(rx_tlv, 775 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 776 RTT_CHE_BUFFER_POINTER_HIGH8); 777 778 ppdu_info->cfr_info.chan_capture_status = 779 HAL_GET_RX_LOCATION_INFO_CHAN_CAPTURE_STATUS(rx_tlv); 780 781 ppdu_info->cfr_info.rx_start_ts = 782 HAL_RX_GET_64(rx_tlv, 783 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 784 RX_START_TS); 785 786 ppdu_info->cfr_info.rtt_cfo_measurement = (int16_t) 787 HAL_RX_GET_64(rx_tlv, 788 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 789 RTT_CFO_MEASUREMENT); 790 791 ppdu_info->cfr_info.agc_gain_info0 = 792 HAL_RX_GET_64(rx_tlv, 793 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 794 GAIN_CHAIN0); 795 796 ppdu_info->cfr_info.agc_gain_info0 |= 797 (((uint32_t)HAL_RX_GET_64(rx_tlv, 798 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 799 GAIN_CHAIN1)) << 16); 800 801 ppdu_info->cfr_info.agc_gain_info1 = 802 HAL_RX_GET_64(rx_tlv, 803 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 804 GAIN_CHAIN2); 805 806 ppdu_info->cfr_info.agc_gain_info1 |= 807 (((uint32_t)HAL_RX_GET_64(rx_tlv, 808 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 809 GAIN_CHAIN3)) << 16); 810 811 ppdu_info->cfr_info.agc_gain_info2 = 0; 812 813 ppdu_info->cfr_info.agc_gain_info3 = 0; 814 815 ppdu_info->cfr_info.mcs_rate = 816 HAL_RX_GET_64(rx_tlv, 817 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 818 RTT_MCS_RATE); 819 ppdu_info->cfr_info.gi_type = 820 HAL_RX_GET_64(rx_tlv, 821 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 822 RTT_GI_TYPE); 823 } 824 #endif 825 826 /** 827 * hal_rx_dump_mpdu_start_tlv_9224: dump RX mpdu_start TLV in structured 828 * human readable format. 829 * @mpdu_start: pointer the rx_attention TLV in pkt. 830 * @dbg_level: log level. 831 * 832 * Return: void 833 */ 834 static inline void hal_rx_dump_mpdu_start_tlv_9224(void *mpdustart, 835 uint8_t dbg_level) 836 { 837 #ifdef CONFIG_WORD_BASED_TLV 838 struct rx_mpdu_start_compact_qca9224 *mpdu_info = 839 (struct rx_mpdu_start_compact_qca9224 *)mpdustart; 840 #else 841 struct rx_mpdu_start *mpdu_start = (struct rx_mpdu_start *)mpdustart; 842 struct rx_mpdu_info *mpdu_info = 843 (struct rx_mpdu_info *)&mpdu_start->rx_mpdu_info_details; 844 #endif 845 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 846 "rx_mpdu_start tlv (1/5) - " 847 "rx_reo_queue_desc_addr_31_0 :%x" 848 "rx_reo_queue_desc_addr_39_32 :%x" 849 "receive_queue_number:%x " 850 "pre_delim_err_warning:%x " 851 "first_delim_err:%x " 852 "reserved_2a:%x " 853 "pn_31_0:%x " 854 "pn_63_32:%x " 855 "pn_95_64:%x " 856 "pn_127_96:%x " 857 "epd_en:%x " 858 "all_frames_shall_be_encrypted :%x" 859 "encrypt_type:%x " 860 "wep_key_width_for_variable_key :%x" 861 "mesh_sta:%x " 862 "bssid_hit:%x " 863 "bssid_number:%x " 864 "tid:%x " 865 "reserved_7a:%x ", 866 mpdu_info->rx_reo_queue_desc_addr_31_0, 867 mpdu_info->rx_reo_queue_desc_addr_39_32, 868 mpdu_info->receive_queue_number, 869 mpdu_info->pre_delim_err_warning, 870 mpdu_info->first_delim_err, 871 mpdu_info->reserved_2a, 872 mpdu_info->pn_31_0, 873 mpdu_info->pn_63_32, 874 mpdu_info->pn_95_64, 875 mpdu_info->pn_127_96, 876 mpdu_info->epd_en, 877 mpdu_info->all_frames_shall_be_encrypted, 878 mpdu_info->encrypt_type, 879 mpdu_info->wep_key_width_for_variable_key, 880 mpdu_info->mesh_sta, 881 mpdu_info->bssid_hit, 882 mpdu_info->bssid_number, 883 mpdu_info->tid, 884 mpdu_info->reserved_7a); 885 886 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 887 "rx_mpdu_start tlv (2/5) - " 888 "ast_index:%x " 889 "sw_peer_id:%x " 890 "mpdu_frame_control_valid:%x " 891 "mpdu_duration_valid:%x " 892 "mac_addr_ad1_valid:%x " 893 "mac_addr_ad2_valid:%x " 894 "mac_addr_ad3_valid:%x " 895 "mac_addr_ad4_valid:%x " 896 "mpdu_sequence_control_valid :%x" 897 "mpdu_qos_control_valid:%x " 898 "mpdu_ht_control_valid:%x " 899 "frame_encryption_info_valid :%x", 900 mpdu_info->ast_index, 901 mpdu_info->sw_peer_id, 902 mpdu_info->mpdu_frame_control_valid, 903 mpdu_info->mpdu_duration_valid, 904 mpdu_info->mac_addr_ad1_valid, 905 mpdu_info->mac_addr_ad2_valid, 906 mpdu_info->mac_addr_ad3_valid, 907 mpdu_info->mac_addr_ad4_valid, 908 mpdu_info->mpdu_sequence_control_valid, 909 mpdu_info->mpdu_qos_control_valid, 910 mpdu_info->mpdu_ht_control_valid, 911 mpdu_info->frame_encryption_info_valid); 912 913 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 914 "rx_mpdu_start tlv (3/5) - " 915 "mpdu_fragment_number:%x " 916 "more_fragment_flag:%x " 917 "reserved_11a:%x " 918 "fr_ds:%x " 919 "to_ds:%x " 920 "encrypted:%x " 921 "mpdu_retry:%x " 922 "mpdu_sequence_number:%x ", 923 mpdu_info->mpdu_fragment_number, 924 mpdu_info->more_fragment_flag, 925 mpdu_info->reserved_11a, 926 mpdu_info->fr_ds, 927 mpdu_info->to_ds, 928 mpdu_info->encrypted, 929 mpdu_info->mpdu_retry, 930 mpdu_info->mpdu_sequence_number); 931 932 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 933 "rx_mpdu_start tlv (4/5) - " 934 "mpdu_frame_control_field:%x " 935 "mpdu_duration_field:%x ", 936 mpdu_info->mpdu_frame_control_field, 937 mpdu_info->mpdu_duration_field); 938 939 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 940 "rx_mpdu_start tlv (5/5) - " 941 "mac_addr_ad1_31_0:%x " 942 "mac_addr_ad1_47_32:%x " 943 "mac_addr_ad2_15_0:%x " 944 "mac_addr_ad2_47_16:%x " 945 "mac_addr_ad3_31_0:%x " 946 "mac_addr_ad3_47_32:%x " 947 "mpdu_sequence_control_field :%x" 948 "mac_addr_ad4_31_0:%x " 949 "mac_addr_ad4_47_32:%x " 950 "mpdu_qos_control_field:%x ", 951 mpdu_info->mac_addr_ad1_31_0, 952 mpdu_info->mac_addr_ad1_47_32, 953 mpdu_info->mac_addr_ad2_15_0, 954 mpdu_info->mac_addr_ad2_47_16, 955 mpdu_info->mac_addr_ad3_31_0, 956 mpdu_info->mac_addr_ad3_47_32, 957 mpdu_info->mpdu_sequence_control_field, 958 mpdu_info->mac_addr_ad4_31_0, 959 mpdu_info->mac_addr_ad4_47_32, 960 mpdu_info->mpdu_qos_control_field); 961 } 962 963 /** 964 * hal_rx_dump_msdu_end_tlv_9224: dump RX msdu_end TLV in structured 965 * human readable format. 966 * @ msdu_end: pointer the msdu_end TLV in pkt. 967 * @ dbg_level: log level. 968 * 969 * Return: void 970 */ 971 static void hal_rx_dump_msdu_end_tlv_9224(void *msduend, 972 uint8_t dbg_level) 973 { 974 #ifdef CONFIG_WORD_BASED_TLV 975 struct rx_msdu_end_compact_qca9224 *msdu_end = 976 (struct rx_msdu_end_compact_qca9224 *)msduend; 977 #else 978 struct rx_msdu_end *msdu_end = 979 (struct rx_msdu_end *)msduend; 980 #endif 981 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 982 "rx_msdu_end tlv - " 983 "key_id_octet: %d " 984 "cce_super_rule: %d " 985 "cce_classify_not_done_truncat: %d " 986 "cce_classify_not_done_cce_dis: %d " 987 "rule_indication_31_0: %d " 988 "tcp_udp_chksum: %d " 989 "sa_idx_timeout: %d " 990 "da_idx_timeout: %d " 991 "msdu_limit_error: %d " 992 "flow_idx_timeout: %d " 993 "flow_idx_invalid: %d " 994 "wifi_parser_error: %d " 995 "sa_is_valid: %d " 996 "da_is_valid: %d " 997 "da_is_mcbc: %d " 998 "tkip_mic_err: %d " 999 "l3_header_padding: %d " 1000 "first_msdu: %d " 1001 "last_msdu: %d " 1002 "sa_idx: %d " 1003 "msdu_drop: %d " 1004 "reo_destination_indication: %d " 1005 "flow_idx: %d " 1006 "fse_metadata: %d " 1007 "cce_metadata: %d " 1008 "sa_sw_peer_id: %d ", 1009 msdu_end->key_id_octet, 1010 msdu_end->cce_super_rule, 1011 msdu_end->cce_classify_not_done_truncate, 1012 msdu_end->cce_classify_not_done_cce_dis, 1013 msdu_end->rule_indication_31_0, 1014 msdu_end->tcp_udp_chksum, 1015 msdu_end->sa_idx_timeout, 1016 msdu_end->da_idx_timeout, 1017 msdu_end->msdu_limit_error, 1018 msdu_end->flow_idx_timeout, 1019 msdu_end->flow_idx_invalid, 1020 msdu_end->wifi_parser_error, 1021 msdu_end->sa_is_valid, 1022 msdu_end->da_is_valid, 1023 msdu_end->da_is_mcbc, 1024 msdu_end->tkip_mic_err, 1025 msdu_end->l3_header_padding, 1026 msdu_end->first_msdu, 1027 msdu_end->last_msdu, 1028 msdu_end->sa_idx, 1029 msdu_end->msdu_drop, 1030 msdu_end->reo_destination_indication, 1031 msdu_end->flow_idx, 1032 msdu_end->fse_metadata, 1033 msdu_end->cce_metadata, 1034 msdu_end->sa_sw_peer_id); 1035 } 1036 1037 /** 1038 * hal_reo_status_get_header_9224 - Process reo desc info 1039 * @d - Pointer to reo descriptior 1040 * @b - tlv type info 1041 * @h1 - Pointer to hal_reo_status_header where info to be stored 1042 * 1043 * Return - none. 1044 * 1045 */ 1046 static void hal_reo_status_get_header_9224(hal_ring_desc_t ring_desc, 1047 int b, void *h1) 1048 { 1049 uint64_t *d = (uint64_t *)ring_desc; 1050 uint64_t val1 = 0; 1051 struct hal_reo_status_header *h = 1052 (struct hal_reo_status_header *)h1; 1053 1054 /* Offsets of descriptor fields defined in HW headers start 1055 * from the field after TLV header 1056 */ 1057 d += HAL_GET_NUM_QWORDS(sizeof(struct tlv_32_hdr)); 1058 1059 switch (b) { 1060 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1061 val1 = d[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS, 1062 STATUS_HEADER_REO_STATUS_NUMBER)]; 1063 break; 1064 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1065 val1 = d[HAL_OFFSET_QW(REO_FLUSH_QUEUE_STATUS, 1066 STATUS_HEADER_REO_STATUS_NUMBER)]; 1067 break; 1068 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1069 val1 = d[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS, 1070 STATUS_HEADER_REO_STATUS_NUMBER)]; 1071 break; 1072 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1073 val1 = d[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS, 1074 STATUS_HEADER_REO_STATUS_NUMBER)]; 1075 break; 1076 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1077 val1 = d[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS, 1078 STATUS_HEADER_REO_STATUS_NUMBER)]; 1079 break; 1080 case HAL_REO_DESC_THRES_STATUS_TLV: 1081 val1 = 1082 d[HAL_OFFSET_QW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS, 1083 STATUS_HEADER_REO_STATUS_NUMBER)]; 1084 break; 1085 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1086 val1 = d[HAL_OFFSET_QW(REO_UPDATE_RX_REO_QUEUE_STATUS, 1087 STATUS_HEADER_REO_STATUS_NUMBER)]; 1088 break; 1089 default: 1090 qdf_nofl_err("ERROR: Unknown tlv\n"); 1091 break; 1092 } 1093 h->cmd_num = 1094 HAL_GET_FIELD( 1095 UNIFORM_REO_STATUS_HEADER, REO_STATUS_NUMBER, 1096 val1); 1097 h->exec_time = 1098 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, 1099 CMD_EXECUTION_TIME, val1); 1100 h->status = 1101 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, 1102 REO_CMD_EXECUTION_STATUS, val1); 1103 switch (b) { 1104 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1105 val1 = d[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS, 1106 STATUS_HEADER_TIMESTAMP)]; 1107 break; 1108 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1109 val1 = d[HAL_OFFSET_QW(REO_FLUSH_QUEUE_STATUS, 1110 STATUS_HEADER_TIMESTAMP)]; 1111 break; 1112 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1113 val1 = d[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS, 1114 STATUS_HEADER_TIMESTAMP)]; 1115 break; 1116 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1117 val1 = d[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS, 1118 STATUS_HEADER_TIMESTAMP)]; 1119 break; 1120 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1121 val1 = d[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS, 1122 STATUS_HEADER_TIMESTAMP)]; 1123 break; 1124 case HAL_REO_DESC_THRES_STATUS_TLV: 1125 val1 = 1126 d[HAL_OFFSET_QW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS, 1127 STATUS_HEADER_TIMESTAMP)]; 1128 break; 1129 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1130 val1 = d[HAL_OFFSET_QW(REO_UPDATE_RX_REO_QUEUE_STATUS, 1131 STATUS_HEADER_TIMESTAMP)]; 1132 break; 1133 default: 1134 qdf_nofl_err("ERROR: Unknown tlv\n"); 1135 break; 1136 } 1137 h->tstamp = 1138 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, TIMESTAMP, val1); 1139 } 1140 1141 static 1142 void *hal_rx_msdu0_buffer_addr_lsb_9224(void *link_desc_va) 1143 { 1144 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 1145 } 1146 1147 static 1148 void *hal_rx_msdu_desc_info_ptr_get_9224(void *msdu0) 1149 { 1150 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 1151 } 1152 1153 static 1154 void *hal_ent_mpdu_desc_info_9224(void *ent_ring_desc) 1155 { 1156 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 1157 } 1158 1159 static 1160 void *hal_dst_mpdu_desc_info_9224(void *dst_ring_desc) 1161 { 1162 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 1163 } 1164 1165 /** 1166 * hal_reo_config_9224(): Set reo config parameters 1167 * @soc: hal soc handle 1168 * @reg_val: value to be set 1169 * @reo_params: reo parameters 1170 * 1171 * Return: void 1172 */ 1173 static void 1174 hal_reo_config_9224(struct hal_soc *soc, 1175 uint32_t reg_val, 1176 struct hal_reo_params *reo_params) 1177 { 1178 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 1179 } 1180 1181 /** 1182 * hal_rx_msdu_desc_info_get_ptr_9224() - Get msdu desc info ptr 1183 * @msdu_details_ptr - Pointer to msdu_details_ptr 1184 * 1185 * Return - Pointer to rx_msdu_desc_info structure. 1186 * 1187 */ 1188 static void *hal_rx_msdu_desc_info_get_ptr_9224(void *msdu_details_ptr) 1189 { 1190 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 1191 } 1192 1193 /** 1194 * hal_rx_link_desc_msdu0_ptr_9224 - Get pointer to rx_msdu details 1195 * @link_desc - Pointer to link desc 1196 * 1197 * Return - Pointer to rx_msdu_details structure 1198 * 1199 */ 1200 static void *hal_rx_link_desc_msdu0_ptr_9224(void *link_desc) 1201 { 1202 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 1203 } 1204 1205 /** 1206 * hal_get_window_address_9224(): Function to get hp/tp address 1207 * @hal_soc: Pointer to hal_soc 1208 * @addr: address offset of register 1209 * 1210 * Return: modified address offset of register 1211 */ 1212 1213 static inline qdf_iomem_t hal_get_window_address_9224(struct hal_soc *hal_soc, 1214 qdf_iomem_t addr) 1215 { 1216 uint32_t offset = addr - hal_soc->dev_base_addr; 1217 qdf_iomem_t new_offset; 1218 1219 /* 1220 * If offset lies within DP register range, use 3rd window to write 1221 * into DP region. 1222 */ 1223 if ((offset ^ UMAC_BASE) < WINDOW_RANGE_MASK) { 1224 new_offset = (hal_soc->dev_base_addr + (3 * WINDOW_START) + 1225 (offset & WINDOW_RANGE_MASK)); 1226 /* 1227 * If offset lies within CE register range, use 2nd window to write 1228 * into CE region. 1229 */ 1230 } else if ((offset ^ CE_WFSS_CE_REG_BASE) < WINDOW_RANGE_MASK) { 1231 new_offset = (hal_soc->dev_base_addr + (2 * WINDOW_START) + 1232 (offset & WINDOW_RANGE_MASK)); 1233 } else { 1234 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 1235 "%s: ERROR: Accessing Wrong register\n", __func__); 1236 qdf_assert_always(0); 1237 return 0; 1238 } 1239 return new_offset; 1240 } 1241 1242 static inline void hal_write_window_register(struct hal_soc *hal_soc) 1243 { 1244 /* Write value into window configuration register */ 1245 qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_REG_ADDRESS, 1246 WINDOW_CONFIGURATION_VALUE_9224); 1247 } 1248 1249 static 1250 void hal_compute_reo_remap_ix2_ix3_9224(uint32_t *ring, uint32_t num_rings, 1251 uint32_t *remap1, uint32_t *remap2) 1252 { 1253 switch (num_rings) { 1254 case 1: 1255 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1256 HAL_REO_REMAP_IX2(ring[0], 17) | 1257 HAL_REO_REMAP_IX2(ring[0], 18) | 1258 HAL_REO_REMAP_IX2(ring[0], 19) | 1259 HAL_REO_REMAP_IX2(ring[0], 20) | 1260 HAL_REO_REMAP_IX2(ring[0], 21) | 1261 HAL_REO_REMAP_IX2(ring[0], 22) | 1262 HAL_REO_REMAP_IX2(ring[0], 23); 1263 1264 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1265 HAL_REO_REMAP_IX3(ring[0], 25) | 1266 HAL_REO_REMAP_IX3(ring[0], 26) | 1267 HAL_REO_REMAP_IX3(ring[0], 27) | 1268 HAL_REO_REMAP_IX3(ring[0], 28) | 1269 HAL_REO_REMAP_IX3(ring[0], 29) | 1270 HAL_REO_REMAP_IX3(ring[0], 30) | 1271 HAL_REO_REMAP_IX3(ring[0], 31); 1272 break; 1273 case 2: 1274 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1275 HAL_REO_REMAP_IX2(ring[0], 17) | 1276 HAL_REO_REMAP_IX2(ring[1], 18) | 1277 HAL_REO_REMAP_IX2(ring[1], 19) | 1278 HAL_REO_REMAP_IX2(ring[0], 20) | 1279 HAL_REO_REMAP_IX2(ring[0], 21) | 1280 HAL_REO_REMAP_IX2(ring[1], 22) | 1281 HAL_REO_REMAP_IX2(ring[1], 23); 1282 1283 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1284 HAL_REO_REMAP_IX3(ring[0], 25) | 1285 HAL_REO_REMAP_IX3(ring[1], 26) | 1286 HAL_REO_REMAP_IX3(ring[1], 27) | 1287 HAL_REO_REMAP_IX3(ring[0], 28) | 1288 HAL_REO_REMAP_IX3(ring[0], 29) | 1289 HAL_REO_REMAP_IX3(ring[1], 30) | 1290 HAL_REO_REMAP_IX3(ring[1], 31); 1291 break; 1292 case 3: 1293 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1294 HAL_REO_REMAP_IX2(ring[1], 17) | 1295 HAL_REO_REMAP_IX2(ring[2], 18) | 1296 HAL_REO_REMAP_IX2(ring[0], 19) | 1297 HAL_REO_REMAP_IX2(ring[1], 20) | 1298 HAL_REO_REMAP_IX2(ring[2], 21) | 1299 HAL_REO_REMAP_IX2(ring[0], 22) | 1300 HAL_REO_REMAP_IX2(ring[1], 23); 1301 1302 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) | 1303 HAL_REO_REMAP_IX3(ring[0], 25) | 1304 HAL_REO_REMAP_IX3(ring[1], 26) | 1305 HAL_REO_REMAP_IX3(ring[2], 27) | 1306 HAL_REO_REMAP_IX3(ring[0], 28) | 1307 HAL_REO_REMAP_IX3(ring[1], 29) | 1308 HAL_REO_REMAP_IX3(ring[2], 30) | 1309 HAL_REO_REMAP_IX3(ring[0], 31); 1310 break; 1311 case 4: 1312 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1313 HAL_REO_REMAP_IX2(ring[1], 17) | 1314 HAL_REO_REMAP_IX2(ring[2], 18) | 1315 HAL_REO_REMAP_IX2(ring[3], 19) | 1316 HAL_REO_REMAP_IX2(ring[0], 20) | 1317 HAL_REO_REMAP_IX2(ring[1], 21) | 1318 HAL_REO_REMAP_IX2(ring[2], 22) | 1319 HAL_REO_REMAP_IX2(ring[3], 23); 1320 1321 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1322 HAL_REO_REMAP_IX3(ring[1], 25) | 1323 HAL_REO_REMAP_IX3(ring[2], 26) | 1324 HAL_REO_REMAP_IX3(ring[3], 27) | 1325 HAL_REO_REMAP_IX3(ring[0], 28) | 1326 HAL_REO_REMAP_IX3(ring[1], 29) | 1327 HAL_REO_REMAP_IX3(ring[2], 30) | 1328 HAL_REO_REMAP_IX3(ring[3], 31); 1329 break; 1330 } 1331 } 1332 1333 /** 1334 * hal_rx_flow_setup_fse_9224() - Setup a flow search entry in HW FST 1335 * @fst: Pointer to the Rx Flow Search Table 1336 * @table_offset: offset into the table where the flow is to be setup 1337 * @flow: Flow Parameters 1338 * 1339 * Return: Success/Failure 1340 */ 1341 static void * 1342 hal_rx_flow_setup_fse_9224(uint8_t *rx_fst, uint32_t table_offset, 1343 uint8_t *rx_flow) 1344 { 1345 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 1346 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 1347 uint8_t *fse; 1348 bool fse_valid; 1349 1350 if (table_offset >= fst->max_entries) { 1351 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 1352 "HAL FSE table offset %u exceeds max entries %u", 1353 table_offset, fst->max_entries); 1354 return NULL; 1355 } 1356 1357 fse = (uint8_t *)fst->base_vaddr + 1358 (table_offset * HAL_RX_FST_ENTRY_SIZE); 1359 1360 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID); 1361 1362 if (fse_valid) { 1363 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 1364 "HAL FSE %pK already valid", fse); 1365 return NULL; 1366 } 1367 1368 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96) = 1369 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96, 1370 qdf_htonl(flow->tuple_info.src_ip_127_96)); 1371 1372 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64) = 1373 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64, 1374 qdf_htonl(flow->tuple_info.src_ip_95_64)); 1375 1376 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32) = 1377 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32, 1378 qdf_htonl(flow->tuple_info.src_ip_63_32)); 1379 1380 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0) = 1381 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0, 1382 qdf_htonl(flow->tuple_info.src_ip_31_0)); 1383 1384 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96) = 1385 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96, 1386 qdf_htonl(flow->tuple_info.dest_ip_127_96)); 1387 1388 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64) = 1389 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64, 1390 qdf_htonl(flow->tuple_info.dest_ip_95_64)); 1391 1392 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32) = 1393 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32, 1394 qdf_htonl(flow->tuple_info.dest_ip_63_32)); 1395 1396 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0) = 1397 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0, 1398 qdf_htonl(flow->tuple_info.dest_ip_31_0)); 1399 1400 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_PORT); 1401 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_PORT) |= 1402 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_PORT, 1403 (flow->tuple_info.dest_port)); 1404 1405 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_PORT); 1406 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_PORT) |= 1407 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_PORT, 1408 (flow->tuple_info.src_port)); 1409 1410 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL); 1411 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL) |= 1412 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL, 1413 flow->tuple_info.l4_protocol); 1414 1415 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER); 1416 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER) |= 1417 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER, 1418 flow->reo_destination_handler); 1419 1420 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID); 1421 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID) |= 1422 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, VALID, 1); 1423 1424 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, METADATA); 1425 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, METADATA) = 1426 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, METADATA, 1427 flow->fse_metadata); 1428 1429 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_INDICATION); 1430 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_INDICATION) |= 1431 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, 1432 REO_DESTINATION_INDICATION, 1433 flow->reo_destination_indication); 1434 1435 /* Reset all the other fields in FSE */ 1436 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, RESERVED_9); 1437 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_DROP); 1438 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_COUNT); 1439 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_BYTE_COUNT); 1440 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, TIMESTAMP); 1441 1442 return fse; 1443 } 1444 1445 #ifndef NO_RX_PKT_HDR_TLV 1446 /** 1447 * hal_rx_dump_pkt_hdr_tlv: dump RX pkt header TLV in hex format 1448 * @ pkt_hdr_tlv: pointer the pkt_hdr_tlv in pkt. 1449 * @ dbg_level: log level. 1450 * 1451 * Return: void 1452 */ 1453 static inline void hal_rx_dump_pkt_hdr_tlv_9224(struct rx_pkt_tlvs *pkt_tlvs, 1454 uint8_t dbg_level) 1455 { 1456 struct rx_pkt_hdr_tlv *pkt_hdr_tlv = &pkt_tlvs->pkt_hdr_tlv; 1457 1458 hal_verbose_debug("\n---------------\n" 1459 "rx_pkt_hdr_tlv\n" 1460 "---------------\n" 1461 "phy_ppdu_id %llu ", 1462 pkt_hdr_tlv->phy_ppdu_id); 1463 1464 hal_verbose_hex_dump(pkt_hdr_tlv->rx_pkt_hdr, 1465 sizeof(pkt_hdr_tlv->rx_pkt_hdr)); 1466 } 1467 #else 1468 /** 1469 * hal_rx_dump_pkt_hdr_tlv: dump RX pkt header TLV in hex format 1470 * @ pkt_hdr_tlv: pointer the pkt_hdr_tlv in pkt. 1471 * @ dbg_level: log level. 1472 * 1473 * Return: void 1474 */ 1475 static inline void hal_rx_dump_pkt_hdr_tlv_9224(struct rx_pkt_tlvs *pkt_tlvs, 1476 uint8_t dbg_level) 1477 { 1478 } 1479 #endif 1480 1481 /* 1482 * hal_tx_dump_ppe_vp_entry_9224() 1483 * @hal_soc_hdl: HAL SoC handle 1484 * 1485 * Return: void 1486 */ 1487 static inline 1488 void hal_tx_dump_ppe_vp_entry_9224(hal_soc_handle_t hal_soc_hdl) 1489 { 1490 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; 1491 uint32_t reg_addr, reg_val = 0, i; 1492 1493 for (i = 0; i < HAL_PPE_VP_ENTRIES_MAX; i++) { 1494 reg_addr = 1495 HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_ADDR( 1496 MAC_TCL_REG_REG_BASE, 1497 i); 1498 reg_val = HAL_REG_READ(soc, reg_addr); 1499 hal_verbose_debug("%d: 0x%x\n", i, reg_val); 1500 } 1501 } 1502 1503 /** 1504 * hal_rx_dump_pkt_tlvs_9224(): API to print RX Pkt TLVS QCN9224 1505 * @hal_soc_hdl: hal_soc handle 1506 * @buf: pointer the pkt buffer 1507 * @dbg_level: log level 1508 * 1509 * Return: void 1510 */ 1511 #ifdef CONFIG_WORD_BASED_TLV 1512 static void hal_rx_dump_pkt_tlvs_9224(hal_soc_handle_t hal_soc_hdl, 1513 uint8_t *buf, uint8_t dbg_level) 1514 { 1515 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1516 struct rx_msdu_end_compact_qca9224 *msdu_end = 1517 &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1518 struct rx_mpdu_start_compact_qca9224 *mpdu_start = 1519 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1520 1521 hal_rx_dump_msdu_end_tlv_9224(msdu_end, dbg_level); 1522 hal_rx_dump_mpdu_start_tlv_9224(mpdu_start, dbg_level); 1523 hal_rx_dump_pkt_hdr_tlv_9224(pkt_tlvs, dbg_level); 1524 } 1525 #else 1526 static void hal_rx_dump_pkt_tlvs_9224(hal_soc_handle_t hal_soc_hdl, 1527 uint8_t *buf, uint8_t dbg_level) 1528 { 1529 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1530 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1531 struct rx_mpdu_start *mpdu_start = 1532 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1533 1534 hal_rx_dump_msdu_end_tlv_9224(msdu_end, dbg_level); 1535 hal_rx_dump_mpdu_start_tlv_9224(mpdu_start, dbg_level); 1536 hal_rx_dump_pkt_hdr_tlv_9224(pkt_tlvs, dbg_level); 1537 } 1538 #endif 1539 1540 #define HAL_NUM_TCL_BANKS_9224 48 1541 1542 /** 1543 * hal_cmem_write_9224() - function for CMEM buffer writing 1544 * @hal_soc_hdl: HAL SOC handle 1545 * @offset: CMEM address 1546 * @value: value to write 1547 * 1548 * Return: None. 1549 */ 1550 static void hal_cmem_write_9224(hal_soc_handle_t hal_soc_hdl, 1551 uint32_t offset, 1552 uint32_t value) 1553 { 1554 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 1555 1556 pld_reg_write(hal->qdf_dev->dev, offset, value); 1557 } 1558 1559 /** 1560 * hal_tx_get_num_tcl_banks_9224() - Get number of banks in target 1561 * 1562 * Returns: number of bank 1563 */ 1564 static uint8_t hal_tx_get_num_tcl_banks_9224(void) 1565 { 1566 return HAL_NUM_TCL_BANKS_9224; 1567 } 1568 1569 static void hal_reo_setup_9224(struct hal_soc *soc, void *reoparams) 1570 { 1571 uint32_t reg_val; 1572 struct hal_reo_params *reo_params = (struct hal_reo_params *)reoparams; 1573 1574 reg_val = HAL_REG_READ(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR( 1575 REO_REG_REG_BASE)); 1576 1577 hal_reo_config_9224(soc, reg_val, reo_params); 1578 /* Other ring enable bits and REO_ENABLE will be set by FW */ 1579 1580 /* TODO: Setup destination ring mapping if enabled */ 1581 1582 /* TODO: Error destination ring setting is left to default. 1583 * Default setting is to send all errors to release ring. 1584 */ 1585 1586 /* Set the reo descriptor swap bits in case of BIG endian platform */ 1587 hal_setup_reo_swap(soc); 1588 1589 HAL_REG_WRITE(soc, 1590 HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(REO_REG_REG_BASE), 1591 HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000); 1592 1593 HAL_REG_WRITE(soc, 1594 HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(REO_REG_REG_BASE), 1595 (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000)); 1596 1597 HAL_REG_WRITE(soc, 1598 HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(REO_REG_REG_BASE), 1599 (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000)); 1600 1601 HAL_REG_WRITE(soc, 1602 HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(REO_REG_REG_BASE), 1603 (HAL_DEFAULT_VO_REO_TIMEOUT_MS * 1000)); 1604 1605 /* 1606 * When hash based routing is enabled, routing of the rx packet 1607 * is done based on the following value: 1 _ _ _ _ The last 4 1608 * bits are based on hash[3:0]. This means the possible values 1609 * are 0x10 to 0x1f. This value is used to look-up the 1610 * ring ID configured in Destination_Ring_Ctrl_IX_* register. 1611 * The Destination_Ring_Ctrl_IX_2 and Destination_Ring_Ctrl_IX_3 1612 * registers need to be configured to set-up the 16 entries to 1613 * map the hash values to a ring number. There are 3 bits per 1614 * hash entry – which are mapped as follows: 1615 * 0: TCL, 1:SW1, 2:SW2, * 3:SW3, 4:SW4, 5:Release, 6:FW(WIFI), 1616 * 7: NOT_USED. 1617 */ 1618 if (reo_params->rx_hash_enabled) { 1619 HAL_REG_WRITE(soc, 1620 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR 1621 (REO_REG_REG_BASE), reo_params->remap0); 1622 1623 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x", 1624 HAL_REG_READ(soc, 1625 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR( 1626 REO_REG_REG_BASE))); 1627 1628 HAL_REG_WRITE(soc, 1629 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 1630 (REO_REG_REG_BASE), reo_params->remap1); 1631 1632 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x", 1633 HAL_REG_READ(soc, 1634 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR( 1635 REO_REG_REG_BASE))); 1636 1637 HAL_REG_WRITE(soc, 1638 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 1639 (REO_REG_REG_BASE), reo_params->remap2); 1640 1641 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 0x%x", 1642 HAL_REG_READ(soc, 1643 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR( 1644 REO_REG_REG_BASE))); 1645 } 1646 1647 /* TODO: Check if the following registers shoould be setup by host: 1648 * AGING_CONTROL 1649 * HIGH_MEMORY_THRESHOLD 1650 * GLOBAL_LINK_DESC_COUNT_THRESH_IX_0[1,2] 1651 * GLOBAL_LINK_DESC_COUNT_CTRL 1652 */ 1653 1654 hal_reo_shared_qaddr_init((hal_soc_handle_t)soc); 1655 } 1656 1657 static uint16_t hal_get_rx_max_ba_window_qcn9224(int tid) 1658 { 1659 return HAL_RX_BA_WINDOW_1024; 1660 } 1661 1662 /** 1663 * hal_qcn9224_get_reo_qdesc_size()- Get the reo queue descriptor size 1664 * from the give Block-Ack window size 1665 * Return: reo queue descriptor size 1666 */ 1667 static uint32_t hal_qcn9224_get_reo_qdesc_size(uint32_t ba_window_size, int tid) 1668 { 1669 /* Hardcode the ba_window_size to HAL_RX_MAX_BA_WINDOW for 1670 * NON_QOS_TID until HW issues are resolved. 1671 */ 1672 if (tid != HAL_NON_QOS_TID) 1673 ba_window_size = hal_get_rx_max_ba_window_qcn9224(tid); 1674 1675 /* Return descriptor size corresponding to window size of 2 since 1676 * we set ba_window_size to 2 while setting up REO descriptors as 1677 * a WAR to get 2k jump exception aggregates are received without 1678 * a BA session. 1679 */ 1680 if (ba_window_size <= 1) { 1681 if (tid != HAL_NON_QOS_TID) 1682 return sizeof(struct rx_reo_queue) + 1683 sizeof(struct rx_reo_queue_ext); 1684 else 1685 return sizeof(struct rx_reo_queue); 1686 } 1687 1688 if (ba_window_size <= 105) 1689 return sizeof(struct rx_reo_queue) + 1690 sizeof(struct rx_reo_queue_ext); 1691 1692 if (ba_window_size <= 210) 1693 return sizeof(struct rx_reo_queue) + 1694 (2 * sizeof(struct rx_reo_queue_ext)); 1695 1696 if (ba_window_size <= 256) 1697 return sizeof(struct rx_reo_queue) + 1698 (3 * sizeof(struct rx_reo_queue_ext)); 1699 1700 return sizeof(struct rx_reo_queue) + 1701 (10 * sizeof(struct rx_reo_queue_ext)) + 1702 sizeof(struct rx_reo_queue_1k); 1703 } 1704 1705 /* 1706 * hal_tx_dump_ppe_vp_entry_9224() 1707 * @hal_soc_hdl: HAL SoC handle 1708 * 1709 * Return: Number of PPE VP entries 1710 */ 1711 static 1712 uint32_t hal_tx_get_num_ppe_vp_tbl_entries_9224(hal_soc_handle_t hal_soc_hdl) 1713 { 1714 return HAL_PPE_VP_ENTRIES_MAX; 1715 } 1716 1717 /** 1718 * hal_rx_tlv_msdu_done_copy_get_9224() - Get msdu done copy bit from rx_tlv 1719 * 1720 * Returns: msdu done copy bit 1721 */ 1722 static inline uint32_t hal_rx_tlv_msdu_done_copy_get_9224(uint8_t *buf) 1723 { 1724 return HAL_RX_TLV_MSDU_DONE_COPY_GET(buf); 1725 } 1726 1727 static void hal_hw_txrx_ops_attach_qcn9224(struct hal_soc *hal_soc) 1728 { 1729 /* init and setup */ 1730 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic; 1731 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic; 1732 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic; 1733 hal_soc->ops->hal_get_window_address = hal_get_window_address_9224; 1734 hal_soc->ops->hal_cmem_write = hal_cmem_write_9224; 1735 1736 /* tx */ 1737 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_9224; 1738 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_9224; 1739 hal_soc->ops->hal_tx_comp_get_status = 1740 hal_tx_comp_get_status_generic_be; 1741 hal_soc->ops->hal_tx_init_cmd_credit_ring = 1742 hal_tx_init_cmd_credit_ring_9224; 1743 hal_soc->ops->hal_tx_set_ppe_cmn_cfg = 1744 hal_tx_set_ppe_cmn_config_9224; 1745 hal_soc->ops->hal_tx_set_ppe_vp_entry = 1746 hal_tx_set_ppe_vp_entry_9224; 1747 hal_soc->ops->hal_tx_set_ppe_pri2tid = 1748 hal_tx_set_ppe_pri2tid_map_9224; 1749 hal_soc->ops->hal_tx_update_ppe_pri2tid = 1750 hal_tx_update_ppe_pri2tid_9224; 1751 hal_soc->ops->hal_tx_dump_ppe_vp_entry = 1752 hal_tx_dump_ppe_vp_entry_9224; 1753 hal_soc->ops->hal_tx_get_num_ppe_vp_tbl_entries = 1754 hal_tx_get_num_ppe_vp_tbl_entries_9224; 1755 hal_soc->ops->hal_tx_enable_pri2tid_map = 1756 hal_tx_enable_pri2tid_map_9224; 1757 hal_soc->ops->hal_tx_config_rbm_mapping_be = 1758 hal_tx_config_rbm_mapping_be_9224; 1759 1760 /* rx */ 1761 hal_soc->ops->hal_rx_msdu_start_nss_get = hal_rx_tlv_nss_get_be; 1762 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status = 1763 hal_rx_mon_hw_desc_get_mpdu_status_be; 1764 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_9224; 1765 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv = 1766 hal_rx_proc_phyrx_other_receive_info_tlv_9224; 1767 1768 hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_9224; 1769 hal_soc->ops->hal_rx_dump_mpdu_start_tlv = 1770 hal_rx_dump_mpdu_start_tlv_9224; 1771 hal_soc->ops->hal_rx_dump_pkt_tlvs = hal_rx_dump_pkt_tlvs_9224; 1772 1773 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_9224; 1774 hal_soc->ops->hal_rx_mpdu_start_tid_get = hal_rx_tlv_tid_get_be; 1775 hal_soc->ops->hal_rx_msdu_start_reception_type_get = 1776 hal_rx_tlv_reception_type_get_be; 1777 hal_soc->ops->hal_rx_msdu_end_da_idx_get = 1778 hal_rx_msdu_end_da_idx_get_be; 1779 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = 1780 hal_rx_msdu_desc_info_get_ptr_9224; 1781 hal_soc->ops->hal_rx_link_desc_msdu0_ptr = 1782 hal_rx_link_desc_msdu0_ptr_9224; 1783 hal_soc->ops->hal_reo_status_get_header = 1784 hal_reo_status_get_header_9224; 1785 hal_soc->ops->hal_rx_status_get_tlv_info = 1786 hal_rx_status_get_tlv_info_wrapper_be; 1787 hal_soc->ops->hal_rx_wbm_err_info_get = 1788 hal_rx_wbm_err_info_get_generic_be; 1789 hal_soc->ops->hal_tx_set_pcp_tid_map = 1790 hal_tx_set_pcp_tid_map_generic_be; 1791 hal_soc->ops->hal_tx_update_pcp_tid_map = 1792 hal_tx_update_pcp_tid_generic_be; 1793 hal_soc->ops->hal_tx_set_tidmap_prty = 1794 hal_tx_update_tidmap_prty_generic_be; 1795 hal_soc->ops->hal_rx_get_rx_fragment_number = 1796 hal_rx_get_rx_fragment_number_be, 1797 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = 1798 hal_rx_tlv_da_is_mcbc_get_be; 1799 hal_soc->ops->hal_rx_msdu_end_is_tkip_mic_err = 1800 hal_rx_tlv_is_tkip_mic_err_get_be; 1801 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = 1802 hal_rx_tlv_sa_is_valid_get_be; 1803 hal_soc->ops->hal_rx_msdu_end_sa_idx_get = hal_rx_tlv_sa_idx_get_be; 1804 hal_soc->ops->hal_rx_desc_is_first_msdu = hal_rx_desc_is_first_msdu_be; 1805 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get = 1806 hal_rx_tlv_l3_hdr_padding_get_be; 1807 hal_soc->ops->hal_rx_encryption_info_valid = 1808 hal_rx_encryption_info_valid_be; 1809 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_be; 1810 hal_soc->ops->hal_rx_msdu_end_first_msdu_get = 1811 hal_rx_tlv_first_msdu_get_be; 1812 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = 1813 hal_rx_tlv_da_is_valid_get_be; 1814 hal_soc->ops->hal_rx_msdu_end_last_msdu_get = 1815 hal_rx_tlv_last_msdu_get_be; 1816 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = 1817 hal_rx_get_mpdu_mac_ad4_valid_be; 1818 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get = 1819 hal_rx_mpdu_start_sw_peer_id_get_be; 1820 hal_soc->ops->hal_rx_mpdu_peer_meta_data_get = 1821 hal_rx_mpdu_peer_meta_data_get_be; 1822 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_be; 1823 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_be; 1824 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid = 1825 hal_rx_get_mpdu_frame_control_valid_be; 1826 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_be; 1827 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_be; 1828 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_be; 1829 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_be; 1830 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid = 1831 hal_rx_get_mpdu_sequence_control_valid_be; 1832 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_be; 1833 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_be; 1834 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = 1835 hal_rx_hw_desc_get_ppduid_get_be; 1836 hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get = 1837 hal_rx_mpdu_start_mpdu_qos_control_valid_get_be; 1838 hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get = 1839 hal_rx_msdu_end_sa_sw_peer_id_get_be; 1840 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = 1841 hal_rx_msdu0_buffer_addr_lsb_9224; 1842 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = 1843 hal_rx_msdu_desc_info_ptr_get_9224; 1844 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_9224; 1845 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_9224; 1846 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_be; 1847 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_be; 1848 hal_soc->ops->hal_rx_get_mac_addr2_valid = 1849 hal_rx_get_mac_addr2_valid_be; 1850 hal_soc->ops->hal_rx_get_filter_category = 1851 hal_rx_get_filter_category_be; 1852 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_be; 1853 hal_soc->ops->hal_reo_config = hal_reo_config_9224; 1854 hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_be; 1855 hal_soc->ops->hal_rx_msdu_flow_idx_invalid = 1856 hal_rx_msdu_flow_idx_invalid_be; 1857 hal_soc->ops->hal_rx_msdu_flow_idx_timeout = 1858 hal_rx_msdu_flow_idx_timeout_be; 1859 hal_soc->ops->hal_rx_msdu_fse_metadata_get = 1860 hal_rx_msdu_fse_metadata_get_be; 1861 hal_soc->ops->hal_rx_msdu_cce_match_get = 1862 hal_rx_msdu_cce_match_get_be; 1863 hal_soc->ops->hal_rx_msdu_cce_metadata_get = 1864 hal_rx_msdu_cce_metadata_get_be; 1865 hal_soc->ops->hal_rx_msdu_get_flow_params = 1866 hal_rx_msdu_get_flow_params_be; 1867 hal_soc->ops->hal_rx_tlv_get_tcp_chksum = hal_rx_tlv_get_tcp_chksum_be; 1868 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_be; 1869 1870 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) 1871 hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_9224; 1872 hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_9224; 1873 #else 1874 hal_soc->ops->hal_rx_get_bb_info = NULL; 1875 hal_soc->ops->hal_rx_get_rtt_info = NULL; 1876 #endif 1877 1878 /* rx - msdu fast path info fields */ 1879 hal_soc->ops->hal_rx_msdu_packet_metadata_get = 1880 hal_rx_msdu_packet_metadata_get_generic_be; 1881 hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid = 1882 hal_rx_mpdu_start_tlv_tag_valid_be; 1883 hal_soc->ops->hal_rx_wbm_err_msdu_continuation_get = 1884 hal_rx_wbm_err_msdu_continuation_get_9224; 1885 1886 /* rx - TLV struct offsets */ 1887 hal_soc->ops->hal_rx_msdu_end_offset_get = 1888 hal_rx_msdu_end_offset_get_generic; 1889 hal_soc->ops->hal_rx_mpdu_start_offset_get = 1890 hal_rx_mpdu_start_offset_get_generic; 1891 #ifndef NO_RX_PKT_HDR_TLV 1892 hal_soc->ops->hal_rx_pkt_tlv_offset_get = 1893 hal_rx_pkt_tlv_offset_get_generic; 1894 #endif 1895 hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_9224; 1896 1897 hal_soc->ops->hal_rx_flow_get_tuple_info = 1898 hal_rx_flow_get_tuple_info_be; 1899 hal_soc->ops->hal_rx_flow_delete_entry = 1900 hal_rx_flow_delete_entry_be; 1901 hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_be; 1902 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = 1903 hal_compute_reo_remap_ix2_ix3_9224; 1904 1905 hal_soc->ops->hal_rx_msdu_get_reo_destination_indication = 1906 hal_rx_msdu_get_reo_destination_indication_be; 1907 hal_soc->ops->hal_rx_get_tlv_size = hal_rx_get_tlv_size_generic_be; 1908 hal_soc->ops->hal_rx_msdu_is_wlan_mcast = 1909 hal_rx_msdu_is_wlan_mcast_generic_be; 1910 hal_soc->ops->hal_tx_get_num_tcl_banks = hal_tx_get_num_tcl_banks_9224; 1911 hal_soc->ops->hal_rx_tlv_decap_format_get = 1912 hal_rx_tlv_decap_format_get_be; 1913 #ifdef RECEIVE_OFFLOAD 1914 hal_soc->ops->hal_rx_tlv_get_offload_info = 1915 hal_rx_tlv_get_offload_info_be; 1916 hal_soc->ops->hal_rx_get_proto_params = hal_rx_get_proto_params_be; 1917 hal_soc->ops->hal_rx_get_l3_l4_offsets = hal_rx_get_l3_l4_offsets_be; 1918 #endif 1919 hal_soc->ops->hal_rx_tlv_phy_ppdu_id_get = 1920 hal_rx_attn_phy_ppdu_id_get_be; 1921 hal_soc->ops->hal_rx_tlv_msdu_done_get = 1922 hal_rx_tlv_msdu_done_copy_get_9224; 1923 hal_soc->ops->hal_rx_tlv_msdu_len_get = 1924 hal_rx_msdu_start_msdu_len_get_be; 1925 hal_soc->ops->hal_rx_get_frame_ctrl_field = 1926 hal_rx_get_frame_ctrl_field_be; 1927 hal_soc->ops->hal_rx_tlv_csum_err_get = hal_rx_tlv_csum_err_get_be; 1928 hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get = 1929 hal_rx_mpdu_info_ampdu_flag_get_be; 1930 hal_soc->ops->hal_rx_tlv_msdu_len_set = 1931 hal_rx_msdu_start_msdu_len_set_be; 1932 hal_soc->ops->hal_rx_tlv_sgi_get = hal_rx_tlv_sgi_get_be; 1933 hal_soc->ops->hal_rx_tlv_rate_mcs_get = hal_rx_tlv_rate_mcs_get_be; 1934 hal_soc->ops->hal_rx_tlv_bw_get = hal_rx_tlv_bw_get_be; 1935 hal_soc->ops->hal_rx_tlv_get_pkt_type = hal_rx_tlv_get_pkt_type_be; 1936 hal_soc->ops->hal_rx_tlv_mic_err_get = hal_rx_tlv_mic_err_get_be; 1937 hal_soc->ops->hal_rx_tlv_decrypt_err_get = 1938 hal_rx_tlv_decrypt_err_get_be; 1939 hal_soc->ops->hal_rx_tlv_first_mpdu_get = hal_rx_tlv_first_mpdu_get_be; 1940 hal_soc->ops->hal_rx_tlv_get_is_decrypted = 1941 hal_rx_tlv_get_is_decrypted_be; 1942 hal_soc->ops->hal_rx_msdu_get_keyid = hal_rx_msdu_get_keyid_be; 1943 hal_soc->ops->hal_rx_tlv_get_freq = hal_rx_tlv_get_freq_be; 1944 hal_soc->ops->hal_rx_priv_info_set_in_tlv = 1945 hal_rx_priv_info_set_in_tlv_be; 1946 hal_soc->ops->hal_rx_priv_info_get_from_tlv = 1947 hal_rx_priv_info_get_from_tlv_be; 1948 hal_soc->ops->hal_rx_pkt_hdr_get = hal_rx_pkt_hdr_get_be; 1949 hal_soc->ops->hal_reo_setup = hal_reo_setup_9224; 1950 #ifdef REO_SHARED_QREF_TABLE_EN 1951 hal_soc->ops->hal_reo_shared_qaddr_setup = hal_reo_shared_qaddr_setup_be; 1952 hal_soc->ops->hal_reo_shared_qaddr_init = hal_reo_shared_qaddr_init_be; 1953 hal_soc->ops->hal_reo_shared_qaddr_detach = hal_reo_shared_qaddr_detach_be; 1954 hal_soc->ops->hal_reo_shared_qaddr_write = hal_reo_shared_qaddr_write_be; 1955 hal_soc->ops->hal_reo_shared_qaddr_cache_clear = hal_reo_shared_qaddr_cache_clear_be; 1956 #endif 1957 /* Overwrite the default BE ops */ 1958 hal_soc->ops->hal_get_rx_max_ba_window = 1959 hal_get_rx_max_ba_window_qcn9224; 1960 hal_soc->ops->hal_get_reo_qdesc_size = hal_qcn9224_get_reo_qdesc_size; 1961 /* TX MONITOR */ 1962 #ifdef QCA_MONITOR_2_0_SUPPORT 1963 hal_soc->ops->hal_txmon_is_mon_buf_addr_tlv = 1964 hal_txmon_is_mon_buf_addr_tlv_generic_be; 1965 hal_soc->ops->hal_txmon_populate_packet_info = 1966 hal_txmon_populate_packet_info_generic_be; 1967 hal_soc->ops->hal_txmon_status_parse_tlv = 1968 hal_txmon_status_parse_tlv_generic_be; 1969 hal_soc->ops->hal_txmon_status_get_num_users = 1970 hal_txmon_status_get_num_users_generic_be; 1971 #endif /* QCA_MONITOR_2_0_SUPPORT */ 1972 hal_soc->ops->hal_compute_reo_remap_ix0 = NULL; 1973 hal_soc->ops->hal_tx_vdev_mismatch_routing_set = 1974 hal_tx_vdev_mismatch_routing_set_generic_be; 1975 hal_soc->ops->hal_tx_mcast_mlo_reinject_routing_set = 1976 hal_tx_mcast_mlo_reinject_routing_set_generic_be; 1977 hal_soc->ops->hal_get_ba_aging_timeout = 1978 hal_get_ba_aging_timeout_be_generic; 1979 hal_soc->ops->hal_setup_link_idle_list = 1980 hal_setup_link_idle_list_generic_be; 1981 hal_soc->ops->hal_cookie_conversion_reg_cfg_be = 1982 hal_cookie_conversion_reg_cfg_generic_be; 1983 hal_soc->ops->hal_set_ba_aging_timeout = 1984 hal_set_ba_aging_timeout_be_generic; 1985 hal_soc->ops->hal_tx_populate_bank_register = 1986 hal_tx_populate_bank_register_be; 1987 hal_soc->ops->hal_tx_vdev_mcast_ctrl_set = 1988 hal_tx_vdev_mcast_ctrl_set_be; 1989 }; 1990 1991 /** 1992 * hal_srng_hw_reg_offset_init_qcn9224() - Initialize the HW srng reg offset 1993 * applicable only for QCN9224 1994 * @hal_soc: HAL Soc handle 1995 * 1996 * Return: None 1997 */ 1998 static inline void hal_srng_hw_reg_offset_init_qcn9224(struct hal_soc *hal_soc) 1999 { 2000 int32_t *hw_reg_offset = hal_soc->hal_hw_reg_offset; 2001 2002 hw_reg_offset[DST_MSI2_BASE_LSB] = REG_OFFSET(DST, MSI2_BASE_LSB), 2003 hw_reg_offset[DST_MSI2_BASE_MSB] = REG_OFFSET(DST, MSI2_BASE_MSB), 2004 hw_reg_offset[DST_MSI2_DATA] = REG_OFFSET(DST, MSI2_DATA), 2005 hw_reg_offset[DST_PRODUCER_INT2_SETUP] = 2006 REG_OFFSET(DST, PRODUCER_INT2_SETUP); 2007 } 2008