1 /* 2 * Copyright (c) 2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 #include "qdf_types.h" 20 #include "qdf_util.h" 21 #include "qdf_mem.h" 22 #include "qdf_nbuf.h" 23 #include "qdf_module.h" 24 25 #include "target_type.h" 26 #include "wcss_version.h" 27 28 #include "hal_be_hw_headers.h" 29 #include "hal_internal.h" 30 #include "hal_api.h" 31 #include "hal_flow.h" 32 #include "rx_flow_search_entry.h" 33 #include "hal_rx_flow_info.h" 34 #include "hal_be_api.h" 35 #include "tcl_entrance_from_ppe_ring.h" 36 #include "sw_monitor_ring.h" 37 #include "wcss_seq_hwioreg_umac.h" 38 #include "wfss_ce_reg_seq_hwioreg.h" 39 #include <uniform_reo_status_header.h> 40 #include <wbm_release_ring_tx.h> 41 #include <phyrx_location.h> 42 #ifdef QCA_MONITOR_2_0_SUPPORT 43 #include <mon_ingress_ring.h> 44 #include <mon_destination_ring.h> 45 #endif 46 #include "rx_reo_queue_1k.h" 47 48 #include <hal_be_rx.h> 49 50 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 51 RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 52 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 53 RX_MSDU_LINK_MSDU_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 54 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 55 RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 56 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 57 RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 58 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 59 REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 60 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER \ 61 STATUS_HEADER_REO_STATUS_NUMBER 62 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 63 STATUS_HEADER_TIMESTAMP 64 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 65 RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 66 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 67 RX_MSDU_LINK_MSDU_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 68 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 69 TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 70 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 71 TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 72 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 73 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_OFFSET 74 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 75 BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 76 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 77 BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 78 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 79 BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB 80 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 81 BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK 82 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 83 BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 84 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 85 BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 86 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 87 BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB 88 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 89 BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK 90 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 91 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_LSB 92 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 93 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MASK 94 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 95 WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 96 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 97 WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 98 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 99 WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 100 101 #include "hal_be_api_mon.h" 102 103 #ifdef CONFIG_WIFI_EMULATION_WIFI_3_0 104 #define CMEM_REG_BASE 0x0010e000 105 106 #define CMEM_WINDOW_ADDRESS_9224 \ 107 ((CMEM_REG_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) 108 #endif 109 110 #define CE_WINDOW_ADDRESS_9224 \ 111 ((CE_WFSS_CE_REG_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) 112 113 #define UMAC_WINDOW_ADDRESS_9224 \ 114 ((UMAC_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) 115 116 #ifdef CONFIG_WIFI_EMULATION_WIFI_3_0 117 #define WINDOW_CONFIGURATION_VALUE_9224 \ 118 ((CE_WINDOW_ADDRESS_9224 << 6) |\ 119 (UMAC_WINDOW_ADDRESS_9224 << 12) | \ 120 CMEM_WINDOW_ADDRESS_9224 | \ 121 WINDOW_ENABLE_BIT) 122 #else 123 #define WINDOW_CONFIGURATION_VALUE_9224 \ 124 ((CE_WINDOW_ADDRESS_9224 << 6) |\ 125 (UMAC_WINDOW_ADDRESS_9224 << 12) | \ 126 WINDOW_ENABLE_BIT) 127 #endif 128 129 /* For Berryllium sw2rxdma ring size increased to 20 bits */ 130 #define HAL_RXDMA_MAX_RING_SIZE_BE 0xFFFFF 131 132 #include "hal_9224_rx.h" 133 #include "hal_9224_tx.h" 134 #include "hal_be_rx_tlv.h" 135 #include <hal_be_generic_api.h> 136 137 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 138 #define HAL_PPE_VP_ENTRIES_MAX 32 139 /** 140 * hal_get_link_desc_size_9224(): API to get the link desc size 141 * 142 * Return: uint32_t 143 */ 144 static uint32_t hal_get_link_desc_size_9224(void) 145 { 146 return LINK_DESC_SIZE; 147 } 148 149 /** 150 * hal_rx_get_tlv_9224(): API to get the tlv 151 * 152 * @rx_tlv: TLV data extracted from the rx packet 153 * Return: uint8_t 154 */ 155 static uint8_t hal_rx_get_tlv_9224(void *rx_tlv) 156 { 157 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY, RECEIVE_BANDWIDTH); 158 } 159 160 /** 161 * hal_rx_wbm_err_msdu_continuation_get_9224 () - API to check if WBM 162 * msdu continuation bit is set 163 * 164 *@wbm_desc: wbm release ring descriptor 165 * 166 * Return: true if msdu continuation bit is set. 167 */ 168 static inline 169 uint8_t hal_rx_wbm_err_msdu_continuation_get_9224(void *wbm_desc) 170 { 171 uint32_t comp_desc = *(uint32_t *)(((uint8_t *)wbm_desc) + 172 WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET); 173 174 return (comp_desc & 175 WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK) >> 176 WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB; 177 } 178 179 #if (defined(WLAN_SA_API_ENABLE)) && (defined(QCA_WIFI_QCA9574)) 180 #define HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, evm, pilot) \ 181 (ppdu_info)->evm_info.pilot_evm[pilot] = HAL_RX_GET(rx_tlv, \ 182 PHYRX_OTHER_RECEIVE_INFO, \ 183 SU_EVM_DETAILS_##evm##_PILOT_##pilot##_EVM) 184 185 static inline void 186 hal_rx_update_su_evm_info(void *rx_tlv, 187 void *ppdu_info_hdl) 188 { 189 struct hal_rx_ppdu_info *ppdu_info = 190 (struct hal_rx_ppdu_info *)ppdu_info_hdl; 191 192 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 1, 0); 193 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 2, 1); 194 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 3, 2); 195 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 4, 3); 196 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 5, 4); 197 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 6, 5); 198 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 7, 6); 199 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 8, 7); 200 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 9, 8); 201 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 10, 9); 202 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 11, 10); 203 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 12, 11); 204 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 13, 12); 205 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 14, 13); 206 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 15, 14); 207 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 16, 15); 208 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 17, 16); 209 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 18, 17); 210 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 19, 18); 211 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 20, 19); 212 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 21, 20); 213 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 22, 21); 214 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 23, 22); 215 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 24, 23); 216 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 25, 24); 217 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 26, 25); 218 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 27, 26); 219 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 28, 27); 220 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 29, 28); 221 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 30, 29); 222 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 31, 30); 223 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 32, 31); 224 } 225 226 static void hal_rx_get_evm_info(void *rx_tlv_hdr, void *ppdu_info_hdl) 227 { 228 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 229 void *rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 230 uint32_t tlv_tag; 231 232 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 233 234 switch (tlv_tag) { 235 case WIFIPHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_E: 236 237 /* Skip TLV length to get TLV content */ 238 rx_tlv = (uint8_t *)rx_tlv + HAL_RX_TLV32_HDR_SIZE; 239 240 ppdu_info->evm_info.number_of_symbols = HAL_RX_GET(rx_tlv, 241 PHYRX_OTHER_RECEIVE_INFO, 242 SU_EVM_DETAILS_0_NUMBER_OF_SYMBOLS); 243 ppdu_info->evm_info.pilot_count = HAL_RX_GET(rx_tlv, 244 PHYRX_OTHER_RECEIVE_INFO, 245 SU_EVM_DETAILS_0_PILOT_COUNT); 246 ppdu_info->evm_info.nss_count = HAL_RX_GET(rx_tlv, 247 PHYRX_OTHER_RECEIVE_INFO, 248 SU_EVM_DETAILS_0_NSS_COUNT); 249 hal_rx_update_su_evm_info(rx_tlv, ppdu_info_hdl); 250 break; 251 } 252 } 253 #else /* WLAN_SA_API_ENABLE && QCA_WIFI_QCA9574 */ 254 static void hal_rx_get_evm_info(void *tlv_tag, void *ppdu_info_hdl) 255 { 256 } 257 #endif /* WLAN_SA_API_ENABLE && QCA_WIFI_QCA9574 */ 258 259 /** 260 * hal_rx_proc_phyrx_other_receive_info_tlv_9224(): API to get tlv info 261 * 262 * Return: uint32_t 263 */ 264 static inline 265 void hal_rx_proc_phyrx_other_receive_info_tlv_9224(void *rx_tlv_hdr, 266 void *ppdu_info_hdl) 267 { 268 uint32_t tlv_tag, tlv_len; 269 uint32_t temp_len, other_tlv_len, other_tlv_tag; 270 void *rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 271 void *other_tlv_hdr = NULL; 272 void *other_tlv = NULL; 273 274 /* Get evm info for Smart Antenna */ 275 hal_rx_get_evm_info(rx_tlv_hdr, ppdu_info_hdl); 276 277 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 278 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 279 temp_len = 0; 280 281 other_tlv_hdr = rx_tlv + HAL_RX_TLV32_HDR_SIZE; 282 other_tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(other_tlv_hdr); 283 other_tlv_len = HAL_RX_GET_USER_TLV32_LEN(other_tlv_hdr); 284 285 temp_len += other_tlv_len; 286 other_tlv = other_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 287 288 switch (other_tlv_tag) { 289 default: 290 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 291 "%s unhandled TLV type: %d, TLV len:%d", 292 __func__, other_tlv_tag, other_tlv_len); 293 break; 294 } 295 } 296 297 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) 298 static inline 299 void hal_rx_get_bb_info_9224(void *rx_tlv, void *ppdu_info_hdl) 300 { 301 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 302 303 ppdu_info->cfr_info.bb_captured_channel = 304 HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_CHANNEL); 305 306 ppdu_info->cfr_info.bb_captured_timeout = 307 HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_TIMEOUT); 308 309 ppdu_info->cfr_info.bb_captured_reason = 310 HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_REASON); 311 } 312 313 static inline 314 void hal_rx_get_rtt_info_9224(void *rx_tlv, void *ppdu_info_hdl) 315 { 316 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 317 318 ppdu_info->cfr_info.rx_location_info_valid = 319 HAL_RX_GET_64(rx_tlv, PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 320 RX_LOCATION_INFO_VALID); 321 322 ppdu_info->cfr_info.rtt_che_buffer_pointer_low32 = 323 HAL_RX_GET_64(rx_tlv, 324 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 325 RTT_CHE_BUFFER_POINTER_LOW32); 326 327 ppdu_info->cfr_info.rtt_che_buffer_pointer_high8 = 328 HAL_RX_GET_64(rx_tlv, 329 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 330 RTT_CHE_BUFFER_POINTER_HIGH8); 331 332 ppdu_info->cfr_info.chan_capture_status = 333 HAL_GET_RX_LOCATION_INFO_CHAN_CAPTURE_STATUS(rx_tlv); 334 335 ppdu_info->cfr_info.rx_start_ts = 336 HAL_RX_GET_64(rx_tlv, 337 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 338 RX_START_TS); 339 340 ppdu_info->cfr_info.rtt_cfo_measurement = (int16_t) 341 HAL_RX_GET_64(rx_tlv, 342 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 343 RTT_CFO_MEASUREMENT); 344 345 ppdu_info->cfr_info.agc_gain_info0 = 346 HAL_RX_GET_64(rx_tlv, 347 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 348 GAIN_CHAIN0); 349 350 ppdu_info->cfr_info.agc_gain_info0 |= 351 (((uint32_t)HAL_RX_GET_64(rx_tlv, 352 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 353 GAIN_CHAIN1)) << 16); 354 355 ppdu_info->cfr_info.agc_gain_info1 = 356 HAL_RX_GET_64(rx_tlv, 357 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 358 GAIN_CHAIN2); 359 360 ppdu_info->cfr_info.agc_gain_info1 |= 361 (((uint32_t)HAL_RX_GET_64(rx_tlv, 362 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 363 GAIN_CHAIN3)) << 16); 364 365 ppdu_info->cfr_info.agc_gain_info2 = 0; 366 367 ppdu_info->cfr_info.agc_gain_info3 = 0; 368 369 ppdu_info->cfr_info.mcs_rate = 370 HAL_RX_GET_64(rx_tlv, 371 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 372 RTT_MCS_RATE); 373 ppdu_info->cfr_info.gi_type = 374 HAL_RX_GET_64(rx_tlv, 375 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 376 RTT_GI_TYPE); 377 } 378 #endif 379 380 /** 381 * hal_rx_dump_mpdu_start_tlv_9224: dump RX mpdu_start TLV in structured 382 * human readable format. 383 * @mpdu_start: pointer the rx_attention TLV in pkt. 384 * @dbg_level: log level. 385 * 386 * Return: void 387 */ 388 static inline void hal_rx_dump_mpdu_start_tlv_9224(void *mpdustart, 389 uint8_t dbg_level) 390 { 391 #ifdef CONFIG_WORD_BASED_TLV 392 struct rx_mpdu_start_compact *mpdu_info = 393 (struct rx_mpdu_start_compact *)mpdustart; 394 #else 395 struct rx_mpdu_start *mpdu_start = (struct rx_mpdu_start *)mpdustart; 396 struct rx_mpdu_info *mpdu_info = 397 (struct rx_mpdu_info *)&mpdu_start->rx_mpdu_info_details; 398 #endif 399 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 400 "rx_mpdu_start tlv (1/5) - " 401 "rx_reo_queue_desc_addr_39_32 :%x" 402 "receive_queue_number:%x " 403 "pre_delim_err_warning:%x " 404 "first_delim_err:%x " 405 "pn_31_0:%x " 406 "pn_63_32:%x " 407 "pn_95_64:%x ", 408 mpdu_info->rx_reo_queue_desc_addr_39_32, 409 mpdu_info->receive_queue_number, 410 mpdu_info->pre_delim_err_warning, 411 mpdu_info->first_delim_err, 412 mpdu_info->pn_31_0, 413 mpdu_info->pn_63_32, 414 mpdu_info->pn_95_64); 415 416 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 417 "rx_mpdu_start tlv (2/5) - " 418 "ast_index:%x " 419 "sw_peer_id:%x " 420 "mpdu_frame_control_valid:%x " 421 "mpdu_duration_valid:%x " 422 "mac_addr_ad1_valid:%x " 423 "mac_addr_ad2_valid:%x " 424 "mac_addr_ad3_valid:%x " 425 "mac_addr_ad4_valid:%x " 426 "mpdu_sequence_control_valid :%x" 427 "mpdu_qos_control_valid:%x " 428 "mpdu_ht_control_valid:%x " 429 "frame_encryption_info_valid :%x", 430 mpdu_info->ast_index, 431 mpdu_info->sw_peer_id, 432 mpdu_info->mpdu_frame_control_valid, 433 mpdu_info->mpdu_duration_valid, 434 mpdu_info->mac_addr_ad1_valid, 435 mpdu_info->mac_addr_ad2_valid, 436 mpdu_info->mac_addr_ad3_valid, 437 mpdu_info->mac_addr_ad4_valid, 438 mpdu_info->mpdu_sequence_control_valid, 439 mpdu_info->mpdu_qos_control_valid, 440 mpdu_info->mpdu_ht_control_valid, 441 mpdu_info->frame_encryption_info_valid); 442 443 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 444 "rx_mpdu_start tlv (3/5) - " 445 "mpdu_fragment_number:%x " 446 "more_fragment_flag:%x " 447 "fr_ds:%x " 448 "to_ds:%x " 449 "encrypted:%x " 450 "mpdu_retry:%x " 451 "mpdu_sequence_number:%x ", 452 mpdu_info->mpdu_fragment_number, 453 mpdu_info->more_fragment_flag, 454 mpdu_info->fr_ds, 455 mpdu_info->to_ds, 456 mpdu_info->encrypted, 457 mpdu_info->mpdu_retry, 458 mpdu_info->mpdu_sequence_number); 459 460 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 461 "rx_mpdu_start tlv (4/5) - " 462 "mpdu_frame_control_field:%x " 463 "mpdu_duration_field:%x ", 464 mpdu_info->mpdu_frame_control_field, 465 mpdu_info->mpdu_duration_field); 466 467 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 468 "rx_mpdu_start tlv (5/5) - " 469 "mac_addr_ad1_31_0:%x " 470 "mac_addr_ad1_47_32:%x " 471 "mac_addr_ad2_15_0:%x " 472 "mac_addr_ad2_47_16:%x " 473 "mac_addr_ad3_31_0:%x " 474 "mac_addr_ad3_47_32:%x " 475 "mpdu_sequence_control_field :%x", 476 mpdu_info->mac_addr_ad1_31_0, 477 mpdu_info->mac_addr_ad1_47_32, 478 mpdu_info->mac_addr_ad2_15_0, 479 mpdu_info->mac_addr_ad2_47_16, 480 mpdu_info->mac_addr_ad3_31_0, 481 mpdu_info->mac_addr_ad3_47_32, 482 mpdu_info->mpdu_sequence_control_field); 483 } 484 485 /** 486 * hal_rx_dump_msdu_end_tlv_9224: dump RX msdu_end TLV in structured 487 * human readable format. 488 * @ msdu_end: pointer the msdu_end TLV in pkt. 489 * @ dbg_level: log level. 490 * 491 * Return: void 492 */ 493 static void hal_rx_dump_msdu_end_tlv_9224(void *msduend, 494 uint8_t dbg_level) 495 { 496 #ifdef CONFIG_WORD_BASED_TLV 497 struct rx_msdu_end_compact *msdu_end = 498 (struct rx_msdu_end_compact *)msduend; 499 #else 500 struct rx_msdu_end *msdu_end = 501 (struct rx_msdu_end *)msduend; 502 #endif 503 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 504 "rx_msdu_end tlv - " 505 "key_id_octet: %d " 506 "tcp_udp_chksum: %d " 507 "sa_idx_timeout: %d " 508 "da_idx_timeout: %d " 509 "msdu_limit_error: %d " 510 "flow_idx_timeout: %d " 511 "flow_idx_invalid: %d " 512 "wifi_parser_error: %d " 513 "sa_is_valid: %d " 514 "da_is_valid: %d " 515 "da_is_mcbc: %d " 516 "tkip_mic_err: %d " 517 "l3_header_padding: %d " 518 "first_msdu: %d " 519 "last_msdu: %d " 520 "sa_idx: %d " 521 "msdu_drop: %d " 522 "reo_destination_indication: %d " 523 "flow_idx: %d " 524 "fse_metadata: %d " 525 "cce_metadata: %d " 526 "sa_sw_peer_id: %d ", 527 msdu_end->key_id_octet, 528 msdu_end->tcp_udp_chksum, 529 msdu_end->sa_idx_timeout, 530 msdu_end->da_idx_timeout, 531 msdu_end->msdu_limit_error, 532 msdu_end->flow_idx_timeout, 533 msdu_end->flow_idx_invalid, 534 msdu_end->wifi_parser_error, 535 msdu_end->sa_is_valid, 536 msdu_end->da_is_valid, 537 msdu_end->da_is_mcbc, 538 msdu_end->tkip_mic_err, 539 msdu_end->l3_header_padding, 540 msdu_end->first_msdu, 541 msdu_end->last_msdu, 542 msdu_end->sa_idx, 543 msdu_end->msdu_drop, 544 msdu_end->reo_destination_indication, 545 msdu_end->flow_idx, 546 msdu_end->fse_metadata, 547 msdu_end->cce_metadata, 548 msdu_end->sa_sw_peer_id); 549 } 550 551 /** 552 * hal_reo_status_get_header_9224 - Process reo desc info 553 * @d - Pointer to reo descriptor 554 * @b - tlv type info 555 * @h1 - Pointer to hal_reo_status_header where info to be stored 556 * 557 * Return - none. 558 * 559 */ 560 static void hal_reo_status_get_header_9224(hal_ring_desc_t ring_desc, 561 int b, void *h1) 562 { 563 uint64_t *d = (uint64_t *)ring_desc; 564 uint64_t val1 = 0; 565 struct hal_reo_status_header *h = 566 (struct hal_reo_status_header *)h1; 567 568 /* Offsets of descriptor fields defined in HW headers start 569 * from the field after TLV header 570 */ 571 d += HAL_GET_NUM_QWORDS(sizeof(struct tlv_32_hdr)); 572 573 switch (b) { 574 case HAL_REO_QUEUE_STATS_STATUS_TLV: 575 val1 = d[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS, 576 STATUS_HEADER_REO_STATUS_NUMBER)]; 577 break; 578 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 579 val1 = d[HAL_OFFSET_QW(REO_FLUSH_QUEUE_STATUS, 580 STATUS_HEADER_REO_STATUS_NUMBER)]; 581 break; 582 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 583 val1 = d[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS, 584 STATUS_HEADER_REO_STATUS_NUMBER)]; 585 break; 586 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 587 val1 = d[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS, 588 STATUS_HEADER_REO_STATUS_NUMBER)]; 589 break; 590 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 591 val1 = d[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS, 592 STATUS_HEADER_REO_STATUS_NUMBER)]; 593 break; 594 case HAL_REO_DESC_THRES_STATUS_TLV: 595 val1 = 596 d[HAL_OFFSET_QW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS, 597 STATUS_HEADER_REO_STATUS_NUMBER)]; 598 break; 599 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 600 val1 = d[HAL_OFFSET_QW(REO_UPDATE_RX_REO_QUEUE_STATUS, 601 STATUS_HEADER_REO_STATUS_NUMBER)]; 602 break; 603 default: 604 qdf_nofl_err("ERROR: Unknown tlv\n"); 605 break; 606 } 607 h->cmd_num = 608 HAL_GET_FIELD( 609 UNIFORM_REO_STATUS_HEADER, REO_STATUS_NUMBER, 610 val1); 611 h->exec_time = 612 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, 613 CMD_EXECUTION_TIME, val1); 614 h->status = 615 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, 616 REO_CMD_EXECUTION_STATUS, val1); 617 switch (b) { 618 case HAL_REO_QUEUE_STATS_STATUS_TLV: 619 val1 = d[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS, 620 STATUS_HEADER_TIMESTAMP)]; 621 break; 622 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 623 val1 = d[HAL_OFFSET_QW(REO_FLUSH_QUEUE_STATUS, 624 STATUS_HEADER_TIMESTAMP)]; 625 break; 626 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 627 val1 = d[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS, 628 STATUS_HEADER_TIMESTAMP)]; 629 break; 630 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 631 val1 = d[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS, 632 STATUS_HEADER_TIMESTAMP)]; 633 break; 634 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 635 val1 = d[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS, 636 STATUS_HEADER_TIMESTAMP)]; 637 break; 638 case HAL_REO_DESC_THRES_STATUS_TLV: 639 val1 = 640 d[HAL_OFFSET_QW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS, 641 STATUS_HEADER_TIMESTAMP)]; 642 break; 643 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 644 val1 = d[HAL_OFFSET_QW(REO_UPDATE_RX_REO_QUEUE_STATUS, 645 STATUS_HEADER_TIMESTAMP)]; 646 break; 647 default: 648 qdf_nofl_err("ERROR: Unknown tlv\n"); 649 break; 650 } 651 h->tstamp = 652 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, TIMESTAMP, val1); 653 } 654 655 static 656 void *hal_rx_msdu0_buffer_addr_lsb_9224(void *link_desc_va) 657 { 658 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 659 } 660 661 static 662 void *hal_rx_msdu_desc_info_ptr_get_9224(void *msdu0) 663 { 664 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 665 } 666 667 static 668 void *hal_ent_mpdu_desc_info_9224(void *ent_ring_desc) 669 { 670 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 671 } 672 673 static 674 void *hal_dst_mpdu_desc_info_9224(void *dst_ring_desc) 675 { 676 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 677 } 678 679 /** 680 * hal_reo_config_9224(): Set reo config parameters 681 * @soc: hal soc handle 682 * @reg_val: value to be set 683 * @reo_params: reo parameters 684 * 685 * Return: void 686 */ 687 static void 688 hal_reo_config_9224(struct hal_soc *soc, 689 uint32_t reg_val, 690 struct hal_reo_params *reo_params) 691 { 692 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 693 } 694 695 /** 696 * hal_rx_msdu_desc_info_get_ptr_9224() - Get msdu desc info ptr 697 * @msdu_details_ptr - Pointer to msdu_details_ptr 698 * 699 * Return - Pointer to rx_msdu_desc_info structure. 700 * 701 */ 702 static void *hal_rx_msdu_desc_info_get_ptr_9224(void *msdu_details_ptr) 703 { 704 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 705 } 706 707 /** 708 * hal_rx_link_desc_msdu0_ptr_9224 - Get pointer to rx_msdu details 709 * @link_desc - Pointer to link desc 710 * 711 * Return - Pointer to rx_msdu_details structure 712 * 713 */ 714 static void *hal_rx_link_desc_msdu0_ptr_9224(void *link_desc) 715 { 716 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 717 } 718 719 /** 720 * hal_get_window_address_9224(): Function to get hp/tp address 721 * @hal_soc: Pointer to hal_soc 722 * @addr: address offset of register 723 * 724 * Return: modified address offset of register 725 */ 726 727 static inline qdf_iomem_t hal_get_window_address_9224(struct hal_soc *hal_soc, 728 qdf_iomem_t addr) 729 { 730 uint32_t offset = addr - hal_soc->dev_base_addr; 731 qdf_iomem_t new_offset; 732 733 /* 734 * If offset lies within DP register range, use 3rd window to write 735 * into DP region. 736 */ 737 if ((offset ^ UMAC_BASE) < WINDOW_RANGE_MASK) { 738 new_offset = (hal_soc->dev_base_addr + (3 * WINDOW_START) + 739 (offset & WINDOW_RANGE_MASK)); 740 /* 741 * If offset lies within CE register range, use 2nd window to write 742 * into CE region. 743 */ 744 } else if ((offset ^ CE_WFSS_CE_REG_BASE) < WINDOW_RANGE_MASK) { 745 new_offset = (hal_soc->dev_base_addr + (2 * WINDOW_START) + 746 (offset & WINDOW_RANGE_MASK)); 747 } else { 748 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 749 "%s: ERROR: Accessing Wrong register\n", __func__); 750 qdf_assert_always(0); 751 return 0; 752 } 753 return new_offset; 754 } 755 756 static inline void hal_write_window_register(struct hal_soc *hal_soc) 757 { 758 /* Write value into window configuration register */ 759 qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_REG_ADDRESS, 760 WINDOW_CONFIGURATION_VALUE_9224); 761 } 762 763 static 764 void hal_compute_reo_remap_ix2_ix3_9224(uint32_t *ring, uint32_t num_rings, 765 uint32_t *remap1, uint32_t *remap2) 766 { 767 switch (num_rings) { 768 case 1: 769 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 770 HAL_REO_REMAP_IX2(ring[0], 17) | 771 HAL_REO_REMAP_IX2(ring[0], 18) | 772 HAL_REO_REMAP_IX2(ring[0], 19) | 773 HAL_REO_REMAP_IX2(ring[0], 20) | 774 HAL_REO_REMAP_IX2(ring[0], 21) | 775 HAL_REO_REMAP_IX2(ring[0], 22) | 776 HAL_REO_REMAP_IX2(ring[0], 23); 777 778 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 779 HAL_REO_REMAP_IX3(ring[0], 25) | 780 HAL_REO_REMAP_IX3(ring[0], 26) | 781 HAL_REO_REMAP_IX3(ring[0], 27) | 782 HAL_REO_REMAP_IX3(ring[0], 28) | 783 HAL_REO_REMAP_IX3(ring[0], 29) | 784 HAL_REO_REMAP_IX3(ring[0], 30) | 785 HAL_REO_REMAP_IX3(ring[0], 31); 786 break; 787 case 2: 788 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 789 HAL_REO_REMAP_IX2(ring[0], 17) | 790 HAL_REO_REMAP_IX2(ring[1], 18) | 791 HAL_REO_REMAP_IX2(ring[1], 19) | 792 HAL_REO_REMAP_IX2(ring[0], 20) | 793 HAL_REO_REMAP_IX2(ring[0], 21) | 794 HAL_REO_REMAP_IX2(ring[1], 22) | 795 HAL_REO_REMAP_IX2(ring[1], 23); 796 797 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 798 HAL_REO_REMAP_IX3(ring[0], 25) | 799 HAL_REO_REMAP_IX3(ring[1], 26) | 800 HAL_REO_REMAP_IX3(ring[1], 27) | 801 HAL_REO_REMAP_IX3(ring[0], 28) | 802 HAL_REO_REMAP_IX3(ring[0], 29) | 803 HAL_REO_REMAP_IX3(ring[1], 30) | 804 HAL_REO_REMAP_IX3(ring[1], 31); 805 break; 806 case 3: 807 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 808 HAL_REO_REMAP_IX2(ring[1], 17) | 809 HAL_REO_REMAP_IX2(ring[2], 18) | 810 HAL_REO_REMAP_IX2(ring[0], 19) | 811 HAL_REO_REMAP_IX2(ring[1], 20) | 812 HAL_REO_REMAP_IX2(ring[2], 21) | 813 HAL_REO_REMAP_IX2(ring[0], 22) | 814 HAL_REO_REMAP_IX2(ring[1], 23); 815 816 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) | 817 HAL_REO_REMAP_IX3(ring[0], 25) | 818 HAL_REO_REMAP_IX3(ring[1], 26) | 819 HAL_REO_REMAP_IX3(ring[2], 27) | 820 HAL_REO_REMAP_IX3(ring[0], 28) | 821 HAL_REO_REMAP_IX3(ring[1], 29) | 822 HAL_REO_REMAP_IX3(ring[2], 30) | 823 HAL_REO_REMAP_IX3(ring[0], 31); 824 break; 825 case 4: 826 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 827 HAL_REO_REMAP_IX2(ring[1], 17) | 828 HAL_REO_REMAP_IX2(ring[2], 18) | 829 HAL_REO_REMAP_IX2(ring[3], 19) | 830 HAL_REO_REMAP_IX2(ring[0], 20) | 831 HAL_REO_REMAP_IX2(ring[1], 21) | 832 HAL_REO_REMAP_IX2(ring[2], 22) | 833 HAL_REO_REMAP_IX2(ring[3], 23); 834 835 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 836 HAL_REO_REMAP_IX3(ring[1], 25) | 837 HAL_REO_REMAP_IX3(ring[2], 26) | 838 HAL_REO_REMAP_IX3(ring[3], 27) | 839 HAL_REO_REMAP_IX3(ring[0], 28) | 840 HAL_REO_REMAP_IX3(ring[1], 29) | 841 HAL_REO_REMAP_IX3(ring[2], 30) | 842 HAL_REO_REMAP_IX3(ring[3], 31); 843 break; 844 } 845 } 846 847 static 848 void hal_compute_reo_remap_ix0_9224(struct hal_soc *soc) 849 { 850 uint32_t remap0; 851 852 remap0 = HAL_REG_READ(soc, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR 853 (REO_REG_REG_BASE)); 854 855 remap0 &= ~(HAL_REO_REMAP_IX0(0xF, 6)); 856 remap0 |= HAL_REO_REMAP_IX0(REO2PPE_DST_RING, 6); 857 858 HAL_REG_WRITE(soc, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR 859 (REO_REG_REG_BASE), remap0); 860 861 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR 0x%x", 862 HAL_REG_READ(soc, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR 863 (REO_REG_REG_BASE))); 864 } 865 866 /** 867 * hal_rx_flow_setup_fse_9224() - Setup a flow search entry in HW FST 868 * @fst: Pointer to the Rx Flow Search Table 869 * @table_offset: offset into the table where the flow is to be setup 870 * @flow: Flow Parameters 871 * 872 * Return: Success/Failure 873 */ 874 static void * 875 hal_rx_flow_setup_fse_9224(uint8_t *rx_fst, uint32_t table_offset, 876 uint8_t *rx_flow) 877 { 878 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 879 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 880 uint8_t *fse; 881 bool fse_valid; 882 883 if (table_offset >= fst->max_entries) { 884 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 885 "HAL FSE table offset %u exceeds max entries %u", 886 table_offset, fst->max_entries); 887 return NULL; 888 } 889 890 fse = (uint8_t *)fst->base_vaddr + 891 (table_offset * HAL_RX_FST_ENTRY_SIZE); 892 893 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID); 894 895 if (fse_valid) { 896 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 897 "HAL FSE %pK already valid", fse); 898 return NULL; 899 } 900 901 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96) = 902 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96, 903 qdf_htonl(flow->tuple_info.src_ip_127_96)); 904 905 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64) = 906 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64, 907 qdf_htonl(flow->tuple_info.src_ip_95_64)); 908 909 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32) = 910 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32, 911 qdf_htonl(flow->tuple_info.src_ip_63_32)); 912 913 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0) = 914 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0, 915 qdf_htonl(flow->tuple_info.src_ip_31_0)); 916 917 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96) = 918 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96, 919 qdf_htonl(flow->tuple_info.dest_ip_127_96)); 920 921 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64) = 922 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64, 923 qdf_htonl(flow->tuple_info.dest_ip_95_64)); 924 925 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32) = 926 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32, 927 qdf_htonl(flow->tuple_info.dest_ip_63_32)); 928 929 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0) = 930 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0, 931 qdf_htonl(flow->tuple_info.dest_ip_31_0)); 932 933 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_PORT); 934 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_PORT) |= 935 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_PORT, 936 (flow->tuple_info.dest_port)); 937 938 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_PORT); 939 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_PORT) |= 940 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_PORT, 941 (flow->tuple_info.src_port)); 942 943 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL); 944 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL) |= 945 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL, 946 flow->tuple_info.l4_protocol); 947 948 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER); 949 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER) |= 950 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER, 951 flow->reo_destination_handler); 952 953 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID); 954 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID) |= 955 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, VALID, 1); 956 957 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, METADATA); 958 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, METADATA) = 959 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, METADATA, 960 flow->fse_metadata); 961 962 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_INDICATION); 963 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_INDICATION) |= 964 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, 965 REO_DESTINATION_INDICATION, 966 flow->reo_destination_indication); 967 968 /* Reset all the other fields in FSE */ 969 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, RESERVED_9); 970 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_DROP); 971 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_COUNT); 972 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_BYTE_COUNT); 973 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, TIMESTAMP); 974 975 return fse; 976 } 977 978 #ifndef NO_RX_PKT_HDR_TLV 979 /** 980 * hal_rx_dump_pkt_hdr_tlv: dump RX pkt header TLV in hex format 981 * @ pkt_hdr_tlv: pointer the pkt_hdr_tlv in pkt. 982 * @ dbg_level: log level. 983 * 984 * Return: void 985 */ 986 static inline void hal_rx_dump_pkt_hdr_tlv_9224(struct rx_pkt_tlvs *pkt_tlvs, 987 uint8_t dbg_level) 988 { 989 struct rx_pkt_hdr_tlv *pkt_hdr_tlv = &pkt_tlvs->pkt_hdr_tlv; 990 991 hal_verbose_debug("\n---------------\n" 992 "rx_pkt_hdr_tlv\n" 993 "---------------\n" 994 "phy_ppdu_id %llu ", 995 pkt_hdr_tlv->phy_ppdu_id); 996 997 hal_verbose_hex_dump(pkt_hdr_tlv->rx_pkt_hdr, 998 sizeof(pkt_hdr_tlv->rx_pkt_hdr)); 999 } 1000 #else 1001 /** 1002 * hal_rx_dump_pkt_hdr_tlv: dump RX pkt header TLV in hex format 1003 * @ pkt_hdr_tlv: pointer the pkt_hdr_tlv in pkt. 1004 * @ dbg_level: log level. 1005 * 1006 * Return: void 1007 */ 1008 static inline void hal_rx_dump_pkt_hdr_tlv_9224(struct rx_pkt_tlvs *pkt_tlvs, 1009 uint8_t dbg_level) 1010 { 1011 } 1012 #endif 1013 1014 /* 1015 * hal_tx_dump_ppe_vp_entry_9224() 1016 * @hal_soc_hdl: HAL SoC handle 1017 * 1018 * Return: void 1019 */ 1020 static inline 1021 void hal_tx_dump_ppe_vp_entry_9224(hal_soc_handle_t hal_soc_hdl) 1022 { 1023 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; 1024 uint32_t reg_addr, reg_val = 0, i; 1025 1026 for (i = 0; i < HAL_PPE_VP_ENTRIES_MAX; i++) { 1027 reg_addr = 1028 HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_ADDR( 1029 MAC_TCL_REG_REG_BASE, 1030 i); 1031 reg_val = HAL_REG_READ(soc, reg_addr); 1032 hal_verbose_debug("%d: 0x%x\n", i, reg_val); 1033 } 1034 } 1035 1036 /** 1037 * hal_rx_dump_pkt_tlvs_9224(): API to print RX Pkt TLVS QCN9224 1038 * @hal_soc_hdl: hal_soc handle 1039 * @buf: pointer the pkt buffer 1040 * @dbg_level: log level 1041 * 1042 * Return: void 1043 */ 1044 #ifdef CONFIG_WORD_BASED_TLV 1045 static void hal_rx_dump_pkt_tlvs_9224(hal_soc_handle_t hal_soc_hdl, 1046 uint8_t *buf, uint8_t dbg_level) 1047 { 1048 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1049 struct rx_msdu_end_compact *msdu_end = 1050 &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1051 struct rx_mpdu_start_compact *mpdu_start = 1052 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1053 1054 hal_rx_dump_msdu_end_tlv_9224(msdu_end, dbg_level); 1055 hal_rx_dump_mpdu_start_tlv_9224(mpdu_start, dbg_level); 1056 hal_rx_dump_pkt_hdr_tlv_9224(pkt_tlvs, dbg_level); 1057 } 1058 #else 1059 static void hal_rx_dump_pkt_tlvs_9224(hal_soc_handle_t hal_soc_hdl, 1060 uint8_t *buf, uint8_t dbg_level) 1061 { 1062 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1063 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1064 struct rx_mpdu_start *mpdu_start = 1065 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1066 1067 hal_rx_dump_msdu_end_tlv_9224(msdu_end, dbg_level); 1068 hal_rx_dump_mpdu_start_tlv_9224(mpdu_start, dbg_level); 1069 hal_rx_dump_pkt_hdr_tlv_9224(pkt_tlvs, dbg_level); 1070 } 1071 #endif 1072 1073 #define HAL_NUM_TCL_BANKS_9224 48 1074 1075 /** 1076 * hal_cmem_write_9224() - function for CMEM buffer writing 1077 * @hal_soc_hdl: HAL SOC handle 1078 * @offset: CMEM address 1079 * @value: value to write 1080 * 1081 * Return: None. 1082 */ 1083 static void hal_cmem_write_9224(hal_soc_handle_t hal_soc_hdl, 1084 uint32_t offset, 1085 uint32_t value) 1086 { 1087 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 1088 1089 pld_reg_write(hal->qdf_dev->dev, offset, value, NULL); 1090 } 1091 1092 /** 1093 * hal_tx_get_num_tcl_banks_9224() - Get number of banks in target 1094 * 1095 * Returns: number of bank 1096 */ 1097 static uint8_t hal_tx_get_num_tcl_banks_9224(void) 1098 { 1099 return HAL_NUM_TCL_BANKS_9224; 1100 } 1101 1102 static void hal_reo_setup_9224(struct hal_soc *soc, void *reoparams, 1103 int qref_reset) 1104 { 1105 uint32_t reg_val; 1106 struct hal_reo_params *reo_params = (struct hal_reo_params *)reoparams; 1107 1108 reg_val = HAL_REG_READ(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR( 1109 REO_REG_REG_BASE)); 1110 1111 hal_reo_config_9224(soc, reg_val, reo_params); 1112 /* Other ring enable bits and REO_ENABLE will be set by FW */ 1113 1114 /* TODO: Setup destination ring mapping if enabled */ 1115 1116 /* TODO: Error destination ring setting is left to default. 1117 * Default setting is to send all errors to release ring. 1118 */ 1119 1120 /* Set the reo descriptor swap bits in case of BIG endian platform */ 1121 hal_setup_reo_swap(soc); 1122 1123 HAL_REG_WRITE(soc, 1124 HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(REO_REG_REG_BASE), 1125 HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000); 1126 1127 HAL_REG_WRITE(soc, 1128 HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(REO_REG_REG_BASE), 1129 (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000)); 1130 1131 HAL_REG_WRITE(soc, 1132 HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(REO_REG_REG_BASE), 1133 (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000)); 1134 1135 HAL_REG_WRITE(soc, 1136 HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(REO_REG_REG_BASE), 1137 (HAL_DEFAULT_VO_REO_TIMEOUT_MS * 1000)); 1138 1139 /* 1140 * When hash based routing is enabled, routing of the rx packet 1141 * is done based on the following value: 1 _ _ _ _ The last 4 1142 * bits are based on hash[3:0]. This means the possible values 1143 * are 0x10 to 0x1f. This value is used to look-up the 1144 * ring ID configured in Destination_Ring_Ctrl_IX_* register. 1145 * The Destination_Ring_Ctrl_IX_2 and Destination_Ring_Ctrl_IX_3 1146 * registers need to be configured to set-up the 16 entries to 1147 * map the hash values to a ring number. There are 3 bits per 1148 * hash entry – which are mapped as follows: 1149 * 0: TCL, 1:SW1, 2:SW2, * 3:SW3, 4:SW4, 5:Release, 6:FW(WIFI), 1150 * 7: NOT_USED. 1151 */ 1152 if (reo_params->rx_hash_enabled) { 1153 hal_compute_reo_remap_ix0_9224(soc); 1154 1155 HAL_REG_WRITE(soc, 1156 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR 1157 (REO_REG_REG_BASE), reo_params->remap0); 1158 1159 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x", 1160 HAL_REG_READ(soc, 1161 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR( 1162 REO_REG_REG_BASE))); 1163 1164 HAL_REG_WRITE(soc, 1165 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 1166 (REO_REG_REG_BASE), reo_params->remap1); 1167 1168 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x", 1169 HAL_REG_READ(soc, 1170 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR( 1171 REO_REG_REG_BASE))); 1172 1173 HAL_REG_WRITE(soc, 1174 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 1175 (REO_REG_REG_BASE), reo_params->remap2); 1176 1177 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 0x%x", 1178 HAL_REG_READ(soc, 1179 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR( 1180 REO_REG_REG_BASE))); 1181 } 1182 1183 /* TODO: Check if the following registers shoould be setup by host: 1184 * AGING_CONTROL 1185 * HIGH_MEMORY_THRESHOLD 1186 * GLOBAL_LINK_DESC_COUNT_THRESH_IX_0[1,2] 1187 * GLOBAL_LINK_DESC_COUNT_CTRL 1188 */ 1189 1190 hal_reo_shared_qaddr_init((hal_soc_handle_t)soc, qref_reset); 1191 } 1192 1193 static uint16_t hal_get_rx_max_ba_window_qcn9224(int tid) 1194 { 1195 return HAL_RX_BA_WINDOW_1024; 1196 } 1197 1198 /** 1199 * hal_qcn9224_get_reo_qdesc_size()- Get the reo queue descriptor size 1200 * from the give Block-Ack window size 1201 * Return: reo queue descriptor size 1202 */ 1203 static uint32_t hal_qcn9224_get_reo_qdesc_size(uint32_t ba_window_size, int tid) 1204 { 1205 /* Hardcode the ba_window_size to HAL_RX_MAX_BA_WINDOW for 1206 * NON_QOS_TID until HW issues are resolved. 1207 */ 1208 if (tid != HAL_NON_QOS_TID) 1209 ba_window_size = hal_get_rx_max_ba_window_qcn9224(tid); 1210 1211 /* Return descriptor size corresponding to window size of 2 since 1212 * we set ba_window_size to 2 while setting up REO descriptors as 1213 * a WAR to get 2k jump exception aggregates are received without 1214 * a BA session. 1215 */ 1216 if (ba_window_size <= 1) { 1217 if (tid != HAL_NON_QOS_TID) 1218 return sizeof(struct rx_reo_queue) + 1219 sizeof(struct rx_reo_queue_ext); 1220 else 1221 return sizeof(struct rx_reo_queue); 1222 } 1223 1224 if (ba_window_size <= 105) 1225 return sizeof(struct rx_reo_queue) + 1226 sizeof(struct rx_reo_queue_ext); 1227 1228 if (ba_window_size <= 210) 1229 return sizeof(struct rx_reo_queue) + 1230 (2 * sizeof(struct rx_reo_queue_ext)); 1231 1232 if (ba_window_size <= 256) 1233 return sizeof(struct rx_reo_queue) + 1234 (3 * sizeof(struct rx_reo_queue_ext)); 1235 1236 return sizeof(struct rx_reo_queue) + 1237 (10 * sizeof(struct rx_reo_queue_ext)) + 1238 sizeof(struct rx_reo_queue_1k); 1239 } 1240 1241 /* 1242 * hal_tx_dump_ppe_vp_entry_9224() 1243 * @hal_soc_hdl: HAL SoC handle 1244 * 1245 * Return: Number of PPE VP entries 1246 */ 1247 static 1248 uint32_t hal_tx_get_num_ppe_vp_tbl_entries_9224(hal_soc_handle_t hal_soc_hdl) 1249 { 1250 return HAL_PPE_VP_ENTRIES_MAX; 1251 } 1252 1253 /** 1254 * hal_rx_tlv_msdu_done_copy_get_9224() - Get msdu done copy bit from rx_tlv 1255 * 1256 * Returns: msdu done copy bit 1257 */ 1258 static inline uint32_t hal_rx_tlv_msdu_done_copy_get_9224(uint8_t *buf) 1259 { 1260 return HAL_RX_TLV_MSDU_DONE_COPY_GET(buf); 1261 } 1262 1263 static void hal_hw_txrx_ops_attach_qcn9224(struct hal_soc *hal_soc) 1264 { 1265 /* init and setup */ 1266 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic; 1267 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic; 1268 hal_soc->ops->hal_srng_hw_disable = hal_srng_hw_disable_generic; 1269 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic; 1270 hal_soc->ops->hal_get_window_address = hal_get_window_address_9224; 1271 hal_soc->ops->hal_cmem_write = hal_cmem_write_9224; 1272 1273 /* tx */ 1274 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_9224; 1275 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_9224; 1276 hal_soc->ops->hal_tx_comp_get_status = 1277 hal_tx_comp_get_status_generic_be; 1278 hal_soc->ops->hal_tx_init_cmd_credit_ring = 1279 hal_tx_init_cmd_credit_ring_9224; 1280 hal_soc->ops->hal_tx_set_ppe_cmn_cfg = 1281 hal_tx_set_ppe_cmn_config_9224; 1282 hal_soc->ops->hal_tx_set_ppe_vp_entry = 1283 hal_tx_set_ppe_vp_entry_9224; 1284 hal_soc->ops->hal_tx_set_ppe_pri2tid = 1285 hal_tx_set_ppe_pri2tid_map_9224; 1286 hal_soc->ops->hal_tx_update_ppe_pri2tid = 1287 hal_tx_update_ppe_pri2tid_9224; 1288 hal_soc->ops->hal_tx_dump_ppe_vp_entry = 1289 hal_tx_dump_ppe_vp_entry_9224; 1290 hal_soc->ops->hal_tx_get_num_ppe_vp_tbl_entries = 1291 hal_tx_get_num_ppe_vp_tbl_entries_9224; 1292 hal_soc->ops->hal_tx_enable_pri2tid_map = 1293 hal_tx_enable_pri2tid_map_9224; 1294 hal_soc->ops->hal_tx_config_rbm_mapping_be = 1295 hal_tx_config_rbm_mapping_be_9224; 1296 1297 /* rx */ 1298 hal_soc->ops->hal_rx_msdu_start_nss_get = hal_rx_tlv_nss_get_be; 1299 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status = 1300 hal_rx_mon_hw_desc_get_mpdu_status_be; 1301 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_9224; 1302 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv = 1303 hal_rx_proc_phyrx_other_receive_info_tlv_9224; 1304 1305 hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_9224; 1306 hal_soc->ops->hal_rx_dump_mpdu_start_tlv = 1307 hal_rx_dump_mpdu_start_tlv_9224; 1308 hal_soc->ops->hal_rx_dump_pkt_tlvs = hal_rx_dump_pkt_tlvs_9224; 1309 1310 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_9224; 1311 hal_soc->ops->hal_rx_mpdu_start_tid_get = hal_rx_tlv_tid_get_be; 1312 hal_soc->ops->hal_rx_msdu_start_reception_type_get = 1313 hal_rx_tlv_reception_type_get_be; 1314 hal_soc->ops->hal_rx_msdu_end_da_idx_get = 1315 hal_rx_msdu_end_da_idx_get_be; 1316 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = 1317 hal_rx_msdu_desc_info_get_ptr_9224; 1318 hal_soc->ops->hal_rx_link_desc_msdu0_ptr = 1319 hal_rx_link_desc_msdu0_ptr_9224; 1320 hal_soc->ops->hal_reo_status_get_header = 1321 hal_reo_status_get_header_9224; 1322 hal_soc->ops->hal_rx_status_get_tlv_info = 1323 hal_rx_status_get_tlv_info_wrapper_be; 1324 hal_soc->ops->hal_rx_wbm_err_info_get = 1325 hal_rx_wbm_err_info_get_generic_be; 1326 hal_soc->ops->hal_tx_set_pcp_tid_map = 1327 hal_tx_set_pcp_tid_map_generic_be; 1328 hal_soc->ops->hal_tx_update_pcp_tid_map = 1329 hal_tx_update_pcp_tid_generic_be; 1330 hal_soc->ops->hal_tx_set_tidmap_prty = 1331 hal_tx_update_tidmap_prty_generic_be; 1332 hal_soc->ops->hal_rx_get_rx_fragment_number = 1333 hal_rx_get_rx_fragment_number_be, 1334 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = 1335 hal_rx_tlv_da_is_mcbc_get_be; 1336 hal_soc->ops->hal_rx_msdu_end_is_tkip_mic_err = 1337 hal_rx_tlv_is_tkip_mic_err_get_be; 1338 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = 1339 hal_rx_tlv_sa_is_valid_get_be; 1340 hal_soc->ops->hal_rx_msdu_end_sa_idx_get = hal_rx_tlv_sa_idx_get_be; 1341 hal_soc->ops->hal_rx_desc_is_first_msdu = hal_rx_desc_is_first_msdu_be; 1342 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get = 1343 hal_rx_tlv_l3_hdr_padding_get_be; 1344 hal_soc->ops->hal_rx_encryption_info_valid = 1345 hal_rx_encryption_info_valid_be; 1346 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_be; 1347 hal_soc->ops->hal_rx_msdu_end_first_msdu_get = 1348 hal_rx_tlv_first_msdu_get_be; 1349 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = 1350 hal_rx_tlv_da_is_valid_get_be; 1351 hal_soc->ops->hal_rx_msdu_end_last_msdu_get = 1352 hal_rx_tlv_last_msdu_get_be; 1353 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = 1354 hal_rx_get_mpdu_mac_ad4_valid_be; 1355 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get = 1356 hal_rx_mpdu_start_sw_peer_id_get_be; 1357 hal_soc->ops->hal_rx_tlv_peer_meta_data_get = 1358 hal_rx_msdu_peer_meta_data_get_be; 1359 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_be; 1360 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_be; 1361 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid = 1362 hal_rx_get_mpdu_frame_control_valid_be; 1363 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_be; 1364 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_be; 1365 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_be; 1366 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid = 1367 hal_rx_get_mpdu_sequence_control_valid_be; 1368 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_be; 1369 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_be; 1370 hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get = 1371 hal_rx_mpdu_start_mpdu_qos_control_valid_get_be; 1372 hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get = 1373 hal_rx_msdu_end_sa_sw_peer_id_get_be; 1374 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = 1375 hal_rx_msdu0_buffer_addr_lsb_9224; 1376 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = 1377 hal_rx_msdu_desc_info_ptr_get_9224; 1378 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_9224; 1379 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_9224; 1380 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_be; 1381 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_be; 1382 hal_soc->ops->hal_rx_get_mac_addr2_valid = 1383 hal_rx_get_mac_addr2_valid_be; 1384 hal_soc->ops->hal_reo_config = hal_reo_config_9224; 1385 hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_be; 1386 hal_soc->ops->hal_rx_msdu_flow_idx_invalid = 1387 hal_rx_msdu_flow_idx_invalid_be; 1388 hal_soc->ops->hal_rx_msdu_flow_idx_timeout = 1389 hal_rx_msdu_flow_idx_timeout_be; 1390 hal_soc->ops->hal_rx_msdu_fse_metadata_get = 1391 hal_rx_msdu_fse_metadata_get_be; 1392 hal_soc->ops->hal_rx_msdu_cce_match_get = 1393 hal_rx_msdu_cce_match_get_be; 1394 hal_soc->ops->hal_rx_msdu_cce_metadata_get = 1395 hal_rx_msdu_cce_metadata_get_be; 1396 hal_soc->ops->hal_rx_msdu_get_flow_params = 1397 hal_rx_msdu_get_flow_params_be; 1398 hal_soc->ops->hal_rx_tlv_get_tcp_chksum = hal_rx_tlv_get_tcp_chksum_be; 1399 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_be; 1400 1401 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) 1402 hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_9224; 1403 hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_9224; 1404 #else 1405 hal_soc->ops->hal_rx_get_bb_info = NULL; 1406 hal_soc->ops->hal_rx_get_rtt_info = NULL; 1407 #endif 1408 1409 /* rx - msdu fast path info fields */ 1410 hal_soc->ops->hal_rx_msdu_packet_metadata_get = 1411 hal_rx_msdu_packet_metadata_get_generic_be; 1412 hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid = 1413 hal_rx_mpdu_start_tlv_tag_valid_be; 1414 hal_soc->ops->hal_rx_wbm_err_msdu_continuation_get = 1415 hal_rx_wbm_err_msdu_continuation_get_9224; 1416 1417 /* rx - TLV struct offsets */ 1418 hal_soc->ops->hal_rx_msdu_end_offset_get = 1419 hal_rx_msdu_end_offset_get_generic; 1420 hal_soc->ops->hal_rx_mpdu_start_offset_get = 1421 hal_rx_mpdu_start_offset_get_generic; 1422 #ifndef NO_RX_PKT_HDR_TLV 1423 hal_soc->ops->hal_rx_pkt_tlv_offset_get = 1424 hal_rx_pkt_tlv_offset_get_generic; 1425 #endif 1426 hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_9224; 1427 1428 hal_soc->ops->hal_rx_flow_get_tuple_info = 1429 hal_rx_flow_get_tuple_info_be; 1430 hal_soc->ops->hal_rx_flow_delete_entry = 1431 hal_rx_flow_delete_entry_be; 1432 hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_be; 1433 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = 1434 hal_compute_reo_remap_ix2_ix3_9224; 1435 1436 hal_soc->ops->hal_rx_msdu_get_reo_destination_indication = 1437 hal_rx_msdu_get_reo_destination_indication_be; 1438 hal_soc->ops->hal_rx_get_tlv_size = hal_rx_get_tlv_size_generic_be; 1439 hal_soc->ops->hal_rx_msdu_is_wlan_mcast = 1440 hal_rx_msdu_is_wlan_mcast_generic_be; 1441 hal_soc->ops->hal_tx_get_num_tcl_banks = hal_tx_get_num_tcl_banks_9224; 1442 hal_soc->ops->hal_rx_tlv_decap_format_get = 1443 hal_rx_tlv_decap_format_get_be; 1444 #ifdef RECEIVE_OFFLOAD 1445 hal_soc->ops->hal_rx_tlv_get_offload_info = 1446 hal_rx_tlv_get_offload_info_be; 1447 hal_soc->ops->hal_rx_get_proto_params = hal_rx_get_proto_params_be; 1448 hal_soc->ops->hal_rx_get_l3_l4_offsets = hal_rx_get_l3_l4_offsets_be; 1449 #endif 1450 hal_soc->ops->hal_rx_tlv_msdu_done_get = 1451 hal_rx_tlv_msdu_done_copy_get_9224; 1452 hal_soc->ops->hal_rx_tlv_msdu_len_get = 1453 hal_rx_msdu_start_msdu_len_get_be; 1454 hal_soc->ops->hal_rx_get_frame_ctrl_field = 1455 hal_rx_get_frame_ctrl_field_be; 1456 hal_soc->ops->hal_rx_tlv_csum_err_get = hal_rx_tlv_csum_err_get_be; 1457 #ifndef CONFIG_WORD_BASED_TLV 1458 hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get = 1459 hal_rx_mpdu_info_ampdu_flag_get_be; 1460 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_be; 1461 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = 1462 hal_rx_hw_desc_get_ppduid_get_be; 1463 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_be; 1464 hal_soc->ops->hal_rx_tlv_phy_ppdu_id_get = 1465 hal_rx_attn_phy_ppdu_id_get_be; 1466 hal_soc->ops->hal_rx_get_filter_category = 1467 hal_rx_get_filter_category_be; 1468 #endif 1469 hal_soc->ops->hal_rx_tlv_msdu_len_set = 1470 hal_rx_msdu_start_msdu_len_set_be; 1471 hal_soc->ops->hal_rx_tlv_sgi_get = hal_rx_tlv_sgi_get_be; 1472 hal_soc->ops->hal_rx_tlv_rate_mcs_get = hal_rx_tlv_rate_mcs_get_be; 1473 hal_soc->ops->hal_rx_tlv_bw_get = hal_rx_tlv_bw_get_be; 1474 hal_soc->ops->hal_rx_tlv_get_pkt_type = hal_rx_tlv_get_pkt_type_be; 1475 hal_soc->ops->hal_rx_tlv_mic_err_get = hal_rx_tlv_mic_err_get_be; 1476 hal_soc->ops->hal_rx_tlv_decrypt_err_get = 1477 hal_rx_tlv_decrypt_err_get_be; 1478 hal_soc->ops->hal_rx_tlv_first_mpdu_get = hal_rx_tlv_first_mpdu_get_be; 1479 hal_soc->ops->hal_rx_tlv_get_is_decrypted = 1480 hal_rx_tlv_get_is_decrypted_be; 1481 hal_soc->ops->hal_rx_msdu_get_keyid = hal_rx_msdu_get_keyid_be; 1482 hal_soc->ops->hal_rx_tlv_get_freq = hal_rx_tlv_get_freq_be; 1483 hal_soc->ops->hal_rx_priv_info_set_in_tlv = 1484 hal_rx_priv_info_set_in_tlv_be; 1485 hal_soc->ops->hal_rx_priv_info_get_from_tlv = 1486 hal_rx_priv_info_get_from_tlv_be; 1487 hal_soc->ops->hal_rx_pkt_hdr_get = hal_rx_pkt_hdr_get_be; 1488 hal_soc->ops->hal_reo_setup = hal_reo_setup_9224; 1489 hal_soc->ops->hal_reo_config_reo2ppe_dest_info = NULL; 1490 #ifdef REO_SHARED_QREF_TABLE_EN 1491 hal_soc->ops->hal_reo_shared_qaddr_setup = hal_reo_shared_qaddr_setup_be; 1492 hal_soc->ops->hal_reo_shared_qaddr_init = hal_reo_shared_qaddr_init_be; 1493 hal_soc->ops->hal_reo_shared_qaddr_detach = hal_reo_shared_qaddr_detach_be; 1494 hal_soc->ops->hal_reo_shared_qaddr_write = hal_reo_shared_qaddr_write_be; 1495 hal_soc->ops->hal_reo_shared_qaddr_cache_clear = hal_reo_shared_qaddr_cache_clear_be; 1496 #endif 1497 /* Overwrite the default BE ops */ 1498 hal_soc->ops->hal_get_rx_max_ba_window = 1499 hal_get_rx_max_ba_window_qcn9224; 1500 hal_soc->ops->hal_get_reo_qdesc_size = hal_qcn9224_get_reo_qdesc_size; 1501 /* TX MONITOR */ 1502 #ifdef QCA_MONITOR_2_0_SUPPORT 1503 hal_soc->ops->hal_txmon_is_mon_buf_addr_tlv = 1504 hal_txmon_is_mon_buf_addr_tlv_generic_be; 1505 hal_soc->ops->hal_txmon_populate_packet_info = 1506 hal_txmon_populate_packet_info_generic_be; 1507 hal_soc->ops->hal_txmon_status_parse_tlv = 1508 hal_txmon_status_parse_tlv_generic_be; 1509 hal_soc->ops->hal_txmon_status_get_num_users = 1510 hal_txmon_status_get_num_users_generic_be; 1511 #endif /* QCA_MONITOR_2_0_SUPPORT */ 1512 hal_soc->ops->hal_compute_reo_remap_ix0 = NULL; 1513 hal_soc->ops->hal_tx_vdev_mismatch_routing_set = 1514 hal_tx_vdev_mismatch_routing_set_generic_be; 1515 hal_soc->ops->hal_tx_mcast_mlo_reinject_routing_set = 1516 hal_tx_mcast_mlo_reinject_routing_set_generic_be; 1517 hal_soc->ops->hal_get_ba_aging_timeout = 1518 hal_get_ba_aging_timeout_be_generic; 1519 hal_soc->ops->hal_setup_link_idle_list = 1520 hal_setup_link_idle_list_generic_be; 1521 hal_soc->ops->hal_cookie_conversion_reg_cfg_be = 1522 hal_cookie_conversion_reg_cfg_generic_be; 1523 hal_soc->ops->hal_set_ba_aging_timeout = 1524 hal_set_ba_aging_timeout_be_generic; 1525 hal_soc->ops->hal_tx_populate_bank_register = 1526 hal_tx_populate_bank_register_be; 1527 hal_soc->ops->hal_tx_vdev_mcast_ctrl_set = 1528 hal_tx_vdev_mcast_ctrl_set_be; 1529 #ifdef CONFIG_WORD_BASED_TLV 1530 hal_soc->ops->hal_rx_mpdu_start_wmask_get = 1531 hal_rx_mpdu_start_wmask_get_be; 1532 hal_soc->ops->hal_rx_msdu_end_wmask_get = 1533 hal_rx_msdu_end_wmask_get_be; 1534 #endif 1535 }; 1536 1537 /** 1538 * hal_srng_hw_reg_offset_init_qcn9224() - Initialize the HW srng reg offset 1539 * applicable only for QCN9224 1540 * @hal_soc: HAL Soc handle 1541 * 1542 * Return: None 1543 */ 1544 static inline void hal_srng_hw_reg_offset_init_qcn9224(struct hal_soc *hal_soc) 1545 { 1546 int32_t *hw_reg_offset = hal_soc->hal_hw_reg_offset; 1547 1548 hw_reg_offset[DST_MSI2_BASE_LSB] = REG_OFFSET(DST, MSI2_BASE_LSB), 1549 hw_reg_offset[DST_MSI2_BASE_MSB] = REG_OFFSET(DST, MSI2_BASE_MSB), 1550 hw_reg_offset[DST_MSI2_DATA] = REG_OFFSET(DST, MSI2_DATA), 1551 hw_reg_offset[DST_PRODUCER_INT2_SETUP] = 1552 REG_OFFSET(DST, PRODUCER_INT2_SETUP); 1553 } 1554