1 /* 2 * Copyright (c) 2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 #include "qdf_types.h" 20 #include "qdf_util.h" 21 #include "qdf_mem.h" 22 #include "qdf_nbuf.h" 23 #include "qdf_module.h" 24 25 #include "target_type.h" 26 #include "wcss_version.h" 27 28 #include "hal_be_hw_headers.h" 29 #include "hal_internal.h" 30 #include "hal_api.h" 31 #include "hal_flow.h" 32 #include "rx_flow_search_entry.h" 33 #include "hal_rx_flow_info.h" 34 #include "hal_be_api.h" 35 #include "tcl_entrance_from_ppe_ring.h" 36 #include "sw_monitor_ring.h" 37 #include "wcss_seq_hwioreg_umac.h" 38 #include "wfss_ce_reg_seq_hwioreg.h" 39 #include <uniform_reo_status_header.h> 40 #include <wbm_release_ring_tx.h> 41 #include <phyrx_location.h> 42 #ifdef QCA_MONITOR_2_0_SUPPORT 43 #include <mon_ingress_ring.h> 44 #include <mon_destination_ring.h> 45 #endif 46 #include "rx_reo_queue_1k.h" 47 48 #include <hal_be_rx.h> 49 50 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 51 RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 52 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 53 RX_MSDU_LINK_MSDU_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 54 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 55 RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 56 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 57 RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 58 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 59 REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 60 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER \ 61 STATUS_HEADER_REO_STATUS_NUMBER 62 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 63 STATUS_HEADER_TIMESTAMP 64 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 65 RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 66 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 67 RX_MSDU_LINK_MSDU_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 68 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 69 TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 70 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 71 TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 72 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 73 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_OFFSET 74 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 75 BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 76 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 77 BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 78 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 79 BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB 80 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 81 BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK 82 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 83 BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 84 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 85 BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 86 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 87 BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB 88 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 89 BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK 90 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 91 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_LSB 92 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 93 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MASK 94 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 95 WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 96 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 97 WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 98 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 99 WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 100 101 #ifdef QCA_MONITOR_2_0_SUPPORT 102 #include "hal_be_api_mon.h" 103 #endif 104 105 #ifdef CONFIG_WIFI_EMULATION_WIFI_3_0 106 #define CMEM_REG_BASE 0x0010e000 107 108 #define CMEM_WINDOW_ADDRESS_9224 \ 109 ((CMEM_REG_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) 110 #endif 111 112 #define CE_WINDOW_ADDRESS_9224 \ 113 ((CE_WFSS_CE_REG_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) 114 115 #define UMAC_WINDOW_ADDRESS_9224 \ 116 ((UMAC_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) 117 118 #ifdef CONFIG_WIFI_EMULATION_WIFI_3_0 119 #define WINDOW_CONFIGURATION_VALUE_9224 \ 120 ((CE_WINDOW_ADDRESS_9224 << 6) |\ 121 (UMAC_WINDOW_ADDRESS_9224 << 12) | \ 122 CMEM_WINDOW_ADDRESS_9224 | \ 123 WINDOW_ENABLE_BIT) 124 #else 125 #define WINDOW_CONFIGURATION_VALUE_9224 \ 126 ((CE_WINDOW_ADDRESS_9224 << 6) |\ 127 (UMAC_WINDOW_ADDRESS_9224 << 12) | \ 128 WINDOW_ENABLE_BIT) 129 #endif 130 131 /* For Berryllium sw2rxdma ring size increased to 20 bits */ 132 #define HAL_RXDMA_MAX_RING_SIZE_BE 0xFFFFF 133 134 #include "hal_9224_rx.h" 135 #include "hal_9224_tx.h" 136 #include "hal_be_rx_tlv.h" 137 #include <hal_be_generic_api.h> 138 139 #define PMM_REG_BASE_QCN9224 0xB500F8 140 141 /** 142 * hal_read_pmm_scratch_reg(): API to read PMM Scratch register 143 * 144 * @soc: HAL soc 145 * @base_addr: Base PMM register 146 * @reg_enum: Enum of the scratch register 147 * 148 * Return: uint32_t 149 */ 150 static inline 151 uint32_t hal_read_pmm_scratch_reg(struct hal_soc *soc, 152 uint32_t base_addr, 153 enum hal_scratch_reg_enum reg_enum) 154 { 155 uint32_t val = 0; 156 157 pld_reg_read(soc->qdf_dev->dev, base_addr + (reg_enum * 4), &val, NULL); 158 return val; 159 } 160 161 /** 162 * hal_get_tsf2_scratch_reg_qcn9224(): API to read tsf2 scratch register 163 * 164 * @hal_soc_hdl: HAL soc context 165 * @mac_id: mac id 166 * @value: Pointer to update tsf2 value 167 * 168 * Return: void 169 */ 170 static void hal_get_tsf2_scratch_reg_qcn9224(hal_soc_handle_t hal_soc_hdl, 171 uint8_t mac_id, uint64_t *value) 172 { 173 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; 174 uint32_t offset_lo, offset_hi; 175 enum hal_scratch_reg_enum enum_lo, enum_hi; 176 177 hal_get_tsf_enum(DEFAULT_TSF_ID, mac_id, &enum_lo, &enum_hi); 178 179 offset_lo = hal_read_pmm_scratch_reg(soc, 180 PMM_REG_BASE_QCN9224, 181 enum_lo); 182 183 offset_hi = hal_read_pmm_scratch_reg(soc, 184 PMM_REG_BASE_QCN9224, 185 enum_hi); 186 187 *value = ((uint64_t)(offset_hi) << 32 | offset_lo); 188 } 189 190 /** 191 * hal_get_tqm_scratch_reg_qcn9224(): API to read tqm scratch register 192 * 193 * @hal_soc_hdl: HAL soc context 194 * @value: Pointer to update tqm value 195 * 196 * Return: void 197 */ 198 static void hal_get_tqm_scratch_reg_qcn9224(hal_soc_handle_t hal_soc_hdl, 199 uint64_t *value) 200 { 201 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; 202 uint32_t offset_lo, offset_hi; 203 204 offset_lo = hal_read_pmm_scratch_reg(soc, 205 PMM_REG_BASE_QCN9224, 206 PMM_TQM_CLOCK_OFFSET_LO_US); 207 208 offset_hi = hal_read_pmm_scratch_reg(soc, 209 PMM_REG_BASE_QCN9224, 210 PMM_TQM_CLOCK_OFFSET_HI_US); 211 212 *value = ((uint64_t)(offset_hi) << 32 | offset_lo); 213 } 214 215 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 216 #define HAL_PPE_VP_ENTRIES_MAX 32 217 #define HAL_PPE_VP_SEARCH_IDX_REG_MAX 8 218 219 /** 220 * hal_get_link_desc_size_9224(): API to get the link desc size 221 * 222 * Return: uint32_t 223 */ 224 static uint32_t hal_get_link_desc_size_9224(void) 225 { 226 return LINK_DESC_SIZE; 227 } 228 229 /** 230 * hal_rx_get_tlv_9224(): API to get the tlv 231 * 232 * @rx_tlv: TLV data extracted from the rx packet 233 * Return: uint8_t 234 */ 235 static uint8_t hal_rx_get_tlv_9224(void *rx_tlv) 236 { 237 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY, RECEIVE_BANDWIDTH); 238 } 239 240 /** 241 * hal_rx_wbm_err_msdu_continuation_get_9224 () - API to check if WBM 242 * msdu continuation bit is set 243 * 244 *@wbm_desc: wbm release ring descriptor 245 * 246 * Return: true if msdu continuation bit is set. 247 */ 248 static inline 249 uint8_t hal_rx_wbm_err_msdu_continuation_get_9224(void *wbm_desc) 250 { 251 uint32_t comp_desc = *(uint32_t *)(((uint8_t *)wbm_desc) + 252 WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET); 253 254 return (comp_desc & 255 WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK) >> 256 WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB; 257 } 258 259 #if (defined(WLAN_SA_API_ENABLE)) && (defined(QCA_WIFI_QCA9574)) 260 #define HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, evm, pilot) \ 261 (ppdu_info)->evm_info.pilot_evm[pilot] = HAL_RX_GET(rx_tlv, \ 262 PHYRX_OTHER_RECEIVE_INFO, \ 263 SU_EVM_DETAILS_##evm##_PILOT_##pilot##_EVM) 264 265 static inline void 266 hal_rx_update_su_evm_info(void *rx_tlv, 267 void *ppdu_info_hdl) 268 { 269 struct hal_rx_ppdu_info *ppdu_info = 270 (struct hal_rx_ppdu_info *)ppdu_info_hdl; 271 272 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 1, 0); 273 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 2, 1); 274 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 3, 2); 275 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 4, 3); 276 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 5, 4); 277 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 6, 5); 278 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 7, 6); 279 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 8, 7); 280 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 9, 8); 281 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 10, 9); 282 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 11, 10); 283 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 12, 11); 284 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 13, 12); 285 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 14, 13); 286 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 15, 14); 287 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 16, 15); 288 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 17, 16); 289 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 18, 17); 290 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 19, 18); 291 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 20, 19); 292 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 21, 20); 293 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 22, 21); 294 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 23, 22); 295 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 24, 23); 296 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 25, 24); 297 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 26, 25); 298 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 27, 26); 299 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 28, 27); 300 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 29, 28); 301 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 30, 29); 302 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 31, 30); 303 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 32, 31); 304 } 305 306 static void hal_rx_get_evm_info(void *rx_tlv_hdr, void *ppdu_info_hdl) 307 { 308 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 309 void *rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 310 uint32_t tlv_tag; 311 312 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 313 314 switch (tlv_tag) { 315 case WIFIPHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_E: 316 317 /* Skip TLV length to get TLV content */ 318 rx_tlv = (uint8_t *)rx_tlv + HAL_RX_TLV32_HDR_SIZE; 319 320 ppdu_info->evm_info.number_of_symbols = HAL_RX_GET(rx_tlv, 321 PHYRX_OTHER_RECEIVE_INFO, 322 SU_EVM_DETAILS_0_NUMBER_OF_SYMBOLS); 323 ppdu_info->evm_info.pilot_count = HAL_RX_GET(rx_tlv, 324 PHYRX_OTHER_RECEIVE_INFO, 325 SU_EVM_DETAILS_0_PILOT_COUNT); 326 ppdu_info->evm_info.nss_count = HAL_RX_GET(rx_tlv, 327 PHYRX_OTHER_RECEIVE_INFO, 328 SU_EVM_DETAILS_0_NSS_COUNT); 329 hal_rx_update_su_evm_info(rx_tlv, ppdu_info_hdl); 330 break; 331 } 332 } 333 #else /* WLAN_SA_API_ENABLE && QCA_WIFI_QCA9574 */ 334 static void hal_rx_get_evm_info(void *tlv_tag, void *ppdu_info_hdl) 335 { 336 } 337 #endif /* WLAN_SA_API_ENABLE && QCA_WIFI_QCA9574 */ 338 339 /** 340 * hal_rx_proc_phyrx_other_receive_info_tlv_9224(): API to get tlv info 341 * 342 * Return: uint32_t 343 */ 344 static inline 345 void hal_rx_proc_phyrx_other_receive_info_tlv_9224(void *rx_tlv_hdr, 346 void *ppdu_info_hdl) 347 { 348 uint32_t tlv_tag, tlv_len; 349 uint32_t temp_len, other_tlv_len, other_tlv_tag; 350 void *rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 351 void *other_tlv_hdr = NULL; 352 void *other_tlv = NULL; 353 354 /* Get evm info for Smart Antenna */ 355 hal_rx_get_evm_info(rx_tlv_hdr, ppdu_info_hdl); 356 357 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 358 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 359 temp_len = 0; 360 361 other_tlv_hdr = rx_tlv + HAL_RX_TLV32_HDR_SIZE; 362 other_tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(other_tlv_hdr); 363 other_tlv_len = HAL_RX_GET_USER_TLV32_LEN(other_tlv_hdr); 364 365 temp_len += other_tlv_len; 366 other_tlv = other_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 367 368 switch (other_tlv_tag) { 369 default: 370 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 371 "%s unhandled TLV type: %d, TLV len:%d", 372 __func__, other_tlv_tag, other_tlv_len); 373 break; 374 } 375 } 376 377 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) 378 static inline 379 void hal_rx_get_bb_info_9224(void *rx_tlv, void *ppdu_info_hdl) 380 { 381 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 382 383 ppdu_info->cfr_info.bb_captured_channel = 384 HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_CHANNEL); 385 386 ppdu_info->cfr_info.bb_captured_timeout = 387 HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_TIMEOUT); 388 389 ppdu_info->cfr_info.bb_captured_reason = 390 HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_REASON); 391 } 392 393 static inline 394 void hal_rx_get_rtt_info_9224(void *rx_tlv, void *ppdu_info_hdl) 395 { 396 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 397 398 ppdu_info->cfr_info.rx_location_info_valid = 399 HAL_RX_GET_64(rx_tlv, PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 400 RX_LOCATION_INFO_VALID); 401 402 ppdu_info->cfr_info.rtt_che_buffer_pointer_low32 = 403 HAL_RX_GET_64(rx_tlv, 404 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 405 RTT_CHE_BUFFER_POINTER_LOW32); 406 407 ppdu_info->cfr_info.rtt_che_buffer_pointer_high8 = 408 HAL_RX_GET_64(rx_tlv, 409 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 410 RTT_CHE_BUFFER_POINTER_HIGH8); 411 412 ppdu_info->cfr_info.chan_capture_status = 413 HAL_GET_RX_LOCATION_INFO_CHAN_CAPTURE_STATUS(rx_tlv); 414 415 ppdu_info->cfr_info.rx_start_ts = 416 HAL_RX_GET_64(rx_tlv, 417 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 418 RX_START_TS); 419 420 ppdu_info->cfr_info.rtt_cfo_measurement = (int16_t) 421 HAL_RX_GET_64(rx_tlv, 422 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 423 RTT_CFO_MEASUREMENT); 424 425 ppdu_info->cfr_info.agc_gain_info0 = 426 HAL_RX_GET_64(rx_tlv, 427 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 428 GAIN_CHAIN0); 429 430 ppdu_info->cfr_info.agc_gain_info0 |= 431 (((uint32_t)HAL_RX_GET_64(rx_tlv, 432 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 433 GAIN_CHAIN1)) << 16); 434 435 ppdu_info->cfr_info.agc_gain_info1 = 436 HAL_RX_GET_64(rx_tlv, 437 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 438 GAIN_CHAIN2); 439 440 ppdu_info->cfr_info.agc_gain_info1 |= 441 (((uint32_t)HAL_RX_GET_64(rx_tlv, 442 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 443 GAIN_CHAIN3)) << 16); 444 445 ppdu_info->cfr_info.agc_gain_info2 = 0; 446 447 ppdu_info->cfr_info.agc_gain_info3 = 0; 448 449 ppdu_info->cfr_info.mcs_rate = 450 HAL_RX_GET_64(rx_tlv, 451 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 452 RTT_MCS_RATE); 453 ppdu_info->cfr_info.gi_type = 454 HAL_RX_GET_64(rx_tlv, 455 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 456 RTT_GI_TYPE); 457 } 458 #endif 459 460 #ifdef CONFIG_WORD_BASED_TLV 461 /** 462 * hal_rx_dump_mpdu_start_tlv_9224: dump RX mpdu_start TLV in structured 463 * human readable format. 464 * @mpdu_start: pointer the rx_attention TLV in pkt. 465 * @dbg_level: log level. 466 * 467 * Return: void 468 */ 469 static inline void hal_rx_dump_mpdu_start_tlv_9224(void *mpdustart, 470 uint8_t dbg_level) 471 { 472 struct rx_mpdu_start_compact *mpdu_info = 473 (struct rx_mpdu_start_compact *)mpdustart; 474 475 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 476 "rx_mpdu_start tlv (1/5) - " 477 "rx_reo_queue_desc_addr_39_32 :%x" 478 "receive_queue_number:%x " 479 "pre_delim_err_warning:%x " 480 "first_delim_err:%x " 481 "pn_31_0:%x " 482 "pn_63_32:%x " 483 "pn_95_64:%x ", 484 mpdu_info->rx_reo_queue_desc_addr_39_32, 485 mpdu_info->receive_queue_number, 486 mpdu_info->pre_delim_err_warning, 487 mpdu_info->first_delim_err, 488 mpdu_info->pn_31_0, 489 mpdu_info->pn_63_32, 490 mpdu_info->pn_95_64); 491 492 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 493 "rx_mpdu_start tlv (2/5) - " 494 "ast_index:%x " 495 "sw_peer_id:%x " 496 "mpdu_frame_control_valid:%x " 497 "mpdu_duration_valid:%x " 498 "mac_addr_ad1_valid:%x " 499 "mac_addr_ad2_valid:%x " 500 "mac_addr_ad3_valid:%x " 501 "mac_addr_ad4_valid:%x " 502 "mpdu_sequence_control_valid :%x" 503 "mpdu_qos_control_valid:%x " 504 "mpdu_ht_control_valid:%x " 505 "frame_encryption_info_valid :%x", 506 mpdu_info->ast_index, 507 mpdu_info->sw_peer_id, 508 mpdu_info->mpdu_frame_control_valid, 509 mpdu_info->mpdu_duration_valid, 510 mpdu_info->mac_addr_ad1_valid, 511 mpdu_info->mac_addr_ad2_valid, 512 mpdu_info->mac_addr_ad3_valid, 513 mpdu_info->mac_addr_ad4_valid, 514 mpdu_info->mpdu_sequence_control_valid, 515 mpdu_info->mpdu_qos_control_valid, 516 mpdu_info->mpdu_ht_control_valid, 517 mpdu_info->frame_encryption_info_valid); 518 519 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 520 "rx_mpdu_start tlv (3/5) - " 521 "mpdu_fragment_number:%x " 522 "more_fragment_flag:%x " 523 "fr_ds:%x " 524 "to_ds:%x " 525 "encrypted:%x " 526 "mpdu_retry:%x " 527 "mpdu_sequence_number:%x ", 528 mpdu_info->mpdu_fragment_number, 529 mpdu_info->more_fragment_flag, 530 mpdu_info->fr_ds, 531 mpdu_info->to_ds, 532 mpdu_info->encrypted, 533 mpdu_info->mpdu_retry, 534 mpdu_info->mpdu_sequence_number); 535 536 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 537 "rx_mpdu_start tlv (4/5) - " 538 "mpdu_frame_control_field:%x " 539 "mpdu_duration_field:%x ", 540 mpdu_info->mpdu_frame_control_field, 541 mpdu_info->mpdu_duration_field); 542 543 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 544 "rx_mpdu_start tlv (5/5) - " 545 "mac_addr_ad1_31_0:%x " 546 "mac_addr_ad1_47_32:%x " 547 "mac_addr_ad2_15_0:%x " 548 "mac_addr_ad2_47_16:%x " 549 "mac_addr_ad3_31_0:%x " 550 "mac_addr_ad3_47_32:%x " 551 "mpdu_sequence_control_field :%x", 552 mpdu_info->mac_addr_ad1_31_0, 553 mpdu_info->mac_addr_ad1_47_32, 554 mpdu_info->mac_addr_ad2_15_0, 555 mpdu_info->mac_addr_ad2_47_16, 556 mpdu_info->mac_addr_ad3_31_0, 557 mpdu_info->mac_addr_ad3_47_32, 558 mpdu_info->mpdu_sequence_control_field); 559 } 560 561 /** 562 * hal_rx_dump_msdu_end_tlv_9224: dump RX msdu_end TLV in structured 563 * human readable format. 564 * @ msdu_end: pointer the msdu_end TLV in pkt. 565 * @ dbg_level: log level. 566 * 567 * Return: void 568 */ 569 static void hal_rx_dump_msdu_end_tlv_9224(void *msduend, 570 uint8_t dbg_level) 571 { 572 struct rx_msdu_end_compact *msdu_end = 573 (struct rx_msdu_end_compact *)msduend; 574 575 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 576 "rx_msdu_end tlv - " 577 "key_id_octet: %d " 578 "tcp_udp_chksum: %d " 579 "sa_idx_timeout: %d " 580 "da_idx_timeout: %d " 581 "msdu_limit_error: %d " 582 "flow_idx_timeout: %d " 583 "flow_idx_invalid: %d " 584 "wifi_parser_error: %d " 585 "sa_is_valid: %d " 586 "da_is_valid: %d " 587 "da_is_mcbc: %d " 588 "tkip_mic_err: %d " 589 "l3_header_padding: %d " 590 "first_msdu: %d " 591 "last_msdu: %d " 592 "sa_idx: %d " 593 "msdu_drop: %d " 594 "reo_destination_indication: %d " 595 "flow_idx: %d " 596 "fse_metadata: %d " 597 "cce_metadata: %d " 598 "sa_sw_peer_id: %d ", 599 msdu_end->key_id_octet, 600 msdu_end->tcp_udp_chksum, 601 msdu_end->sa_idx_timeout, 602 msdu_end->da_idx_timeout, 603 msdu_end->msdu_limit_error, 604 msdu_end->flow_idx_timeout, 605 msdu_end->flow_idx_invalid, 606 msdu_end->wifi_parser_error, 607 msdu_end->sa_is_valid, 608 msdu_end->da_is_valid, 609 msdu_end->da_is_mcbc, 610 msdu_end->tkip_mic_err, 611 msdu_end->l3_header_padding, 612 msdu_end->first_msdu, 613 msdu_end->last_msdu, 614 msdu_end->sa_idx, 615 msdu_end->msdu_drop, 616 msdu_end->reo_destination_indication, 617 msdu_end->flow_idx, 618 msdu_end->fse_metadata, 619 msdu_end->cce_metadata, 620 msdu_end->sa_sw_peer_id); 621 } 622 #else 623 static inline void hal_rx_dump_mpdu_start_tlv_9224(void *mpdustart, 624 uint8_t dbg_level) 625 { 626 struct rx_mpdu_start *mpdu_start = (struct rx_mpdu_start *)mpdustart; 627 struct rx_mpdu_info *mpdu_info = 628 (struct rx_mpdu_info *)&mpdu_start->rx_mpdu_info_details; 629 630 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 631 "rx_mpdu_start tlv (1/5) - " 632 "rx_reo_queue_desc_addr_31_0 :%x" 633 "rx_reo_queue_desc_addr_39_32 :%x" 634 "receive_queue_number:%x " 635 "pre_delim_err_warning:%x " 636 "first_delim_err:%x " 637 "reserved_2a:%x " 638 "pn_31_0:%x " 639 "pn_63_32:%x " 640 "pn_95_64:%x " 641 "pn_127_96:%x " 642 "epd_en:%x " 643 "all_frames_shall_be_encrypted :%x" 644 "encrypt_type:%x " 645 "wep_key_width_for_variable_key :%x" 646 "mesh_sta:%x " 647 "bssid_hit:%x " 648 "bssid_number:%x " 649 "tid:%x " 650 "reserved_7a:%x ", 651 mpdu_info->rx_reo_queue_desc_addr_31_0, 652 mpdu_info->rx_reo_queue_desc_addr_39_32, 653 mpdu_info->receive_queue_number, 654 mpdu_info->pre_delim_err_warning, 655 mpdu_info->first_delim_err, 656 mpdu_info->reserved_2a, 657 mpdu_info->pn_31_0, 658 mpdu_info->pn_63_32, 659 mpdu_info->pn_95_64, 660 mpdu_info->pn_127_96, 661 mpdu_info->epd_en, 662 mpdu_info->all_frames_shall_be_encrypted, 663 mpdu_info->encrypt_type, 664 mpdu_info->wep_key_width_for_variable_key, 665 mpdu_info->mesh_sta, 666 mpdu_info->bssid_hit, 667 mpdu_info->bssid_number, 668 mpdu_info->tid, 669 mpdu_info->reserved_7a); 670 671 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 672 "rx_mpdu_start tlv (2/5) - " 673 "ast_index:%x " 674 "sw_peer_id:%x " 675 "mpdu_frame_control_valid:%x " 676 "mpdu_duration_valid:%x " 677 "mac_addr_ad1_valid:%x " 678 "mac_addr_ad2_valid:%x " 679 "mac_addr_ad3_valid:%x " 680 "mac_addr_ad4_valid:%x " 681 "mpdu_sequence_control_valid :%x" 682 "mpdu_qos_control_valid:%x " 683 "mpdu_ht_control_valid:%x " 684 "frame_encryption_info_valid :%x", 685 mpdu_info->ast_index, 686 mpdu_info->sw_peer_id, 687 mpdu_info->mpdu_frame_control_valid, 688 mpdu_info->mpdu_duration_valid, 689 mpdu_info->mac_addr_ad1_valid, 690 mpdu_info->mac_addr_ad2_valid, 691 mpdu_info->mac_addr_ad3_valid, 692 mpdu_info->mac_addr_ad4_valid, 693 mpdu_info->mpdu_sequence_control_valid, 694 mpdu_info->mpdu_qos_control_valid, 695 mpdu_info->mpdu_ht_control_valid, 696 mpdu_info->frame_encryption_info_valid); 697 698 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 699 "rx_mpdu_start tlv (3/5) - " 700 "mpdu_fragment_number:%x " 701 "more_fragment_flag:%x " 702 "reserved_11a:%x " 703 "fr_ds:%x " 704 "to_ds:%x " 705 "encrypted:%x " 706 "mpdu_retry:%x " 707 "mpdu_sequence_number:%x ", 708 mpdu_info->mpdu_fragment_number, 709 mpdu_info->more_fragment_flag, 710 mpdu_info->reserved_11a, 711 mpdu_info->fr_ds, 712 mpdu_info->to_ds, 713 mpdu_info->encrypted, 714 mpdu_info->mpdu_retry, 715 mpdu_info->mpdu_sequence_number); 716 717 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 718 "rx_mpdu_start tlv (4/5) - " 719 "mpdu_frame_control_field:%x " 720 "mpdu_duration_field:%x ", 721 mpdu_info->mpdu_frame_control_field, 722 mpdu_info->mpdu_duration_field); 723 724 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 725 "rx_mpdu_start tlv (5/5) - " 726 "mac_addr_ad1_31_0:%x " 727 "mac_addr_ad1_47_32:%x " 728 "mac_addr_ad2_15_0:%x " 729 "mac_addr_ad2_47_16:%x " 730 "mac_addr_ad3_31_0:%x " 731 "mac_addr_ad3_47_32:%x " 732 "mpdu_sequence_control_field :%x" 733 "mac_addr_ad4_31_0:%x " 734 "mac_addr_ad4_47_32:%x " 735 "mpdu_qos_control_field:%x ", 736 mpdu_info->mac_addr_ad1_31_0, 737 mpdu_info->mac_addr_ad1_47_32, 738 mpdu_info->mac_addr_ad2_15_0, 739 mpdu_info->mac_addr_ad2_47_16, 740 mpdu_info->mac_addr_ad3_31_0, 741 mpdu_info->mac_addr_ad3_47_32, 742 mpdu_info->mpdu_sequence_control_field, 743 mpdu_info->mac_addr_ad4_31_0, 744 mpdu_info->mac_addr_ad4_47_32, 745 mpdu_info->mpdu_qos_control_field); 746 } 747 748 static void hal_rx_dump_msdu_end_tlv_9224(void *msduend, 749 uint8_t dbg_level) 750 { 751 struct rx_msdu_end *msdu_end = 752 (struct rx_msdu_end *)msduend; 753 754 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 755 "rx_msdu_end tlv - " 756 "key_id_octet: %d " 757 "cce_super_rule: %d " 758 "cce_classify_not_done_truncat: %d " 759 "cce_classify_not_done_cce_dis: %d " 760 "rule_indication_31_0: %d " 761 "tcp_udp_chksum: %d " 762 "sa_idx_timeout: %d " 763 "da_idx_timeout: %d " 764 "msdu_limit_error: %d " 765 "flow_idx_timeout: %d " 766 "flow_idx_invalid: %d " 767 "wifi_parser_error: %d " 768 "sa_is_valid: %d " 769 "da_is_valid: %d " 770 "da_is_mcbc: %d " 771 "tkip_mic_err: %d " 772 "l3_header_padding: %d " 773 "first_msdu: %d " 774 "last_msdu: %d " 775 "sa_idx: %d " 776 "msdu_drop: %d " 777 "reo_destination_indication: %d " 778 "flow_idx: %d " 779 "fse_metadata: %d " 780 "cce_metadata: %d " 781 "sa_sw_peer_id: %d ", 782 msdu_end->key_id_octet, 783 msdu_end->cce_super_rule, 784 msdu_end->cce_classify_not_done_truncate, 785 msdu_end->cce_classify_not_done_cce_dis, 786 msdu_end->rule_indication_31_0, 787 msdu_end->tcp_udp_chksum, 788 msdu_end->sa_idx_timeout, 789 msdu_end->da_idx_timeout, 790 msdu_end->msdu_limit_error, 791 msdu_end->flow_idx_timeout, 792 msdu_end->flow_idx_invalid, 793 msdu_end->wifi_parser_error, 794 msdu_end->sa_is_valid, 795 msdu_end->da_is_valid, 796 msdu_end->da_is_mcbc, 797 msdu_end->tkip_mic_err, 798 msdu_end->l3_header_padding, 799 msdu_end->first_msdu, 800 msdu_end->last_msdu, 801 msdu_end->sa_idx, 802 msdu_end->msdu_drop, 803 msdu_end->reo_destination_indication, 804 msdu_end->flow_idx, 805 msdu_end->fse_metadata, 806 msdu_end->cce_metadata, 807 msdu_end->sa_sw_peer_id); 808 } 809 #endif 810 811 /** 812 * hal_reo_status_get_header_9224 - Process reo desc info 813 * @d - Pointer to reo descriptor 814 * @b - tlv type info 815 * @h1 - Pointer to hal_reo_status_header where info to be stored 816 * 817 * Return - none. 818 * 819 */ 820 static void hal_reo_status_get_header_9224(hal_ring_desc_t ring_desc, 821 int b, void *h1) 822 { 823 uint64_t *d = (uint64_t *)ring_desc; 824 uint64_t val1 = 0; 825 struct hal_reo_status_header *h = 826 (struct hal_reo_status_header *)h1; 827 828 /* Offsets of descriptor fields defined in HW headers start 829 * from the field after TLV header 830 */ 831 d += HAL_GET_NUM_QWORDS(sizeof(struct tlv_32_hdr)); 832 833 switch (b) { 834 case HAL_REO_QUEUE_STATS_STATUS_TLV: 835 val1 = d[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS, 836 STATUS_HEADER_REO_STATUS_NUMBER)]; 837 break; 838 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 839 val1 = d[HAL_OFFSET_QW(REO_FLUSH_QUEUE_STATUS, 840 STATUS_HEADER_REO_STATUS_NUMBER)]; 841 break; 842 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 843 val1 = d[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS, 844 STATUS_HEADER_REO_STATUS_NUMBER)]; 845 break; 846 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 847 val1 = d[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS, 848 STATUS_HEADER_REO_STATUS_NUMBER)]; 849 break; 850 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 851 val1 = d[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS, 852 STATUS_HEADER_REO_STATUS_NUMBER)]; 853 break; 854 case HAL_REO_DESC_THRES_STATUS_TLV: 855 val1 = 856 d[HAL_OFFSET_QW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS, 857 STATUS_HEADER_REO_STATUS_NUMBER)]; 858 break; 859 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 860 val1 = d[HAL_OFFSET_QW(REO_UPDATE_RX_REO_QUEUE_STATUS, 861 STATUS_HEADER_REO_STATUS_NUMBER)]; 862 break; 863 default: 864 qdf_nofl_err("ERROR: Unknown tlv\n"); 865 break; 866 } 867 h->cmd_num = 868 HAL_GET_FIELD( 869 UNIFORM_REO_STATUS_HEADER, REO_STATUS_NUMBER, 870 val1); 871 h->exec_time = 872 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, 873 CMD_EXECUTION_TIME, val1); 874 h->status = 875 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, 876 REO_CMD_EXECUTION_STATUS, val1); 877 switch (b) { 878 case HAL_REO_QUEUE_STATS_STATUS_TLV: 879 val1 = d[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS, 880 STATUS_HEADER_TIMESTAMP)]; 881 break; 882 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 883 val1 = d[HAL_OFFSET_QW(REO_FLUSH_QUEUE_STATUS, 884 STATUS_HEADER_TIMESTAMP)]; 885 break; 886 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 887 val1 = d[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS, 888 STATUS_HEADER_TIMESTAMP)]; 889 break; 890 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 891 val1 = d[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS, 892 STATUS_HEADER_TIMESTAMP)]; 893 break; 894 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 895 val1 = d[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS, 896 STATUS_HEADER_TIMESTAMP)]; 897 break; 898 case HAL_REO_DESC_THRES_STATUS_TLV: 899 val1 = 900 d[HAL_OFFSET_QW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS, 901 STATUS_HEADER_TIMESTAMP)]; 902 break; 903 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 904 val1 = d[HAL_OFFSET_QW(REO_UPDATE_RX_REO_QUEUE_STATUS, 905 STATUS_HEADER_TIMESTAMP)]; 906 break; 907 default: 908 qdf_nofl_err("ERROR: Unknown tlv\n"); 909 break; 910 } 911 h->tstamp = 912 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, TIMESTAMP, val1); 913 } 914 915 static 916 void *hal_rx_msdu0_buffer_addr_lsb_9224(void *link_desc_va) 917 { 918 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 919 } 920 921 static 922 void *hal_rx_msdu_desc_info_ptr_get_9224(void *msdu0) 923 { 924 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 925 } 926 927 static 928 void *hal_ent_mpdu_desc_info_9224(void *ent_ring_desc) 929 { 930 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 931 } 932 933 static 934 void *hal_dst_mpdu_desc_info_9224(void *dst_ring_desc) 935 { 936 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 937 } 938 939 /** 940 * hal_reo_config_9224(): Set reo config parameters 941 * @soc: hal soc handle 942 * @reg_val: value to be set 943 * @reo_params: reo parameters 944 * 945 * Return: void 946 */ 947 static void 948 hal_reo_config_9224(struct hal_soc *soc, 949 uint32_t reg_val, 950 struct hal_reo_params *reo_params) 951 { 952 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 953 } 954 955 /** 956 * hal_rx_msdu_desc_info_get_ptr_9224() - Get msdu desc info ptr 957 * @msdu_details_ptr - Pointer to msdu_details_ptr 958 * 959 * Return - Pointer to rx_msdu_desc_info structure. 960 * 961 */ 962 static void *hal_rx_msdu_desc_info_get_ptr_9224(void *msdu_details_ptr) 963 { 964 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 965 } 966 967 /** 968 * hal_rx_link_desc_msdu0_ptr_9224 - Get pointer to rx_msdu details 969 * @link_desc - Pointer to link desc 970 * 971 * Return - Pointer to rx_msdu_details structure 972 * 973 */ 974 static void *hal_rx_link_desc_msdu0_ptr_9224(void *link_desc) 975 { 976 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 977 } 978 979 /** 980 * hal_get_window_address_9224(): Function to get hp/tp address 981 * @hal_soc: Pointer to hal_soc 982 * @addr: address offset of register 983 * 984 * Return: modified address offset of register 985 */ 986 987 static inline qdf_iomem_t hal_get_window_address_9224(struct hal_soc *hal_soc, 988 qdf_iomem_t addr) 989 { 990 uint32_t offset = addr - hal_soc->dev_base_addr; 991 qdf_iomem_t new_offset; 992 993 /* 994 * If offset lies within DP register range, use 3rd window to write 995 * into DP region. 996 */ 997 if ((offset ^ UMAC_BASE) < WINDOW_RANGE_MASK) { 998 new_offset = (hal_soc->dev_base_addr + (3 * WINDOW_START) + 999 (offset & WINDOW_RANGE_MASK)); 1000 /* 1001 * If offset lies within CE register range, use 2nd window to write 1002 * into CE region. 1003 */ 1004 } else if ((offset ^ CE_WFSS_CE_REG_BASE) < WINDOW_RANGE_MASK) { 1005 new_offset = (hal_soc->dev_base_addr + (2 * WINDOW_START) + 1006 (offset & WINDOW_RANGE_MASK)); 1007 } else { 1008 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 1009 "%s: ERROR: Accessing Wrong register\n", __func__); 1010 qdf_assert_always(0); 1011 return 0; 1012 } 1013 return new_offset; 1014 } 1015 1016 static inline void hal_write_window_register(struct hal_soc *hal_soc) 1017 { 1018 /* Write value into window configuration register */ 1019 qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_REG_ADDRESS, 1020 WINDOW_CONFIGURATION_VALUE_9224); 1021 } 1022 1023 static 1024 void hal_compute_reo_remap_ix2_ix3_9224(uint32_t *ring, uint32_t num_rings, 1025 uint32_t *remap1, uint32_t *remap2) 1026 { 1027 switch (num_rings) { 1028 case 1: 1029 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1030 HAL_REO_REMAP_IX2(ring[0], 17) | 1031 HAL_REO_REMAP_IX2(ring[0], 18) | 1032 HAL_REO_REMAP_IX2(ring[0], 19) | 1033 HAL_REO_REMAP_IX2(ring[0], 20) | 1034 HAL_REO_REMAP_IX2(ring[0], 21) | 1035 HAL_REO_REMAP_IX2(ring[0], 22) | 1036 HAL_REO_REMAP_IX2(ring[0], 23); 1037 1038 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1039 HAL_REO_REMAP_IX3(ring[0], 25) | 1040 HAL_REO_REMAP_IX3(ring[0], 26) | 1041 HAL_REO_REMAP_IX3(ring[0], 27) | 1042 HAL_REO_REMAP_IX3(ring[0], 28) | 1043 HAL_REO_REMAP_IX3(ring[0], 29) | 1044 HAL_REO_REMAP_IX3(ring[0], 30) | 1045 HAL_REO_REMAP_IX3(ring[0], 31); 1046 break; 1047 case 2: 1048 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1049 HAL_REO_REMAP_IX2(ring[0], 17) | 1050 HAL_REO_REMAP_IX2(ring[1], 18) | 1051 HAL_REO_REMAP_IX2(ring[1], 19) | 1052 HAL_REO_REMAP_IX2(ring[0], 20) | 1053 HAL_REO_REMAP_IX2(ring[0], 21) | 1054 HAL_REO_REMAP_IX2(ring[1], 22) | 1055 HAL_REO_REMAP_IX2(ring[1], 23); 1056 1057 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1058 HAL_REO_REMAP_IX3(ring[0], 25) | 1059 HAL_REO_REMAP_IX3(ring[1], 26) | 1060 HAL_REO_REMAP_IX3(ring[1], 27) | 1061 HAL_REO_REMAP_IX3(ring[0], 28) | 1062 HAL_REO_REMAP_IX3(ring[0], 29) | 1063 HAL_REO_REMAP_IX3(ring[1], 30) | 1064 HAL_REO_REMAP_IX3(ring[1], 31); 1065 break; 1066 case 3: 1067 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1068 HAL_REO_REMAP_IX2(ring[1], 17) | 1069 HAL_REO_REMAP_IX2(ring[2], 18) | 1070 HAL_REO_REMAP_IX2(ring[0], 19) | 1071 HAL_REO_REMAP_IX2(ring[1], 20) | 1072 HAL_REO_REMAP_IX2(ring[2], 21) | 1073 HAL_REO_REMAP_IX2(ring[0], 22) | 1074 HAL_REO_REMAP_IX2(ring[1], 23); 1075 1076 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) | 1077 HAL_REO_REMAP_IX3(ring[0], 25) | 1078 HAL_REO_REMAP_IX3(ring[1], 26) | 1079 HAL_REO_REMAP_IX3(ring[2], 27) | 1080 HAL_REO_REMAP_IX3(ring[0], 28) | 1081 HAL_REO_REMAP_IX3(ring[1], 29) | 1082 HAL_REO_REMAP_IX3(ring[2], 30) | 1083 HAL_REO_REMAP_IX3(ring[0], 31); 1084 break; 1085 case 4: 1086 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1087 HAL_REO_REMAP_IX2(ring[1], 17) | 1088 HAL_REO_REMAP_IX2(ring[2], 18) | 1089 HAL_REO_REMAP_IX2(ring[3], 19) | 1090 HAL_REO_REMAP_IX2(ring[0], 20) | 1091 HAL_REO_REMAP_IX2(ring[1], 21) | 1092 HAL_REO_REMAP_IX2(ring[2], 22) | 1093 HAL_REO_REMAP_IX2(ring[3], 23); 1094 1095 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1096 HAL_REO_REMAP_IX3(ring[1], 25) | 1097 HAL_REO_REMAP_IX3(ring[2], 26) | 1098 HAL_REO_REMAP_IX3(ring[3], 27) | 1099 HAL_REO_REMAP_IX3(ring[0], 28) | 1100 HAL_REO_REMAP_IX3(ring[1], 29) | 1101 HAL_REO_REMAP_IX3(ring[2], 30) | 1102 HAL_REO_REMAP_IX3(ring[3], 31); 1103 break; 1104 } 1105 } 1106 1107 static 1108 void hal_compute_reo_remap_ix0_9224(struct hal_soc *soc) 1109 { 1110 uint32_t remap0; 1111 1112 remap0 = HAL_REG_READ(soc, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR 1113 (REO_REG_REG_BASE)); 1114 1115 remap0 &= ~(HAL_REO_REMAP_IX0(0xF, 6)); 1116 remap0 |= HAL_REO_REMAP_IX0(REO2PPE_DST_RING, 6); 1117 1118 HAL_REG_WRITE(soc, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR 1119 (REO_REG_REG_BASE), remap0); 1120 1121 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR 0x%x", 1122 HAL_REG_READ(soc, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR 1123 (REO_REG_REG_BASE))); 1124 } 1125 1126 /** 1127 * hal_rx_flow_setup_fse_9224() - Setup a flow search entry in HW FST 1128 * @fst: Pointer to the Rx Flow Search Table 1129 * @table_offset: offset into the table where the flow is to be setup 1130 * @flow: Flow Parameters 1131 * 1132 * Return: Success/Failure 1133 */ 1134 static void * 1135 hal_rx_flow_setup_fse_9224(uint8_t *rx_fst, uint32_t table_offset, 1136 uint8_t *rx_flow) 1137 { 1138 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 1139 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 1140 uint8_t *fse; 1141 bool fse_valid; 1142 1143 if (table_offset >= fst->max_entries) { 1144 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 1145 "HAL FSE table offset %u exceeds max entries %u", 1146 table_offset, fst->max_entries); 1147 return NULL; 1148 } 1149 1150 fse = (uint8_t *)fst->base_vaddr + 1151 (table_offset * HAL_RX_FST_ENTRY_SIZE); 1152 1153 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID); 1154 1155 if (fse_valid) { 1156 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 1157 "HAL FSE %pK already valid", fse); 1158 return NULL; 1159 } 1160 1161 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96) = 1162 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96, 1163 qdf_htonl(flow->tuple_info.src_ip_127_96)); 1164 1165 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64) = 1166 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64, 1167 qdf_htonl(flow->tuple_info.src_ip_95_64)); 1168 1169 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32) = 1170 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32, 1171 qdf_htonl(flow->tuple_info.src_ip_63_32)); 1172 1173 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0) = 1174 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0, 1175 qdf_htonl(flow->tuple_info.src_ip_31_0)); 1176 1177 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96) = 1178 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96, 1179 qdf_htonl(flow->tuple_info.dest_ip_127_96)); 1180 1181 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64) = 1182 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64, 1183 qdf_htonl(flow->tuple_info.dest_ip_95_64)); 1184 1185 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32) = 1186 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32, 1187 qdf_htonl(flow->tuple_info.dest_ip_63_32)); 1188 1189 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0) = 1190 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0, 1191 qdf_htonl(flow->tuple_info.dest_ip_31_0)); 1192 1193 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_PORT); 1194 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_PORT) |= 1195 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_PORT, 1196 (flow->tuple_info.dest_port)); 1197 1198 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_PORT); 1199 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_PORT) |= 1200 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_PORT, 1201 (flow->tuple_info.src_port)); 1202 1203 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL); 1204 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL) |= 1205 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL, 1206 flow->tuple_info.l4_protocol); 1207 1208 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, USE_PPE); 1209 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, USE_PPE) |= 1210 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, USE_PPE, flow->use_ppe_ds); 1211 1212 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, PRIORITY_VALID); 1213 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, PRIORITY_VALID) |= 1214 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, PRIORITY_VALID, 1215 flow->priority_vld); 1216 1217 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, SERVICE_CODE); 1218 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SERVICE_CODE) |= 1219 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SERVICE_CODE, 1220 flow->service_code); 1221 1222 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER); 1223 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER) |= 1224 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER, 1225 flow->reo_destination_handler); 1226 1227 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID); 1228 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID) |= 1229 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, VALID, 1); 1230 1231 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, METADATA); 1232 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, METADATA) = 1233 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, METADATA, 1234 flow->fse_metadata); 1235 1236 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_INDICATION); 1237 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_INDICATION) |= 1238 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, 1239 REO_DESTINATION_INDICATION, 1240 flow->reo_destination_indication); 1241 1242 /* Reset all the other fields in FSE */ 1243 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, RESERVED_9); 1244 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_DROP); 1245 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_COUNT); 1246 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_BYTE_COUNT); 1247 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, TIMESTAMP); 1248 1249 return fse; 1250 } 1251 1252 #ifndef NO_RX_PKT_HDR_TLV 1253 /** 1254 * hal_rx_dump_pkt_hdr_tlv: dump RX pkt header TLV in hex format 1255 * @ pkt_hdr_tlv: pointer the pkt_hdr_tlv in pkt. 1256 * @ dbg_level: log level. 1257 * 1258 * Return: void 1259 */ 1260 static inline void hal_rx_dump_pkt_hdr_tlv_9224(struct rx_pkt_tlvs *pkt_tlvs, 1261 uint8_t dbg_level) 1262 { 1263 struct rx_pkt_hdr_tlv *pkt_hdr_tlv = &pkt_tlvs->pkt_hdr_tlv; 1264 1265 hal_verbose_debug("\n---------------\n" 1266 "rx_pkt_hdr_tlv\n" 1267 "---------------\n" 1268 "phy_ppdu_id %llu ", 1269 pkt_hdr_tlv->phy_ppdu_id); 1270 1271 hal_verbose_hex_dump(pkt_hdr_tlv->rx_pkt_hdr, 1272 sizeof(pkt_hdr_tlv->rx_pkt_hdr)); 1273 } 1274 #else 1275 /** 1276 * hal_rx_dump_pkt_hdr_tlv: dump RX pkt header TLV in hex format 1277 * @ pkt_hdr_tlv: pointer the pkt_hdr_tlv in pkt. 1278 * @ dbg_level: log level. 1279 * 1280 * Return: void 1281 */ 1282 static inline void hal_rx_dump_pkt_hdr_tlv_9224(struct rx_pkt_tlvs *pkt_tlvs, 1283 uint8_t dbg_level) 1284 { 1285 } 1286 #endif 1287 1288 /* 1289 * hal_tx_dump_ppe_vp_entry_9224() 1290 * @hal_soc_hdl: HAL SoC handle 1291 * 1292 * Return: void 1293 */ 1294 static inline 1295 void hal_tx_dump_ppe_vp_entry_9224(hal_soc_handle_t hal_soc_hdl) 1296 { 1297 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; 1298 uint32_t reg_addr, reg_val = 0, i; 1299 1300 for (i = 0; i < HAL_PPE_VP_ENTRIES_MAX; i++) { 1301 reg_addr = 1302 HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_ADDR( 1303 MAC_TCL_REG_REG_BASE, 1304 i); 1305 reg_val = HAL_REG_READ(soc, reg_addr); 1306 hal_verbose_debug("%d: 0x%x\n", i, reg_val); 1307 } 1308 } 1309 1310 /** 1311 * hal_rx_dump_pkt_tlvs_9224(): API to print RX Pkt TLVS QCN9224 1312 * @hal_soc_hdl: hal_soc handle 1313 * @buf: pointer the pkt buffer 1314 * @dbg_level: log level 1315 * 1316 * Return: void 1317 */ 1318 #ifdef CONFIG_WORD_BASED_TLV 1319 static void hal_rx_dump_pkt_tlvs_9224(hal_soc_handle_t hal_soc_hdl, 1320 uint8_t *buf, uint8_t dbg_level) 1321 { 1322 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1323 struct rx_msdu_end_compact *msdu_end = 1324 &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1325 struct rx_mpdu_start_compact *mpdu_start = 1326 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1327 1328 hal_rx_dump_msdu_end_tlv_9224(msdu_end, dbg_level); 1329 hal_rx_dump_mpdu_start_tlv_9224(mpdu_start, dbg_level); 1330 hal_rx_dump_pkt_hdr_tlv_9224(pkt_tlvs, dbg_level); 1331 } 1332 #else 1333 static void hal_rx_dump_pkt_tlvs_9224(hal_soc_handle_t hal_soc_hdl, 1334 uint8_t *buf, uint8_t dbg_level) 1335 { 1336 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1337 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1338 struct rx_mpdu_start *mpdu_start = 1339 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1340 1341 hal_rx_dump_msdu_end_tlv_9224(msdu_end, dbg_level); 1342 hal_rx_dump_mpdu_start_tlv_9224(mpdu_start, dbg_level); 1343 hal_rx_dump_pkt_hdr_tlv_9224(pkt_tlvs, dbg_level); 1344 } 1345 #endif 1346 1347 #define HAL_NUM_TCL_BANKS_9224 48 1348 1349 /** 1350 * hal_cmem_write_9224() - function for CMEM buffer writing 1351 * @hal_soc_hdl: HAL SOC handle 1352 * @offset: CMEM address 1353 * @value: value to write 1354 * 1355 * Return: None. 1356 */ 1357 static void hal_cmem_write_9224(hal_soc_handle_t hal_soc_hdl, 1358 uint32_t offset, 1359 uint32_t value) 1360 { 1361 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 1362 1363 pld_reg_write(hal->qdf_dev->dev, offset, value, NULL); 1364 } 1365 1366 /** 1367 * hal_tx_get_num_tcl_banks_9224() - Get number of banks in target 1368 * 1369 * Returns: number of bank 1370 */ 1371 static uint8_t hal_tx_get_num_tcl_banks_9224(void) 1372 { 1373 return HAL_NUM_TCL_BANKS_9224; 1374 } 1375 1376 static void hal_reo_setup_9224(struct hal_soc *soc, void *reoparams, 1377 int qref_reset) 1378 { 1379 uint32_t reg_val; 1380 struct hal_reo_params *reo_params = (struct hal_reo_params *)reoparams; 1381 1382 reg_val = HAL_REG_READ(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR( 1383 REO_REG_REG_BASE)); 1384 1385 hal_reo_config_9224(soc, reg_val, reo_params); 1386 /* Other ring enable bits and REO_ENABLE will be set by FW */ 1387 1388 /* TODO: Setup destination ring mapping if enabled */ 1389 1390 /* TODO: Error destination ring setting is left to default. 1391 * Default setting is to send all errors to release ring. 1392 */ 1393 1394 /* Set the reo descriptor swap bits in case of BIG endian platform */ 1395 hal_setup_reo_swap(soc); 1396 1397 HAL_REG_WRITE(soc, 1398 HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(REO_REG_REG_BASE), 1399 HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000); 1400 1401 HAL_REG_WRITE(soc, 1402 HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(REO_REG_REG_BASE), 1403 (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000)); 1404 1405 HAL_REG_WRITE(soc, 1406 HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(REO_REG_REG_BASE), 1407 (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000)); 1408 1409 HAL_REG_WRITE(soc, 1410 HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(REO_REG_REG_BASE), 1411 (HAL_DEFAULT_VO_REO_TIMEOUT_MS * 1000)); 1412 1413 /* 1414 * When hash based routing is enabled, routing of the rx packet 1415 * is done based on the following value: 1 _ _ _ _ The last 4 1416 * bits are based on hash[3:0]. This means the possible values 1417 * are 0x10 to 0x1f. This value is used to look-up the 1418 * ring ID configured in Destination_Ring_Ctrl_IX_* register. 1419 * The Destination_Ring_Ctrl_IX_2 and Destination_Ring_Ctrl_IX_3 1420 * registers need to be configured to set-up the 16 entries to 1421 * map the hash values to a ring number. There are 3 bits per 1422 * hash entry – which are mapped as follows: 1423 * 0: TCL, 1:SW1, 2:SW2, * 3:SW3, 4:SW4, 5:Release, 6:FW(WIFI), 1424 * 7: NOT_USED. 1425 */ 1426 if (reo_params->rx_hash_enabled) { 1427 hal_compute_reo_remap_ix0_9224(soc); 1428 1429 HAL_REG_WRITE(soc, 1430 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR 1431 (REO_REG_REG_BASE), reo_params->remap0); 1432 1433 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x", 1434 HAL_REG_READ(soc, 1435 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR( 1436 REO_REG_REG_BASE))); 1437 1438 HAL_REG_WRITE(soc, 1439 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 1440 (REO_REG_REG_BASE), reo_params->remap1); 1441 1442 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x", 1443 HAL_REG_READ(soc, 1444 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR( 1445 REO_REG_REG_BASE))); 1446 1447 HAL_REG_WRITE(soc, 1448 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 1449 (REO_REG_REG_BASE), reo_params->remap2); 1450 1451 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 0x%x", 1452 HAL_REG_READ(soc, 1453 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR( 1454 REO_REG_REG_BASE))); 1455 } 1456 1457 /* TODO: Check if the following registers shoould be setup by host: 1458 * AGING_CONTROL 1459 * HIGH_MEMORY_THRESHOLD 1460 * GLOBAL_LINK_DESC_COUNT_THRESH_IX_0[1,2] 1461 * GLOBAL_LINK_DESC_COUNT_CTRL 1462 */ 1463 1464 soc->reo_qref = *reo_params->reo_qref; 1465 hal_reo_shared_qaddr_init((hal_soc_handle_t)soc, qref_reset); 1466 } 1467 1468 static uint16_t hal_get_rx_max_ba_window_qcn9224(int tid) 1469 { 1470 return HAL_RX_BA_WINDOW_1024; 1471 } 1472 1473 /** 1474 * hal_qcn9224_get_reo_qdesc_size()- Get the reo queue descriptor size 1475 * from the give Block-Ack window size 1476 * Return: reo queue descriptor size 1477 */ 1478 static uint32_t hal_qcn9224_get_reo_qdesc_size(uint32_t ba_window_size, int tid) 1479 { 1480 /* Hardcode the ba_window_size to HAL_RX_MAX_BA_WINDOW for 1481 * NON_QOS_TID until HW issues are resolved. 1482 */ 1483 if (tid != HAL_NON_QOS_TID) 1484 ba_window_size = hal_get_rx_max_ba_window_qcn9224(tid); 1485 1486 /* Return descriptor size corresponding to window size of 2 since 1487 * we set ba_window_size to 2 while setting up REO descriptors as 1488 * a WAR to get 2k jump exception aggregates are received without 1489 * a BA session. 1490 */ 1491 if (ba_window_size <= 1) { 1492 if (tid != HAL_NON_QOS_TID) 1493 return sizeof(struct rx_reo_queue) + 1494 sizeof(struct rx_reo_queue_ext); 1495 else 1496 return sizeof(struct rx_reo_queue); 1497 } 1498 1499 if (ba_window_size <= 105) 1500 return sizeof(struct rx_reo_queue) + 1501 sizeof(struct rx_reo_queue_ext); 1502 1503 if (ba_window_size <= 210) 1504 return sizeof(struct rx_reo_queue) + 1505 (2 * sizeof(struct rx_reo_queue_ext)); 1506 1507 if (ba_window_size <= 256) 1508 return sizeof(struct rx_reo_queue) + 1509 (3 * sizeof(struct rx_reo_queue_ext)); 1510 1511 return sizeof(struct rx_reo_queue) + 1512 (10 * sizeof(struct rx_reo_queue_ext)) + 1513 sizeof(struct rx_reo_queue_1k); 1514 } 1515 1516 /* 1517 * hal_tx_get_num_ppe_vp_tbl_entries_9224() 1518 * @hal_soc_hdl: HAL SoC handle 1519 * 1520 * Return: Number of PPE VP entries 1521 */ 1522 static 1523 uint32_t hal_tx_get_num_ppe_vp_tbl_entries_9224(hal_soc_handle_t hal_soc_hdl) 1524 { 1525 return HAL_PPE_VP_ENTRIES_MAX; 1526 } 1527 1528 /* 1529 * hal_tx_get_num_ppe_vp_search_idx_reg_entries_9224() 1530 * @hal_soc_hdl: HAL SoC handle 1531 * 1532 * Return: Number of PPE VP search index registers 1533 */ 1534 static 1535 uint32_t hal_tx_get_num_ppe_vp_search_idx_reg_entries_9224(hal_soc_handle_t hal_soc_hdl) 1536 { 1537 return HAL_PPE_VP_SEARCH_IDX_REG_MAX; 1538 } 1539 1540 /** 1541 * hal_rx_tlv_msdu_done_copy_get_9224() - Get msdu done copy bit from rx_tlv 1542 * 1543 * Returns: msdu done copy bit 1544 */ 1545 static inline uint32_t hal_rx_tlv_msdu_done_copy_get_9224(uint8_t *buf) 1546 { 1547 return HAL_RX_TLV_MSDU_DONE_COPY_GET(buf); 1548 } 1549 1550 static void hal_hw_txrx_ops_attach_qcn9224(struct hal_soc *hal_soc) 1551 { 1552 /* init and setup */ 1553 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic; 1554 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic; 1555 hal_soc->ops->hal_srng_hw_disable = hal_srng_hw_disable_generic; 1556 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic; 1557 hal_soc->ops->hal_get_window_address = hal_get_window_address_9224; 1558 hal_soc->ops->hal_cmem_write = hal_cmem_write_9224; 1559 1560 /* tx */ 1561 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_9224; 1562 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_9224; 1563 hal_soc->ops->hal_tx_comp_get_status = 1564 hal_tx_comp_get_status_generic_be; 1565 hal_soc->ops->hal_tx_init_cmd_credit_ring = 1566 hal_tx_init_cmd_credit_ring_9224; 1567 hal_soc->ops->hal_tx_set_ppe_cmn_cfg = 1568 hal_tx_set_ppe_cmn_config_9224; 1569 hal_soc->ops->hal_tx_set_ppe_vp_entry = 1570 hal_tx_set_ppe_vp_entry_9224; 1571 hal_soc->ops->hal_ppeds_cfg_ast_override_map_reg = 1572 hal_ppeds_cfg_ast_override_map_reg_9224; 1573 hal_soc->ops->hal_tx_set_ppe_pri2tid = 1574 hal_tx_set_ppe_pri2tid_map_9224; 1575 hal_soc->ops->hal_tx_update_ppe_pri2tid = 1576 hal_tx_update_ppe_pri2tid_9224; 1577 hal_soc->ops->hal_tx_dump_ppe_vp_entry = 1578 hal_tx_dump_ppe_vp_entry_9224; 1579 hal_soc->ops->hal_tx_get_num_ppe_vp_tbl_entries = 1580 hal_tx_get_num_ppe_vp_tbl_entries_9224; 1581 hal_soc->ops->hal_tx_enable_pri2tid_map = 1582 hal_tx_enable_pri2tid_map_9224; 1583 hal_soc->ops->hal_tx_config_rbm_mapping_be = 1584 hal_tx_config_rbm_mapping_be_9224; 1585 1586 /* rx */ 1587 hal_soc->ops->hal_rx_msdu_start_nss_get = hal_rx_tlv_nss_get_be; 1588 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status = 1589 hal_rx_mon_hw_desc_get_mpdu_status_be; 1590 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_9224; 1591 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv = 1592 hal_rx_proc_phyrx_other_receive_info_tlv_9224; 1593 1594 hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_9224; 1595 hal_soc->ops->hal_rx_dump_mpdu_start_tlv = 1596 hal_rx_dump_mpdu_start_tlv_9224; 1597 hal_soc->ops->hal_rx_dump_pkt_tlvs = hal_rx_dump_pkt_tlvs_9224; 1598 1599 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_9224; 1600 hal_soc->ops->hal_rx_mpdu_start_tid_get = hal_rx_tlv_tid_get_be; 1601 hal_soc->ops->hal_rx_msdu_start_reception_type_get = 1602 hal_rx_tlv_reception_type_get_be; 1603 hal_soc->ops->hal_rx_msdu_end_da_idx_get = 1604 hal_rx_msdu_end_da_idx_get_be; 1605 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = 1606 hal_rx_msdu_desc_info_get_ptr_9224; 1607 hal_soc->ops->hal_rx_link_desc_msdu0_ptr = 1608 hal_rx_link_desc_msdu0_ptr_9224; 1609 hal_soc->ops->hal_reo_status_get_header = 1610 hal_reo_status_get_header_9224; 1611 #ifdef QCA_MONITOR_2_0_SUPPORT 1612 hal_soc->ops->hal_rx_status_get_tlv_info = 1613 hal_rx_status_get_tlv_info_wrapper_be; 1614 #endif 1615 hal_soc->ops->hal_rx_wbm_err_info_get = 1616 hal_rx_wbm_err_info_get_generic_be; 1617 hal_soc->ops->hal_tx_set_pcp_tid_map = 1618 hal_tx_set_pcp_tid_map_generic_be; 1619 hal_soc->ops->hal_tx_update_pcp_tid_map = 1620 hal_tx_update_pcp_tid_generic_be; 1621 hal_soc->ops->hal_tx_set_tidmap_prty = 1622 hal_tx_update_tidmap_prty_generic_be; 1623 hal_soc->ops->hal_rx_get_rx_fragment_number = 1624 hal_rx_get_rx_fragment_number_be, 1625 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = 1626 hal_rx_tlv_da_is_mcbc_get_be; 1627 hal_soc->ops->hal_rx_msdu_end_is_tkip_mic_err = 1628 hal_rx_tlv_is_tkip_mic_err_get_be; 1629 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = 1630 hal_rx_tlv_sa_is_valid_get_be; 1631 hal_soc->ops->hal_rx_msdu_end_sa_idx_get = hal_rx_tlv_sa_idx_get_be; 1632 hal_soc->ops->hal_rx_desc_is_first_msdu = hal_rx_desc_is_first_msdu_be; 1633 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get = 1634 hal_rx_tlv_l3_hdr_padding_get_be; 1635 hal_soc->ops->hal_rx_encryption_info_valid = 1636 hal_rx_encryption_info_valid_be; 1637 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_be; 1638 hal_soc->ops->hal_rx_msdu_end_first_msdu_get = 1639 hal_rx_tlv_first_msdu_get_be; 1640 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = 1641 hal_rx_tlv_da_is_valid_get_be; 1642 hal_soc->ops->hal_rx_msdu_end_last_msdu_get = 1643 hal_rx_tlv_last_msdu_get_be; 1644 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = 1645 hal_rx_get_mpdu_mac_ad4_valid_be; 1646 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get = 1647 hal_rx_mpdu_start_sw_peer_id_get_be; 1648 hal_soc->ops->hal_rx_tlv_peer_meta_data_get = 1649 hal_rx_msdu_peer_meta_data_get_be; 1650 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_be; 1651 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_be; 1652 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid = 1653 hal_rx_get_mpdu_frame_control_valid_be; 1654 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_be; 1655 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_be; 1656 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_be; 1657 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid = 1658 hal_rx_get_mpdu_sequence_control_valid_be; 1659 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_be; 1660 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_be; 1661 hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get = 1662 hal_rx_mpdu_start_mpdu_qos_control_valid_get_be; 1663 hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get = 1664 hal_rx_msdu_end_sa_sw_peer_id_get_be; 1665 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = 1666 hal_rx_msdu0_buffer_addr_lsb_9224; 1667 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = 1668 hal_rx_msdu_desc_info_ptr_get_9224; 1669 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_9224; 1670 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_9224; 1671 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_be; 1672 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_be; 1673 hal_soc->ops->hal_rx_get_mac_addr2_valid = 1674 hal_rx_get_mac_addr2_valid_be; 1675 hal_soc->ops->hal_reo_config = hal_reo_config_9224; 1676 hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_be; 1677 hal_soc->ops->hal_rx_msdu_flow_idx_invalid = 1678 hal_rx_msdu_flow_idx_invalid_be; 1679 hal_soc->ops->hal_rx_msdu_flow_idx_timeout = 1680 hal_rx_msdu_flow_idx_timeout_be; 1681 hal_soc->ops->hal_rx_msdu_fse_metadata_get = 1682 hal_rx_msdu_fse_metadata_get_be; 1683 hal_soc->ops->hal_rx_msdu_cce_match_get = 1684 hal_rx_msdu_cce_match_get_be; 1685 hal_soc->ops->hal_rx_msdu_cce_metadata_get = 1686 hal_rx_msdu_cce_metadata_get_be; 1687 hal_soc->ops->hal_rx_msdu_get_flow_params = 1688 hal_rx_msdu_get_flow_params_be; 1689 hal_soc->ops->hal_rx_tlv_get_tcp_chksum = hal_rx_tlv_get_tcp_chksum_be; 1690 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_be; 1691 1692 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) 1693 hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_9224; 1694 hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_9224; 1695 #else 1696 hal_soc->ops->hal_rx_get_bb_info = NULL; 1697 hal_soc->ops->hal_rx_get_rtt_info = NULL; 1698 #endif 1699 1700 /* rx - msdu fast path info fields */ 1701 hal_soc->ops->hal_rx_msdu_packet_metadata_get = 1702 hal_rx_msdu_packet_metadata_get_generic_be; 1703 hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid = 1704 hal_rx_mpdu_start_tlv_tag_valid_be; 1705 hal_soc->ops->hal_rx_wbm_err_msdu_continuation_get = 1706 hal_rx_wbm_err_msdu_continuation_get_9224; 1707 1708 /* rx - TLV struct offsets */ 1709 hal_soc->ops->hal_rx_msdu_end_offset_get = 1710 hal_rx_msdu_end_offset_get_generic; 1711 hal_soc->ops->hal_rx_mpdu_start_offset_get = 1712 hal_rx_mpdu_start_offset_get_generic; 1713 #ifndef NO_RX_PKT_HDR_TLV 1714 hal_soc->ops->hal_rx_pkt_tlv_offset_get = 1715 hal_rx_pkt_tlv_offset_get_generic; 1716 #endif 1717 hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_9224; 1718 1719 hal_soc->ops->hal_rx_flow_get_tuple_info = 1720 hal_rx_flow_get_tuple_info_be; 1721 hal_soc->ops->hal_rx_flow_delete_entry = 1722 hal_rx_flow_delete_entry_be; 1723 hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_be; 1724 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = 1725 hal_compute_reo_remap_ix2_ix3_9224; 1726 1727 hal_soc->ops->hal_rx_msdu_get_reo_destination_indication = 1728 hal_rx_msdu_get_reo_destination_indication_be; 1729 hal_soc->ops->hal_rx_get_tlv_size = hal_rx_get_tlv_size_generic_be; 1730 hal_soc->ops->hal_rx_msdu_is_wlan_mcast = 1731 hal_rx_msdu_is_wlan_mcast_generic_be; 1732 hal_soc->ops->hal_tx_get_num_tcl_banks = hal_tx_get_num_tcl_banks_9224; 1733 hal_soc->ops->hal_rx_tlv_decap_format_get = 1734 hal_rx_tlv_decap_format_get_be; 1735 #ifdef RECEIVE_OFFLOAD 1736 hal_soc->ops->hal_rx_tlv_get_offload_info = 1737 hal_rx_tlv_get_offload_info_be; 1738 hal_soc->ops->hal_rx_get_proto_params = hal_rx_get_proto_params_be; 1739 hal_soc->ops->hal_rx_get_l3_l4_offsets = hal_rx_get_l3_l4_offsets_be; 1740 #endif 1741 hal_soc->ops->hal_rx_tlv_msdu_done_get = 1742 hal_rx_tlv_msdu_done_copy_get_9224; 1743 hal_soc->ops->hal_rx_tlv_msdu_len_get = 1744 hal_rx_msdu_start_msdu_len_get_be; 1745 hal_soc->ops->hal_rx_get_frame_ctrl_field = 1746 hal_rx_get_frame_ctrl_field_be; 1747 hal_soc->ops->hal_rx_tlv_csum_err_get = hal_rx_tlv_csum_err_get_be; 1748 #ifndef CONFIG_WORD_BASED_TLV 1749 hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get = 1750 hal_rx_mpdu_info_ampdu_flag_get_be; 1751 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_be; 1752 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = 1753 hal_rx_hw_desc_get_ppduid_get_be; 1754 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_be; 1755 hal_soc->ops->hal_rx_tlv_phy_ppdu_id_get = 1756 hal_rx_attn_phy_ppdu_id_get_be; 1757 hal_soc->ops->hal_rx_get_filter_category = 1758 hal_rx_get_filter_category_be; 1759 #endif 1760 hal_soc->ops->hal_rx_tlv_msdu_len_set = 1761 hal_rx_msdu_start_msdu_len_set_be; 1762 hal_soc->ops->hal_rx_tlv_sgi_get = hal_rx_tlv_sgi_get_be; 1763 hal_soc->ops->hal_rx_tlv_rate_mcs_get = hal_rx_tlv_rate_mcs_get_be; 1764 hal_soc->ops->hal_rx_tlv_bw_get = hal_rx_tlv_bw_get_be; 1765 hal_soc->ops->hal_rx_tlv_get_pkt_type = hal_rx_tlv_get_pkt_type_be; 1766 hal_soc->ops->hal_rx_tlv_mic_err_get = hal_rx_tlv_mic_err_get_be; 1767 hal_soc->ops->hal_rx_tlv_decrypt_err_get = 1768 hal_rx_tlv_decrypt_err_get_be; 1769 hal_soc->ops->hal_rx_tlv_first_mpdu_get = hal_rx_tlv_first_mpdu_get_be; 1770 hal_soc->ops->hal_rx_tlv_get_is_decrypted = 1771 hal_rx_tlv_get_is_decrypted_be; 1772 hal_soc->ops->hal_rx_msdu_get_keyid = hal_rx_msdu_get_keyid_be; 1773 hal_soc->ops->hal_rx_tlv_get_freq = hal_rx_tlv_get_freq_be; 1774 hal_soc->ops->hal_rx_priv_info_set_in_tlv = 1775 hal_rx_priv_info_set_in_tlv_be; 1776 hal_soc->ops->hal_rx_priv_info_get_from_tlv = 1777 hal_rx_priv_info_get_from_tlv_be; 1778 hal_soc->ops->hal_rx_pkt_hdr_get = hal_rx_pkt_hdr_get_be; 1779 hal_soc->ops->hal_reo_setup = hal_reo_setup_9224; 1780 hal_soc->ops->hal_reo_config_reo2ppe_dest_info = NULL; 1781 #ifdef REO_SHARED_QREF_TABLE_EN 1782 hal_soc->ops->hal_reo_shared_qaddr_setup = hal_reo_shared_qaddr_setup_be; 1783 hal_soc->ops->hal_reo_shared_qaddr_init = hal_reo_shared_qaddr_init_be; 1784 hal_soc->ops->hal_reo_shared_qaddr_detach = hal_reo_shared_qaddr_detach_be; 1785 hal_soc->ops->hal_reo_shared_qaddr_write = hal_reo_shared_qaddr_write_be; 1786 hal_soc->ops->hal_reo_shared_qaddr_cache_clear = hal_reo_shared_qaddr_cache_clear_be; 1787 #endif 1788 /* Overwrite the default BE ops */ 1789 hal_soc->ops->hal_get_rx_max_ba_window = 1790 hal_get_rx_max_ba_window_qcn9224; 1791 hal_soc->ops->hal_get_reo_qdesc_size = hal_qcn9224_get_reo_qdesc_size; 1792 /* TX MONITOR */ 1793 #ifdef QCA_MONITOR_2_0_SUPPORT 1794 hal_soc->ops->hal_txmon_is_mon_buf_addr_tlv = 1795 hal_txmon_is_mon_buf_addr_tlv_generic_be; 1796 hal_soc->ops->hal_txmon_populate_packet_info = 1797 hal_txmon_populate_packet_info_generic_be; 1798 hal_soc->ops->hal_txmon_status_parse_tlv = 1799 hal_txmon_status_parse_tlv_generic_be; 1800 hal_soc->ops->hal_txmon_status_get_num_users = 1801 hal_txmon_status_get_num_users_generic_be; 1802 #endif /* QCA_MONITOR_2_0_SUPPORT */ 1803 hal_soc->ops->hal_compute_reo_remap_ix0 = NULL; 1804 hal_soc->ops->hal_tx_vdev_mismatch_routing_set = 1805 hal_tx_vdev_mismatch_routing_set_generic_be; 1806 hal_soc->ops->hal_tx_mcast_mlo_reinject_routing_set = 1807 hal_tx_mcast_mlo_reinject_routing_set_generic_be; 1808 hal_soc->ops->hal_get_ba_aging_timeout = 1809 hal_get_ba_aging_timeout_be_generic; 1810 hal_soc->ops->hal_setup_link_idle_list = 1811 hal_setup_link_idle_list_generic_be; 1812 hal_soc->ops->hal_cookie_conversion_reg_cfg_be = 1813 hal_cookie_conversion_reg_cfg_generic_be; 1814 hal_soc->ops->hal_set_ba_aging_timeout = 1815 hal_set_ba_aging_timeout_be_generic; 1816 hal_soc->ops->hal_tx_populate_bank_register = 1817 hal_tx_populate_bank_register_be; 1818 hal_soc->ops->hal_tx_vdev_mcast_ctrl_set = 1819 hal_tx_vdev_mcast_ctrl_set_be; 1820 #ifdef CONFIG_WORD_BASED_TLV 1821 hal_soc->ops->hal_rx_mpdu_start_wmask_get = 1822 hal_rx_mpdu_start_wmask_get_be; 1823 hal_soc->ops->hal_rx_msdu_end_wmask_get = 1824 hal_rx_msdu_end_wmask_get_be; 1825 #endif 1826 hal_soc->ops->hal_get_tsf2_scratch_reg = 1827 hal_get_tsf2_scratch_reg_qcn9224; 1828 hal_soc->ops->hal_get_tqm_scratch_reg = 1829 hal_get_tqm_scratch_reg_qcn9224; 1830 hal_soc->ops->hal_tx_ring_halt_set = hal_tx_ppe2tcl_ring_halt_set_9224; 1831 hal_soc->ops->hal_tx_ring_halt_reset = 1832 hal_tx_ppe2tcl_ring_halt_reset_9224; 1833 hal_soc->ops->hal_tx_ring_halt_poll = 1834 hal_tx_ppe2tcl_ring_halt_done_9224; 1835 hal_soc->ops->hal_tx_get_num_ppe_vp_search_idx_tbl_entries = 1836 hal_tx_get_num_ppe_vp_search_idx_reg_entries_9224; 1837 }; 1838 1839 /** 1840 * hal_srng_hw_reg_offset_init_qcn9224() - Initialize the HW srng reg offset 1841 * applicable only for QCN9224 1842 * @hal_soc: HAL Soc handle 1843 * 1844 * Return: None 1845 */ 1846 static inline void hal_srng_hw_reg_offset_init_qcn9224(struct hal_soc *hal_soc) 1847 { 1848 int32_t *hw_reg_offset = hal_soc->hal_hw_reg_offset; 1849 1850 hw_reg_offset[DST_MSI2_BASE_LSB] = REG_OFFSET(DST, MSI2_BASE_LSB), 1851 hw_reg_offset[DST_MSI2_BASE_MSB] = REG_OFFSET(DST, MSI2_BASE_MSB), 1852 hw_reg_offset[DST_MSI2_DATA] = REG_OFFSET(DST, MSI2_DATA), 1853 hw_reg_offset[DST_PRODUCER_INT2_SETUP] = 1854 REG_OFFSET(DST, PRODUCER_INT2_SETUP); 1855 } 1856