1 /* 2 * Copyright (c) 2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 #include "qdf_types.h" 20 #include "qdf_util.h" 21 #include "qdf_mem.h" 22 #include "qdf_nbuf.h" 23 #include "qdf_module.h" 24 25 #include "target_type.h" 26 #include "wcss_version.h" 27 28 #include "hal_be_hw_headers.h" 29 #include "hal_internal.h" 30 #include "hal_api.h" 31 #include "hal_flow.h" 32 #include "rx_flow_search_entry.h" 33 #include "hal_rx_flow_info.h" 34 #include "hal_be_api.h" 35 #include "tcl_entrance_from_ppe_ring.h" 36 #include "sw_monitor_ring.h" 37 #include "wcss_seq_hwioreg_umac.h" 38 #include "wfss_ce_reg_seq_hwioreg.h" 39 #include <uniform_reo_status_header.h> 40 #include <wbm_release_ring_tx.h> 41 #include <phyrx_location.h> 42 #ifdef WLAN_PKT_CAPTURE_TX_2_0 43 #include <mon_ingress_ring.h> 44 #include <mon_destination_ring.h> 45 #endif 46 #include "rx_reo_queue_1k.h" 47 48 #include <hal_be_rx.h> 49 50 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 51 RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 52 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 53 RX_MSDU_LINK_MSDU_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 54 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 55 RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 56 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 57 RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 58 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 59 REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 60 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER \ 61 STATUS_HEADER_REO_STATUS_NUMBER 62 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 63 STATUS_HEADER_TIMESTAMP 64 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 65 RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 66 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 67 RX_MSDU_LINK_MSDU_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 68 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 69 TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 70 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 71 TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 72 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 73 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_OFFSET 74 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 75 BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 76 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 77 BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 78 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 79 BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB 80 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 81 BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK 82 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 83 BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 84 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 85 BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 86 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 87 BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB 88 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 89 BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK 90 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 91 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_LSB 92 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 93 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MASK 94 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 95 WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 96 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 97 WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 98 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 99 WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 100 101 #if defined(WLAN_PKT_CAPTURE_TX_2_0) || defined(WLAN_PKT_CAPTURE_RX_2_0) 102 #include "hal_be_api_mon.h" 103 #endif 104 105 #ifdef CONFIG_WIFI_EMULATION_WIFI_3_0 106 #define CMEM_REG_BASE 0x0010e000 107 108 #define CMEM_WINDOW_ADDRESS_9224 \ 109 ((CMEM_REG_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) 110 #endif 111 112 #define CE_WINDOW_ADDRESS_9224 \ 113 ((CE_WFSS_CE_REG_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) 114 115 #define UMAC_WINDOW_ADDRESS_9224 \ 116 ((UMAC_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) 117 118 #ifdef CONFIG_WIFI_EMULATION_WIFI_3_0 119 #define WINDOW_CONFIGURATION_VALUE_9224 \ 120 ((CE_WINDOW_ADDRESS_9224 << 6) |\ 121 (UMAC_WINDOW_ADDRESS_9224 << 12) | \ 122 CMEM_WINDOW_ADDRESS_9224 | \ 123 WINDOW_ENABLE_BIT) 124 #else 125 #define WINDOW_CONFIGURATION_VALUE_9224 \ 126 ((CE_WINDOW_ADDRESS_9224 << 6) |\ 127 (UMAC_WINDOW_ADDRESS_9224 << 12) | \ 128 WINDOW_ENABLE_BIT) 129 #endif 130 131 /* For Berryllium sw2rxdma ring size increased to 20 bits */ 132 #define HAL_RXDMA_MAX_RING_SIZE_BE 0xFFFFF 133 134 #include "hal_9224_rx.h" 135 #include "hal_9224_tx.h" 136 #include "hal_be_rx_tlv.h" 137 #include <hal_be_generic_api.h> 138 139 #define PMM_REG_BASE_QCN9224 0xB500F8 140 141 /** 142 * hal_read_pmm_scratch_reg() - API to read PMM Scratch register 143 * @soc: HAL soc 144 * @base_addr: Base PMM register 145 * @reg_enum: Enum of the scratch register 146 * 147 * Return: uint32_t 148 */ 149 static inline 150 uint32_t hal_read_pmm_scratch_reg(struct hal_soc *soc, 151 uint32_t base_addr, 152 enum hal_scratch_reg_enum reg_enum) 153 { 154 uint32_t val = 0; 155 156 pld_reg_read(soc->qdf_dev->dev, base_addr + (reg_enum * 4), &val, NULL); 157 return val; 158 } 159 160 /** 161 * hal_get_tsf2_scratch_reg_qcn9224() - API to read tsf2 scratch register 162 * @hal_soc_hdl: HAL soc context 163 * @mac_id: mac id 164 * @value: Pointer to update tsf2 value 165 * 166 * Return: void 167 */ 168 static void hal_get_tsf2_scratch_reg_qcn9224(hal_soc_handle_t hal_soc_hdl, 169 uint8_t mac_id, uint64_t *value) 170 { 171 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; 172 uint32_t offset_lo, offset_hi; 173 enum hal_scratch_reg_enum enum_lo, enum_hi; 174 175 hal_get_tsf_enum(DEFAULT_TSF_ID, mac_id, &enum_lo, &enum_hi); 176 177 offset_lo = hal_read_pmm_scratch_reg(soc, 178 PMM_REG_BASE_QCN9224, 179 enum_lo); 180 181 offset_hi = hal_read_pmm_scratch_reg(soc, 182 PMM_REG_BASE_QCN9224, 183 enum_hi); 184 185 *value = ((uint64_t)(offset_hi) << 32 | offset_lo); 186 } 187 188 /** 189 * hal_get_tqm_scratch_reg_qcn9224() - API to read tqm scratch register 190 * @hal_soc_hdl: HAL soc context 191 * @value: Pointer to update tqm value 192 * 193 * Return: void 194 */ 195 static void hal_get_tqm_scratch_reg_qcn9224(hal_soc_handle_t hal_soc_hdl, 196 uint64_t *value) 197 { 198 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; 199 uint32_t offset_lo, offset_hi; 200 201 offset_lo = hal_read_pmm_scratch_reg(soc, 202 PMM_REG_BASE_QCN9224, 203 PMM_TQM_CLOCK_OFFSET_LO_US); 204 205 offset_hi = hal_read_pmm_scratch_reg(soc, 206 PMM_REG_BASE_QCN9224, 207 PMM_TQM_CLOCK_OFFSET_HI_US); 208 209 *value = ((uint64_t)(offset_hi) << 32 | offset_lo); 210 } 211 212 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 213 #define HAL_PPE_VP_ENTRIES_MAX 32 214 #define HAL_PPE_VP_SEARCH_IDX_REG_MAX 8 215 216 /** 217 * hal_get_link_desc_size_9224() - API to get the link desc size 218 * 219 * Return: uint32_t 220 */ 221 static uint32_t hal_get_link_desc_size_9224(void) 222 { 223 return LINK_DESC_SIZE; 224 } 225 226 /** 227 * hal_rx_get_tlv_9224() - API to get the tlv 228 * @rx_tlv: TLV data extracted from the rx packet 229 * 230 * Return: uint8_t 231 */ 232 static uint8_t hal_rx_get_tlv_9224(void *rx_tlv) 233 { 234 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY, RECEIVE_BANDWIDTH); 235 } 236 237 /** 238 * hal_rx_wbm_err_msdu_continuation_get_9224() - API to check if WBM msdu 239 * continuation bit is set 240 * @wbm_desc: wbm release ring descriptor 241 * 242 * Return: true if msdu continuation bit is set. 243 */ 244 static inline 245 uint8_t hal_rx_wbm_err_msdu_continuation_get_9224(void *wbm_desc) 246 { 247 uint32_t comp_desc = *(uint32_t *)(((uint8_t *)wbm_desc) + 248 WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET); 249 250 return (comp_desc & 251 WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK) >> 252 WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB; 253 } 254 255 #if (defined(WLAN_SA_API_ENABLE)) && (defined(QCA_WIFI_QCA9574)) 256 #define HAL_RX_EVM_DEMF_SEGMENT_SIZE 128 257 #define HAL_RX_EVM_DEMF_MAX_STREAMS 2 258 #define HAL_RX_SU_EVM_MEMBER_LEN 4 259 static inline void 260 hal_rx_update_su_evm_info(void *rx_tlv, 261 void *ppdu_info_hdl) 262 { 263 uint32_t nss_count, pilot_count; 264 uint16_t istream = 0, ipilot = 0; 265 uint8_t pilot_shift = 0; 266 uint8_t *pilot_ptr = NULL; 267 uint16_t segment = 0; 268 269 struct hal_rx_ppdu_info *ppdu_info = 270 (struct hal_rx_ppdu_info *)ppdu_info_hdl; 271 nss_count = ppdu_info->evm_info.nss_count; 272 pilot_count = ppdu_info->evm_info.pilot_count; 273 274 if (nss_count * pilot_count > HAL_RX_MAX_SU_EVM_COUNT) 275 return; 276 277 /* move rx_tlv by 4 to skip no_of_data_sym, nss_cnt and pilot_cnt */ 278 rx_tlv = (uint8_t *)rx_tlv + HAL_RX_SU_EVM_MEMBER_LEN; 279 280 /* EVM values = number_of_streams * number_of_pilots 281 * each EVM value is 8 bits, So, each variable acc_linear_evm_x_y 282 * is (32 bits) will contain 4 EVM values. 283 * For ex: 284 * acc_linear_evm_0_0 : <Pilot0, stream0>, <Pilot0, stream1>, 285 * <Pilot1, stream0>, <Pilot1, stream1> 286 * ..... 287 * acc_linear_evm_1_15 : <Pilot62, stream0>, <Pilot62, stream1>, 288 * <Pilot63, stream0>, <Pilot63, stream1> ... 289 */ 290 291 for (istream = 0; istream < nss_count; istream++) { 292 segment = HAL_RX_EVM_DEMF_SEGMENT_SIZE * (istream / HAL_RX_EVM_DEMF_MAX_STREAMS); 293 pilot_ptr = (uint8_t *)rx_tlv + segment; 294 for (ipilot = 0; ipilot < pilot_count; ipilot++) { 295 /* In case there is one stream in Demf segment, 296 * pilots are one after the other 297 */ 298 if (nss_count == 1 || 299 ((nss_count == HAL_RX_EVM_DEMF_MAX_STREAMS + 1) && 300 (istream == HAL_RX_EVM_DEMF_MAX_STREAMS))) 301 pilot_shift = ipilot; 302 /* In case there are more than one stream in DemF 303 * segment, pilot 0 of all streams come one after the 304 * other before pilot 1 305 */ 306 else 307 pilot_shift = (ipilot * HAL_RX_EVM_DEMF_MAX_STREAMS) 308 + (istream % HAL_RX_EVM_DEMF_MAX_STREAMS); 309 310 ppdu_info->evm_info.pilot_evm[segment + pilot_shift] = 311 *(pilot_ptr + pilot_shift); 312 } 313 } 314 } 315 316 /** 317 * hal_rx_proc_phyrx_other_receive_info_tlv_9224() - API to get tlv info 318 * @rx_tlv_hdr: RX TLV header 319 * @ppdu_info_hdl: Handle to PPDU info to update 320 * 321 * Return: None 322 */ 323 static inline 324 void hal_rx_proc_phyrx_other_receive_info_tlv_9224(void *rx_tlv_hdr, 325 void *ppdu_info_hdl) 326 { 327 uint32_t tlv_len, tlv_tag; 328 void *rx_tlv; 329 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 330 331 tlv_len = HAL_RX_GET_USER_TLV64_LEN(rx_tlv_hdr); 332 rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV64_HDR_SIZE; 333 334 if (!tlv_len) 335 return; 336 337 tlv_tag = HAL_RX_GET_USER_TLV64_TYPE(rx_tlv); 338 tlv_len = HAL_RX_GET_USER_TLV64_LEN(rx_tlv); 339 340 if (!tlv_len) 341 return; 342 343 switch (tlv_tag) { 344 case WIFIPHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_E: 345 /* Skip TLV length to get TLV content */ 346 rx_tlv = (uint8_t *)rx_tlv + HAL_RX_TLV64_HDR_SIZE; 347 ppdu_info->evm_info.number_of_symbols = HAL_RX_GET(rx_tlv, 348 PHYRX_OTHER_RECEIVE_INFO, 349 EVM_DETAILS_NUMBER_OF_DATA_SYM); 350 ppdu_info->evm_info.pilot_count = HAL_RX_GET(rx_tlv, 351 PHYRX_OTHER_RECEIVE_INFO, 352 EVM_DETAILS_NUMBER_OF_PILOTS); 353 ppdu_info->evm_info.nss_count = HAL_RX_GET(rx_tlv, 354 PHYRX_OTHER_RECEIVE_INFO, 355 EVM_DETAILS_NUMBER_OF_STREAMS); 356 hal_rx_update_su_evm_info(rx_tlv, ppdu_info_hdl); 357 break; 358 default: 359 QDF_TRACE(QDF_MODULE_ID_HAL, QDF_TRACE_LEVEL_DEBUG, 360 "%s unhandled TLV type: %d, TLV len:%d", 361 __func__, tlv_tag, tlv_len); 362 break; 363 } 364 } 365 366 #else 367 /** 368 * hal_rx_proc_phyrx_other_receive_info_tlv_9224() - API to get tlv info 369 * @rx_tlv_hdr: RX TLV header 370 * @ppdu_info_hdl: Handle to PPDU info to update 371 * 372 * Return: None 373 */ 374 static inline 375 void hal_rx_proc_phyrx_other_receive_info_tlv_9224(void *rx_tlv_hdr, 376 void *ppdu_info_hdl) 377 { 378 } 379 #endif /* WLAN_SA_API_ENABLE && QCA_WIFI_QCA9574 */ 380 381 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) 382 static inline 383 void hal_rx_get_bb_info_9224(void *rx_tlv, void *ppdu_info_hdl) 384 { 385 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 386 387 ppdu_info->cfr_info.bb_captured_channel = 388 HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_CHANNEL); 389 390 ppdu_info->cfr_info.bb_captured_timeout = 391 HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_TIMEOUT); 392 393 ppdu_info->cfr_info.bb_captured_reason = 394 HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_REASON); 395 } 396 397 static inline 398 void hal_rx_get_rtt_info_9224(void *rx_tlv, void *ppdu_info_hdl) 399 { 400 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 401 402 ppdu_info->cfr_info.rx_location_info_valid = 403 HAL_RX_GET_64(rx_tlv, PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 404 RX_LOCATION_INFO_VALID); 405 406 ppdu_info->cfr_info.rtt_che_buffer_pointer_low32 = 407 HAL_RX_GET_64(rx_tlv, 408 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 409 RTT_CHE_BUFFER_POINTER_LOW32); 410 411 ppdu_info->cfr_info.rtt_che_buffer_pointer_high8 = 412 HAL_RX_GET_64(rx_tlv, 413 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 414 RTT_CHE_BUFFER_POINTER_HIGH8); 415 416 ppdu_info->cfr_info.chan_capture_status = 417 HAL_GET_RX_LOCATION_INFO_CHAN_CAPTURE_STATUS(rx_tlv); 418 419 ppdu_info->cfr_info.rx_start_ts = 420 HAL_RX_GET_64(rx_tlv, 421 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 422 RX_START_TS); 423 424 ppdu_info->cfr_info.rtt_cfo_measurement = (int16_t) 425 HAL_RX_GET_64(rx_tlv, 426 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 427 RTT_CFO_MEASUREMENT); 428 429 ppdu_info->cfr_info.agc_gain_info0 = 430 HAL_RX_GET_64(rx_tlv, 431 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 432 GAIN_CHAIN0); 433 434 ppdu_info->cfr_info.agc_gain_info0 |= 435 (((uint32_t)HAL_RX_GET_64(rx_tlv, 436 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 437 GAIN_CHAIN1)) << 16); 438 439 ppdu_info->cfr_info.agc_gain_info1 = 440 HAL_RX_GET_64(rx_tlv, 441 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 442 GAIN_CHAIN2); 443 444 ppdu_info->cfr_info.agc_gain_info1 |= 445 (((uint32_t)HAL_RX_GET_64(rx_tlv, 446 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 447 GAIN_CHAIN3)) << 16); 448 449 ppdu_info->cfr_info.agc_gain_info2 = 0; 450 451 ppdu_info->cfr_info.agc_gain_info3 = 0; 452 453 ppdu_info->cfr_info.mcs_rate = 454 HAL_RX_GET_64(rx_tlv, 455 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 456 RTT_MCS_RATE); 457 ppdu_info->cfr_info.gi_type = 458 HAL_RX_GET_64(rx_tlv, 459 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 460 RTT_GI_TYPE); 461 } 462 #endif 463 464 #ifdef CONFIG_WORD_BASED_TLV 465 /** 466 * hal_rx_dump_mpdu_start_tlv_9224() - dump RX mpdu_start TLV in structured 467 * human readable format. 468 * @mpdustart: pointer the rx_attention TLV in pkt. 469 * @dbg_level: log level. 470 * 471 * Return: void 472 */ 473 static inline void hal_rx_dump_mpdu_start_tlv_9224(void *mpdustart, 474 uint8_t dbg_level) 475 { 476 struct rx_mpdu_start_compact *mpdu_info = 477 (struct rx_mpdu_start_compact *)mpdustart; 478 479 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 480 "rx_mpdu_start tlv (1/5) - " 481 "rx_reo_queue_desc_addr_39_32 :%x" 482 "receive_queue_number:%x " 483 "pre_delim_err_warning:%x " 484 "first_delim_err:%x " 485 "pn_31_0:%x " 486 "pn_63_32:%x " 487 "pn_95_64:%x ", 488 mpdu_info->rx_reo_queue_desc_addr_39_32, 489 mpdu_info->receive_queue_number, 490 mpdu_info->pre_delim_err_warning, 491 mpdu_info->first_delim_err, 492 mpdu_info->pn_31_0, 493 mpdu_info->pn_63_32, 494 mpdu_info->pn_95_64); 495 496 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 497 "rx_mpdu_start tlv (2/5) - " 498 "ast_index:%x " 499 "sw_peer_id:%x " 500 "mpdu_frame_control_valid:%x " 501 "mpdu_duration_valid:%x " 502 "mac_addr_ad1_valid:%x " 503 "mac_addr_ad2_valid:%x " 504 "mac_addr_ad3_valid:%x " 505 "mac_addr_ad4_valid:%x " 506 "mpdu_sequence_control_valid :%x" 507 "mpdu_qos_control_valid:%x " 508 "mpdu_ht_control_valid:%x " 509 "frame_encryption_info_valid :%x", 510 mpdu_info->ast_index, 511 mpdu_info->sw_peer_id, 512 mpdu_info->mpdu_frame_control_valid, 513 mpdu_info->mpdu_duration_valid, 514 mpdu_info->mac_addr_ad1_valid, 515 mpdu_info->mac_addr_ad2_valid, 516 mpdu_info->mac_addr_ad3_valid, 517 mpdu_info->mac_addr_ad4_valid, 518 mpdu_info->mpdu_sequence_control_valid, 519 mpdu_info->mpdu_qos_control_valid, 520 mpdu_info->mpdu_ht_control_valid, 521 mpdu_info->frame_encryption_info_valid); 522 523 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 524 "rx_mpdu_start tlv (3/5) - " 525 "mpdu_fragment_number:%x " 526 "more_fragment_flag:%x " 527 "fr_ds:%x " 528 "to_ds:%x " 529 "encrypted:%x " 530 "mpdu_retry:%x " 531 "mpdu_sequence_number:%x ", 532 mpdu_info->mpdu_fragment_number, 533 mpdu_info->more_fragment_flag, 534 mpdu_info->fr_ds, 535 mpdu_info->to_ds, 536 mpdu_info->encrypted, 537 mpdu_info->mpdu_retry, 538 mpdu_info->mpdu_sequence_number); 539 540 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 541 "rx_mpdu_start tlv (4/5) - " 542 "mpdu_frame_control_field:%x " 543 "mpdu_duration_field:%x ", 544 mpdu_info->mpdu_frame_control_field, 545 mpdu_info->mpdu_duration_field); 546 547 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 548 "rx_mpdu_start tlv (5/5) - " 549 "mac_addr_ad1_31_0:%x " 550 "mac_addr_ad1_47_32:%x " 551 "mac_addr_ad2_15_0:%x " 552 "mac_addr_ad2_47_16:%x " 553 "mac_addr_ad3_31_0:%x " 554 "mac_addr_ad3_47_32:%x " 555 "mpdu_sequence_control_field :%x", 556 mpdu_info->mac_addr_ad1_31_0, 557 mpdu_info->mac_addr_ad1_47_32, 558 mpdu_info->mac_addr_ad2_15_0, 559 mpdu_info->mac_addr_ad2_47_16, 560 mpdu_info->mac_addr_ad3_31_0, 561 mpdu_info->mac_addr_ad3_47_32, 562 mpdu_info->mpdu_sequence_control_field); 563 } 564 565 /** 566 * hal_rx_dump_msdu_end_tlv_9224() - dump RX msdu_end TLV in structured human 567 * readable format. 568 * @msduend: pointer the msdu_end TLV in pkt. 569 * @dbg_level: log level. 570 * 571 * Return: void 572 */ 573 static void hal_rx_dump_msdu_end_tlv_9224(void *msduend, 574 uint8_t dbg_level) 575 { 576 struct rx_msdu_end_compact *msdu_end = 577 (struct rx_msdu_end_compact *)msduend; 578 579 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 580 "rx_msdu_end tlv - " 581 "key_id_octet: %d " 582 "tcp_udp_chksum: %d " 583 "sa_idx_timeout: %d " 584 "da_idx_timeout: %d " 585 "msdu_limit_error: %d " 586 "flow_idx_timeout: %d " 587 "flow_idx_invalid: %d " 588 "wifi_parser_error: %d " 589 "sa_is_valid: %d " 590 "da_is_valid: %d " 591 "da_is_mcbc: %d " 592 "tkip_mic_err: %d " 593 "l3_header_padding: %d " 594 "first_msdu: %d " 595 "last_msdu: %d " 596 "sa_idx: %d " 597 "msdu_drop: %d " 598 "reo_destination_indication: %d " 599 "flow_idx: %d " 600 "fse_metadata: %d " 601 "cce_metadata: %d " 602 "sa_sw_peer_id: %d ", 603 msdu_end->key_id_octet, 604 msdu_end->tcp_udp_chksum, 605 msdu_end->sa_idx_timeout, 606 msdu_end->da_idx_timeout, 607 msdu_end->msdu_limit_error, 608 msdu_end->flow_idx_timeout, 609 msdu_end->flow_idx_invalid, 610 msdu_end->wifi_parser_error, 611 msdu_end->sa_is_valid, 612 msdu_end->da_is_valid, 613 msdu_end->da_is_mcbc, 614 msdu_end->tkip_mic_err, 615 msdu_end->l3_header_padding, 616 msdu_end->first_msdu, 617 msdu_end->last_msdu, 618 msdu_end->sa_idx, 619 msdu_end->msdu_drop, 620 msdu_end->reo_destination_indication, 621 msdu_end->flow_idx, 622 msdu_end->fse_metadata, 623 msdu_end->cce_metadata, 624 msdu_end->sa_sw_peer_id); 625 } 626 #else 627 static inline void hal_rx_dump_mpdu_start_tlv_9224(void *mpdustart, 628 uint8_t dbg_level) 629 { 630 struct rx_mpdu_start *mpdu_start = (struct rx_mpdu_start *)mpdustart; 631 struct rx_mpdu_info *mpdu_info = 632 (struct rx_mpdu_info *)&mpdu_start->rx_mpdu_info_details; 633 634 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 635 "rx_mpdu_start tlv (1/5) - " 636 "rx_reo_queue_desc_addr_31_0 :%x" 637 "rx_reo_queue_desc_addr_39_32 :%x" 638 "receive_queue_number:%x " 639 "pre_delim_err_warning:%x " 640 "first_delim_err:%x " 641 "reserved_2a:%x " 642 "pn_31_0:%x " 643 "pn_63_32:%x " 644 "pn_95_64:%x " 645 "pn_127_96:%x " 646 "epd_en:%x " 647 "all_frames_shall_be_encrypted :%x" 648 "encrypt_type:%x " 649 "wep_key_width_for_variable_key :%x" 650 "mesh_sta:%x " 651 "bssid_hit:%x " 652 "bssid_number:%x " 653 "tid:%x " 654 "reserved_7a:%x ", 655 mpdu_info->rx_reo_queue_desc_addr_31_0, 656 mpdu_info->rx_reo_queue_desc_addr_39_32, 657 mpdu_info->receive_queue_number, 658 mpdu_info->pre_delim_err_warning, 659 mpdu_info->first_delim_err, 660 mpdu_info->reserved_2a, 661 mpdu_info->pn_31_0, 662 mpdu_info->pn_63_32, 663 mpdu_info->pn_95_64, 664 mpdu_info->pn_127_96, 665 mpdu_info->epd_en, 666 mpdu_info->all_frames_shall_be_encrypted, 667 mpdu_info->encrypt_type, 668 mpdu_info->wep_key_width_for_variable_key, 669 mpdu_info->mesh_sta, 670 mpdu_info->bssid_hit, 671 mpdu_info->bssid_number, 672 mpdu_info->tid, 673 mpdu_info->reserved_7a); 674 675 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 676 "rx_mpdu_start tlv (2/5) - " 677 "ast_index:%x " 678 "sw_peer_id:%x " 679 "mpdu_frame_control_valid:%x " 680 "mpdu_duration_valid:%x " 681 "mac_addr_ad1_valid:%x " 682 "mac_addr_ad2_valid:%x " 683 "mac_addr_ad3_valid:%x " 684 "mac_addr_ad4_valid:%x " 685 "mpdu_sequence_control_valid :%x" 686 "mpdu_qos_control_valid:%x " 687 "mpdu_ht_control_valid:%x " 688 "frame_encryption_info_valid :%x", 689 mpdu_info->ast_index, 690 mpdu_info->sw_peer_id, 691 mpdu_info->mpdu_frame_control_valid, 692 mpdu_info->mpdu_duration_valid, 693 mpdu_info->mac_addr_ad1_valid, 694 mpdu_info->mac_addr_ad2_valid, 695 mpdu_info->mac_addr_ad3_valid, 696 mpdu_info->mac_addr_ad4_valid, 697 mpdu_info->mpdu_sequence_control_valid, 698 mpdu_info->mpdu_qos_control_valid, 699 mpdu_info->mpdu_ht_control_valid, 700 mpdu_info->frame_encryption_info_valid); 701 702 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 703 "rx_mpdu_start tlv (3/5) - " 704 "mpdu_fragment_number:%x " 705 "more_fragment_flag:%x " 706 "reserved_11a:%x " 707 "fr_ds:%x " 708 "to_ds:%x " 709 "encrypted:%x " 710 "mpdu_retry:%x " 711 "mpdu_sequence_number:%x ", 712 mpdu_info->mpdu_fragment_number, 713 mpdu_info->more_fragment_flag, 714 mpdu_info->reserved_11a, 715 mpdu_info->fr_ds, 716 mpdu_info->to_ds, 717 mpdu_info->encrypted, 718 mpdu_info->mpdu_retry, 719 mpdu_info->mpdu_sequence_number); 720 721 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 722 "rx_mpdu_start tlv (4/5) - " 723 "mpdu_frame_control_field:%x " 724 "mpdu_duration_field:%x ", 725 mpdu_info->mpdu_frame_control_field, 726 mpdu_info->mpdu_duration_field); 727 728 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 729 "rx_mpdu_start tlv (5/5) - " 730 "mac_addr_ad1_31_0:%x " 731 "mac_addr_ad1_47_32:%x " 732 "mac_addr_ad2_15_0:%x " 733 "mac_addr_ad2_47_16:%x " 734 "mac_addr_ad3_31_0:%x " 735 "mac_addr_ad3_47_32:%x " 736 "mpdu_sequence_control_field :%x" 737 "mac_addr_ad4_31_0:%x " 738 "mac_addr_ad4_47_32:%x " 739 "mpdu_qos_control_field:%x ", 740 mpdu_info->mac_addr_ad1_31_0, 741 mpdu_info->mac_addr_ad1_47_32, 742 mpdu_info->mac_addr_ad2_15_0, 743 mpdu_info->mac_addr_ad2_47_16, 744 mpdu_info->mac_addr_ad3_31_0, 745 mpdu_info->mac_addr_ad3_47_32, 746 mpdu_info->mpdu_sequence_control_field, 747 mpdu_info->mac_addr_ad4_31_0, 748 mpdu_info->mac_addr_ad4_47_32, 749 mpdu_info->mpdu_qos_control_field); 750 } 751 752 static void hal_rx_dump_msdu_end_tlv_9224(void *msduend, 753 uint8_t dbg_level) 754 { 755 struct rx_msdu_end *msdu_end = 756 (struct rx_msdu_end *)msduend; 757 758 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 759 "rx_msdu_end tlv - " 760 "key_id_octet: %d " 761 "cce_super_rule: %d " 762 "cce_classify_not_done_truncat: %d " 763 "cce_classify_not_done_cce_dis: %d " 764 "rule_indication_31_0: %d " 765 "tcp_udp_chksum: %d " 766 "sa_idx_timeout: %d " 767 "da_idx_timeout: %d " 768 "msdu_limit_error: %d " 769 "flow_idx_timeout: %d " 770 "flow_idx_invalid: %d " 771 "wifi_parser_error: %d " 772 "sa_is_valid: %d " 773 "da_is_valid: %d " 774 "da_is_mcbc: %d " 775 "tkip_mic_err: %d " 776 "l3_header_padding: %d " 777 "first_msdu: %d " 778 "last_msdu: %d " 779 "sa_idx: %d " 780 "msdu_drop: %d " 781 "reo_destination_indication: %d " 782 "flow_idx: %d " 783 "fse_metadata: %d " 784 "cce_metadata: %d " 785 "sa_sw_peer_id: %d ", 786 msdu_end->key_id_octet, 787 msdu_end->cce_super_rule, 788 msdu_end->cce_classify_not_done_truncate, 789 msdu_end->cce_classify_not_done_cce_dis, 790 msdu_end->rule_indication_31_0, 791 msdu_end->tcp_udp_chksum, 792 msdu_end->sa_idx_timeout, 793 msdu_end->da_idx_timeout, 794 msdu_end->msdu_limit_error, 795 msdu_end->flow_idx_timeout, 796 msdu_end->flow_idx_invalid, 797 msdu_end->wifi_parser_error, 798 msdu_end->sa_is_valid, 799 msdu_end->da_is_valid, 800 msdu_end->da_is_mcbc, 801 msdu_end->tkip_mic_err, 802 msdu_end->l3_header_padding, 803 msdu_end->first_msdu, 804 msdu_end->last_msdu, 805 msdu_end->sa_idx, 806 msdu_end->msdu_drop, 807 msdu_end->reo_destination_indication, 808 msdu_end->flow_idx, 809 msdu_end->fse_metadata, 810 msdu_end->cce_metadata, 811 msdu_end->sa_sw_peer_id); 812 } 813 #endif 814 815 /** 816 * hal_reo_status_get_header_9224() - Process reo desc info 817 * @ring_desc: Pointer to reo descriptor 818 * @b: tlv type info 819 * @h1: Pointer to hal_reo_status_header where info to be stored 820 * 821 * Return: none. 822 * 823 */ 824 static void hal_reo_status_get_header_9224(hal_ring_desc_t ring_desc, 825 int b, void *h1) 826 { 827 uint64_t *d = (uint64_t *)ring_desc; 828 uint64_t val1 = 0; 829 struct hal_reo_status_header *h = 830 (struct hal_reo_status_header *)h1; 831 832 /* Offsets of descriptor fields defined in HW headers start 833 * from the field after TLV header 834 */ 835 d += HAL_GET_NUM_QWORDS(sizeof(struct tlv_32_hdr)); 836 837 switch (b) { 838 case HAL_REO_QUEUE_STATS_STATUS_TLV: 839 val1 = d[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS, 840 STATUS_HEADER_REO_STATUS_NUMBER)]; 841 break; 842 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 843 val1 = d[HAL_OFFSET_QW(REO_FLUSH_QUEUE_STATUS, 844 STATUS_HEADER_REO_STATUS_NUMBER)]; 845 break; 846 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 847 val1 = d[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS, 848 STATUS_HEADER_REO_STATUS_NUMBER)]; 849 break; 850 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 851 val1 = d[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS, 852 STATUS_HEADER_REO_STATUS_NUMBER)]; 853 break; 854 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 855 val1 = d[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS, 856 STATUS_HEADER_REO_STATUS_NUMBER)]; 857 break; 858 case HAL_REO_DESC_THRES_STATUS_TLV: 859 val1 = 860 d[HAL_OFFSET_QW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS, 861 STATUS_HEADER_REO_STATUS_NUMBER)]; 862 break; 863 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 864 val1 = d[HAL_OFFSET_QW(REO_UPDATE_RX_REO_QUEUE_STATUS, 865 STATUS_HEADER_REO_STATUS_NUMBER)]; 866 break; 867 default: 868 qdf_nofl_err("ERROR: Unknown tlv\n"); 869 break; 870 } 871 h->cmd_num = 872 HAL_GET_FIELD( 873 UNIFORM_REO_STATUS_HEADER, REO_STATUS_NUMBER, 874 val1); 875 h->exec_time = 876 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, 877 CMD_EXECUTION_TIME, val1); 878 h->status = 879 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, 880 REO_CMD_EXECUTION_STATUS, val1); 881 switch (b) { 882 case HAL_REO_QUEUE_STATS_STATUS_TLV: 883 val1 = d[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS, 884 STATUS_HEADER_TIMESTAMP)]; 885 break; 886 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 887 val1 = d[HAL_OFFSET_QW(REO_FLUSH_QUEUE_STATUS, 888 STATUS_HEADER_TIMESTAMP)]; 889 break; 890 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 891 val1 = d[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS, 892 STATUS_HEADER_TIMESTAMP)]; 893 break; 894 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 895 val1 = d[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS, 896 STATUS_HEADER_TIMESTAMP)]; 897 break; 898 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 899 val1 = d[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS, 900 STATUS_HEADER_TIMESTAMP)]; 901 break; 902 case HAL_REO_DESC_THRES_STATUS_TLV: 903 val1 = 904 d[HAL_OFFSET_QW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS, 905 STATUS_HEADER_TIMESTAMP)]; 906 break; 907 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 908 val1 = d[HAL_OFFSET_QW(REO_UPDATE_RX_REO_QUEUE_STATUS, 909 STATUS_HEADER_TIMESTAMP)]; 910 break; 911 default: 912 qdf_nofl_err("ERROR: Unknown tlv\n"); 913 break; 914 } 915 h->tstamp = 916 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, TIMESTAMP, val1); 917 } 918 919 static 920 void *hal_rx_msdu0_buffer_addr_lsb_9224(void *link_desc_va) 921 { 922 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 923 } 924 925 static 926 void *hal_rx_msdu_desc_info_ptr_get_9224(void *msdu0) 927 { 928 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 929 } 930 931 static 932 void *hal_ent_mpdu_desc_info_9224(void *ent_ring_desc) 933 { 934 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 935 } 936 937 static 938 void *hal_dst_mpdu_desc_info_9224(void *dst_ring_desc) 939 { 940 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 941 } 942 943 /** 944 * hal_reo_config_9224() - Set reo config parameters 945 * @soc: hal soc handle 946 * @reg_val: value to be set 947 * @reo_params: reo parameters 948 * 949 * Return: void 950 */ 951 static void 952 hal_reo_config_9224(struct hal_soc *soc, 953 uint32_t reg_val, 954 struct hal_reo_params *reo_params) 955 { 956 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 957 } 958 959 /** 960 * hal_rx_msdu_desc_info_get_ptr_9224() - Get msdu desc info ptr 961 * @msdu_details_ptr: Pointer to msdu_details_ptr 962 * 963 * Return: Pointer to rx_msdu_desc_info structure. 964 * 965 */ 966 static void *hal_rx_msdu_desc_info_get_ptr_9224(void *msdu_details_ptr) 967 { 968 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 969 } 970 971 /** 972 * hal_rx_link_desc_msdu0_ptr_9224() - Get pointer to rx_msdu details 973 * @link_desc: Pointer to link desc 974 * 975 * Return: Pointer to rx_msdu_details structure 976 * 977 */ 978 static void *hal_rx_link_desc_msdu0_ptr_9224(void *link_desc) 979 { 980 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 981 } 982 983 /** 984 * hal_get_window_address_9224() - Function to get hp/tp address 985 * @hal_soc: Pointer to hal_soc 986 * @addr: address offset of register 987 * 988 * Return: modified address offset of register 989 */ 990 991 static inline qdf_iomem_t hal_get_window_address_9224(struct hal_soc *hal_soc, 992 qdf_iomem_t addr) 993 { 994 uint32_t offset = addr - hal_soc->dev_base_addr; 995 qdf_iomem_t new_offset; 996 997 /* 998 * If offset lies within DP register range, use 3rd window to write 999 * into DP region. 1000 */ 1001 if ((offset ^ UMAC_BASE) < WINDOW_RANGE_MASK) { 1002 new_offset = (hal_soc->dev_base_addr + (3 * WINDOW_START) + 1003 (offset & WINDOW_RANGE_MASK)); 1004 /* 1005 * If offset lies within CE register range, use 2nd window to write 1006 * into CE region. 1007 */ 1008 } else if ((offset ^ CE_WFSS_CE_REG_BASE) < WINDOW_RANGE_MASK) { 1009 new_offset = (hal_soc->dev_base_addr + (2 * WINDOW_START) + 1010 (offset & WINDOW_RANGE_MASK)); 1011 } else { 1012 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 1013 "%s: ERROR: Accessing Wrong register\n", __func__); 1014 qdf_assert_always(0); 1015 return 0; 1016 } 1017 return new_offset; 1018 } 1019 1020 static inline void hal_write_window_register(struct hal_soc *hal_soc) 1021 { 1022 /* Write value into window configuration register */ 1023 qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_REG_ADDRESS, 1024 WINDOW_CONFIGURATION_VALUE_9224); 1025 } 1026 1027 static 1028 void hal_compute_reo_remap_ix2_ix3_9224(uint32_t *ring, uint32_t num_rings, 1029 uint32_t *remap1, uint32_t *remap2) 1030 { 1031 switch (num_rings) { 1032 case 1: 1033 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1034 HAL_REO_REMAP_IX2(ring[0], 17) | 1035 HAL_REO_REMAP_IX2(ring[0], 18) | 1036 HAL_REO_REMAP_IX2(ring[0], 19) | 1037 HAL_REO_REMAP_IX2(ring[0], 20) | 1038 HAL_REO_REMAP_IX2(ring[0], 21) | 1039 HAL_REO_REMAP_IX2(ring[0], 22) | 1040 HAL_REO_REMAP_IX2(ring[0], 23); 1041 1042 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1043 HAL_REO_REMAP_IX3(ring[0], 25) | 1044 HAL_REO_REMAP_IX3(ring[0], 26) | 1045 HAL_REO_REMAP_IX3(ring[0], 27) | 1046 HAL_REO_REMAP_IX3(ring[0], 28) | 1047 HAL_REO_REMAP_IX3(ring[0], 29) | 1048 HAL_REO_REMAP_IX3(ring[0], 30) | 1049 HAL_REO_REMAP_IX3(ring[0], 31); 1050 break; 1051 case 2: 1052 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1053 HAL_REO_REMAP_IX2(ring[0], 17) | 1054 HAL_REO_REMAP_IX2(ring[1], 18) | 1055 HAL_REO_REMAP_IX2(ring[1], 19) | 1056 HAL_REO_REMAP_IX2(ring[0], 20) | 1057 HAL_REO_REMAP_IX2(ring[0], 21) | 1058 HAL_REO_REMAP_IX2(ring[1], 22) | 1059 HAL_REO_REMAP_IX2(ring[1], 23); 1060 1061 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1062 HAL_REO_REMAP_IX3(ring[0], 25) | 1063 HAL_REO_REMAP_IX3(ring[1], 26) | 1064 HAL_REO_REMAP_IX3(ring[1], 27) | 1065 HAL_REO_REMAP_IX3(ring[0], 28) | 1066 HAL_REO_REMAP_IX3(ring[0], 29) | 1067 HAL_REO_REMAP_IX3(ring[1], 30) | 1068 HAL_REO_REMAP_IX3(ring[1], 31); 1069 break; 1070 case 3: 1071 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1072 HAL_REO_REMAP_IX2(ring[1], 17) | 1073 HAL_REO_REMAP_IX2(ring[2], 18) | 1074 HAL_REO_REMAP_IX2(ring[0], 19) | 1075 HAL_REO_REMAP_IX2(ring[1], 20) | 1076 HAL_REO_REMAP_IX2(ring[2], 21) | 1077 HAL_REO_REMAP_IX2(ring[0], 22) | 1078 HAL_REO_REMAP_IX2(ring[1], 23); 1079 1080 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) | 1081 HAL_REO_REMAP_IX3(ring[0], 25) | 1082 HAL_REO_REMAP_IX3(ring[1], 26) | 1083 HAL_REO_REMAP_IX3(ring[2], 27) | 1084 HAL_REO_REMAP_IX3(ring[0], 28) | 1085 HAL_REO_REMAP_IX3(ring[1], 29) | 1086 HAL_REO_REMAP_IX3(ring[2], 30) | 1087 HAL_REO_REMAP_IX3(ring[0], 31); 1088 break; 1089 case 4: 1090 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1091 HAL_REO_REMAP_IX2(ring[1], 17) | 1092 HAL_REO_REMAP_IX2(ring[2], 18) | 1093 HAL_REO_REMAP_IX2(ring[3], 19) | 1094 HAL_REO_REMAP_IX2(ring[0], 20) | 1095 HAL_REO_REMAP_IX2(ring[1], 21) | 1096 HAL_REO_REMAP_IX2(ring[2], 22) | 1097 HAL_REO_REMAP_IX2(ring[3], 23); 1098 1099 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1100 HAL_REO_REMAP_IX3(ring[1], 25) | 1101 HAL_REO_REMAP_IX3(ring[2], 26) | 1102 HAL_REO_REMAP_IX3(ring[3], 27) | 1103 HAL_REO_REMAP_IX3(ring[0], 28) | 1104 HAL_REO_REMAP_IX3(ring[1], 29) | 1105 HAL_REO_REMAP_IX3(ring[2], 30) | 1106 HAL_REO_REMAP_IX3(ring[3], 31); 1107 break; 1108 } 1109 } 1110 1111 static 1112 void hal_compute_reo_remap_ix0_9224(struct hal_soc *soc) 1113 { 1114 uint32_t remap0; 1115 1116 remap0 = HAL_REG_READ(soc, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR 1117 (REO_REG_REG_BASE)); 1118 1119 remap0 &= ~(HAL_REO_REMAP_IX0(0xF, 6)); 1120 remap0 |= HAL_REO_REMAP_IX0(REO2PPE_DST_RING, 6); 1121 1122 HAL_REG_WRITE(soc, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR 1123 (REO_REG_REG_BASE), remap0); 1124 1125 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR 0x%x", 1126 HAL_REG_READ(soc, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR 1127 (REO_REG_REG_BASE))); 1128 } 1129 1130 /** 1131 * hal_rx_flow_setup_fse_9224() - Setup a flow search entry in HW FST 1132 * @rx_fst: Pointer to the Rx Flow Search Table 1133 * @table_offset: offset into the table where the flow is to be setup 1134 * @rx_flow: Flow Parameters 1135 * 1136 * Return: Success/Failure 1137 */ 1138 static void * 1139 hal_rx_flow_setup_fse_9224(uint8_t *rx_fst, uint32_t table_offset, 1140 uint8_t *rx_flow) 1141 { 1142 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 1143 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 1144 uint8_t *fse; 1145 bool fse_valid; 1146 1147 if (table_offset >= fst->max_entries) { 1148 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 1149 "HAL FSE table offset %u exceeds max entries %u", 1150 table_offset, fst->max_entries); 1151 return NULL; 1152 } 1153 1154 fse = (uint8_t *)fst->base_vaddr + 1155 (table_offset * HAL_RX_FST_ENTRY_SIZE); 1156 1157 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID); 1158 1159 if (fse_valid) { 1160 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 1161 "HAL FSE %pK already valid", fse); 1162 return NULL; 1163 } 1164 1165 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96) = 1166 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96, 1167 qdf_htonl(flow->tuple_info.src_ip_127_96)); 1168 1169 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64) = 1170 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64, 1171 qdf_htonl(flow->tuple_info.src_ip_95_64)); 1172 1173 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32) = 1174 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32, 1175 qdf_htonl(flow->tuple_info.src_ip_63_32)); 1176 1177 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0) = 1178 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0, 1179 qdf_htonl(flow->tuple_info.src_ip_31_0)); 1180 1181 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96) = 1182 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96, 1183 qdf_htonl(flow->tuple_info.dest_ip_127_96)); 1184 1185 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64) = 1186 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64, 1187 qdf_htonl(flow->tuple_info.dest_ip_95_64)); 1188 1189 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32) = 1190 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32, 1191 qdf_htonl(flow->tuple_info.dest_ip_63_32)); 1192 1193 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0) = 1194 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0, 1195 qdf_htonl(flow->tuple_info.dest_ip_31_0)); 1196 1197 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_PORT); 1198 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_PORT) |= 1199 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_PORT, 1200 (flow->tuple_info.dest_port)); 1201 1202 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_PORT); 1203 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_PORT) |= 1204 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_PORT, 1205 (flow->tuple_info.src_port)); 1206 1207 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL); 1208 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL) |= 1209 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL, 1210 flow->tuple_info.l4_protocol); 1211 1212 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, USE_PPE); 1213 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, USE_PPE) |= 1214 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, USE_PPE, flow->use_ppe_ds); 1215 1216 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, PRIORITY_VALID); 1217 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, PRIORITY_VALID) |= 1218 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, PRIORITY_VALID, 1219 flow->priority_vld); 1220 1221 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, SERVICE_CODE); 1222 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SERVICE_CODE) |= 1223 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SERVICE_CODE, 1224 flow->service_code); 1225 1226 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER); 1227 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER) |= 1228 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER, 1229 flow->reo_destination_handler); 1230 1231 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID); 1232 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID) |= 1233 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, VALID, 1); 1234 1235 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, METADATA); 1236 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, METADATA) = 1237 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, METADATA, 1238 flow->fse_metadata); 1239 1240 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_INDICATION); 1241 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_INDICATION) |= 1242 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, 1243 REO_DESTINATION_INDICATION, 1244 flow->reo_destination_indication); 1245 1246 /* Reset all the other fields in FSE */ 1247 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, RESERVED_9); 1248 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_DROP); 1249 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_COUNT); 1250 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_BYTE_COUNT); 1251 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, TIMESTAMP); 1252 1253 return fse; 1254 } 1255 1256 /** 1257 * hal_rx_dump_pkt_hdr_tlv_9224() - dump RX pkt header TLV in hex format 1258 * @pkt_tlvs: pointer the pkt_hdr_tlv in pkt. 1259 * @dbg_level: log level. 1260 * 1261 * Return: void 1262 */ 1263 #ifndef NO_RX_PKT_HDR_TLV 1264 static inline void hal_rx_dump_pkt_hdr_tlv_9224(struct rx_pkt_tlvs *pkt_tlvs, 1265 uint8_t dbg_level) 1266 { 1267 struct rx_pkt_hdr_tlv *pkt_hdr_tlv = &pkt_tlvs->pkt_hdr_tlv; 1268 1269 hal_verbose_debug("\n---------------\n" 1270 "rx_pkt_hdr_tlv\n" 1271 "---------------\n" 1272 "phy_ppdu_id %llu ", 1273 pkt_hdr_tlv->phy_ppdu_id); 1274 1275 hal_verbose_hex_dump(pkt_hdr_tlv->rx_pkt_hdr, 1276 sizeof(pkt_hdr_tlv->rx_pkt_hdr)); 1277 } 1278 #else 1279 static inline void hal_rx_dump_pkt_hdr_tlv_9224(struct rx_pkt_tlvs *pkt_tlvs, 1280 uint8_t dbg_level) 1281 { 1282 } 1283 #endif 1284 1285 /** 1286 * hal_tx_dump_ppe_vp_entry_9224() - API to print PPE VP entries 1287 * @hal_soc_hdl: HAL SoC handle 1288 * 1289 * Return: void 1290 */ 1291 static inline 1292 void hal_tx_dump_ppe_vp_entry_9224(hal_soc_handle_t hal_soc_hdl) 1293 { 1294 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; 1295 uint32_t reg_addr, reg_val = 0, i; 1296 1297 for (i = 0; i < HAL_PPE_VP_ENTRIES_MAX; i++) { 1298 reg_addr = 1299 HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_ADDR( 1300 MAC_TCL_REG_REG_BASE, 1301 i); 1302 reg_val = HAL_REG_READ(soc, reg_addr); 1303 hal_verbose_debug("%d: 0x%x\n", i, reg_val); 1304 } 1305 } 1306 1307 /** 1308 * hal_rx_dump_pkt_tlvs_9224() - API to print RX Pkt TLVS QCN9224 1309 * @hal_soc_hdl: hal_soc handle 1310 * @buf: pointer the pkt buffer 1311 * @dbg_level: log level 1312 * 1313 * Return: void 1314 */ 1315 #ifdef CONFIG_WORD_BASED_TLV 1316 static void hal_rx_dump_pkt_tlvs_9224(hal_soc_handle_t hal_soc_hdl, 1317 uint8_t *buf, uint8_t dbg_level) 1318 { 1319 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1320 struct rx_msdu_end_compact *msdu_end = 1321 &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1322 struct rx_mpdu_start_compact *mpdu_start = 1323 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1324 1325 hal_rx_dump_msdu_end_tlv_9224(msdu_end, dbg_level); 1326 hal_rx_dump_mpdu_start_tlv_9224(mpdu_start, dbg_level); 1327 hal_rx_dump_pkt_hdr_tlv_9224(pkt_tlvs, dbg_level); 1328 } 1329 #else 1330 static void hal_rx_dump_pkt_tlvs_9224(hal_soc_handle_t hal_soc_hdl, 1331 uint8_t *buf, uint8_t dbg_level) 1332 { 1333 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1334 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1335 struct rx_mpdu_start *mpdu_start = 1336 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1337 1338 hal_rx_dump_msdu_end_tlv_9224(msdu_end, dbg_level); 1339 hal_rx_dump_mpdu_start_tlv_9224(mpdu_start, dbg_level); 1340 hal_rx_dump_pkt_hdr_tlv_9224(pkt_tlvs, dbg_level); 1341 } 1342 #endif 1343 1344 #define HAL_NUM_TCL_BANKS_9224 48 1345 1346 /** 1347 * hal_cmem_write_9224() - function for CMEM buffer writing 1348 * @hal_soc_hdl: HAL SOC handle 1349 * @offset: CMEM address 1350 * @value: value to write 1351 * 1352 * Return: None. 1353 */ 1354 static void hal_cmem_write_9224(hal_soc_handle_t hal_soc_hdl, 1355 uint32_t offset, 1356 uint32_t value) 1357 { 1358 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 1359 1360 pld_reg_write(hal->qdf_dev->dev, offset, value, NULL); 1361 } 1362 1363 /** 1364 * hal_tx_get_num_tcl_banks_9224() - Get number of banks in target 1365 * 1366 * Return: number of bank 1367 */ 1368 static uint8_t hal_tx_get_num_tcl_banks_9224(void) 1369 { 1370 return HAL_NUM_TCL_BANKS_9224; 1371 } 1372 1373 static void hal_reo_setup_9224(struct hal_soc *soc, void *reoparams, 1374 int qref_reset) 1375 { 1376 uint32_t reg_val; 1377 struct hal_reo_params *reo_params = (struct hal_reo_params *)reoparams; 1378 1379 reg_val = HAL_REG_READ(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR( 1380 REO_REG_REG_BASE)); 1381 1382 hal_reo_config_9224(soc, reg_val, reo_params); 1383 /* Other ring enable bits and REO_ENABLE will be set by FW */ 1384 1385 /* TODO: Setup destination ring mapping if enabled */ 1386 1387 /* TODO: Error destination ring setting is left to default. 1388 * Default setting is to send all errors to release ring. 1389 */ 1390 1391 /* Set the reo descriptor swap bits in case of BIG endian platform */ 1392 hal_setup_reo_swap(soc); 1393 1394 HAL_REG_WRITE(soc, 1395 HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(REO_REG_REG_BASE), 1396 HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000); 1397 1398 HAL_REG_WRITE(soc, 1399 HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(REO_REG_REG_BASE), 1400 (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000)); 1401 1402 HAL_REG_WRITE(soc, 1403 HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(REO_REG_REG_BASE), 1404 (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000)); 1405 1406 HAL_REG_WRITE(soc, 1407 HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(REO_REG_REG_BASE), 1408 (HAL_DEFAULT_VO_REO_TIMEOUT_MS * 1000)); 1409 1410 /* 1411 * When hash based routing is enabled, routing of the rx packet 1412 * is done based on the following value: 1 _ _ _ _ The last 4 1413 * bits are based on hash[3:0]. This means the possible values 1414 * are 0x10 to 0x1f. This value is used to look-up the 1415 * ring ID configured in Destination_Ring_Ctrl_IX_* register. 1416 * The Destination_Ring_Ctrl_IX_2 and Destination_Ring_Ctrl_IX_3 1417 * registers need to be configured to set-up the 16 entries to 1418 * map the hash values to a ring number. There are 3 bits per 1419 * hash entry – which are mapped as follows: 1420 * 0: TCL, 1:SW1, 2:SW2, * 3:SW3, 4:SW4, 5:Release, 6:FW(WIFI), 1421 * 7: NOT_USED. 1422 */ 1423 if (reo_params->rx_hash_enabled) { 1424 hal_compute_reo_remap_ix0_9224(soc); 1425 1426 HAL_REG_WRITE(soc, 1427 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR 1428 (REO_REG_REG_BASE), reo_params->remap0); 1429 1430 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x", 1431 HAL_REG_READ(soc, 1432 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR( 1433 REO_REG_REG_BASE))); 1434 1435 HAL_REG_WRITE(soc, 1436 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 1437 (REO_REG_REG_BASE), reo_params->remap1); 1438 1439 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x", 1440 HAL_REG_READ(soc, 1441 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR( 1442 REO_REG_REG_BASE))); 1443 1444 HAL_REG_WRITE(soc, 1445 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 1446 (REO_REG_REG_BASE), reo_params->remap2); 1447 1448 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 0x%x", 1449 HAL_REG_READ(soc, 1450 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR( 1451 REO_REG_REG_BASE))); 1452 } 1453 1454 /* TODO: Check if the following registers shoould be setup by host: 1455 * AGING_CONTROL 1456 * HIGH_MEMORY_THRESHOLD 1457 * GLOBAL_LINK_DESC_COUNT_THRESH_IX_0[1,2] 1458 * GLOBAL_LINK_DESC_COUNT_CTRL 1459 */ 1460 1461 soc->reo_qref = *reo_params->reo_qref; 1462 hal_reo_shared_qaddr_init((hal_soc_handle_t)soc, qref_reset); 1463 } 1464 1465 static uint16_t hal_get_rx_max_ba_window_qcn9224(int tid) 1466 { 1467 return HAL_RX_BA_WINDOW_1024; 1468 } 1469 1470 /** 1471 * hal_qcn9224_get_reo_qdesc_size() - Get the reo queue descriptor size from the 1472 * given Block-Ack window size 1473 * @ba_window_size: Block-Ack window size 1474 * @tid: Traffic id 1475 * 1476 * Return: reo queue descriptor size 1477 */ 1478 static uint32_t hal_qcn9224_get_reo_qdesc_size(uint32_t ba_window_size, int tid) 1479 { 1480 /* Hardcode the ba_window_size to HAL_RX_MAX_BA_WINDOW for 1481 * NON_QOS_TID until HW issues are resolved. 1482 */ 1483 if (tid != HAL_NON_QOS_TID) 1484 ba_window_size = hal_get_rx_max_ba_window_qcn9224(tid); 1485 1486 /* Return descriptor size corresponding to window size of 2 since 1487 * we set ba_window_size to 2 while setting up REO descriptors as 1488 * a WAR to get 2k jump exception aggregates are received without 1489 * a BA session. 1490 */ 1491 if (ba_window_size <= 1) { 1492 if (tid != HAL_NON_QOS_TID) 1493 return sizeof(struct rx_reo_queue) + 1494 sizeof(struct rx_reo_queue_ext); 1495 else 1496 return sizeof(struct rx_reo_queue); 1497 } 1498 1499 if (ba_window_size <= 105) 1500 return sizeof(struct rx_reo_queue) + 1501 sizeof(struct rx_reo_queue_ext); 1502 1503 if (ba_window_size <= 210) 1504 return sizeof(struct rx_reo_queue) + 1505 (2 * sizeof(struct rx_reo_queue_ext)); 1506 1507 if (ba_window_size <= 256) 1508 return sizeof(struct rx_reo_queue) + 1509 (3 * sizeof(struct rx_reo_queue_ext)); 1510 1511 return sizeof(struct rx_reo_queue) + 1512 (10 * sizeof(struct rx_reo_queue_ext)) + 1513 sizeof(struct rx_reo_queue_1k); 1514 } 1515 1516 /** 1517 * hal_tx_get_num_ppe_vp_tbl_entries_9224() - get number of PPE VP entries 1518 * @hal_soc_hdl: HAL SoC handle 1519 * 1520 * Return: Number of PPE VP entries 1521 */ 1522 static 1523 uint32_t hal_tx_get_num_ppe_vp_tbl_entries_9224(hal_soc_handle_t hal_soc_hdl) 1524 { 1525 return HAL_PPE_VP_ENTRIES_MAX; 1526 } 1527 1528 /** 1529 * hal_tx_get_num_ppe_vp_search_idx_reg_entries_9224() - get number of PPE VP 1530 * search index registers 1531 * @hal_soc_hdl: HAL SoC handle 1532 * 1533 * Return: Number of PPE VP search index registers 1534 */ 1535 static 1536 uint32_t hal_tx_get_num_ppe_vp_search_idx_reg_entries_9224(hal_soc_handle_t hal_soc_hdl) 1537 { 1538 return HAL_PPE_VP_SEARCH_IDX_REG_MAX; 1539 } 1540 1541 /** 1542 * hal_rx_tlv_msdu_done_copy_get_9224() - Get msdu done copy bit from rx_tlv 1543 * @buf: pointer the RX TLV 1544 * 1545 * Return: msdu done copy bit 1546 */ 1547 static inline uint32_t hal_rx_tlv_msdu_done_copy_get_9224(uint8_t *buf) 1548 { 1549 return HAL_RX_TLV_MSDU_DONE_COPY_GET(buf); 1550 } 1551 1552 static void hal_hw_txrx_ops_attach_qcn9224(struct hal_soc *hal_soc) 1553 { 1554 /* init and setup */ 1555 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic; 1556 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic; 1557 hal_soc->ops->hal_srng_hw_disable = hal_srng_hw_disable_generic; 1558 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic; 1559 hal_soc->ops->hal_get_window_address = hal_get_window_address_9224; 1560 hal_soc->ops->hal_cmem_write = hal_cmem_write_9224; 1561 1562 /* tx */ 1563 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_9224; 1564 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_9224; 1565 hal_soc->ops->hal_tx_comp_get_status = 1566 hal_tx_comp_get_status_generic_be; 1567 hal_soc->ops->hal_tx_init_cmd_credit_ring = 1568 hal_tx_init_cmd_credit_ring_9224; 1569 hal_soc->ops->hal_tx_set_ppe_cmn_cfg = 1570 hal_tx_set_ppe_cmn_config_9224; 1571 hal_soc->ops->hal_tx_set_ppe_vp_entry = 1572 hal_tx_set_ppe_vp_entry_9224; 1573 hal_soc->ops->hal_ppeds_cfg_ast_override_map_reg = 1574 hal_ppeds_cfg_ast_override_map_reg_9224; 1575 hal_soc->ops->hal_tx_set_ppe_pri2tid = 1576 hal_tx_set_ppe_pri2tid_map_9224; 1577 hal_soc->ops->hal_tx_update_ppe_pri2tid = 1578 hal_tx_update_ppe_pri2tid_9224; 1579 hal_soc->ops->hal_tx_dump_ppe_vp_entry = 1580 hal_tx_dump_ppe_vp_entry_9224; 1581 hal_soc->ops->hal_tx_get_num_ppe_vp_tbl_entries = 1582 hal_tx_get_num_ppe_vp_tbl_entries_9224; 1583 hal_soc->ops->hal_tx_enable_pri2tid_map = 1584 hal_tx_enable_pri2tid_map_9224; 1585 hal_soc->ops->hal_tx_config_rbm_mapping_be = 1586 hal_tx_config_rbm_mapping_be_9224; 1587 1588 /* rx */ 1589 hal_soc->ops->hal_rx_msdu_start_nss_get = hal_rx_tlv_nss_get_be; 1590 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status = 1591 hal_rx_mon_hw_desc_get_mpdu_status_be; 1592 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_9224; 1593 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv = 1594 hal_rx_proc_phyrx_other_receive_info_tlv_9224; 1595 1596 hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_9224; 1597 hal_soc->ops->hal_rx_dump_mpdu_start_tlv = 1598 hal_rx_dump_mpdu_start_tlv_9224; 1599 hal_soc->ops->hal_rx_dump_pkt_tlvs = hal_rx_dump_pkt_tlvs_9224; 1600 1601 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_9224; 1602 hal_soc->ops->hal_rx_mpdu_start_tid_get = hal_rx_tlv_tid_get_be; 1603 hal_soc->ops->hal_rx_msdu_start_reception_type_get = 1604 hal_rx_tlv_reception_type_get_be; 1605 hal_soc->ops->hal_rx_msdu_end_da_idx_get = 1606 hal_rx_msdu_end_da_idx_get_be; 1607 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = 1608 hal_rx_msdu_desc_info_get_ptr_9224; 1609 hal_soc->ops->hal_rx_link_desc_msdu0_ptr = 1610 hal_rx_link_desc_msdu0_ptr_9224; 1611 hal_soc->ops->hal_reo_status_get_header = 1612 hal_reo_status_get_header_9224; 1613 #ifdef WLAN_PKT_CAPTURE_RX_2_0 1614 hal_soc->ops->hal_rx_status_get_tlv_info = 1615 hal_rx_status_get_tlv_info_wrapper_be; 1616 #endif 1617 hal_soc->ops->hal_rx_wbm_err_info_get = 1618 hal_rx_wbm_err_info_get_generic_be; 1619 hal_soc->ops->hal_tx_set_pcp_tid_map = 1620 hal_tx_set_pcp_tid_map_generic_be; 1621 hal_soc->ops->hal_tx_update_pcp_tid_map = 1622 hal_tx_update_pcp_tid_generic_be; 1623 hal_soc->ops->hal_tx_set_tidmap_prty = 1624 hal_tx_update_tidmap_prty_generic_be; 1625 hal_soc->ops->hal_rx_get_rx_fragment_number = 1626 hal_rx_get_rx_fragment_number_be, 1627 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = 1628 hal_rx_tlv_da_is_mcbc_get_be; 1629 hal_soc->ops->hal_rx_msdu_end_is_tkip_mic_err = 1630 hal_rx_tlv_is_tkip_mic_err_get_be; 1631 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = 1632 hal_rx_tlv_sa_is_valid_get_be; 1633 hal_soc->ops->hal_rx_msdu_end_sa_idx_get = hal_rx_tlv_sa_idx_get_be; 1634 hal_soc->ops->hal_rx_desc_is_first_msdu = hal_rx_desc_is_first_msdu_be; 1635 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get = 1636 hal_rx_tlv_l3_hdr_padding_get_be; 1637 hal_soc->ops->hal_rx_encryption_info_valid = 1638 hal_rx_encryption_info_valid_be; 1639 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_be; 1640 hal_soc->ops->hal_rx_msdu_end_first_msdu_get = 1641 hal_rx_tlv_first_msdu_get_be; 1642 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = 1643 hal_rx_tlv_da_is_valid_get_be; 1644 hal_soc->ops->hal_rx_msdu_end_last_msdu_get = 1645 hal_rx_tlv_last_msdu_get_be; 1646 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = 1647 hal_rx_get_mpdu_mac_ad4_valid_be; 1648 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get = 1649 hal_rx_mpdu_start_sw_peer_id_get_be; 1650 hal_soc->ops->hal_rx_tlv_peer_meta_data_get = 1651 hal_rx_msdu_peer_meta_data_get_be; 1652 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_be; 1653 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_be; 1654 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid = 1655 hal_rx_get_mpdu_frame_control_valid_be; 1656 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_be; 1657 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_be; 1658 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_be; 1659 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid = 1660 hal_rx_get_mpdu_sequence_control_valid_be; 1661 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_be; 1662 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_be; 1663 hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get = 1664 hal_rx_mpdu_start_mpdu_qos_control_valid_get_be; 1665 hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get = 1666 hal_rx_msdu_end_sa_sw_peer_id_get_be; 1667 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = 1668 hal_rx_msdu0_buffer_addr_lsb_9224; 1669 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = 1670 hal_rx_msdu_desc_info_ptr_get_9224; 1671 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_9224; 1672 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_9224; 1673 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_be; 1674 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_be; 1675 hal_soc->ops->hal_rx_get_mac_addr2_valid = 1676 hal_rx_get_mac_addr2_valid_be; 1677 hal_soc->ops->hal_reo_config = hal_reo_config_9224; 1678 hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_be; 1679 hal_soc->ops->hal_rx_msdu_flow_idx_invalid = 1680 hal_rx_msdu_flow_idx_invalid_be; 1681 hal_soc->ops->hal_rx_msdu_flow_idx_timeout = 1682 hal_rx_msdu_flow_idx_timeout_be; 1683 hal_soc->ops->hal_rx_msdu_fse_metadata_get = 1684 hal_rx_msdu_fse_metadata_get_be; 1685 hal_soc->ops->hal_rx_msdu_cce_match_get = 1686 hal_rx_msdu_cce_match_get_be; 1687 hal_soc->ops->hal_rx_msdu_cce_metadata_get = 1688 hal_rx_msdu_cce_metadata_get_be; 1689 hal_soc->ops->hal_rx_msdu_get_flow_params = 1690 hal_rx_msdu_get_flow_params_be; 1691 hal_soc->ops->hal_rx_tlv_get_tcp_chksum = hal_rx_tlv_get_tcp_chksum_be; 1692 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_be; 1693 1694 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) 1695 hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_9224; 1696 hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_9224; 1697 #else 1698 hal_soc->ops->hal_rx_get_bb_info = NULL; 1699 hal_soc->ops->hal_rx_get_rtt_info = NULL; 1700 #endif 1701 1702 /* rx - msdu fast path info fields */ 1703 hal_soc->ops->hal_rx_msdu_packet_metadata_get = 1704 hal_rx_msdu_packet_metadata_get_generic_be; 1705 hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid = 1706 hal_rx_mpdu_start_tlv_tag_valid_be; 1707 hal_soc->ops->hal_rx_wbm_err_msdu_continuation_get = 1708 hal_rx_wbm_err_msdu_continuation_get_9224; 1709 1710 /* rx - TLV struct offsets */ 1711 hal_soc->ops->hal_rx_msdu_end_offset_get = 1712 hal_rx_msdu_end_offset_get_generic; 1713 hal_soc->ops->hal_rx_mpdu_start_offset_get = 1714 hal_rx_mpdu_start_offset_get_generic; 1715 #ifndef NO_RX_PKT_HDR_TLV 1716 hal_soc->ops->hal_rx_pkt_tlv_offset_get = 1717 hal_rx_pkt_tlv_offset_get_generic; 1718 #endif 1719 hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_9224; 1720 1721 hal_soc->ops->hal_rx_flow_get_tuple_info = 1722 hal_rx_flow_get_tuple_info_be; 1723 hal_soc->ops->hal_rx_flow_delete_entry = 1724 hal_rx_flow_delete_entry_be; 1725 hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_be; 1726 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = 1727 hal_compute_reo_remap_ix2_ix3_9224; 1728 1729 hal_soc->ops->hal_rx_msdu_get_reo_destination_indication = 1730 hal_rx_msdu_get_reo_destination_indication_be; 1731 hal_soc->ops->hal_rx_get_tlv_size = hal_rx_get_tlv_size_generic_be; 1732 hal_soc->ops->hal_rx_msdu_is_wlan_mcast = 1733 hal_rx_msdu_is_wlan_mcast_generic_be; 1734 hal_soc->ops->hal_tx_get_num_tcl_banks = hal_tx_get_num_tcl_banks_9224; 1735 hal_soc->ops->hal_rx_tlv_decap_format_get = 1736 hal_rx_tlv_decap_format_get_be; 1737 #ifdef RECEIVE_OFFLOAD 1738 hal_soc->ops->hal_rx_tlv_get_offload_info = 1739 hal_rx_tlv_get_offload_info_be; 1740 hal_soc->ops->hal_rx_get_proto_params = hal_rx_get_proto_params_be; 1741 hal_soc->ops->hal_rx_get_l3_l4_offsets = hal_rx_get_l3_l4_offsets_be; 1742 #endif 1743 hal_soc->ops->hal_rx_tlv_msdu_done_get = 1744 hal_rx_tlv_msdu_done_copy_get_9224; 1745 hal_soc->ops->hal_rx_tlv_msdu_len_get = 1746 hal_rx_msdu_start_msdu_len_get_be; 1747 hal_soc->ops->hal_rx_get_frame_ctrl_field = 1748 hal_rx_get_frame_ctrl_field_be; 1749 hal_soc->ops->hal_rx_tlv_csum_err_get = hal_rx_tlv_csum_err_get_be; 1750 #ifndef CONFIG_WORD_BASED_TLV 1751 hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get = 1752 hal_rx_mpdu_info_ampdu_flag_get_be; 1753 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_be; 1754 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = 1755 hal_rx_hw_desc_get_ppduid_get_be; 1756 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_be; 1757 hal_soc->ops->hal_rx_tlv_phy_ppdu_id_get = 1758 hal_rx_attn_phy_ppdu_id_get_be; 1759 hal_soc->ops->hal_rx_get_filter_category = 1760 hal_rx_get_filter_category_be; 1761 #endif 1762 hal_soc->ops->hal_rx_tlv_msdu_len_set = 1763 hal_rx_msdu_start_msdu_len_set_be; 1764 hal_soc->ops->hal_rx_tlv_sgi_get = hal_rx_tlv_sgi_get_be; 1765 hal_soc->ops->hal_rx_tlv_rate_mcs_get = hal_rx_tlv_rate_mcs_get_be; 1766 hal_soc->ops->hal_rx_tlv_bw_get = hal_rx_tlv_bw_get_be; 1767 hal_soc->ops->hal_rx_tlv_get_pkt_type = hal_rx_tlv_get_pkt_type_be; 1768 hal_soc->ops->hal_rx_tlv_mic_err_get = hal_rx_tlv_mic_err_get_be; 1769 hal_soc->ops->hal_rx_tlv_decrypt_err_get = 1770 hal_rx_tlv_decrypt_err_get_be; 1771 hal_soc->ops->hal_rx_tlv_first_mpdu_get = hal_rx_tlv_first_mpdu_get_be; 1772 hal_soc->ops->hal_rx_tlv_get_is_decrypted = 1773 hal_rx_tlv_get_is_decrypted_be; 1774 hal_soc->ops->hal_rx_msdu_get_keyid = hal_rx_msdu_get_keyid_be; 1775 hal_soc->ops->hal_rx_tlv_get_freq = hal_rx_tlv_get_freq_be; 1776 hal_soc->ops->hal_rx_priv_info_set_in_tlv = 1777 hal_rx_priv_info_set_in_tlv_be; 1778 hal_soc->ops->hal_rx_priv_info_get_from_tlv = 1779 hal_rx_priv_info_get_from_tlv_be; 1780 hal_soc->ops->hal_rx_pkt_hdr_get = hal_rx_pkt_hdr_get_be; 1781 hal_soc->ops->hal_reo_setup = hal_reo_setup_9224; 1782 hal_soc->ops->hal_reo_config_reo2ppe_dest_info = NULL; 1783 #ifdef REO_SHARED_QREF_TABLE_EN 1784 hal_soc->ops->hal_reo_shared_qaddr_setup = hal_reo_shared_qaddr_setup_be; 1785 hal_soc->ops->hal_reo_shared_qaddr_init = hal_reo_shared_qaddr_init_be; 1786 hal_soc->ops->hal_reo_shared_qaddr_detach = hal_reo_shared_qaddr_detach_be; 1787 hal_soc->ops->hal_reo_shared_qaddr_write = hal_reo_shared_qaddr_write_be; 1788 hal_soc->ops->hal_reo_shared_qaddr_cache_clear = hal_reo_shared_qaddr_cache_clear_be; 1789 #endif 1790 /* Overwrite the default BE ops */ 1791 hal_soc->ops->hal_get_rx_max_ba_window = 1792 hal_get_rx_max_ba_window_qcn9224; 1793 hal_soc->ops->hal_get_reo_qdesc_size = hal_qcn9224_get_reo_qdesc_size; 1794 /* TX MONITOR */ 1795 #ifdef WLAN_PKT_CAPTURE_TX_2_0 1796 hal_soc->ops->hal_txmon_is_mon_buf_addr_tlv = 1797 hal_txmon_is_mon_buf_addr_tlv_generic_be; 1798 hal_soc->ops->hal_txmon_populate_packet_info = 1799 hal_txmon_populate_packet_info_generic_be; 1800 hal_soc->ops->hal_txmon_status_parse_tlv = 1801 hal_txmon_status_parse_tlv_generic_be; 1802 hal_soc->ops->hal_txmon_status_get_num_users = 1803 hal_txmon_status_get_num_users_generic_be; 1804 #if defined(TX_MONITOR_WORD_MASK) 1805 hal_soc->ops->hal_txmon_get_word_mask = 1806 hal_txmon_get_word_mask_qcn9224; 1807 #else 1808 hal_soc->ops->hal_txmon_get_word_mask = 1809 hal_txmon_get_word_mask_generic_be; 1810 #endif /* TX_MONITOR_WORD_MASK */ 1811 #endif /* WLAN_PKT_CAPTURE_TX_2_0 */ 1812 hal_soc->ops->hal_compute_reo_remap_ix0 = NULL; 1813 hal_soc->ops->hal_tx_vdev_mismatch_routing_set = 1814 hal_tx_vdev_mismatch_routing_set_generic_be; 1815 hal_soc->ops->hal_tx_mcast_mlo_reinject_routing_set = 1816 hal_tx_mcast_mlo_reinject_routing_set_generic_be; 1817 hal_soc->ops->hal_get_ba_aging_timeout = 1818 hal_get_ba_aging_timeout_be_generic; 1819 hal_soc->ops->hal_setup_link_idle_list = 1820 hal_setup_link_idle_list_generic_be; 1821 hal_soc->ops->hal_cookie_conversion_reg_cfg_be = 1822 hal_cookie_conversion_reg_cfg_generic_be; 1823 hal_soc->ops->hal_set_ba_aging_timeout = 1824 hal_set_ba_aging_timeout_be_generic; 1825 hal_soc->ops->hal_tx_populate_bank_register = 1826 hal_tx_populate_bank_register_be; 1827 hal_soc->ops->hal_tx_vdev_mcast_ctrl_set = 1828 hal_tx_vdev_mcast_ctrl_set_be; 1829 #ifdef CONFIG_WORD_BASED_TLV 1830 hal_soc->ops->hal_rx_mpdu_start_wmask_get = 1831 hal_rx_mpdu_start_wmask_get_be; 1832 hal_soc->ops->hal_rx_msdu_end_wmask_get = 1833 hal_rx_msdu_end_wmask_get_be; 1834 #endif 1835 hal_soc->ops->hal_get_tsf2_scratch_reg = 1836 hal_get_tsf2_scratch_reg_qcn9224; 1837 hal_soc->ops->hal_get_tqm_scratch_reg = 1838 hal_get_tqm_scratch_reg_qcn9224; 1839 hal_soc->ops->hal_tx_ring_halt_set = hal_tx_ppe2tcl_ring_halt_set_9224; 1840 hal_soc->ops->hal_tx_ring_halt_reset = 1841 hal_tx_ppe2tcl_ring_halt_reset_9224; 1842 hal_soc->ops->hal_tx_ring_halt_poll = 1843 hal_tx_ppe2tcl_ring_halt_done_9224; 1844 hal_soc->ops->hal_tx_get_num_ppe_vp_search_idx_tbl_entries = 1845 hal_tx_get_num_ppe_vp_search_idx_reg_entries_9224; 1846 hal_soc->ops->hal_tx_ring_halt_get = hal_tx_ppe2tcl_ring_halt_get_9224; 1847 }; 1848 1849 /** 1850 * hal_srng_hw_reg_offset_init_qcn9224() - Initialize the HW srng reg offset 1851 * applicable only for QCN9224 1852 * @hal_soc: HAL Soc handle 1853 * 1854 * Return: None 1855 */ 1856 static inline void hal_srng_hw_reg_offset_init_qcn9224(struct hal_soc *hal_soc) 1857 { 1858 int32_t *hw_reg_offset = hal_soc->hal_hw_reg_offset; 1859 1860 hw_reg_offset[DST_MSI2_BASE_LSB] = REG_OFFSET(DST, MSI2_BASE_LSB), 1861 hw_reg_offset[DST_MSI2_BASE_MSB] = REG_OFFSET(DST, MSI2_BASE_MSB), 1862 hw_reg_offset[DST_MSI2_DATA] = REG_OFFSET(DST, MSI2_DATA), 1863 hw_reg_offset[DST_PRODUCER_INT2_SETUP] = 1864 REG_OFFSET(DST, PRODUCER_INT2_SETUP); 1865 } 1866