1 /* 2 * Copyright (c) 2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 #include "qdf_types.h" 20 #include "qdf_util.h" 21 #include "qdf_mem.h" 22 #include "qdf_nbuf.h" 23 #include "qdf_module.h" 24 25 #include "target_type.h" 26 #include "wcss_version.h" 27 28 #include "hal_be_hw_headers.h" 29 #include "hal_internal.h" 30 #include "hal_api.h" 31 #include "hal_flow.h" 32 #include "rx_flow_search_entry.h" 33 #include "hal_rx_flow_info.h" 34 #include "hal_be_api.h" 35 #include "tcl_entrance_from_ppe_ring.h" 36 #include "sw_monitor_ring.h" 37 #include "wcss_seq_hwioreg_umac.h" 38 #include "wfss_ce_reg_seq_hwioreg.h" 39 #include <uniform_reo_status_header.h> 40 #include <wbm_release_ring_tx.h> 41 #include <phyrx_location.h> 42 #ifdef QCA_MONITOR_2_0_SUPPORT 43 #include <mon_ingress_ring.h> 44 #include <mon_destination_ring.h> 45 #endif 46 #include "rx_reo_queue_1k.h" 47 48 #include <hal_be_rx.h> 49 50 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 51 RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 52 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 53 RX_MSDU_LINK_MSDU_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 54 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 55 RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 56 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 57 RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 58 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 59 REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 60 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER \ 61 STATUS_HEADER_REO_STATUS_NUMBER 62 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 63 STATUS_HEADER_TIMESTAMP 64 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 65 RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 66 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 67 RX_MSDU_LINK_MSDU_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 68 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 69 TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 70 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 71 TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 72 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 73 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_OFFSET 74 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 75 BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 76 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 77 BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 78 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 79 BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB 80 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 81 BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK 82 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 83 BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 84 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 85 BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 86 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 87 BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB 88 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 89 BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK 90 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 91 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_LSB 92 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 93 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MASK 94 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 95 WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 96 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 97 WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 98 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 99 WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 100 101 #include "hal_be_api_mon.h" 102 103 #ifdef CONFIG_WIFI_EMULATION_WIFI_3_0 104 #define CMEM_REG_BASE 0x0010e000 105 106 #define CMEM_WINDOW_ADDRESS_9224 \ 107 ((CMEM_REG_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) 108 #endif 109 110 #define CE_WINDOW_ADDRESS_9224 \ 111 ((CE_WFSS_CE_REG_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) 112 113 #define UMAC_WINDOW_ADDRESS_9224 \ 114 ((UMAC_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) 115 116 #ifdef CONFIG_WIFI_EMULATION_WIFI_3_0 117 #define WINDOW_CONFIGURATION_VALUE_9224 \ 118 ((CE_WINDOW_ADDRESS_9224 << 6) |\ 119 (UMAC_WINDOW_ADDRESS_9224 << 12) | \ 120 CMEM_WINDOW_ADDRESS_9224 | \ 121 WINDOW_ENABLE_BIT) 122 #else 123 #define WINDOW_CONFIGURATION_VALUE_9224 \ 124 ((CE_WINDOW_ADDRESS_9224 << 6) |\ 125 (UMAC_WINDOW_ADDRESS_9224 << 12) | \ 126 WINDOW_ENABLE_BIT) 127 #endif 128 129 /* For Berryllium sw2rxdma ring size increased to 20 bits */ 130 #define HAL_RXDMA_MAX_RING_SIZE_BE 0xFFFFF 131 132 #ifdef CONFIG_WORD_BASED_TLV 133 #ifndef BIG_ENDIAN_HOST 134 struct rx_msdu_end_compact_qca9224 { 135 uint32_t rxpcu_mpdu_filter_in_category : 2, // [1:0] 136 sw_frame_group_id : 7, // [8:2] 137 reserved_0 : 7, // [15:9] 138 phy_ppdu_id : 16; // [31:16] 139 uint32_t ip_hdr_chksum : 16, // [15:0] 140 reported_mpdu_length : 14, // [29:16] 141 reserved_1a : 2; // [31:30] 142 uint32_t key_id_octet : 8, // [7:0] 143 cce_super_rule : 6, // [13:8] 144 cce_classify_not_done_truncate : 1, // [14:14] 145 cce_classify_not_done_cce_dis : 1, // [15:15] 146 cumulative_l3_checksum : 16; // [31:16] 147 uint32_t rule_indication_31_0 : 32; // [31:0] 148 uint32_t rule_indication_63_32 : 32; // [31:0] 149 uint32_t da_offset : 6, // [5:0] 150 sa_offset : 6, // [11:6] 151 da_offset_valid : 1, // [12:12] 152 sa_offset_valid : 1, // [13:13] 153 reserved_5a : 2, // [15:14] 154 l3_type : 16; // [31:16] 155 uint32_t ipv6_options_crc : 32; // [31:0] 156 uint32_t tcp_seq_number : 32; // [31:0] 157 uint32_t tcp_ack_number : 32; // [31:0] 158 uint32_t tcp_flag : 9, // [8:0] 159 lro_eligible : 1, // [9:9] 160 reserved_9a : 6, // [15:10] 161 window_size : 16; // [31:16] 162 uint32_t tcp_udp_chksum : 16, // [15:0] 163 sa_idx_timeout : 1, // [16:16] 164 da_idx_timeout : 1, // [17:17] 165 msdu_limit_error : 1, // [18:18] 166 flow_idx_timeout : 1, // [19:19] 167 flow_idx_invalid : 1, // [20:20] 168 wifi_parser_error : 1, // [21:21] 169 amsdu_parser_error : 1, // [22:22] 170 sa_is_valid : 1, // [23:23] 171 da_is_valid : 1, // [24:24] 172 da_is_mcbc : 1, // [25:25] 173 l3_header_padding : 2, // [27:26] 174 first_msdu : 1, // [28:28] 175 last_msdu : 1, // [29:29] 176 tcp_udp_chksum_fail_copy : 1, // [30:30] 177 ip_chksum_fail_copy : 1; // [31:31] 178 uint32_t sa_idx : 16, // [15:0] 179 da_idx_or_sw_peer_id : 16; // [31:16] 180 uint32_t msdu_drop : 1, // [0:0] 181 reo_destination_indication : 5, // [5:1] 182 flow_idx : 20, // [25:6] 183 use_ppe : 1, // [26:26] 184 reserved_12a : 5; // [31:27] 185 uint32_t fse_metadata : 32; // [31:0] 186 uint32_t cce_metadata : 16, // [15:0] 187 sa_sw_peer_id : 16; // [31:16] 188 uint32_t aggregation_count : 8, // [7:0] 189 flow_aggregation_continuation : 1, // [8:8] 190 fisa_timeout : 1, // [9:9] 191 reserved_15a : 22; // [31:10] 192 uint32_t cumulative_l4_checksum : 16, // [15:0] 193 cumulative_ip_length : 16; // [31:16] 194 uint32_t reserved_17a : 6, // [5:0] 195 service_code : 9, // [14:6] 196 priority_valid : 1, // [15:15] 197 intra_bss : 1, // [16:16] 198 dest_chip_id : 2, // [18:17] 199 multicast_echo : 1, // [19:19] 200 wds_learning_event : 1, // [20:20] 201 wds_roaming_event : 1, // [21:21] 202 wds_keep_alive_event : 1, // [22:22] 203 reserved_17b : 9; // [31:23] 204 uint32_t msdu_length : 14, // [13:0] 205 stbc : 1, // [14:14] 206 ipsec_esp : 1, // [15:15] 207 l3_offset : 7, // [22:16] 208 ipsec_ah : 1, // [23:23] 209 l4_offset : 8; // [31:24] 210 uint32_t msdu_number : 8, // [7:0] 211 decap_format : 2, // [9:8] 212 ipv4_proto : 1, // [10:10] 213 ipv6_proto : 1, // [11:11] 214 tcp_proto : 1, // [12:12] 215 udp_proto : 1, // [13:13] 216 ip_frag : 1, // [14:14] 217 tcp_only_ack : 1, // [15:15] 218 da_is_bcast_mcast : 1, // [16:16] 219 toeplitz_hash_sel : 2, // [18:17] 220 ip_fixed_header_valid : 1, // [19:19] 221 ip_extn_header_valid : 1, // [20:20] 222 tcp_udp_header_valid : 1, // [21:21] 223 mesh_control_present : 1, // [22:22] 224 ldpc : 1, // [23:23] 225 ip4_protocol_ip6_next_header : 8; // [31:24] 226 uint32_t toeplitz_hash_2_or_4 : 32; // [31:0] 227 uint32_t flow_id_toeplitz : 32; // [31:0] 228 uint32_t user_rssi : 8, // [7:0] 229 pkt_type : 4, // [11:8] 230 sgi : 2, // [13:12] 231 rate_mcs : 4, // [17:14] 232 receive_bandwidth : 3, // [20:18] 233 reception_type : 3, // [23:21] 234 mimo_ss_bitmap : 8; // [31:24] 235 uint32_t ppdu_start_timestamp_31_0 : 32; // [31:0] 236 uint32_t ppdu_start_timestamp_63_32 : 32; // [31:0] 237 uint32_t sw_phy_meta_data : 32; // [31:0] 238 uint32_t vlan_ctag_ci : 16, // [15:0] 239 vlan_stag_ci : 16; // [31:16] 240 uint32_t reserved_27a : 32; // [31:0] 241 uint32_t reserved_28a : 32; // [31:0] 242 uint32_t reserved_29a : 32; // [31:0] 243 uint32_t first_mpdu : 1, // [0:0] 244 reserved_30a : 1, // [1:1] 245 mcast_bcast : 1, // [2:2] 246 ast_index_not_found : 1, // [3:3] 247 ast_index_timeout : 1, // [4:4] 248 power_mgmt : 1, // [5:5] 249 non_qos : 1, // [6:6] 250 null_data : 1, // [7:7] 251 mgmt_type : 1, // [8:8] 252 ctrl_type : 1, // [9:9] 253 more_data : 1, // [10:10] 254 eosp : 1, // [11:11] 255 a_msdu_error : 1, // [12:12] 256 fragment_flag : 1, // [13:13] 257 order : 1, // [14:14] 258 cce_match : 1, // [15:15] 259 overflow_err : 1, // [16:16] 260 msdu_length_err : 1, // [17:17] 261 tcp_udp_chksum_fail : 1, // [18:18] 262 ip_chksum_fail : 1, // [19:19] 263 sa_idx_invalid : 1, // [20:20] 264 da_idx_invalid : 1, // [21:21] 265 reserved_30b : 1, // [22:22] 266 rx_in_tx_decrypt_byp : 1, // [23:23] 267 encrypt_required : 1, // [24:24] 268 directed : 1, // [25:25] 269 buffer_fragment : 1, // [26:26] 270 mpdu_length_err : 1, // [27:27] 271 tkip_mic_err : 1, // [28:28] 272 decrypt_err : 1, // [29:29] 273 unencrypted_frame_err : 1, // [30:30] 274 fcs_err : 1; // [31:31] 275 uint32_t reserved_31a : 10, // [9:0] 276 decrypt_status_code : 3, // [12:10] 277 rx_bitmap_not_updated : 1, // [13:13] 278 reserved_31b : 17, // [30:14] 279 msdu_done : 1; // [31:31] 280 281 }; 282 283 struct rx_mpdu_start_compact_qca9224 { 284 struct rxpt_classify_info rxpt_classify_info_details; 285 uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0] 286 uint32_t rx_reo_queue_desc_addr_39_32 : 8, // [7:0] 287 receive_queue_number : 16, // [23:8] 288 pre_delim_err_warning : 1, // [24:24] 289 first_delim_err : 1, // [25:25] 290 reserved_2a : 6; // [31:26] 291 uint32_t pn_31_0 : 32; // [31:0] 292 uint32_t pn_63_32 : 32; // [31:0] 293 uint32_t pn_95_64 : 32; // [31:0] 294 uint32_t pn_127_96 : 32; // [31:0] 295 uint32_t epd_en : 1, // [0:0] 296 all_frames_shall_be_encrypted : 1, // [1:1] 297 encrypt_type : 4, // [5:2] 298 wep_key_width_for_variable_key : 2, // [7:6] 299 mesh_sta : 2, // [9:8] 300 bssid_hit : 1, // [10:10] 301 bssid_number : 4, // [14:11] 302 tid : 4, // [18:15] 303 reserved_7a : 13; // [31:19] 304 uint32_t peer_meta_data : 32; // [31:0] 305 uint32_t rxpcu_mpdu_filter_in_category : 2, // [1:0] 306 sw_frame_group_id : 7, // [8:2] 307 ndp_frame : 1, // [9:9] 308 phy_err : 1, // [10:10] 309 phy_err_during_mpdu_header : 1, // [11:11] 310 protocol_version_err : 1, // [12:12] 311 ast_based_lookup_valid : 1, // [13:13] 312 ranging : 1, // [14:14] 313 reserved_9a : 1, // [15:15] 314 phy_ppdu_id : 16; // [31:16] 315 uint32_t ast_index : 16, // [15:0] 316 sw_peer_id : 16; // [31:16] 317 uint32_t mpdu_frame_control_valid : 1, // [0:0] 318 mpdu_duration_valid : 1, // [1:1] 319 mac_addr_ad1_valid : 1, // [2:2] 320 mac_addr_ad2_valid : 1, // [3:3] 321 mac_addr_ad3_valid : 1, // [4:4] 322 mac_addr_ad4_valid : 1, // [5:5] 323 mpdu_sequence_control_valid : 1, // [6:6] 324 mpdu_qos_control_valid : 1, // [7:7] 325 mpdu_ht_control_valid : 1, // [8:8] 326 frame_encryption_info_valid : 1, // [9:9] 327 mpdu_fragment_number : 4, // [13:10] 328 more_fragment_flag : 1, // [14:14] 329 reserved_11a : 1, // [15:15] 330 fr_ds : 1, // [16:16] 331 to_ds : 1, // [17:17] 332 encrypted : 1, // [18:18] 333 mpdu_retry : 1, // [19:19] 334 mpdu_sequence_number : 12; // [31:20] 335 uint32_t key_id_octet : 8, // [7:0] 336 new_peer_entry : 1, // [8:8] 337 decrypt_needed : 1, // [9:9] 338 decap_type : 2, // [11:10] 339 rx_insert_vlan_c_tag_padding : 1, // [12:12] 340 rx_insert_vlan_s_tag_padding : 1, // [13:13] 341 strip_vlan_c_tag_decap : 1, // [14:14] 342 strip_vlan_s_tag_decap : 1, // [15:15] 343 pre_delim_count : 12, // [27:16] 344 ampdu_flag : 1, // [28:28] 345 bar_frame : 1, // [29:29] 346 raw_mpdu : 1, // [30:30] 347 reserved_12 : 1; // [31:31] 348 uint32_t mpdu_length : 14, // [13:0] 349 first_mpdu : 1, // [14:14] 350 mcast_bcast : 1, // [15:15] 351 ast_index_not_found : 1, // [16:16] 352 ast_index_timeout : 1, // [17:17] 353 power_mgmt : 1, // [18:18] 354 non_qos : 1, // [19:19] 355 null_data : 1, // [20:20] 356 mgmt_type : 1, // [21:21] 357 ctrl_type : 1, // [22:22] 358 more_data : 1, // [23:23] 359 eosp : 1, // [24:24] 360 fragment_flag : 1, // [25:25] 361 order : 1, // [26:26] 362 u_apsd_trigger : 1, // [27:27] 363 encrypt_required : 1, // [28:28] 364 directed : 1, // [29:29] 365 amsdu_present : 1, // [30:30] 366 reserved_13 : 1; // [31:31] 367 uint32_t mpdu_frame_control_field : 16, // [15:0] 368 mpdu_duration_field : 16; // [31:16] 369 uint32_t mac_addr_ad1_31_0 : 32; // [31:0] 370 uint32_t mac_addr_ad1_47_32 : 16, // [15:0] 371 mac_addr_ad2_15_0 : 16; // [31:16] 372 uint32_t mac_addr_ad2_47_16 : 32; // [31:0] 373 uint32_t mac_addr_ad3_31_0 : 32; // [31:0] 374 uint32_t mac_addr_ad3_47_32 : 16, // [15:0] 375 mpdu_sequence_control_field : 16; // [31:16] 376 uint32_t mac_addr_ad4_31_0 : 32; // [31:0] 377 uint32_t mac_addr_ad4_47_32 : 16, // [15:0] 378 mpdu_qos_control_field : 16; // [31:16] 379 uint32_t mpdu_ht_control_field : 32; // [31:0] 380 uint32_t vdev_id : 8, // [7:0] 381 service_code : 9, // [16:8] 382 priority_valid : 1, // [17:17] 383 src_info : 12, // [29:18] 384 reserved_23a : 1, // [30:30] 385 multi_link_addr_ad1_ad2_valid : 1; // [31:31] 386 uint32_t multi_link_addr_ad1_31_0 : 32; // [31:0] 387 uint32_t multi_link_addr_ad1_47_32 : 16, // [15:0] 388 multi_link_addr_ad2_15_0 : 16; // [31:16] 389 uint32_t multi_link_addr_ad2_47_16 : 32; // [31:0] 390 uint32_t reserved_27a : 32; // [31:0] 391 uint32_t reserved_28a : 32; // [31:0] 392 uint32_t reserved_29a : 32; // [31:0] 393 }; 394 #else 395 struct rx_msdu_end_compact_qca9224 { 396 uint32_t phy_ppdu_id : 16, // [31:16] 397 reserved_0 : 7, // [15:9] 398 sw_frame_group_id : 7, // [8:2] 399 rxpcu_mpdu_filter_in_category : 2; // [1:0] 400 uint32_t reserved_1a : 2, // [31:30] 401 reported_mpdu_length : 14, // [29:16] 402 ip_hdr_chksum : 16; // [15:0] 403 uint32_t cumulative_l3_checksum : 16, // [31:16] 404 cce_classify_not_done_cce_dis : 1, // [15:15] 405 cce_classify_not_done_truncate : 1, // [14:14] 406 cce_super_rule : 6, // [13:8] 407 key_id_octet : 8; // [7:0] 408 uint32_t rule_indication_31_0 : 32; // [31:0] 409 uint32_t rule_indication_63_32 : 32; // [31:0] 410 uint32_t l3_type : 16, // [31:16] 411 reserved_5a : 2, // [15:14] 412 sa_offset_valid : 1, // [13:13] 413 da_offset_valid : 1, // [12:12] 414 sa_offset : 6, // [11:6] 415 da_offset : 6; // [5:0] 416 uint32_t ipv6_options_crc : 32; // [31:0] 417 uint32_t tcp_seq_number : 32; // [31:0] 418 uint32_t tcp_ack_number : 32; // [31:0] 419 uint32_t window_size : 16, // [31:16] 420 reserved_9a : 6, // [15:10] 421 lro_eligible : 1, // [9:9] 422 tcp_flag : 9; // [8:0] 423 uint32_t ip_chksum_fail_copy : 1, // [31:31] 424 tcp_udp_chksum_fail_copy : 1, // [30:30] 425 last_msdu : 1, // [29:29] 426 first_msdu : 1, // [28:28] 427 l3_header_padding : 2, // [27:26] 428 da_is_mcbc : 1, // [25:25] 429 da_is_valid : 1, // [24:24] 430 sa_is_valid : 1, // [23:23] 431 amsdu_parser_error : 1, // [22:22] 432 wifi_parser_error : 1, // [21:21] 433 flow_idx_invalid : 1, // [20:20] 434 flow_idx_timeout : 1, // [19:19] 435 msdu_limit_error : 1, // [18:18] 436 da_idx_timeout : 1, // [17:17] 437 sa_idx_timeout : 1, // [16:16] 438 tcp_udp_chksum : 16; // [15:0] 439 uint32_t da_idx_or_sw_peer_id : 16, // [31:16] 440 sa_idx : 16; // [15:0] 441 uint32_t reserved_12a : 5, // [31:27] 442 use_ppe : 1, // [26:26] 443 flow_idx : 20, // [25:6] 444 reo_destination_indication : 5, // [5:1] 445 msdu_drop : 1; // [0:0] 446 uint32_t fse_metadata : 32; // [31:0] 447 uint32_t sa_sw_peer_id : 16, // [31:16] 448 cce_metadata : 16; // [15:0] 449 uint32_t reserved_15a : 22, // [31:10] 450 fisa_timeout : 1, // [9:9] 451 flow_aggregation_continuation : 1, // [8:8] 452 aggregation_count : 8; // [7:0] 453 uint32_t cumulative_ip_length : 16, // [31:16] 454 cumulative_l4_checksum : 16; // [15:0] 455 uint32_t reserved_17b : 9, // [31:23] 456 wds_keep_alive_event : 1, // [22:22] 457 wds_roaming_event : 1, // [21:21] 458 wds_learning_event : 1, // [20:20] 459 multicast_echo : 1, // [19:19] 460 dest_chip_id : 2, // [18:17] 461 intra_bss : 1, // [16:16] 462 priority_valid : 1, // [15:15] 463 service_code : 9, // [14:6] 464 reserved_17a : 6; // [5:0] 465 uint32_t l4_offset : 8, // [31:24] 466 ipsec_ah : 1, // [23:23] 467 l3_offset : 7, // [22:16] 468 ipsec_esp : 1, // [15:15] 469 stbc : 1, // [14:14] 470 msdu_length : 14; // [13:0] 471 uint32_t ip4_protocol_ip6_next_header : 8, // [31:24] 472 ldpc : 1, // [23:23] 473 mesh_control_present : 1, // [22:22] 474 tcp_udp_header_valid : 1, // [21:21] 475 ip_extn_header_valid : 1, // [20:20] 476 ip_fixed_header_valid : 1, // [19:19] 477 toeplitz_hash_sel : 2, // [18:17] 478 da_is_bcast_mcast : 1, // [16:16] 479 tcp_only_ack : 1, // [15:15] 480 ip_frag : 1, // [14:14] 481 udp_proto : 1, // [13:13] 482 tcp_proto : 1, // [12:12] 483 ipv6_proto : 1, // [11:11] 484 ipv4_proto : 1, // [10:10] 485 decap_format : 2, // [9:8] 486 msdu_number : 8; // [7:0] 487 uint32_t toeplitz_hash_2_or_4 : 32; // [31:0] 488 uint32_t flow_id_toeplitz : 32; // [31:0] 489 uint32_t mimo_ss_bitmap : 8, // [31:24] 490 reception_type : 3, // [23:21] 491 receive_bandwidth : 3, // [20:18] 492 rate_mcs : 4, // [17:14] 493 sgi : 2, // [13:12] 494 pkt_type : 4, // [11:8] 495 user_rssi : 8; // [7:0] 496 uint32_t ppdu_start_timestamp_31_0 : 32; // [31:0] 497 uint32_t ppdu_start_timestamp_63_32 : 32; // [31:0] 498 uint32_t sw_phy_meta_data : 32; // [31:0] 499 uint32_t vlan_stag_ci : 16, // [31:16] 500 vlan_ctag_ci : 16; // [15:0] 501 uint32_t reserved_27a : 32; // [31:0] 502 uint32_t reserved_28a : 32; // [31:0] 503 uint32_t reserved_29a : 32; // [31:0] 504 uint32_t fcs_err : 1, // [31:31] 505 unencrypted_frame_err : 1, // [30:30] 506 decrypt_err : 1, // [29:29] 507 tkip_mic_err : 1, // [28:28] 508 mpdu_length_err : 1, // [27:27] 509 buffer_fragment : 1, // [26:26] 510 directed : 1, // [25:25] 511 encrypt_required : 1, // [24:24] 512 rx_in_tx_decrypt_byp : 1, // [23:23] 513 reserved_30b : 1, // [22:22] 514 da_idx_invalid : 1, // [21:21] 515 sa_idx_invalid : 1, // [20:20] 516 ip_chksum_fail : 1, // [19:19] 517 tcp_udp_chksum_fail : 1, // [18:18] 518 msdu_length_err : 1, // [17:17] 519 overflow_err : 1, // [16:16] 520 cce_match : 1, // [15:15] 521 order : 1, // [14:14] 522 fragment_flag : 1, // [13:13] 523 a_msdu_error : 1, // [12:12] 524 eosp : 1, // [11:11] 525 more_data : 1, // [10:10] 526 ctrl_type : 1, // [9:9] 527 mgmt_type : 1, // [8:8] 528 null_data : 1, // [7:7] 529 non_qos : 1, // [6:6] 530 power_mgmt : 1, // [5:5] 531 ast_index_timeout : 1, // [4:4] 532 ast_index_not_found : 1, // [3:3] 533 mcast_bcast : 1, // [2:2] 534 reserved_30a : 1, // [1:1] 535 first_mpdu : 1; // [0:0] 536 uint32_t msdu_done : 1, // [31:31] 537 reserved_31b : 17, // [30:14] 538 rx_bitmap_not_updated : 1, // [13:13] 539 decrypt_status_code : 3, // [12:10] 540 reserved_31a : 10; // [9:0] 541 }; 542 543 struct rx_mpdu_start_compact_qca9224 { 544 struct rxpt_classify_info rxpt_classify_info_details; 545 uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0] 546 uint32_t reserved_2a : 6, // [31:26] 547 first_delim_err : 1, // [25:25] 548 pre_delim_err_warning : 1, // [24:24] 549 receive_queue_number : 16, // [23:8] 550 rx_reo_queue_desc_addr_39_32 : 8; // [7:0] 551 uint32_t pn_31_0 : 32; // [31:0] 552 uint32_t pn_63_32 : 32; // [31:0] 553 uint32_t pn_95_64 : 32; // [31:0] 554 uint32_t pn_127_96 : 32; // [31:0] 555 uint32_t reserved_7a : 13, // [31:19] 556 tid : 4, // [18:15] 557 bssid_number : 4, // [14:11] 558 bssid_hit : 1, // [10:10] 559 mesh_sta : 2, // [9:8] 560 wep_key_width_for_variable_key : 2, // [7:6] 561 encrypt_type : 4, // [5:2] 562 all_frames_shall_be_encrypted : 1, // [1:1] 563 epd_en : 1; // [0:0] 564 uint32_t peer_meta_data : 32; // [31:0] 565 uint32_t phy_ppdu_id : 16, // [31:16] 566 reserved_9a : 1, // [15:15] 567 ranging : 1, // [14:14] 568 ast_based_lookup_valid : 1, // [13:13] 569 protocol_version_err : 1, // [12:12] 570 phy_err_during_mpdu_header : 1, // [11:11] 571 phy_err : 1, // [10:10] 572 ndp_frame : 1, // [9:9] 573 sw_frame_group_id : 7, // [8:2] 574 rxpcu_mpdu_filter_in_category : 2; // [1:0] 575 uint32_t sw_peer_id : 16, // [31:16] 576 ast_index : 16; // [15:0] 577 uint32_t mpdu_sequence_number : 12, // [31:20] 578 mpdu_retry : 1, // [19:19] 579 encrypted : 1, // [18:18] 580 to_ds : 1, // [17:17] 581 fr_ds : 1, // [16:16] 582 reserved_11a : 1, // [15:15] 583 more_fragment_flag : 1, // [14:14] 584 mpdu_fragment_number : 4, // [13:10] 585 frame_encryption_info_valid : 1, // [9:9] 586 mpdu_ht_control_valid : 1, // [8:8] 587 mpdu_qos_control_valid : 1, // [7:7] 588 mpdu_sequence_control_valid : 1, // [6:6] 589 mac_addr_ad4_valid : 1, // [5:5] 590 mac_addr_ad3_valid : 1, // [4:4] 591 mac_addr_ad2_valid : 1, // [3:3] 592 mac_addr_ad1_valid : 1, // [2:2] 593 mpdu_duration_valid : 1, // [1:1] 594 mpdu_frame_control_valid : 1; // [0:0] 595 uint32_t reserved_12 : 1, // [31:31] 596 raw_mpdu : 1, // [30:30] 597 bar_frame : 1, // [29:29] 598 ampdu_flag : 1, // [28:28] 599 pre_delim_count : 12, // [27:16] 600 strip_vlan_s_tag_decap : 1, // [15:15] 601 strip_vlan_c_tag_decap : 1, // [14:14] 602 rx_insert_vlan_s_tag_padding : 1, // [13:13] 603 rx_insert_vlan_c_tag_padding : 1, // [12:12] 604 decap_type : 2, // [11:10] 605 decrypt_needed : 1, // [9:9] 606 new_peer_entry : 1, // [8:8] 607 key_id_octet : 8; // [7:0] 608 uint32_t reserved_13 : 1, // [31:31] 609 amsdu_present : 1, // [30:30] 610 directed : 1, // [29:29] 611 encrypt_required : 1, // [28:28] 612 u_apsd_trigger : 1, // [27:27] 613 order : 1, // [26:26] 614 fragment_flag : 1, // [25:25] 615 eosp : 1, // [24:24] 616 more_data : 1, // [23:23] 617 ctrl_type : 1, // [22:22] 618 mgmt_type : 1, // [21:21] 619 null_data : 1, // [20:20] 620 non_qos : 1, // [19:19] 621 power_mgmt : 1, // [18:18] 622 ast_index_timeout : 1, // [17:17] 623 ast_index_not_found : 1, // [16:16] 624 mcast_bcast : 1, // [15:15] 625 first_mpdu : 1, // [14:14] 626 mpdu_length : 14; // [13:0] 627 uint32_t mpdu_duration_field : 16, // [31:16] 628 mpdu_frame_control_field : 16; // [15:0] 629 uint32_t mac_addr_ad1_31_0 : 32; // [31:0] 630 uint32_t mac_addr_ad2_15_0 : 16, // [31:16] 631 mac_addr_ad1_47_32 : 16; // [15:0] 632 uint32_t mac_addr_ad2_47_16 : 32; // [31:0] 633 uint32_t mac_addr_ad3_31_0 : 32; // [31:0] 634 uint32_t mpdu_sequence_control_field : 16, // [31:16] 635 mac_addr_ad3_47_32 : 16; // [15:0] 636 uint32_t mac_addr_ad4_31_0 : 32; // [31:0] 637 uint32_t mpdu_qos_control_field : 16, // [31:16] 638 mac_addr_ad4_47_32 : 16; // [15:0] 639 uint32_t mpdu_ht_control_field : 32; // [31:0] 640 uint32_t multi_link_addr_ad1_ad2_valid : 1, // [31:31] 641 reserved_23a : 1, // [30:30] 642 src_info : 12, // [29:18] 643 priority_valid : 1, // [17:17] 644 service_code : 9, // [16:8] 645 vdev_id : 8; // [7:0] 646 uint32_t multi_link_addr_ad1_31_0 : 32; // [31:0] 647 uint32_t multi_link_addr_ad2_15_0 : 16, // [31:16] 648 multi_link_addr_ad1_47_32 : 16; // [15:0] 649 uint32_t multi_link_addr_ad2_47_16 : 32; // [31:0] 650 uint32_t reserved_27a : 32; // [31:0] 651 uint32_t reserved_28a : 32; // [31:0] 652 uint32_t reserved_29a : 32; // [31:0] 653 }; 654 #endif /* BIG_ENDIAN_HOST */ 655 656 /* TLV struct for word based Tlv */ 657 typedef struct rx_mpdu_start_compact_qca9224 hal_rx_mpdu_start_t; 658 typedef struct rx_msdu_end_compact_qca9224 hal_rx_msdu_end_t; 659 #endif /* CONFIG_WORD_BASED_TLV */ 660 661 #include "hal_9224_rx.h" 662 #include "hal_9224_tx.h" 663 #include "hal_be_rx_tlv.h" 664 #include <hal_be_generic_api.h> 665 666 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 667 #define HAL_PPE_VP_ENTRIES_MAX 32 668 /** 669 * hal_get_link_desc_size_9224(): API to get the link desc size 670 * 671 * Return: uint32_t 672 */ 673 static uint32_t hal_get_link_desc_size_9224(void) 674 { 675 return LINK_DESC_SIZE; 676 } 677 678 /** 679 * hal_rx_get_tlv_9224(): API to get the tlv 680 * 681 * @rx_tlv: TLV data extracted from the rx packet 682 * Return: uint8_t 683 */ 684 static uint8_t hal_rx_get_tlv_9224(void *rx_tlv) 685 { 686 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY, RECEIVE_BANDWIDTH); 687 } 688 689 /** 690 * hal_rx_wbm_err_msdu_continuation_get_9224 () - API to check if WBM 691 * msdu continuation bit is set 692 * 693 *@wbm_desc: wbm release ring descriptor 694 * 695 * Return: true if msdu continuation bit is set. 696 */ 697 static inline 698 uint8_t hal_rx_wbm_err_msdu_continuation_get_9224(void *wbm_desc) 699 { 700 uint32_t comp_desc = *(uint32_t *)(((uint8_t *)wbm_desc) + 701 WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET); 702 703 return (comp_desc & 704 WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK) >> 705 WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB; 706 } 707 708 #if (defined(WLAN_SA_API_ENABLE)) && (defined(QCA_WIFI_QCA9574)) 709 #define HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, evm, pilot) \ 710 (ppdu_info)->evm_info.pilot_evm[pilot] = HAL_RX_GET(rx_tlv, \ 711 PHYRX_OTHER_RECEIVE_INFO, \ 712 SU_EVM_DETAILS_##evm##_PILOT_##pilot##_EVM) 713 714 static inline void 715 hal_rx_update_su_evm_info(void *rx_tlv, 716 void *ppdu_info_hdl) 717 { 718 struct hal_rx_ppdu_info *ppdu_info = 719 (struct hal_rx_ppdu_info *)ppdu_info_hdl; 720 721 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 1, 0); 722 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 2, 1); 723 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 3, 2); 724 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 4, 3); 725 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 5, 4); 726 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 6, 5); 727 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 7, 6); 728 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 8, 7); 729 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 9, 8); 730 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 10, 9); 731 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 11, 10); 732 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 12, 11); 733 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 13, 12); 734 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 14, 13); 735 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 15, 14); 736 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 16, 15); 737 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 17, 16); 738 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 18, 17); 739 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 19, 18); 740 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 20, 19); 741 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 21, 20); 742 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 22, 21); 743 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 23, 22); 744 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 24, 23); 745 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 25, 24); 746 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 26, 25); 747 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 27, 26); 748 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 28, 27); 749 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 29, 28); 750 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 30, 29); 751 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 31, 30); 752 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 32, 31); 753 } 754 755 static void hal_rx_get_evm_info(void *rx_tlv_hdr, void *ppdu_info_hdl) 756 { 757 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 758 void *rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 759 uint32_t tlv_tag; 760 761 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 762 763 switch (tlv_tag) { 764 case WIFIPHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_E: 765 766 /* Skip TLV length to get TLV content */ 767 rx_tlv = (uint8_t *)rx_tlv + HAL_RX_TLV32_HDR_SIZE; 768 769 ppdu_info->evm_info.number_of_symbols = HAL_RX_GET(rx_tlv, 770 PHYRX_OTHER_RECEIVE_INFO, 771 SU_EVM_DETAILS_0_NUMBER_OF_SYMBOLS); 772 ppdu_info->evm_info.pilot_count = HAL_RX_GET(rx_tlv, 773 PHYRX_OTHER_RECEIVE_INFO, 774 SU_EVM_DETAILS_0_PILOT_COUNT); 775 ppdu_info->evm_info.nss_count = HAL_RX_GET(rx_tlv, 776 PHYRX_OTHER_RECEIVE_INFO, 777 SU_EVM_DETAILS_0_NSS_COUNT); 778 hal_rx_update_su_evm_info(rx_tlv, ppdu_info_hdl); 779 break; 780 } 781 } 782 #else /* WLAN_SA_API_ENABLE && QCA_WIFI_QCA9574 */ 783 static void hal_rx_get_evm_info(void *tlv_tag, void *ppdu_info_hdl) 784 { 785 } 786 #endif /* WLAN_SA_API_ENABLE && QCA_WIFI_QCA9574 */ 787 788 /** 789 * hal_rx_proc_phyrx_other_receive_info_tlv_9224(): API to get tlv info 790 * 791 * Return: uint32_t 792 */ 793 static inline 794 void hal_rx_proc_phyrx_other_receive_info_tlv_9224(void *rx_tlv_hdr, 795 void *ppdu_info_hdl) 796 { 797 uint32_t tlv_tag, tlv_len; 798 uint32_t temp_len, other_tlv_len, other_tlv_tag; 799 void *rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 800 void *other_tlv_hdr = NULL; 801 void *other_tlv = NULL; 802 803 /* Get evm info for Smart Antenna */ 804 hal_rx_get_evm_info(rx_tlv_hdr, ppdu_info_hdl); 805 806 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 807 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 808 temp_len = 0; 809 810 other_tlv_hdr = rx_tlv + HAL_RX_TLV32_HDR_SIZE; 811 other_tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(other_tlv_hdr); 812 other_tlv_len = HAL_RX_GET_USER_TLV32_LEN(other_tlv_hdr); 813 814 temp_len += other_tlv_len; 815 other_tlv = other_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 816 817 switch (other_tlv_tag) { 818 default: 819 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 820 "%s unhandled TLV type: %d, TLV len:%d", 821 __func__, other_tlv_tag, other_tlv_len); 822 break; 823 } 824 } 825 826 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) 827 static inline 828 void hal_rx_get_bb_info_9224(void *rx_tlv, void *ppdu_info_hdl) 829 { 830 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 831 832 ppdu_info->cfr_info.bb_captured_channel = 833 HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_CHANNEL); 834 835 ppdu_info->cfr_info.bb_captured_timeout = 836 HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_TIMEOUT); 837 838 ppdu_info->cfr_info.bb_captured_reason = 839 HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_REASON); 840 } 841 842 static inline 843 void hal_rx_get_rtt_info_9224(void *rx_tlv, void *ppdu_info_hdl) 844 { 845 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 846 847 ppdu_info->cfr_info.rx_location_info_valid = 848 HAL_RX_GET_64(rx_tlv, PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 849 RX_LOCATION_INFO_VALID); 850 851 ppdu_info->cfr_info.rtt_che_buffer_pointer_low32 = 852 HAL_RX_GET_64(rx_tlv, 853 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 854 RTT_CHE_BUFFER_POINTER_LOW32); 855 856 ppdu_info->cfr_info.rtt_che_buffer_pointer_high8 = 857 HAL_RX_GET_64(rx_tlv, 858 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 859 RTT_CHE_BUFFER_POINTER_HIGH8); 860 861 ppdu_info->cfr_info.chan_capture_status = 862 HAL_GET_RX_LOCATION_INFO_CHAN_CAPTURE_STATUS(rx_tlv); 863 864 ppdu_info->cfr_info.rx_start_ts = 865 HAL_RX_GET_64(rx_tlv, 866 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 867 RX_START_TS); 868 869 ppdu_info->cfr_info.rtt_cfo_measurement = (int16_t) 870 HAL_RX_GET_64(rx_tlv, 871 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 872 RTT_CFO_MEASUREMENT); 873 874 ppdu_info->cfr_info.agc_gain_info0 = 875 HAL_RX_GET_64(rx_tlv, 876 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 877 GAIN_CHAIN0); 878 879 ppdu_info->cfr_info.agc_gain_info0 |= 880 (((uint32_t)HAL_RX_GET_64(rx_tlv, 881 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 882 GAIN_CHAIN1)) << 16); 883 884 ppdu_info->cfr_info.agc_gain_info1 = 885 HAL_RX_GET_64(rx_tlv, 886 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 887 GAIN_CHAIN2); 888 889 ppdu_info->cfr_info.agc_gain_info1 |= 890 (((uint32_t)HAL_RX_GET_64(rx_tlv, 891 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 892 GAIN_CHAIN3)) << 16); 893 894 ppdu_info->cfr_info.agc_gain_info2 = 0; 895 896 ppdu_info->cfr_info.agc_gain_info3 = 0; 897 898 ppdu_info->cfr_info.mcs_rate = 899 HAL_RX_GET_64(rx_tlv, 900 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 901 RTT_MCS_RATE); 902 ppdu_info->cfr_info.gi_type = 903 HAL_RX_GET_64(rx_tlv, 904 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 905 RTT_GI_TYPE); 906 } 907 #endif 908 909 /** 910 * hal_rx_dump_mpdu_start_tlv_9224: dump RX mpdu_start TLV in structured 911 * human readable format. 912 * @mpdu_start: pointer the rx_attention TLV in pkt. 913 * @dbg_level: log level. 914 * 915 * Return: void 916 */ 917 static inline void hal_rx_dump_mpdu_start_tlv_9224(void *mpdustart, 918 uint8_t dbg_level) 919 { 920 #ifdef CONFIG_WORD_BASED_TLV 921 struct rx_mpdu_start_compact_qca9224 *mpdu_info = 922 (struct rx_mpdu_start_compact_qca9224 *)mpdustart; 923 #else 924 struct rx_mpdu_start *mpdu_start = (struct rx_mpdu_start *)mpdustart; 925 struct rx_mpdu_info *mpdu_info = 926 (struct rx_mpdu_info *)&mpdu_start->rx_mpdu_info_details; 927 #endif 928 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 929 "rx_mpdu_start tlv (1/5) - " 930 "rx_reo_queue_desc_addr_31_0 :%x" 931 "rx_reo_queue_desc_addr_39_32 :%x" 932 "receive_queue_number:%x " 933 "pre_delim_err_warning:%x " 934 "first_delim_err:%x " 935 "reserved_2a:%x " 936 "pn_31_0:%x " 937 "pn_63_32:%x " 938 "pn_95_64:%x " 939 "pn_127_96:%x " 940 "epd_en:%x " 941 "all_frames_shall_be_encrypted :%x" 942 "encrypt_type:%x " 943 "wep_key_width_for_variable_key :%x" 944 "mesh_sta:%x " 945 "bssid_hit:%x " 946 "bssid_number:%x " 947 "tid:%x " 948 "reserved_7a:%x ", 949 mpdu_info->rx_reo_queue_desc_addr_31_0, 950 mpdu_info->rx_reo_queue_desc_addr_39_32, 951 mpdu_info->receive_queue_number, 952 mpdu_info->pre_delim_err_warning, 953 mpdu_info->first_delim_err, 954 mpdu_info->reserved_2a, 955 mpdu_info->pn_31_0, 956 mpdu_info->pn_63_32, 957 mpdu_info->pn_95_64, 958 mpdu_info->pn_127_96, 959 mpdu_info->epd_en, 960 mpdu_info->all_frames_shall_be_encrypted, 961 mpdu_info->encrypt_type, 962 mpdu_info->wep_key_width_for_variable_key, 963 mpdu_info->mesh_sta, 964 mpdu_info->bssid_hit, 965 mpdu_info->bssid_number, 966 mpdu_info->tid, 967 mpdu_info->reserved_7a); 968 969 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 970 "rx_mpdu_start tlv (2/5) - " 971 "ast_index:%x " 972 "sw_peer_id:%x " 973 "mpdu_frame_control_valid:%x " 974 "mpdu_duration_valid:%x " 975 "mac_addr_ad1_valid:%x " 976 "mac_addr_ad2_valid:%x " 977 "mac_addr_ad3_valid:%x " 978 "mac_addr_ad4_valid:%x " 979 "mpdu_sequence_control_valid :%x" 980 "mpdu_qos_control_valid:%x " 981 "mpdu_ht_control_valid:%x " 982 "frame_encryption_info_valid :%x", 983 mpdu_info->ast_index, 984 mpdu_info->sw_peer_id, 985 mpdu_info->mpdu_frame_control_valid, 986 mpdu_info->mpdu_duration_valid, 987 mpdu_info->mac_addr_ad1_valid, 988 mpdu_info->mac_addr_ad2_valid, 989 mpdu_info->mac_addr_ad3_valid, 990 mpdu_info->mac_addr_ad4_valid, 991 mpdu_info->mpdu_sequence_control_valid, 992 mpdu_info->mpdu_qos_control_valid, 993 mpdu_info->mpdu_ht_control_valid, 994 mpdu_info->frame_encryption_info_valid); 995 996 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 997 "rx_mpdu_start tlv (3/5) - " 998 "mpdu_fragment_number:%x " 999 "more_fragment_flag:%x " 1000 "reserved_11a:%x " 1001 "fr_ds:%x " 1002 "to_ds:%x " 1003 "encrypted:%x " 1004 "mpdu_retry:%x " 1005 "mpdu_sequence_number:%x ", 1006 mpdu_info->mpdu_fragment_number, 1007 mpdu_info->more_fragment_flag, 1008 mpdu_info->reserved_11a, 1009 mpdu_info->fr_ds, 1010 mpdu_info->to_ds, 1011 mpdu_info->encrypted, 1012 mpdu_info->mpdu_retry, 1013 mpdu_info->mpdu_sequence_number); 1014 1015 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 1016 "rx_mpdu_start tlv (4/5) - " 1017 "mpdu_frame_control_field:%x " 1018 "mpdu_duration_field:%x ", 1019 mpdu_info->mpdu_frame_control_field, 1020 mpdu_info->mpdu_duration_field); 1021 1022 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 1023 "rx_mpdu_start tlv (5/5) - " 1024 "mac_addr_ad1_31_0:%x " 1025 "mac_addr_ad1_47_32:%x " 1026 "mac_addr_ad2_15_0:%x " 1027 "mac_addr_ad2_47_16:%x " 1028 "mac_addr_ad3_31_0:%x " 1029 "mac_addr_ad3_47_32:%x " 1030 "mpdu_sequence_control_field :%x" 1031 "mac_addr_ad4_31_0:%x " 1032 "mac_addr_ad4_47_32:%x " 1033 "mpdu_qos_control_field:%x ", 1034 mpdu_info->mac_addr_ad1_31_0, 1035 mpdu_info->mac_addr_ad1_47_32, 1036 mpdu_info->mac_addr_ad2_15_0, 1037 mpdu_info->mac_addr_ad2_47_16, 1038 mpdu_info->mac_addr_ad3_31_0, 1039 mpdu_info->mac_addr_ad3_47_32, 1040 mpdu_info->mpdu_sequence_control_field, 1041 mpdu_info->mac_addr_ad4_31_0, 1042 mpdu_info->mac_addr_ad4_47_32, 1043 mpdu_info->mpdu_qos_control_field); 1044 } 1045 1046 /** 1047 * hal_rx_dump_msdu_end_tlv_9224: dump RX msdu_end TLV in structured 1048 * human readable format. 1049 * @ msdu_end: pointer the msdu_end TLV in pkt. 1050 * @ dbg_level: log level. 1051 * 1052 * Return: void 1053 */ 1054 static void hal_rx_dump_msdu_end_tlv_9224(void *msduend, 1055 uint8_t dbg_level) 1056 { 1057 #ifdef CONFIG_WORD_BASED_TLV 1058 struct rx_msdu_end_compact_qca9224 *msdu_end = 1059 (struct rx_msdu_end_compact_qca9224 *)msduend; 1060 #else 1061 struct rx_msdu_end *msdu_end = 1062 (struct rx_msdu_end *)msduend; 1063 #endif 1064 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 1065 "rx_msdu_end tlv - " 1066 "key_id_octet: %d " 1067 "cce_super_rule: %d " 1068 "cce_classify_not_done_truncat: %d " 1069 "cce_classify_not_done_cce_dis: %d " 1070 "rule_indication_31_0: %d " 1071 "tcp_udp_chksum: %d " 1072 "sa_idx_timeout: %d " 1073 "da_idx_timeout: %d " 1074 "msdu_limit_error: %d " 1075 "flow_idx_timeout: %d " 1076 "flow_idx_invalid: %d " 1077 "wifi_parser_error: %d " 1078 "sa_is_valid: %d " 1079 "da_is_valid: %d " 1080 "da_is_mcbc: %d " 1081 "tkip_mic_err: %d " 1082 "l3_header_padding: %d " 1083 "first_msdu: %d " 1084 "last_msdu: %d " 1085 "sa_idx: %d " 1086 "msdu_drop: %d " 1087 "reo_destination_indication: %d " 1088 "flow_idx: %d " 1089 "fse_metadata: %d " 1090 "cce_metadata: %d " 1091 "sa_sw_peer_id: %d ", 1092 msdu_end->key_id_octet, 1093 msdu_end->cce_super_rule, 1094 msdu_end->cce_classify_not_done_truncate, 1095 msdu_end->cce_classify_not_done_cce_dis, 1096 msdu_end->rule_indication_31_0, 1097 msdu_end->tcp_udp_chksum, 1098 msdu_end->sa_idx_timeout, 1099 msdu_end->da_idx_timeout, 1100 msdu_end->msdu_limit_error, 1101 msdu_end->flow_idx_timeout, 1102 msdu_end->flow_idx_invalid, 1103 msdu_end->wifi_parser_error, 1104 msdu_end->sa_is_valid, 1105 msdu_end->da_is_valid, 1106 msdu_end->da_is_mcbc, 1107 msdu_end->tkip_mic_err, 1108 msdu_end->l3_header_padding, 1109 msdu_end->first_msdu, 1110 msdu_end->last_msdu, 1111 msdu_end->sa_idx, 1112 msdu_end->msdu_drop, 1113 msdu_end->reo_destination_indication, 1114 msdu_end->flow_idx, 1115 msdu_end->fse_metadata, 1116 msdu_end->cce_metadata, 1117 msdu_end->sa_sw_peer_id); 1118 } 1119 1120 /** 1121 * hal_reo_status_get_header_9224 - Process reo desc info 1122 * @d - Pointer to reo descriptior 1123 * @b - tlv type info 1124 * @h1 - Pointer to hal_reo_status_header where info to be stored 1125 * 1126 * Return - none. 1127 * 1128 */ 1129 static void hal_reo_status_get_header_9224(hal_ring_desc_t ring_desc, 1130 int b, void *h1) 1131 { 1132 uint64_t *d = (uint64_t *)ring_desc; 1133 uint64_t val1 = 0; 1134 struct hal_reo_status_header *h = 1135 (struct hal_reo_status_header *)h1; 1136 1137 /* Offsets of descriptor fields defined in HW headers start 1138 * from the field after TLV header 1139 */ 1140 d += HAL_GET_NUM_QWORDS(sizeof(struct tlv_32_hdr)); 1141 1142 switch (b) { 1143 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1144 val1 = d[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS, 1145 STATUS_HEADER_REO_STATUS_NUMBER)]; 1146 break; 1147 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1148 val1 = d[HAL_OFFSET_QW(REO_FLUSH_QUEUE_STATUS, 1149 STATUS_HEADER_REO_STATUS_NUMBER)]; 1150 break; 1151 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1152 val1 = d[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS, 1153 STATUS_HEADER_REO_STATUS_NUMBER)]; 1154 break; 1155 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1156 val1 = d[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS, 1157 STATUS_HEADER_REO_STATUS_NUMBER)]; 1158 break; 1159 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1160 val1 = d[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS, 1161 STATUS_HEADER_REO_STATUS_NUMBER)]; 1162 break; 1163 case HAL_REO_DESC_THRES_STATUS_TLV: 1164 val1 = 1165 d[HAL_OFFSET_QW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS, 1166 STATUS_HEADER_REO_STATUS_NUMBER)]; 1167 break; 1168 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1169 val1 = d[HAL_OFFSET_QW(REO_UPDATE_RX_REO_QUEUE_STATUS, 1170 STATUS_HEADER_REO_STATUS_NUMBER)]; 1171 break; 1172 default: 1173 qdf_nofl_err("ERROR: Unknown tlv\n"); 1174 break; 1175 } 1176 h->cmd_num = 1177 HAL_GET_FIELD( 1178 UNIFORM_REO_STATUS_HEADER, REO_STATUS_NUMBER, 1179 val1); 1180 h->exec_time = 1181 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, 1182 CMD_EXECUTION_TIME, val1); 1183 h->status = 1184 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, 1185 REO_CMD_EXECUTION_STATUS, val1); 1186 switch (b) { 1187 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1188 val1 = d[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS, 1189 STATUS_HEADER_TIMESTAMP)]; 1190 break; 1191 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1192 val1 = d[HAL_OFFSET_QW(REO_FLUSH_QUEUE_STATUS, 1193 STATUS_HEADER_TIMESTAMP)]; 1194 break; 1195 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1196 val1 = d[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS, 1197 STATUS_HEADER_TIMESTAMP)]; 1198 break; 1199 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1200 val1 = d[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS, 1201 STATUS_HEADER_TIMESTAMP)]; 1202 break; 1203 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1204 val1 = d[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS, 1205 STATUS_HEADER_TIMESTAMP)]; 1206 break; 1207 case HAL_REO_DESC_THRES_STATUS_TLV: 1208 val1 = 1209 d[HAL_OFFSET_QW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS, 1210 STATUS_HEADER_TIMESTAMP)]; 1211 break; 1212 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1213 val1 = d[HAL_OFFSET_QW(REO_UPDATE_RX_REO_QUEUE_STATUS, 1214 STATUS_HEADER_TIMESTAMP)]; 1215 break; 1216 default: 1217 qdf_nofl_err("ERROR: Unknown tlv\n"); 1218 break; 1219 } 1220 h->tstamp = 1221 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, TIMESTAMP, val1); 1222 } 1223 1224 static 1225 void *hal_rx_msdu0_buffer_addr_lsb_9224(void *link_desc_va) 1226 { 1227 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 1228 } 1229 1230 static 1231 void *hal_rx_msdu_desc_info_ptr_get_9224(void *msdu0) 1232 { 1233 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 1234 } 1235 1236 static 1237 void *hal_ent_mpdu_desc_info_9224(void *ent_ring_desc) 1238 { 1239 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 1240 } 1241 1242 static 1243 void *hal_dst_mpdu_desc_info_9224(void *dst_ring_desc) 1244 { 1245 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 1246 } 1247 1248 /** 1249 * hal_reo_config_9224(): Set reo config parameters 1250 * @soc: hal soc handle 1251 * @reg_val: value to be set 1252 * @reo_params: reo parameters 1253 * 1254 * Return: void 1255 */ 1256 static void 1257 hal_reo_config_9224(struct hal_soc *soc, 1258 uint32_t reg_val, 1259 struct hal_reo_params *reo_params) 1260 { 1261 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 1262 } 1263 1264 /** 1265 * hal_rx_msdu_desc_info_get_ptr_9224() - Get msdu desc info ptr 1266 * @msdu_details_ptr - Pointer to msdu_details_ptr 1267 * 1268 * Return - Pointer to rx_msdu_desc_info structure. 1269 * 1270 */ 1271 static void *hal_rx_msdu_desc_info_get_ptr_9224(void *msdu_details_ptr) 1272 { 1273 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 1274 } 1275 1276 /** 1277 * hal_rx_link_desc_msdu0_ptr_9224 - Get pointer to rx_msdu details 1278 * @link_desc - Pointer to link desc 1279 * 1280 * Return - Pointer to rx_msdu_details structure 1281 * 1282 */ 1283 static void *hal_rx_link_desc_msdu0_ptr_9224(void *link_desc) 1284 { 1285 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 1286 } 1287 1288 /** 1289 * hal_get_window_address_9224(): Function to get hp/tp address 1290 * @hal_soc: Pointer to hal_soc 1291 * @addr: address offset of register 1292 * 1293 * Return: modified address offset of register 1294 */ 1295 1296 static inline qdf_iomem_t hal_get_window_address_9224(struct hal_soc *hal_soc, 1297 qdf_iomem_t addr) 1298 { 1299 uint32_t offset = addr - hal_soc->dev_base_addr; 1300 qdf_iomem_t new_offset; 1301 1302 /* 1303 * If offset lies within DP register range, use 3rd window to write 1304 * into DP region. 1305 */ 1306 if ((offset ^ UMAC_BASE) < WINDOW_RANGE_MASK) { 1307 new_offset = (hal_soc->dev_base_addr + (3 * WINDOW_START) + 1308 (offset & WINDOW_RANGE_MASK)); 1309 /* 1310 * If offset lies within CE register range, use 2nd window to write 1311 * into CE region. 1312 */ 1313 } else if ((offset ^ CE_WFSS_CE_REG_BASE) < WINDOW_RANGE_MASK) { 1314 new_offset = (hal_soc->dev_base_addr + (2 * WINDOW_START) + 1315 (offset & WINDOW_RANGE_MASK)); 1316 } else { 1317 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 1318 "%s: ERROR: Accessing Wrong register\n", __func__); 1319 qdf_assert_always(0); 1320 return 0; 1321 } 1322 return new_offset; 1323 } 1324 1325 static inline void hal_write_window_register(struct hal_soc *hal_soc) 1326 { 1327 /* Write value into window configuration register */ 1328 qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_REG_ADDRESS, 1329 WINDOW_CONFIGURATION_VALUE_9224); 1330 } 1331 1332 static 1333 void hal_compute_reo_remap_ix2_ix3_9224(uint32_t *ring, uint32_t num_rings, 1334 uint32_t *remap1, uint32_t *remap2) 1335 { 1336 switch (num_rings) { 1337 case 1: 1338 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1339 HAL_REO_REMAP_IX2(ring[0], 17) | 1340 HAL_REO_REMAP_IX2(ring[0], 18) | 1341 HAL_REO_REMAP_IX2(ring[0], 19) | 1342 HAL_REO_REMAP_IX2(ring[0], 20) | 1343 HAL_REO_REMAP_IX2(ring[0], 21) | 1344 HAL_REO_REMAP_IX2(ring[0], 22) | 1345 HAL_REO_REMAP_IX2(ring[0], 23); 1346 1347 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1348 HAL_REO_REMAP_IX3(ring[0], 25) | 1349 HAL_REO_REMAP_IX3(ring[0], 26) | 1350 HAL_REO_REMAP_IX3(ring[0], 27) | 1351 HAL_REO_REMAP_IX3(ring[0], 28) | 1352 HAL_REO_REMAP_IX3(ring[0], 29) | 1353 HAL_REO_REMAP_IX3(ring[0], 30) | 1354 HAL_REO_REMAP_IX3(ring[0], 31); 1355 break; 1356 case 2: 1357 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1358 HAL_REO_REMAP_IX2(ring[0], 17) | 1359 HAL_REO_REMAP_IX2(ring[1], 18) | 1360 HAL_REO_REMAP_IX2(ring[1], 19) | 1361 HAL_REO_REMAP_IX2(ring[0], 20) | 1362 HAL_REO_REMAP_IX2(ring[0], 21) | 1363 HAL_REO_REMAP_IX2(ring[1], 22) | 1364 HAL_REO_REMAP_IX2(ring[1], 23); 1365 1366 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1367 HAL_REO_REMAP_IX3(ring[0], 25) | 1368 HAL_REO_REMAP_IX3(ring[1], 26) | 1369 HAL_REO_REMAP_IX3(ring[1], 27) | 1370 HAL_REO_REMAP_IX3(ring[0], 28) | 1371 HAL_REO_REMAP_IX3(ring[0], 29) | 1372 HAL_REO_REMAP_IX3(ring[1], 30) | 1373 HAL_REO_REMAP_IX3(ring[1], 31); 1374 break; 1375 case 3: 1376 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1377 HAL_REO_REMAP_IX2(ring[1], 17) | 1378 HAL_REO_REMAP_IX2(ring[2], 18) | 1379 HAL_REO_REMAP_IX2(ring[0], 19) | 1380 HAL_REO_REMAP_IX2(ring[1], 20) | 1381 HAL_REO_REMAP_IX2(ring[2], 21) | 1382 HAL_REO_REMAP_IX2(ring[0], 22) | 1383 HAL_REO_REMAP_IX2(ring[1], 23); 1384 1385 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) | 1386 HAL_REO_REMAP_IX3(ring[0], 25) | 1387 HAL_REO_REMAP_IX3(ring[1], 26) | 1388 HAL_REO_REMAP_IX3(ring[2], 27) | 1389 HAL_REO_REMAP_IX3(ring[0], 28) | 1390 HAL_REO_REMAP_IX3(ring[1], 29) | 1391 HAL_REO_REMAP_IX3(ring[2], 30) | 1392 HAL_REO_REMAP_IX3(ring[0], 31); 1393 break; 1394 case 4: 1395 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1396 HAL_REO_REMAP_IX2(ring[1], 17) | 1397 HAL_REO_REMAP_IX2(ring[2], 18) | 1398 HAL_REO_REMAP_IX2(ring[3], 19) | 1399 HAL_REO_REMAP_IX2(ring[0], 20) | 1400 HAL_REO_REMAP_IX2(ring[1], 21) | 1401 HAL_REO_REMAP_IX2(ring[2], 22) | 1402 HAL_REO_REMAP_IX2(ring[3], 23); 1403 1404 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1405 HAL_REO_REMAP_IX3(ring[1], 25) | 1406 HAL_REO_REMAP_IX3(ring[2], 26) | 1407 HAL_REO_REMAP_IX3(ring[3], 27) | 1408 HAL_REO_REMAP_IX3(ring[0], 28) | 1409 HAL_REO_REMAP_IX3(ring[1], 29) | 1410 HAL_REO_REMAP_IX3(ring[2], 30) | 1411 HAL_REO_REMAP_IX3(ring[3], 31); 1412 break; 1413 } 1414 } 1415 1416 static 1417 void hal_compute_reo_remap_ix0_9224(struct hal_soc *soc) 1418 { 1419 uint32_t remap0; 1420 1421 remap0 = HAL_REG_READ(soc, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR 1422 (REO_REG_REG_BASE)); 1423 1424 remap0 &= ~(HAL_REO_REMAP_IX0(0xF, 6)); 1425 remap0 |= HAL_REO_REMAP_IX0(REO2PPE_DST_IND, 6); 1426 1427 HAL_REG_WRITE(soc, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR 1428 (REO_REG_REG_BASE), remap0); 1429 1430 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR 0x%x", 1431 HAL_REG_READ(soc, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR 1432 (REO_REG_REG_BASE))); 1433 } 1434 1435 /** 1436 * hal_rx_flow_setup_fse_9224() - Setup a flow search entry in HW FST 1437 * @fst: Pointer to the Rx Flow Search Table 1438 * @table_offset: offset into the table where the flow is to be setup 1439 * @flow: Flow Parameters 1440 * 1441 * Return: Success/Failure 1442 */ 1443 static void * 1444 hal_rx_flow_setup_fse_9224(uint8_t *rx_fst, uint32_t table_offset, 1445 uint8_t *rx_flow) 1446 { 1447 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 1448 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 1449 uint8_t *fse; 1450 bool fse_valid; 1451 1452 if (table_offset >= fst->max_entries) { 1453 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 1454 "HAL FSE table offset %u exceeds max entries %u", 1455 table_offset, fst->max_entries); 1456 return NULL; 1457 } 1458 1459 fse = (uint8_t *)fst->base_vaddr + 1460 (table_offset * HAL_RX_FST_ENTRY_SIZE); 1461 1462 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID); 1463 1464 if (fse_valid) { 1465 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 1466 "HAL FSE %pK already valid", fse); 1467 return NULL; 1468 } 1469 1470 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96) = 1471 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96, 1472 qdf_htonl(flow->tuple_info.src_ip_127_96)); 1473 1474 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64) = 1475 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64, 1476 qdf_htonl(flow->tuple_info.src_ip_95_64)); 1477 1478 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32) = 1479 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32, 1480 qdf_htonl(flow->tuple_info.src_ip_63_32)); 1481 1482 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0) = 1483 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0, 1484 qdf_htonl(flow->tuple_info.src_ip_31_0)); 1485 1486 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96) = 1487 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96, 1488 qdf_htonl(flow->tuple_info.dest_ip_127_96)); 1489 1490 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64) = 1491 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64, 1492 qdf_htonl(flow->tuple_info.dest_ip_95_64)); 1493 1494 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32) = 1495 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32, 1496 qdf_htonl(flow->tuple_info.dest_ip_63_32)); 1497 1498 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0) = 1499 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0, 1500 qdf_htonl(flow->tuple_info.dest_ip_31_0)); 1501 1502 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_PORT); 1503 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_PORT) |= 1504 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_PORT, 1505 (flow->tuple_info.dest_port)); 1506 1507 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_PORT); 1508 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_PORT) |= 1509 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_PORT, 1510 (flow->tuple_info.src_port)); 1511 1512 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL); 1513 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL) |= 1514 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL, 1515 flow->tuple_info.l4_protocol); 1516 1517 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER); 1518 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER) |= 1519 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER, 1520 flow->reo_destination_handler); 1521 1522 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID); 1523 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID) |= 1524 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, VALID, 1); 1525 1526 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, METADATA); 1527 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, METADATA) = 1528 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, METADATA, 1529 flow->fse_metadata); 1530 1531 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_INDICATION); 1532 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_INDICATION) |= 1533 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, 1534 REO_DESTINATION_INDICATION, 1535 flow->reo_destination_indication); 1536 1537 /* Reset all the other fields in FSE */ 1538 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, RESERVED_9); 1539 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_DROP); 1540 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_COUNT); 1541 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_BYTE_COUNT); 1542 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, TIMESTAMP); 1543 1544 return fse; 1545 } 1546 1547 #ifndef NO_RX_PKT_HDR_TLV 1548 /** 1549 * hal_rx_dump_pkt_hdr_tlv: dump RX pkt header TLV in hex format 1550 * @ pkt_hdr_tlv: pointer the pkt_hdr_tlv in pkt. 1551 * @ dbg_level: log level. 1552 * 1553 * Return: void 1554 */ 1555 static inline void hal_rx_dump_pkt_hdr_tlv_9224(struct rx_pkt_tlvs *pkt_tlvs, 1556 uint8_t dbg_level) 1557 { 1558 struct rx_pkt_hdr_tlv *pkt_hdr_tlv = &pkt_tlvs->pkt_hdr_tlv; 1559 1560 hal_verbose_debug("\n---------------\n" 1561 "rx_pkt_hdr_tlv\n" 1562 "---------------\n" 1563 "phy_ppdu_id %llu ", 1564 pkt_hdr_tlv->phy_ppdu_id); 1565 1566 hal_verbose_hex_dump(pkt_hdr_tlv->rx_pkt_hdr, 1567 sizeof(pkt_hdr_tlv->rx_pkt_hdr)); 1568 } 1569 #else 1570 /** 1571 * hal_rx_dump_pkt_hdr_tlv: dump RX pkt header TLV in hex format 1572 * @ pkt_hdr_tlv: pointer the pkt_hdr_tlv in pkt. 1573 * @ dbg_level: log level. 1574 * 1575 * Return: void 1576 */ 1577 static inline void hal_rx_dump_pkt_hdr_tlv_9224(struct rx_pkt_tlvs *pkt_tlvs, 1578 uint8_t dbg_level) 1579 { 1580 } 1581 #endif 1582 1583 /* 1584 * hal_tx_dump_ppe_vp_entry_9224() 1585 * @hal_soc_hdl: HAL SoC handle 1586 * 1587 * Return: void 1588 */ 1589 static inline 1590 void hal_tx_dump_ppe_vp_entry_9224(hal_soc_handle_t hal_soc_hdl) 1591 { 1592 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; 1593 uint32_t reg_addr, reg_val = 0, i; 1594 1595 for (i = 0; i < HAL_PPE_VP_ENTRIES_MAX; i++) { 1596 reg_addr = 1597 HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_ADDR( 1598 MAC_TCL_REG_REG_BASE, 1599 i); 1600 reg_val = HAL_REG_READ(soc, reg_addr); 1601 hal_verbose_debug("%d: 0x%x\n", i, reg_val); 1602 } 1603 } 1604 1605 /** 1606 * hal_rx_dump_pkt_tlvs_9224(): API to print RX Pkt TLVS QCN9224 1607 * @hal_soc_hdl: hal_soc handle 1608 * @buf: pointer the pkt buffer 1609 * @dbg_level: log level 1610 * 1611 * Return: void 1612 */ 1613 #ifdef CONFIG_WORD_BASED_TLV 1614 static void hal_rx_dump_pkt_tlvs_9224(hal_soc_handle_t hal_soc_hdl, 1615 uint8_t *buf, uint8_t dbg_level) 1616 { 1617 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1618 struct rx_msdu_end_compact_qca9224 *msdu_end = 1619 &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1620 struct rx_mpdu_start_compact_qca9224 *mpdu_start = 1621 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1622 1623 hal_rx_dump_msdu_end_tlv_9224(msdu_end, dbg_level); 1624 hal_rx_dump_mpdu_start_tlv_9224(mpdu_start, dbg_level); 1625 hal_rx_dump_pkt_hdr_tlv_9224(pkt_tlvs, dbg_level); 1626 } 1627 #else 1628 static void hal_rx_dump_pkt_tlvs_9224(hal_soc_handle_t hal_soc_hdl, 1629 uint8_t *buf, uint8_t dbg_level) 1630 { 1631 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1632 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1633 struct rx_mpdu_start *mpdu_start = 1634 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1635 1636 hal_rx_dump_msdu_end_tlv_9224(msdu_end, dbg_level); 1637 hal_rx_dump_mpdu_start_tlv_9224(mpdu_start, dbg_level); 1638 hal_rx_dump_pkt_hdr_tlv_9224(pkt_tlvs, dbg_level); 1639 } 1640 #endif 1641 1642 #define HAL_NUM_TCL_BANKS_9224 48 1643 1644 /** 1645 * hal_cmem_write_9224() - function for CMEM buffer writing 1646 * @hal_soc_hdl: HAL SOC handle 1647 * @offset: CMEM address 1648 * @value: value to write 1649 * 1650 * Return: None. 1651 */ 1652 static void hal_cmem_write_9224(hal_soc_handle_t hal_soc_hdl, 1653 uint32_t offset, 1654 uint32_t value) 1655 { 1656 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 1657 1658 pld_reg_write(hal->qdf_dev->dev, offset, value); 1659 } 1660 1661 /** 1662 * hal_tx_get_num_tcl_banks_9224() - Get number of banks in target 1663 * 1664 * Returns: number of bank 1665 */ 1666 static uint8_t hal_tx_get_num_tcl_banks_9224(void) 1667 { 1668 return HAL_NUM_TCL_BANKS_9224; 1669 } 1670 1671 static void hal_reo_setup_9224(struct hal_soc *soc, void *reoparams, 1672 int qref_reset) 1673 { 1674 uint32_t reg_val; 1675 struct hal_reo_params *reo_params = (struct hal_reo_params *)reoparams; 1676 1677 reg_val = HAL_REG_READ(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR( 1678 REO_REG_REG_BASE)); 1679 1680 if (soc->version >= 2) { 1681 struct hal_reo_params *reo_params = reoparams; 1682 1683 reo_params->reo_ref_peer_id_fix_enable = 1; 1684 } 1685 hal_reo_config_9224(soc, reg_val, reo_params); 1686 /* Other ring enable bits and REO_ENABLE will be set by FW */ 1687 1688 /* TODO: Setup destination ring mapping if enabled */ 1689 1690 /* TODO: Error destination ring setting is left to default. 1691 * Default setting is to send all errors to release ring. 1692 */ 1693 1694 /* Set the reo descriptor swap bits in case of BIG endian platform */ 1695 hal_setup_reo_swap(soc); 1696 1697 HAL_REG_WRITE(soc, 1698 HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(REO_REG_REG_BASE), 1699 HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000); 1700 1701 HAL_REG_WRITE(soc, 1702 HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(REO_REG_REG_BASE), 1703 (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000)); 1704 1705 HAL_REG_WRITE(soc, 1706 HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(REO_REG_REG_BASE), 1707 (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000)); 1708 1709 HAL_REG_WRITE(soc, 1710 HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(REO_REG_REG_BASE), 1711 (HAL_DEFAULT_VO_REO_TIMEOUT_MS * 1000)); 1712 1713 /* 1714 * When hash based routing is enabled, routing of the rx packet 1715 * is done based on the following value: 1 _ _ _ _ The last 4 1716 * bits are based on hash[3:0]. This means the possible values 1717 * are 0x10 to 0x1f. This value is used to look-up the 1718 * ring ID configured in Destination_Ring_Ctrl_IX_* register. 1719 * The Destination_Ring_Ctrl_IX_2 and Destination_Ring_Ctrl_IX_3 1720 * registers need to be configured to set-up the 16 entries to 1721 * map the hash values to a ring number. There are 3 bits per 1722 * hash entry – which are mapped as follows: 1723 * 0: TCL, 1:SW1, 2:SW2, * 3:SW3, 4:SW4, 5:Release, 6:FW(WIFI), 1724 * 7: NOT_USED. 1725 */ 1726 if (reo_params->rx_hash_enabled) { 1727 hal_compute_reo_remap_ix0_9224(soc); 1728 1729 HAL_REG_WRITE(soc, 1730 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR 1731 (REO_REG_REG_BASE), reo_params->remap0); 1732 1733 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x", 1734 HAL_REG_READ(soc, 1735 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR( 1736 REO_REG_REG_BASE))); 1737 1738 HAL_REG_WRITE(soc, 1739 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 1740 (REO_REG_REG_BASE), reo_params->remap1); 1741 1742 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x", 1743 HAL_REG_READ(soc, 1744 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR( 1745 REO_REG_REG_BASE))); 1746 1747 HAL_REG_WRITE(soc, 1748 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 1749 (REO_REG_REG_BASE), reo_params->remap2); 1750 1751 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 0x%x", 1752 HAL_REG_READ(soc, 1753 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR( 1754 REO_REG_REG_BASE))); 1755 } 1756 1757 /* TODO: Check if the following registers shoould be setup by host: 1758 * AGING_CONTROL 1759 * HIGH_MEMORY_THRESHOLD 1760 * GLOBAL_LINK_DESC_COUNT_THRESH_IX_0[1,2] 1761 * GLOBAL_LINK_DESC_COUNT_CTRL 1762 */ 1763 1764 hal_reo_shared_qaddr_init((hal_soc_handle_t)soc, qref_reset); 1765 } 1766 1767 static uint16_t hal_get_rx_max_ba_window_qcn9224(int tid) 1768 { 1769 return HAL_RX_BA_WINDOW_1024; 1770 } 1771 1772 /** 1773 * hal_qcn9224_get_reo_qdesc_size()- Get the reo queue descriptor size 1774 * from the give Block-Ack window size 1775 * Return: reo queue descriptor size 1776 */ 1777 static uint32_t hal_qcn9224_get_reo_qdesc_size(uint32_t ba_window_size, int tid) 1778 { 1779 /* Hardcode the ba_window_size to HAL_RX_MAX_BA_WINDOW for 1780 * NON_QOS_TID until HW issues are resolved. 1781 */ 1782 if (tid != HAL_NON_QOS_TID) 1783 ba_window_size = hal_get_rx_max_ba_window_qcn9224(tid); 1784 1785 /* Return descriptor size corresponding to window size of 2 since 1786 * we set ba_window_size to 2 while setting up REO descriptors as 1787 * a WAR to get 2k jump exception aggregates are received without 1788 * a BA session. 1789 */ 1790 if (ba_window_size <= 1) { 1791 if (tid != HAL_NON_QOS_TID) 1792 return sizeof(struct rx_reo_queue) + 1793 sizeof(struct rx_reo_queue_ext); 1794 else 1795 return sizeof(struct rx_reo_queue); 1796 } 1797 1798 if (ba_window_size <= 105) 1799 return sizeof(struct rx_reo_queue) + 1800 sizeof(struct rx_reo_queue_ext); 1801 1802 if (ba_window_size <= 210) 1803 return sizeof(struct rx_reo_queue) + 1804 (2 * sizeof(struct rx_reo_queue_ext)); 1805 1806 if (ba_window_size <= 256) 1807 return sizeof(struct rx_reo_queue) + 1808 (3 * sizeof(struct rx_reo_queue_ext)); 1809 1810 return sizeof(struct rx_reo_queue) + 1811 (10 * sizeof(struct rx_reo_queue_ext)) + 1812 sizeof(struct rx_reo_queue_1k); 1813 } 1814 1815 /* 1816 * hal_tx_dump_ppe_vp_entry_9224() 1817 * @hal_soc_hdl: HAL SoC handle 1818 * 1819 * Return: Number of PPE VP entries 1820 */ 1821 static 1822 uint32_t hal_tx_get_num_ppe_vp_tbl_entries_9224(hal_soc_handle_t hal_soc_hdl) 1823 { 1824 return HAL_PPE_VP_ENTRIES_MAX; 1825 } 1826 1827 /** 1828 * hal_rx_tlv_msdu_done_copy_get_9224() - Get msdu done copy bit from rx_tlv 1829 * 1830 * Returns: msdu done copy bit 1831 */ 1832 static inline uint32_t hal_rx_tlv_msdu_done_copy_get_9224(uint8_t *buf) 1833 { 1834 return HAL_RX_TLV_MSDU_DONE_COPY_GET(buf); 1835 } 1836 1837 static void hal_hw_txrx_ops_attach_qcn9224(struct hal_soc *hal_soc) 1838 { 1839 /* init and setup */ 1840 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic; 1841 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic; 1842 hal_soc->ops->hal_srng_hw_disable = hal_srng_hw_disable_generic; 1843 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic; 1844 hal_soc->ops->hal_get_window_address = hal_get_window_address_9224; 1845 hal_soc->ops->hal_cmem_write = hal_cmem_write_9224; 1846 1847 /* tx */ 1848 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_9224; 1849 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_9224; 1850 hal_soc->ops->hal_tx_comp_get_status = 1851 hal_tx_comp_get_status_generic_be; 1852 hal_soc->ops->hal_tx_init_cmd_credit_ring = 1853 hal_tx_init_cmd_credit_ring_9224; 1854 hal_soc->ops->hal_tx_set_ppe_cmn_cfg = 1855 hal_tx_set_ppe_cmn_config_9224; 1856 hal_soc->ops->hal_tx_set_ppe_vp_entry = 1857 hal_tx_set_ppe_vp_entry_9224; 1858 hal_soc->ops->hal_tx_set_ppe_pri2tid = 1859 hal_tx_set_ppe_pri2tid_map_9224; 1860 hal_soc->ops->hal_tx_update_ppe_pri2tid = 1861 hal_tx_update_ppe_pri2tid_9224; 1862 hal_soc->ops->hal_tx_dump_ppe_vp_entry = 1863 hal_tx_dump_ppe_vp_entry_9224; 1864 hal_soc->ops->hal_tx_get_num_ppe_vp_tbl_entries = 1865 hal_tx_get_num_ppe_vp_tbl_entries_9224; 1866 hal_soc->ops->hal_tx_enable_pri2tid_map = 1867 hal_tx_enable_pri2tid_map_9224; 1868 hal_soc->ops->hal_tx_config_rbm_mapping_be = 1869 hal_tx_config_rbm_mapping_be_9224; 1870 1871 /* rx */ 1872 hal_soc->ops->hal_rx_msdu_start_nss_get = hal_rx_tlv_nss_get_be; 1873 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status = 1874 hal_rx_mon_hw_desc_get_mpdu_status_be; 1875 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_9224; 1876 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv = 1877 hal_rx_proc_phyrx_other_receive_info_tlv_9224; 1878 1879 hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_9224; 1880 hal_soc->ops->hal_rx_dump_mpdu_start_tlv = 1881 hal_rx_dump_mpdu_start_tlv_9224; 1882 hal_soc->ops->hal_rx_dump_pkt_tlvs = hal_rx_dump_pkt_tlvs_9224; 1883 1884 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_9224; 1885 hal_soc->ops->hal_rx_mpdu_start_tid_get = hal_rx_tlv_tid_get_be; 1886 hal_soc->ops->hal_rx_msdu_start_reception_type_get = 1887 hal_rx_tlv_reception_type_get_be; 1888 hal_soc->ops->hal_rx_msdu_end_da_idx_get = 1889 hal_rx_msdu_end_da_idx_get_be; 1890 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = 1891 hal_rx_msdu_desc_info_get_ptr_9224; 1892 hal_soc->ops->hal_rx_link_desc_msdu0_ptr = 1893 hal_rx_link_desc_msdu0_ptr_9224; 1894 hal_soc->ops->hal_reo_status_get_header = 1895 hal_reo_status_get_header_9224; 1896 hal_soc->ops->hal_rx_status_get_tlv_info = 1897 hal_rx_status_get_tlv_info_wrapper_be; 1898 hal_soc->ops->hal_rx_wbm_err_info_get = 1899 hal_rx_wbm_err_info_get_generic_be; 1900 hal_soc->ops->hal_tx_set_pcp_tid_map = 1901 hal_tx_set_pcp_tid_map_generic_be; 1902 hal_soc->ops->hal_tx_update_pcp_tid_map = 1903 hal_tx_update_pcp_tid_generic_be; 1904 hal_soc->ops->hal_tx_set_tidmap_prty = 1905 hal_tx_update_tidmap_prty_generic_be; 1906 hal_soc->ops->hal_rx_get_rx_fragment_number = 1907 hal_rx_get_rx_fragment_number_be, 1908 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = 1909 hal_rx_tlv_da_is_mcbc_get_be; 1910 hal_soc->ops->hal_rx_msdu_end_is_tkip_mic_err = 1911 hal_rx_tlv_is_tkip_mic_err_get_be; 1912 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = 1913 hal_rx_tlv_sa_is_valid_get_be; 1914 hal_soc->ops->hal_rx_msdu_end_sa_idx_get = hal_rx_tlv_sa_idx_get_be; 1915 hal_soc->ops->hal_rx_desc_is_first_msdu = hal_rx_desc_is_first_msdu_be; 1916 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get = 1917 hal_rx_tlv_l3_hdr_padding_get_be; 1918 hal_soc->ops->hal_rx_encryption_info_valid = 1919 hal_rx_encryption_info_valid_be; 1920 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_be; 1921 hal_soc->ops->hal_rx_msdu_end_first_msdu_get = 1922 hal_rx_tlv_first_msdu_get_be; 1923 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = 1924 hal_rx_tlv_da_is_valid_get_be; 1925 hal_soc->ops->hal_rx_msdu_end_last_msdu_get = 1926 hal_rx_tlv_last_msdu_get_be; 1927 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = 1928 hal_rx_get_mpdu_mac_ad4_valid_be; 1929 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get = 1930 hal_rx_mpdu_start_sw_peer_id_get_be; 1931 hal_soc->ops->hal_rx_tlv_peer_meta_data_get = 1932 hal_rx_msdu_peer_meta_data_get_be; 1933 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_be; 1934 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_be; 1935 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid = 1936 hal_rx_get_mpdu_frame_control_valid_be; 1937 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_be; 1938 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_be; 1939 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_be; 1940 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_be; 1941 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid = 1942 hal_rx_get_mpdu_sequence_control_valid_be; 1943 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_be; 1944 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_be; 1945 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = 1946 hal_rx_hw_desc_get_ppduid_get_be; 1947 hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get = 1948 hal_rx_mpdu_start_mpdu_qos_control_valid_get_be; 1949 hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get = 1950 hal_rx_msdu_end_sa_sw_peer_id_get_be; 1951 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = 1952 hal_rx_msdu0_buffer_addr_lsb_9224; 1953 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = 1954 hal_rx_msdu_desc_info_ptr_get_9224; 1955 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_9224; 1956 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_9224; 1957 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_be; 1958 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_be; 1959 hal_soc->ops->hal_rx_get_mac_addr2_valid = 1960 hal_rx_get_mac_addr2_valid_be; 1961 hal_soc->ops->hal_rx_get_filter_category = 1962 hal_rx_get_filter_category_be; 1963 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_be; 1964 hal_soc->ops->hal_reo_config = hal_reo_config_9224; 1965 hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_be; 1966 hal_soc->ops->hal_rx_msdu_flow_idx_invalid = 1967 hal_rx_msdu_flow_idx_invalid_be; 1968 hal_soc->ops->hal_rx_msdu_flow_idx_timeout = 1969 hal_rx_msdu_flow_idx_timeout_be; 1970 hal_soc->ops->hal_rx_msdu_fse_metadata_get = 1971 hal_rx_msdu_fse_metadata_get_be; 1972 hal_soc->ops->hal_rx_msdu_cce_match_get = 1973 hal_rx_msdu_cce_match_get_be; 1974 hal_soc->ops->hal_rx_msdu_cce_metadata_get = 1975 hal_rx_msdu_cce_metadata_get_be; 1976 hal_soc->ops->hal_rx_msdu_get_flow_params = 1977 hal_rx_msdu_get_flow_params_be; 1978 hal_soc->ops->hal_rx_tlv_get_tcp_chksum = hal_rx_tlv_get_tcp_chksum_be; 1979 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_be; 1980 1981 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) 1982 hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_9224; 1983 hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_9224; 1984 #else 1985 hal_soc->ops->hal_rx_get_bb_info = NULL; 1986 hal_soc->ops->hal_rx_get_rtt_info = NULL; 1987 #endif 1988 1989 /* rx - msdu fast path info fields */ 1990 hal_soc->ops->hal_rx_msdu_packet_metadata_get = 1991 hal_rx_msdu_packet_metadata_get_generic_be; 1992 hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid = 1993 hal_rx_mpdu_start_tlv_tag_valid_be; 1994 hal_soc->ops->hal_rx_wbm_err_msdu_continuation_get = 1995 hal_rx_wbm_err_msdu_continuation_get_9224; 1996 1997 /* rx - TLV struct offsets */ 1998 hal_soc->ops->hal_rx_msdu_end_offset_get = 1999 hal_rx_msdu_end_offset_get_generic; 2000 hal_soc->ops->hal_rx_mpdu_start_offset_get = 2001 hal_rx_mpdu_start_offset_get_generic; 2002 #ifndef NO_RX_PKT_HDR_TLV 2003 hal_soc->ops->hal_rx_pkt_tlv_offset_get = 2004 hal_rx_pkt_tlv_offset_get_generic; 2005 #endif 2006 hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_9224; 2007 2008 hal_soc->ops->hal_rx_flow_get_tuple_info = 2009 hal_rx_flow_get_tuple_info_be; 2010 hal_soc->ops->hal_rx_flow_delete_entry = 2011 hal_rx_flow_delete_entry_be; 2012 hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_be; 2013 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = 2014 hal_compute_reo_remap_ix2_ix3_9224; 2015 2016 hal_soc->ops->hal_rx_msdu_get_reo_destination_indication = 2017 hal_rx_msdu_get_reo_destination_indication_be; 2018 hal_soc->ops->hal_rx_get_tlv_size = hal_rx_get_tlv_size_generic_be; 2019 hal_soc->ops->hal_rx_msdu_is_wlan_mcast = 2020 hal_rx_msdu_is_wlan_mcast_generic_be; 2021 hal_soc->ops->hal_tx_get_num_tcl_banks = hal_tx_get_num_tcl_banks_9224; 2022 hal_soc->ops->hal_rx_tlv_decap_format_get = 2023 hal_rx_tlv_decap_format_get_be; 2024 #ifdef RECEIVE_OFFLOAD 2025 hal_soc->ops->hal_rx_tlv_get_offload_info = 2026 hal_rx_tlv_get_offload_info_be; 2027 hal_soc->ops->hal_rx_get_proto_params = hal_rx_get_proto_params_be; 2028 hal_soc->ops->hal_rx_get_l3_l4_offsets = hal_rx_get_l3_l4_offsets_be; 2029 #endif 2030 hal_soc->ops->hal_rx_tlv_phy_ppdu_id_get = 2031 hal_rx_attn_phy_ppdu_id_get_be; 2032 hal_soc->ops->hal_rx_tlv_msdu_done_get = 2033 hal_rx_tlv_msdu_done_copy_get_9224; 2034 hal_soc->ops->hal_rx_tlv_msdu_len_get = 2035 hal_rx_msdu_start_msdu_len_get_be; 2036 hal_soc->ops->hal_rx_get_frame_ctrl_field = 2037 hal_rx_get_frame_ctrl_field_be; 2038 hal_soc->ops->hal_rx_tlv_csum_err_get = hal_rx_tlv_csum_err_get_be; 2039 hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get = 2040 hal_rx_mpdu_info_ampdu_flag_get_be; 2041 hal_soc->ops->hal_rx_tlv_msdu_len_set = 2042 hal_rx_msdu_start_msdu_len_set_be; 2043 hal_soc->ops->hal_rx_tlv_sgi_get = hal_rx_tlv_sgi_get_be; 2044 hal_soc->ops->hal_rx_tlv_rate_mcs_get = hal_rx_tlv_rate_mcs_get_be; 2045 hal_soc->ops->hal_rx_tlv_bw_get = hal_rx_tlv_bw_get_be; 2046 hal_soc->ops->hal_rx_tlv_get_pkt_type = hal_rx_tlv_get_pkt_type_be; 2047 hal_soc->ops->hal_rx_tlv_mic_err_get = hal_rx_tlv_mic_err_get_be; 2048 hal_soc->ops->hal_rx_tlv_decrypt_err_get = 2049 hal_rx_tlv_decrypt_err_get_be; 2050 hal_soc->ops->hal_rx_tlv_first_mpdu_get = hal_rx_tlv_first_mpdu_get_be; 2051 hal_soc->ops->hal_rx_tlv_get_is_decrypted = 2052 hal_rx_tlv_get_is_decrypted_be; 2053 hal_soc->ops->hal_rx_msdu_get_keyid = hal_rx_msdu_get_keyid_be; 2054 hal_soc->ops->hal_rx_tlv_get_freq = hal_rx_tlv_get_freq_be; 2055 hal_soc->ops->hal_rx_priv_info_set_in_tlv = 2056 hal_rx_priv_info_set_in_tlv_be; 2057 hal_soc->ops->hal_rx_priv_info_get_from_tlv = 2058 hal_rx_priv_info_get_from_tlv_be; 2059 hal_soc->ops->hal_rx_pkt_hdr_get = hal_rx_pkt_hdr_get_be; 2060 hal_soc->ops->hal_reo_setup = hal_reo_setup_9224; 2061 hal_soc->ops->hal_reo_config_reo2ppe_dest_info = NULL; 2062 #ifdef REO_SHARED_QREF_TABLE_EN 2063 hal_soc->ops->hal_reo_shared_qaddr_setup = hal_reo_shared_qaddr_setup_be; 2064 hal_soc->ops->hal_reo_shared_qaddr_init = hal_reo_shared_qaddr_init_be; 2065 hal_soc->ops->hal_reo_shared_qaddr_detach = hal_reo_shared_qaddr_detach_be; 2066 hal_soc->ops->hal_reo_shared_qaddr_write = hal_reo_shared_qaddr_write_be; 2067 hal_soc->ops->hal_reo_shared_qaddr_cache_clear = hal_reo_shared_qaddr_cache_clear_be; 2068 #endif 2069 /* Overwrite the default BE ops */ 2070 hal_soc->ops->hal_get_rx_max_ba_window = 2071 hal_get_rx_max_ba_window_qcn9224; 2072 hal_soc->ops->hal_get_reo_qdesc_size = hal_qcn9224_get_reo_qdesc_size; 2073 /* TX MONITOR */ 2074 #ifdef QCA_MONITOR_2_0_SUPPORT 2075 hal_soc->ops->hal_txmon_is_mon_buf_addr_tlv = 2076 hal_txmon_is_mon_buf_addr_tlv_generic_be; 2077 hal_soc->ops->hal_txmon_populate_packet_info = 2078 hal_txmon_populate_packet_info_generic_be; 2079 hal_soc->ops->hal_txmon_status_parse_tlv = 2080 hal_txmon_status_parse_tlv_generic_be; 2081 hal_soc->ops->hal_txmon_status_get_num_users = 2082 hal_txmon_status_get_num_users_generic_be; 2083 #endif /* QCA_MONITOR_2_0_SUPPORT */ 2084 hal_soc->ops->hal_compute_reo_remap_ix0 = NULL; 2085 hal_soc->ops->hal_tx_vdev_mismatch_routing_set = 2086 hal_tx_vdev_mismatch_routing_set_generic_be; 2087 hal_soc->ops->hal_tx_mcast_mlo_reinject_routing_set = 2088 hal_tx_mcast_mlo_reinject_routing_set_generic_be; 2089 hal_soc->ops->hal_get_ba_aging_timeout = 2090 hal_get_ba_aging_timeout_be_generic; 2091 hal_soc->ops->hal_setup_link_idle_list = 2092 hal_setup_link_idle_list_generic_be; 2093 hal_soc->ops->hal_cookie_conversion_reg_cfg_be = 2094 hal_cookie_conversion_reg_cfg_generic_be; 2095 hal_soc->ops->hal_set_ba_aging_timeout = 2096 hal_set_ba_aging_timeout_be_generic; 2097 hal_soc->ops->hal_tx_populate_bank_register = 2098 hal_tx_populate_bank_register_be; 2099 hal_soc->ops->hal_tx_vdev_mcast_ctrl_set = 2100 hal_tx_vdev_mcast_ctrl_set_be; 2101 }; 2102 2103 /** 2104 * hal_srng_hw_reg_offset_init_qcn9224() - Initialize the HW srng reg offset 2105 * applicable only for QCN9224 2106 * @hal_soc: HAL Soc handle 2107 * 2108 * Return: None 2109 */ 2110 static inline void hal_srng_hw_reg_offset_init_qcn9224(struct hal_soc *hal_soc) 2111 { 2112 int32_t *hw_reg_offset = hal_soc->hal_hw_reg_offset; 2113 2114 hw_reg_offset[DST_MSI2_BASE_LSB] = REG_OFFSET(DST, MSI2_BASE_LSB), 2115 hw_reg_offset[DST_MSI2_BASE_MSB] = REG_OFFSET(DST, MSI2_BASE_MSB), 2116 hw_reg_offset[DST_MSI2_DATA] = REG_OFFSET(DST, MSI2_DATA), 2117 hw_reg_offset[DST_PRODUCER_INT2_SETUP] = 2118 REG_OFFSET(DST, PRODUCER_INT2_SETUP); 2119 } 2120