1 /* 2 * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #define HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va) \ 20 ((uint8_t *)(link_desc_va) + \ 21 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET) 22 23 #define HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0) \ 24 ((uint8_t *)(msdu0) + \ 25 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET) 26 27 #define HAL_ENT_MPDU_DESC_INFO(ent_ring_desc) \ 28 ((uint8_t *)(ent_ring_desc) + \ 29 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET) 30 31 #define HAL_DST_MPDU_DESC_INFO(dst_ring_desc) \ 32 ((uint8_t *)(dst_ring_desc) + \ 33 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET) 34 35 #define HAL_RX_GET_FC_VALID(rx_mpdu_start) \ 36 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_11, MPDU_FRAME_CONTROL_VALID) 37 38 #define HAL_RX_GET_TO_DS_FLAG(rx_mpdu_start) \ 39 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_11, TO_DS) 40 41 #define HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start) \ 42 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_11, MAC_ADDR_AD1_VALID) 43 44 #define HAL_RX_GET_MAC_ADDR2_VALID(rx_mpdu_start) \ 45 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_11, MAC_ADDR_AD2_VALID) 46 47 #define HAL_RX_GET_FILTER_CATEGORY(rx_mpdu_start) \ 48 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_9, RXPCU_MPDU_FILTER_IN_CATEGORY) 49 50 #define HAL_RX_GET_PPDU_ID(rx_mpdu_start) \ 51 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_9, PHY_PPDU_ID) 52 53 #define HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start) \ 54 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_9, SW_FRAME_GROUP_ID) 55 56 #define HAL_REO_R0_CONFIG(soc, reg_val, reo_params) \ 57 do { \ 58 reg_val &= \ 59 ~(HWIO_REO_R0_GENERAL_ENABLE_FRAGMENT_DEST_RING_BMSK |\ 60 HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK | \ 61 HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK); \ 62 reg_val |= \ 63 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 64 FRAGMENT_DEST_RING, \ 65 (reo_params)->frag_dst_ring) | \ 66 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 67 AGING_LIST_ENABLE, 1) |\ 68 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 69 AGING_FLUSH_ENABLE, 1);\ 70 HAL_REG_WRITE((soc), \ 71 HWIO_REO_R0_GENERAL_ENABLE_ADDR( \ 72 SEQ_WCSS_UMAC_REO_REG_OFFSET), \ 73 (reg_val)); \ 74 } while (0) 75 76 #define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \ 77 ((struct rx_msdu_desc_info *) \ 78 _OFFSET_TO_BYTE_PTR((msdu_details_ptr), \ 79 UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET)) 80 81 #define HAL_RX_LINK_DESC_MSDU0_PTR(link_desc) \ 82 ((struct rx_msdu_details *) \ 83 _OFFSET_TO_BYTE_PTR((link_desc),\ 84 UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET)) 85 86 #define HAL_RX_TLV_GET_TCP_CHKSUM(buf) \ 87 (_HAL_MS( \ 88 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 89 msdu_end_tlv.rx_msdu_end), \ 90 RX_MSDU_END_10_TCP_UDP_CHKSUM_OFFSET)), \ 91 RX_MSDU_END_10_TCP_UDP_CHKSUM_MASK, \ 92 RX_MSDU_END_10_TCP_UDP_CHKSUM_LSB)) 93 94 #define HAL_RX_MSDU_END_FIRST_MSDU_GET(_rx_msdu_end) \ 95 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 96 RX_MSDU_END_10_FIRST_MSDU_OFFSET)), \ 97 RX_MSDU_END_10_FIRST_MSDU_MASK, \ 98 RX_MSDU_END_10_FIRST_MSDU_LSB)) 99 100 #define HAL_RX_MSDU_END_LAST_MSDU_GET(_rx_msdu_end) \ 101 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 102 RX_MSDU_END_10_LAST_MSDU_OFFSET)), \ 103 RX_MSDU_END_10_LAST_MSDU_MASK, \ 104 RX_MSDU_END_10_LAST_MSDU_LSB)) 105 106 #define HAL_RX_MSDU_END_SA_IS_VALID_GET(_rx_msdu_end) \ 107 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 108 RX_MSDU_END_10_SA_IS_VALID_OFFSET)), \ 109 RX_MSDU_END_10_SA_IS_VALID_MASK, \ 110 RX_MSDU_END_10_SA_IS_VALID_LSB)) 111 112 #define HAL_RX_MSDU_END_DA_IS_VALID_GET(_rx_msdu_end) \ 113 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 114 RX_MSDU_END_10_DA_IS_VALID_OFFSET)), \ 115 RX_MSDU_END_10_DA_IS_VALID_MASK, \ 116 RX_MSDU_END_10_DA_IS_VALID_LSB)) 117 118 #define HAL_RX_MSDU_END_DA_IS_MCBC_GET(_rx_msdu_end) \ 119 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 120 RX_MSDU_END_10_DA_IS_MCBC_OFFSET)), \ 121 RX_MSDU_END_10_DA_IS_MCBC_MASK, \ 122 RX_MSDU_END_10_DA_IS_MCBC_LSB)) 123 124 #define HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(_rx_msdu_end) \ 125 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 126 RX_MSDU_END_10_L3_HEADER_PADDING_OFFSET)), \ 127 RX_MSDU_END_10_L3_HEADER_PADDING_MASK, \ 128 RX_MSDU_END_10_L3_HEADER_PADDING_LSB)) 129 130 #define HAL_RX_MSDU_END_SA_IDX_GET(_rx_msdu_end) \ 131 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 132 RX_MSDU_END_11_SA_IDX_OFFSET)), \ 133 RX_MSDU_END_11_SA_IDX_MASK, \ 134 RX_MSDU_END_11_SA_IDX_LSB)) 135 136 #define HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(_rx_msdu_end) \ 137 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 138 RX_MSDU_END_14_SA_SW_PEER_ID_OFFSET)), \ 139 RX_MSDU_END_14_SA_SW_PEER_ID_MASK, \ 140 RX_MSDU_END_14_SA_SW_PEER_ID_LSB)) 141 142 #define HAL_RX_MSDU_END_CCE_METADATA_GET(_rx_msdu_end) \ 143 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 144 RX_MSDU_END_14_CCE_METADATA_OFFSET)), \ 145 RX_MSDU_END_14_CCE_METADATA_MASK, \ 146 RX_MSDU_END_14_CCE_METADATA_LSB)) 147 148 #define HAL_RX_MSDU_END_DA_IDX_GET(_rx_msdu_end) \ 149 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 150 RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_OFFSET)), \ 151 RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_MASK, \ 152 RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_LSB)) 153 154 #define HAL_RX_MPDU_SW_FRAME_GROUP_ID_GET(_rx_mpdu_info) \ 155 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 156 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_OFFSET)), \ 157 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_MASK, \ 158 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_LSB)) \ 159 160 #define HAL_RX_MPDU_INFO_SW_PEER_ID_GET(_rx_mpdu_info) \ 161 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 162 RX_MPDU_INFO_10_SW_PEER_ID_OFFSET)), \ 163 RX_MPDU_INFO_10_SW_PEER_ID_MASK, \ 164 RX_MPDU_INFO_10_SW_PEER_ID_LSB)) 165 166 #define HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(_rx_mpdu_info) \ 167 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 168 RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_OFFSET)), \ 169 RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_MASK, \ 170 RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_LSB)) 171 172 #define HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(_rx_mpdu_info) \ 173 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 174 RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_OFFSET)), \ 175 RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_MASK, \ 176 RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_LSB)) 177 178 #define HAL_RX_MPDU_AD1_31_0_GET(_rx_mpdu_info) \ 179 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 180 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET)), \ 181 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK, \ 182 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB)) 183 184 #define HAL_RX_MPDU_AD1_47_32_GET(_rx_mpdu_info) \ 185 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 186 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET)), \ 187 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK, \ 188 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB)) 189 190 #define HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(_rx_mpdu_info) \ 191 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 192 RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_OFFSET)), \ 193 RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_MASK, \ 194 RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_LSB)) 195 196 #define HAL_RX_MPDU_AD2_15_0_GET(_rx_mpdu_info) \ 197 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 198 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET)), \ 199 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK, \ 200 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB)) 201 202 #define HAL_RX_MPDU_AD2_47_16_GET(_rx_mpdu_info) \ 203 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 204 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET)), \ 205 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK, \ 206 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB)) 207 208 #define HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(_rx_mpdu_info) \ 209 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 210 RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_OFFSET)), \ 211 RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_MASK, \ 212 RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_LSB)) 213 214 #define HAL_RX_MPDU_AD3_31_0_GET(_rx_mpdu_info) \ 215 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 216 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_OFFSET)), \ 217 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_MASK, \ 218 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_LSB)) 219 220 #define HAL_RX_MPDU_AD3_47_32_GET(_rx_mpdu_info) \ 221 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 222 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_OFFSET)), \ 223 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_MASK, \ 224 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_LSB)) 225 226 #define HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(_rx_mpdu_info) \ 227 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 228 RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_OFFSET)), \ 229 RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_MASK, \ 230 RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_LSB)) 231 232 #define HAL_RX_MPDU_AD4_31_0_GET(_rx_mpdu_info) \ 233 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 234 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET)), \ 235 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK, \ 236 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB)) 237 238 #define HAL_RX_MPDU_AD4_47_32_GET(_rx_mpdu_info) \ 239 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 240 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET)), \ 241 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK, \ 242 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB)) 243 244 #define HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(_rx_mpdu_info) \ 245 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 246 RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_OFFSET)), \ 247 RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_MASK, \ 248 RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_LSB)) 249 250 #define HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(_rx_mpdu_info) \ 251 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 252 RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_OFFSET)), \ 253 RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_MASK, \ 254 RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_LSB)) 255 256 #define HAL_RX_MPDU_ENCRYPTION_INFO_VALID(_rx_mpdu_info) \ 257 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 258 RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_OFFSET)), \ 259 RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_MASK, \ 260 RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_LSB)) 261 262 #define HAL_RX_MPDU_GET_FROMDS(_rx_mpdu_info) \ 263 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 264 RX_MPDU_INFO_11_FR_DS_OFFSET)), \ 265 RX_MPDU_INFO_11_FR_DS_MASK, \ 266 RX_MPDU_INFO_11_FR_DS_LSB)) 267 268 #define HAL_RX_MPDU_GET_TODS(_rx_mpdu_info) \ 269 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 270 RX_MPDU_INFO_11_TO_DS_OFFSET)), \ 271 RX_MPDU_INFO_11_TO_DS_MASK, \ 272 RX_MPDU_INFO_11_TO_DS_LSB)) 273 274 #define HAL_RX_MPDU_GET_SEQUENCE_NUMBER(_rx_mpdu_info) \ 275 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 276 RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_OFFSET)), \ 277 RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_MASK, \ 278 RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_LSB)) 279 280 #define HAL_RX_MPDU_PN_31_0_GET(_rx_mpdu_info) \ 281 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 282 RX_MPDU_INFO_3_PN_31_0_OFFSET)), \ 283 RX_MPDU_INFO_3_PN_31_0_MASK, \ 284 RX_MPDU_INFO_3_PN_31_0_LSB)) 285 286 #define HAL_RX_MPDU_PN_63_32_GET(_rx_mpdu_info) \ 287 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 288 RX_MPDU_INFO_4_PN_63_32_OFFSET)), \ 289 RX_MPDU_INFO_4_PN_63_32_MASK, \ 290 RX_MPDU_INFO_4_PN_63_32_LSB)) 291 292 #define HAL_RX_MPDU_PN_95_64_GET(_rx_mpdu_info) \ 293 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 294 RX_MPDU_INFO_5_PN_95_64_OFFSET)), \ 295 RX_MPDU_INFO_5_PN_95_64_MASK, \ 296 RX_MPDU_INFO_5_PN_95_64_LSB)) 297 298 #define HAL_RX_MPDU_PN_127_96_GET(_rx_mpdu_info) \ 299 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 300 RX_MPDU_INFO_6_PN_127_96_OFFSET)), \ 301 RX_MPDU_INFO_6_PN_127_96_MASK, \ 302 RX_MPDU_INFO_6_PN_127_96_LSB)) 303 304 #define HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(_rx_msdu_end) \ 305 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 306 RX_MSDU_END_10_FLOW_IDX_TIMEOUT_OFFSET)), \ 307 RX_MSDU_END_10_FLOW_IDX_TIMEOUT_MASK, \ 308 RX_MSDU_END_10_FLOW_IDX_TIMEOUT_LSB)) 309 310 #define HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(_rx_msdu_end) \ 311 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 312 RX_MSDU_END_10_FLOW_IDX_INVALID_OFFSET)), \ 313 RX_MSDU_END_10_FLOW_IDX_INVALID_MASK, \ 314 RX_MSDU_END_10_FLOW_IDX_INVALID_LSB)) 315 316 #define HAL_RX_MSDU_END_FLOW_IDX_GET(_rx_msdu_end) \ 317 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 318 RX_MSDU_END_12_FLOW_IDX_OFFSET)), \ 319 RX_MSDU_END_12_FLOW_IDX_MASK, \ 320 RX_MSDU_END_12_FLOW_IDX_LSB)) 321 322 #define HAL_RX_MSDU_END_FSE_METADATA_GET(_rx_msdu_end) \ 323 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 324 RX_MSDU_END_13_FSE_METADATA_OFFSET)), \ 325 RX_MSDU_END_13_FSE_METADATA_MASK, \ 326 RX_MSDU_END_13_FSE_METADATA_LSB)) 327 328 #define HAL_RX_MPDU_GET_PHY_PPDU_ID(_rx_mpdu_info) \ 329 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 330 RX_MPDU_INFO_9_PHY_PPDU_ID_OFFSET)), \ 331 RX_MPDU_INFO_9_PHY_PPDU_ID_MASK, \ 332 RX_MPDU_INFO_9_PHY_PPDU_ID_LSB)) \ 333 334 #define HAL_RX_MSDU_START_MIMO_SS_BITMAP(_rx_msdu_start)\ 335 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ 336 RX_MSDU_START_5_MIMO_SS_BITMAP_OFFSET)), \ 337 RX_MSDU_START_5_MIMO_SS_BITMAP_MASK, \ 338 RX_MSDU_START_5_MIMO_SS_BITMAP_LSB)) 339 340 #ifdef GET_MSDU_AGGREGATION 341 #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs)\ 342 {\ 343 struct rx_msdu_end *rx_msdu_end;\ 344 bool first_msdu, last_msdu; \ 345 rx_msdu_end = &rx_desc->msdu_end_tlv.rx_msdu_end;\ 346 first_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_10, FIRST_MSDU);\ 347 last_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_10, LAST_MSDU);\ 348 if (first_msdu && last_msdu)\ 349 rs->rs_flags &= (~IEEE80211_AMSDU_FLAG);\ 350 else\ 351 rs->rs_flags |= (IEEE80211_AMSDU_FLAG); \ 352 } \ 353 354 #else 355 #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs) 356 #endif 357 358 #define HAL_RX_MPDU_INFO_TID_GET(_rx_mpdu_info) \ 359 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 360 RX_MPDU_INFO_7_TID_OFFSET)), \ 361 RX_MPDU_INFO_7_TID_MASK, \ 362 RX_MPDU_INFO_7_TID_LSB)) 363 364 #define HAL_RX_MSDU_START_RECEPTION_TYPE_GET(_rx_msdu_start) \ 365 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \ 366 RX_MSDU_START_5_RECEPTION_TYPE_OFFSET)), \ 367 RX_MSDU_START_5_RECEPTION_TYPE_MASK, \ 368 RX_MSDU_START_5_RECEPTION_TYPE_LSB)) 369