1 /* 2 * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #include "sw_monitor_ring.h" 20 #include "hal_rx.h" 21 #include "hal_api_mon.h" 22 23 #define HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va) \ 24 ((uint8_t *)(link_desc_va) + \ 25 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET) 26 27 #define HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0) \ 28 ((uint8_t *)(msdu0) + \ 29 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET) 30 31 #define HAL_ENT_MPDU_DESC_INFO(ent_ring_desc) \ 32 ((uint8_t *)(ent_ring_desc) + \ 33 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET) 34 35 #define HAL_DST_MPDU_DESC_INFO(dst_ring_desc) \ 36 ((uint8_t *)(dst_ring_desc) + \ 37 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET) 38 39 #define HAL_RX_GET_FC_VALID(rx_mpdu_start) \ 40 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_11, MPDU_FRAME_CONTROL_VALID) 41 42 #define HAL_RX_GET_TO_DS_FLAG(rx_mpdu_start) \ 43 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_11, TO_DS) 44 45 #define HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start) \ 46 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_11, MAC_ADDR_AD1_VALID) 47 48 #define HAL_RX_GET_MAC_ADDR2_VALID(rx_mpdu_start) \ 49 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_11, MAC_ADDR_AD2_VALID) 50 51 #define HAL_RX_GET_FILTER_CATEGORY(rx_mpdu_start) \ 52 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_9, RXPCU_MPDU_FILTER_IN_CATEGORY) 53 54 #define HAL_RX_GET_PPDU_ID(rx_mpdu_start) \ 55 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_9, PHY_PPDU_ID) 56 57 #define HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start) \ 58 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_9, SW_FRAME_GROUP_ID) 59 60 #define HAL_REO_R0_CONFIG(soc, reg_val, reo_params) \ 61 do { \ 62 reg_val &= \ 63 ~(HWIO_REO_R0_GENERAL_ENABLE_FRAGMENT_DEST_RING_BMSK |\ 64 HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK | \ 65 HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK); \ 66 reg_val |= \ 67 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 68 FRAGMENT_DEST_RING, \ 69 (reo_params)->frag_dst_ring) | \ 70 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 71 AGING_LIST_ENABLE, 1) |\ 72 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 73 AGING_FLUSH_ENABLE, 1);\ 74 HAL_REG_WRITE((soc), \ 75 HWIO_REO_R0_GENERAL_ENABLE_ADDR( \ 76 SEQ_WCSS_UMAC_REO_REG_OFFSET), \ 77 (reg_val)); \ 78 } while (0) 79 80 #define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \ 81 ((struct rx_msdu_desc_info *) \ 82 _OFFSET_TO_BYTE_PTR((msdu_details_ptr), \ 83 UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET)) 84 85 #define HAL_RX_LINK_DESC_MSDU0_PTR(link_desc) \ 86 ((struct rx_msdu_details *) \ 87 _OFFSET_TO_BYTE_PTR((link_desc),\ 88 UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET)) 89 90 #define HAL_RX_TLV_GET_TCP_CHKSUM(buf) \ 91 (_HAL_MS( \ 92 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 93 msdu_end_tlv.rx_msdu_end), \ 94 RX_MSDU_END_10_TCP_UDP_CHKSUM_OFFSET)), \ 95 RX_MSDU_END_10_TCP_UDP_CHKSUM_MASK, \ 96 RX_MSDU_END_10_TCP_UDP_CHKSUM_LSB)) 97 98 #define HAL_RX_MSDU_END_FIRST_MSDU_GET(_rx_msdu_end) \ 99 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 100 RX_MSDU_END_10_FIRST_MSDU_OFFSET)), \ 101 RX_MSDU_END_10_FIRST_MSDU_MASK, \ 102 RX_MSDU_END_10_FIRST_MSDU_LSB)) 103 104 #define HAL_RX_MSDU_END_LAST_MSDU_GET(_rx_msdu_end) \ 105 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 106 RX_MSDU_END_10_LAST_MSDU_OFFSET)), \ 107 RX_MSDU_END_10_LAST_MSDU_MASK, \ 108 RX_MSDU_END_10_LAST_MSDU_LSB)) 109 110 #define HAL_RX_MSDU_END_SA_IS_VALID_GET(_rx_msdu_end) \ 111 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 112 RX_MSDU_END_10_SA_IS_VALID_OFFSET)), \ 113 RX_MSDU_END_10_SA_IS_VALID_MASK, \ 114 RX_MSDU_END_10_SA_IS_VALID_LSB)) 115 116 #define HAL_RX_MSDU_END_DA_IS_VALID_GET(_rx_msdu_end) \ 117 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 118 RX_MSDU_END_10_DA_IS_VALID_OFFSET)), \ 119 RX_MSDU_END_10_DA_IS_VALID_MASK, \ 120 RX_MSDU_END_10_DA_IS_VALID_LSB)) 121 122 #define HAL_RX_MSDU_END_DA_IS_MCBC_GET(_rx_msdu_end) \ 123 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 124 RX_MSDU_END_10_DA_IS_MCBC_OFFSET)), \ 125 RX_MSDU_END_10_DA_IS_MCBC_MASK, \ 126 RX_MSDU_END_10_DA_IS_MCBC_LSB)) 127 128 #define HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(_rx_msdu_end) \ 129 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 130 RX_MSDU_END_10_L3_HEADER_PADDING_OFFSET)), \ 131 RX_MSDU_END_10_L3_HEADER_PADDING_MASK, \ 132 RX_MSDU_END_10_L3_HEADER_PADDING_LSB)) 133 134 #define HAL_RX_MSDU_END_SA_IDX_GET(_rx_msdu_end) \ 135 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 136 RX_MSDU_END_11_SA_IDX_OFFSET)), \ 137 RX_MSDU_END_11_SA_IDX_MASK, \ 138 RX_MSDU_END_11_SA_IDX_LSB)) 139 140 #define HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(_rx_msdu_end) \ 141 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 142 RX_MSDU_END_14_SA_SW_PEER_ID_OFFSET)), \ 143 RX_MSDU_END_14_SA_SW_PEER_ID_MASK, \ 144 RX_MSDU_END_14_SA_SW_PEER_ID_LSB)) 145 146 #define HAL_RX_MSDU_END_CCE_METADATA_GET(_rx_msdu_end) \ 147 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 148 RX_MSDU_END_14_CCE_METADATA_OFFSET)), \ 149 RX_MSDU_END_14_CCE_METADATA_MASK, \ 150 RX_MSDU_END_14_CCE_METADATA_LSB)) 151 152 #define HAL_RX_MSDU_END_DA_IDX_GET(_rx_msdu_end) \ 153 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 154 RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_OFFSET)), \ 155 RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_MASK, \ 156 RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_LSB)) 157 158 #define HAL_RX_MPDU_SW_FRAME_GROUP_ID_GET(_rx_mpdu_info) \ 159 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 160 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_OFFSET)), \ 161 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_MASK, \ 162 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_LSB)) \ 163 164 #define HAL_RX_MPDU_INFO_SW_PEER_ID_GET(_rx_mpdu_info) \ 165 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 166 RX_MPDU_INFO_10_SW_PEER_ID_OFFSET)), \ 167 RX_MPDU_INFO_10_SW_PEER_ID_MASK, \ 168 RX_MPDU_INFO_10_SW_PEER_ID_LSB)) 169 170 #define HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(_rx_mpdu_info) \ 171 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 172 RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_OFFSET)), \ 173 RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_MASK, \ 174 RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_LSB)) 175 176 #define HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(_rx_mpdu_info) \ 177 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 178 RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_OFFSET)), \ 179 RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_MASK, \ 180 RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_LSB)) 181 182 #define HAL_RX_MPDU_AD1_31_0_GET(_rx_mpdu_info) \ 183 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 184 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET)), \ 185 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK, \ 186 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB)) 187 188 #define HAL_RX_MPDU_AD1_47_32_GET(_rx_mpdu_info) \ 189 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 190 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET)), \ 191 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK, \ 192 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB)) 193 194 #define HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(_rx_mpdu_info) \ 195 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 196 RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_OFFSET)), \ 197 RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_MASK, \ 198 RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_LSB)) 199 200 #define HAL_RX_MPDU_AD2_15_0_GET(_rx_mpdu_info) \ 201 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 202 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET)), \ 203 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK, \ 204 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB)) 205 206 #define HAL_RX_MPDU_AD2_47_16_GET(_rx_mpdu_info) \ 207 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 208 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET)), \ 209 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK, \ 210 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB)) 211 212 #define HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(_rx_mpdu_info) \ 213 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 214 RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_OFFSET)), \ 215 RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_MASK, \ 216 RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_LSB)) 217 218 #define HAL_RX_MPDU_AD3_31_0_GET(_rx_mpdu_info) \ 219 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 220 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_OFFSET)), \ 221 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_MASK, \ 222 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_LSB)) 223 224 #define HAL_RX_MPDU_AD3_47_32_GET(_rx_mpdu_info) \ 225 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 226 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_OFFSET)), \ 227 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_MASK, \ 228 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_LSB)) 229 230 #define HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(_rx_mpdu_info) \ 231 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 232 RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_OFFSET)), \ 233 RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_MASK, \ 234 RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_LSB)) 235 236 #define HAL_RX_MPDU_AD4_31_0_GET(_rx_mpdu_info) \ 237 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 238 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET)), \ 239 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK, \ 240 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB)) 241 242 #define HAL_RX_MPDU_AD4_47_32_GET(_rx_mpdu_info) \ 243 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 244 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET)), \ 245 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK, \ 246 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB)) 247 248 #define HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(_rx_mpdu_info) \ 249 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 250 RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_OFFSET)), \ 251 RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_MASK, \ 252 RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_LSB)) 253 254 #define HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(_rx_mpdu_info) \ 255 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 256 RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_OFFSET)), \ 257 RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_MASK, \ 258 RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_LSB)) 259 260 #define HAL_RX_MPDU_ENCRYPTION_INFO_VALID(_rx_mpdu_info) \ 261 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 262 RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_OFFSET)), \ 263 RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_MASK, \ 264 RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_LSB)) 265 266 #define HAL_RX_MPDU_GET_FROMDS(_rx_mpdu_info) \ 267 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 268 RX_MPDU_INFO_11_FR_DS_OFFSET)), \ 269 RX_MPDU_INFO_11_FR_DS_MASK, \ 270 RX_MPDU_INFO_11_FR_DS_LSB)) 271 272 #define HAL_RX_MPDU_GET_TODS(_rx_mpdu_info) \ 273 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 274 RX_MPDU_INFO_11_TO_DS_OFFSET)), \ 275 RX_MPDU_INFO_11_TO_DS_MASK, \ 276 RX_MPDU_INFO_11_TO_DS_LSB)) 277 278 #define HAL_RX_MPDU_GET_SEQUENCE_NUMBER(_rx_mpdu_info) \ 279 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 280 RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_OFFSET)), \ 281 RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_MASK, \ 282 RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_LSB)) 283 284 #define HAL_RX_MPDU_PN_31_0_GET(_rx_mpdu_info) \ 285 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 286 RX_MPDU_INFO_3_PN_31_0_OFFSET)), \ 287 RX_MPDU_INFO_3_PN_31_0_MASK, \ 288 RX_MPDU_INFO_3_PN_31_0_LSB)) 289 290 #define HAL_RX_MPDU_PN_63_32_GET(_rx_mpdu_info) \ 291 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 292 RX_MPDU_INFO_4_PN_63_32_OFFSET)), \ 293 RX_MPDU_INFO_4_PN_63_32_MASK, \ 294 RX_MPDU_INFO_4_PN_63_32_LSB)) 295 296 #define HAL_RX_MPDU_PN_95_64_GET(_rx_mpdu_info) \ 297 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 298 RX_MPDU_INFO_5_PN_95_64_OFFSET)), \ 299 RX_MPDU_INFO_5_PN_95_64_MASK, \ 300 RX_MPDU_INFO_5_PN_95_64_LSB)) 301 302 #define HAL_RX_MPDU_PN_127_96_GET(_rx_mpdu_info) \ 303 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 304 RX_MPDU_INFO_6_PN_127_96_OFFSET)), \ 305 RX_MPDU_INFO_6_PN_127_96_MASK, \ 306 RX_MPDU_INFO_6_PN_127_96_LSB)) 307 308 #define HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(_rx_msdu_end) \ 309 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 310 RX_MSDU_END_10_FLOW_IDX_TIMEOUT_OFFSET)), \ 311 RX_MSDU_END_10_FLOW_IDX_TIMEOUT_MASK, \ 312 RX_MSDU_END_10_FLOW_IDX_TIMEOUT_LSB)) 313 314 #define HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(_rx_msdu_end) \ 315 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 316 RX_MSDU_END_10_FLOW_IDX_INVALID_OFFSET)), \ 317 RX_MSDU_END_10_FLOW_IDX_INVALID_MASK, \ 318 RX_MSDU_END_10_FLOW_IDX_INVALID_LSB)) 319 320 #define HAL_RX_MSDU_END_FLOW_IDX_GET(_rx_msdu_end) \ 321 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 322 RX_MSDU_END_12_FLOW_IDX_OFFSET)), \ 323 RX_MSDU_END_12_FLOW_IDX_MASK, \ 324 RX_MSDU_END_12_FLOW_IDX_LSB)) 325 326 #define HAL_RX_MSDU_END_FSE_METADATA_GET(_rx_msdu_end) \ 327 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 328 RX_MSDU_END_13_FSE_METADATA_OFFSET)), \ 329 RX_MSDU_END_13_FSE_METADATA_MASK, \ 330 RX_MSDU_END_13_FSE_METADATA_LSB)) 331 332 #define HAL_RX_MPDU_GET_PHY_PPDU_ID(_rx_mpdu_info) \ 333 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 334 RX_MPDU_INFO_9_PHY_PPDU_ID_OFFSET)), \ 335 RX_MPDU_INFO_9_PHY_PPDU_ID_MASK, \ 336 RX_MPDU_INFO_9_PHY_PPDU_ID_LSB)) \ 337 338 #define HAL_RX_MSDU_START_MIMO_SS_BITMAP(_rx_msdu_start)\ 339 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ 340 RX_MSDU_START_5_MIMO_SS_BITMAP_OFFSET)), \ 341 RX_MSDU_START_5_MIMO_SS_BITMAP_MASK, \ 342 RX_MSDU_START_5_MIMO_SS_BITMAP_LSB)) 343 344 #ifdef GET_MSDU_AGGREGATION 345 #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs)\ 346 {\ 347 struct rx_msdu_end *rx_msdu_end;\ 348 bool first_msdu, last_msdu; \ 349 rx_msdu_end = &rx_desc->msdu_end_tlv.rx_msdu_end;\ 350 first_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_10, FIRST_MSDU);\ 351 last_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_10, LAST_MSDU);\ 352 if (first_msdu && last_msdu)\ 353 rs->rs_flags &= (~IEEE80211_AMSDU_FLAG);\ 354 else\ 355 rs->rs_flags |= (IEEE80211_AMSDU_FLAG); \ 356 } \ 357 358 #else 359 #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs) 360 #endif 361 362 #define HAL_RX_MPDU_INFO_TID_GET(_rx_mpdu_info) \ 363 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 364 RX_MPDU_INFO_7_TID_OFFSET)), \ 365 RX_MPDU_INFO_7_TID_MASK, \ 366 RX_MPDU_INFO_7_TID_LSB)) 367 368 #define HAL_RX_MSDU_START_RECEPTION_TYPE_GET(_rx_msdu_start) \ 369 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \ 370 RX_MSDU_START_5_RECEPTION_TYPE_OFFSET)), \ 371 RX_MSDU_START_5_RECEPTION_TYPE_MASK, \ 372 RX_MSDU_START_5_RECEPTION_TYPE_LSB)) 373