1 /* 2 * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #include "hal_hw_headers.h" 19 #include "hal_internal.h" 20 #include "hal_api.h" 21 #include "target_type.h" 22 #include "wcss_version.h" 23 #include "qdf_module.h" 24 #include "hal_9000_rx.h" 25 #include "hal_api_mon.h" 26 #include "hal_flow.h" 27 #include "rx_flow_search_entry.h" 28 #include "hal_rx_flow_info.h" 29 30 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 31 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET 32 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 33 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK 34 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 35 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB 36 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 37 PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 38 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 39 PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 40 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 41 PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 42 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 43 PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 44 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 45 PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 46 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 47 PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 48 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 49 PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 50 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 51 PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 52 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 53 PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 54 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 55 PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 56 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 57 PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 58 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 59 RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 60 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 61 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 62 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 63 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 64 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 65 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 66 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 67 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 68 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER \ 69 STATUS_HEADER_REO_STATUS_NUMBER 70 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 71 STATUS_HEADER_TIMESTAMP 72 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 73 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 74 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 75 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 76 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 77 TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 78 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 79 TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 80 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 81 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 82 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 83 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 84 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 85 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 86 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 87 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 88 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 89 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 90 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 91 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 92 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 93 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 94 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 95 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 96 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 97 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 98 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 99 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 100 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 101 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 102 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 103 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 104 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 105 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 106 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 107 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 108 109 #define CE_WINDOW_ADDRESS_9000 \ 110 ((CE_WFSS_CE_REG_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) 111 112 #define UMAC_WINDOW_ADDRESS_9000 \ 113 ((SEQ_WCSS_UMAC_OFFSET >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) 114 115 #define WINDOW_CONFIGURATION_VALUE_9000 \ 116 ((CE_WINDOW_ADDRESS_9000 << 6) |\ 117 (UMAC_WINDOW_ADDRESS_9000 << 12) | \ 118 WINDOW_ENABLE_BIT) 119 120 #include <hal_9000_tx.h> 121 #include <hal_9000_rx.h> 122 #include <hal_generic_api.h> 123 #include <hal_wbm.h> 124 125 /** 126 * hal_rx_sw_mon_desc_info_get_9000(): API to read the 127 * sw monitor ring descriptor 128 * 129 * @rxdma_dst_ring_desc: sw monitor ring descriptor 130 * @desc_info_buf: Descriptor info buffer to which 131 * sw monitor ring descriptor is populated to 132 * 133 * Return: void 134 */ 135 static void 136 hal_rx_sw_mon_desc_info_get_9000(hal_ring_desc_t rxdma_dst_ring_desc, 137 hal_rx_mon_desc_info_t desc_info_buf) 138 { 139 struct sw_monitor_ring *sw_mon_ring = 140 (struct sw_monitor_ring *)rxdma_dst_ring_desc; 141 struct buffer_addr_info *buf_addr_info; 142 uint32_t *mpdu_info; 143 uint32_t loop_cnt; 144 struct hal_rx_mon_desc_info *desc_info; 145 146 desc_info = (struct hal_rx_mon_desc_info *)desc_info_buf; 147 mpdu_info = (uint32_t *)&sw_mon_ring-> 148 reo_level_mpdu_frame_info.rx_mpdu_desc_info_details; 149 150 loop_cnt = HAL_RX_GET(sw_mon_ring, SW_MONITOR_RING_7, LOOPING_COUNT); 151 desc_info->msdu_count = HAL_RX_MPDU_MSDU_COUNT_GET(mpdu_info); 152 153 /* Get msdu link descriptor buf_addr_info */ 154 buf_addr_info = &sw_mon_ring-> 155 reo_level_mpdu_frame_info.msdu_link_desc_addr_info; 156 desc_info->link_desc.paddr = HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) 157 | ((uint64_t)(HAL_RX_BUFFER_ADDR_39_32_GET( 158 buf_addr_info)) << 32); 159 desc_info->link_desc.sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info); 160 buf_addr_info = &sw_mon_ring->status_buff_addr_info; 161 desc_info->status_buf.paddr = HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) 162 | ((uint64_t) 163 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32); 164 desc_info->status_buf.sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info); 165 desc_info->end_of_ppdu = HAL_RX_GET(sw_mon_ring, 166 SW_MONITOR_RING_6, 167 END_OF_PPDU); 168 desc_info->status_buf_count = HAL_RX_GET(sw_mon_ring, 169 SW_MONITOR_RING_6, 170 STATUS_BUF_COUNT); 171 desc_info->rxdma_push_reason = HAL_RX_GET(sw_mon_ring, 172 SW_MONITOR_RING_6, 173 RXDMA_PUSH_REASON); 174 desc_info->ppdu_id = HAL_RX_GET(sw_mon_ring, 175 SW_MONITOR_RING_7, 176 PHY_PPDU_ID); 177 } 178 179 /** 180 * hal_rx_msdu_start_nss_get_9000(): API to get the NSS 181 * Interval from rx_msdu_start 182 * 183 * @buf: pointer to the start of RX PKT TLV header 184 * Return: uint32_t(nss) 185 */ 186 static uint32_t hal_rx_msdu_start_nss_get_9000(uint8_t *buf) 187 { 188 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 189 struct rx_msdu_start *msdu_start = 190 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 191 uint8_t mimo_ss_bitmap; 192 193 mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start); 194 195 return qdf_get_hweight8(mimo_ss_bitmap); 196 } 197 198 /** 199 * hal_rx_mon_hw_desc_get_mpdu_status_9000(): Retrieve MPDU status 200 * 201 * @ hw_desc_addr: Start address of Rx HW TLVs 202 * @ rs: Status for monitor mode 203 * 204 * Return: void 205 */ 206 static void hal_rx_mon_hw_desc_get_mpdu_status_9000(void *hw_desc_addr, 207 struct mon_rx_status *rs) 208 { 209 struct rx_msdu_start *rx_msdu_start; 210 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 211 uint32_t reg_value; 212 const uint32_t sgi_hw_to_cdp[] = { 213 CDP_SGI_0_8_US, 214 CDP_SGI_0_4_US, 215 CDP_SGI_1_6_US, 216 CDP_SGI_3_2_US, 217 }; 218 219 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 220 221 HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs); 222 223 rs->ant_signal_db = HAL_RX_GET(rx_msdu_start, 224 RX_MSDU_START_5, USER_RSSI); 225 rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC); 226 227 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI); 228 rs->sgi = sgi_hw_to_cdp[reg_value]; 229 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE); 230 rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0; 231 /* TODO: rs->beamformed should be set for SU beamforming also */ 232 } 233 234 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 235 /** 236 * hal_get_link_desc_size_9000(): API to get the link desc size 237 * 238 * Return: uint32_t 239 */ 240 static uint32_t hal_get_link_desc_size_9000(void) 241 { 242 return LINK_DESC_SIZE; 243 } 244 245 /** 246 * hal_rx_get_tlv_9000(): API to get the tlv 247 * 248 * @rx_tlv: TLV data extracted from the rx packet 249 * Return: uint8_t 250 */ 251 static uint8_t hal_rx_get_tlv_9000(void *rx_tlv) 252 { 253 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH); 254 } 255 256 /** 257 * hal_rx_mpdu_start_tlv_tag_valid_9000 () - API to check if RX_MPDU_START 258 * tlv tag is valid 259 * 260 *@rx_tlv_hdr: start address of rx_pkt_tlvs 261 * 262 * Return: true if RX_MPDU_START is valied, else false. 263 */ 264 uint8_t hal_rx_mpdu_start_tlv_tag_valid_9000(void *rx_tlv_hdr) 265 { 266 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 267 uint32_t tlv_tag; 268 269 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(&rx_desc->mpdu_start_tlv); 270 271 return tlv_tag == WIFIRX_MPDU_START_E ? true : false; 272 } 273 274 /** 275 * hal_rx_wbm_err_msdu_continuation_get_9000 () - API to check if WBM 276 * msdu continuation bit is set 277 * 278 *@wbm_desc: wbm release ring descriptor 279 * 280 * Return: true if msdu continuation bit is set. 281 */ 282 uint8_t hal_rx_wbm_err_msdu_continuation_get_9000(void *wbm_desc) 283 { 284 uint32_t comp_desc = 285 *(uint32_t *)(((uint8_t *)wbm_desc) + 286 WBM_RELEASE_RING_3_MSDU_CONTINUATION_OFFSET); 287 288 return (comp_desc & WBM_RELEASE_RING_3_MSDU_CONTINUATION_MASK) >> 289 WBM_RELEASE_RING_3_MSDU_CONTINUATION_LSB; 290 } 291 292 /** 293 * hal_rx_proc_phyrx_other_receive_info_tlv_9000(): API to get tlv info 294 * 295 * Return: uint32_t 296 */ 297 static inline 298 void hal_rx_proc_phyrx_other_receive_info_tlv_9000(void *rx_tlv_hdr, 299 void *ppdu_info_hdl) 300 { 301 } 302 303 /** 304 * hal_rx_dump_msdu_start_tlv_9000() : dump RX msdu_start TLV in structured 305 * human readable format. 306 * @ msdu_start: pointer the msdu_start TLV in pkt. 307 * @ dbg_level: log level. 308 * 309 * Return: void 310 */ 311 static void hal_rx_dump_msdu_start_tlv_9000(void *msdustart, 312 uint8_t dbg_level) 313 { 314 struct rx_msdu_start *msdu_start = (struct rx_msdu_start *)msdustart; 315 316 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 317 "rx_msdu_start tlv - " 318 "rxpcu_mpdu_filter_in_category: %d " 319 "sw_frame_group_id: %d " 320 "phy_ppdu_id: %d " 321 "msdu_length: %d " 322 "ipsec_esp: %d " 323 "l3_offset: %d " 324 "ipsec_ah: %d " 325 "l4_offset: %d " 326 "msdu_number: %d " 327 "decap_format: %d " 328 "ipv4_proto: %d " 329 "ipv6_proto: %d " 330 "tcp_proto: %d " 331 "udp_proto: %d " 332 "ip_frag: %d " 333 "tcp_only_ack: %d " 334 "da_is_bcast_mcast: %d " 335 "ip4_protocol_ip6_next_header: %d " 336 "toeplitz_hash_2_or_4: %d " 337 "flow_id_toeplitz: %d " 338 "user_rssi: %d " 339 "pkt_type: %d " 340 "stbc: %d " 341 "sgi: %d " 342 "rate_mcs: %d " 343 "receive_bandwidth: %d " 344 "reception_type: %d " 345 "ppdu_start_timestamp: %d " 346 "sw_phy_meta_data: %d ", 347 msdu_start->rxpcu_mpdu_filter_in_category, 348 msdu_start->sw_frame_group_id, 349 msdu_start->phy_ppdu_id, 350 msdu_start->msdu_length, 351 msdu_start->ipsec_esp, 352 msdu_start->l3_offset, 353 msdu_start->ipsec_ah, 354 msdu_start->l4_offset, 355 msdu_start->msdu_number, 356 msdu_start->decap_format, 357 msdu_start->ipv4_proto, 358 msdu_start->ipv6_proto, 359 msdu_start->tcp_proto, 360 msdu_start->udp_proto, 361 msdu_start->ip_frag, 362 msdu_start->tcp_only_ack, 363 msdu_start->da_is_bcast_mcast, 364 msdu_start->ip4_protocol_ip6_next_header, 365 msdu_start->toeplitz_hash_2_or_4, 366 msdu_start->flow_id_toeplitz, 367 msdu_start->user_rssi, 368 msdu_start->pkt_type, 369 msdu_start->stbc, 370 msdu_start->sgi, 371 msdu_start->rate_mcs, 372 msdu_start->receive_bandwidth, 373 msdu_start->reception_type, 374 msdu_start->ppdu_start_timestamp, 375 msdu_start->sw_phy_meta_data); 376 } 377 378 /** 379 * hal_rx_dump_msdu_end_tlv_9000: dump RX msdu_end TLV in structured 380 * human readable format. 381 * @ msdu_end: pointer the msdu_end TLV in pkt. 382 * @ dbg_level: log level. 383 * 384 * Return: void 385 */ 386 static void hal_rx_dump_msdu_end_tlv_9000(void *msduend, 387 uint8_t dbg_level) 388 { 389 struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend; 390 391 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 392 "rx_msdu_end tlv - " 393 "rxpcu_mpdu_filter_in_category: %d " 394 "sw_frame_group_id: %d " 395 "phy_ppdu_id: %d " 396 "ip_hdr_chksum: %d " 397 "reported_mpdu_length: %d " 398 "key_id_octet: %d " 399 "cce_super_rule: %d " 400 "cce_classify_not_done_truncat: %d " 401 "cce_classify_not_done_cce_dis: %d " 402 "rule_indication_31_0: %d " 403 "rule_indication_63_32: %d " 404 "da_offset: %d " 405 "sa_offset: %d " 406 "da_offset_valid: %d " 407 "sa_offset_valid: %d " 408 "ipv6_options_crc: %d " 409 "tcp_seq_number: %d " 410 "tcp_ack_number: %d " 411 "tcp_flag: %d " 412 "lro_eligible: %d " 413 "window_size: %d " 414 "tcp_udp_chksum: %d " 415 "sa_idx_timeout: %d " 416 "da_idx_timeout: %d " 417 "msdu_limit_error: %d " 418 "flow_idx_timeout: %d " 419 "flow_idx_invalid: %d " 420 "wifi_parser_error: %d " 421 "amsdu_parser_error: %d " 422 "sa_is_valid: %d " 423 "da_is_valid: %d " 424 "da_is_mcbc: %d " 425 "l3_header_padding: %d " 426 "first_msdu: %d " 427 "last_msdu: %d " 428 "sa_idx: %d " 429 "msdu_drop: %d " 430 "reo_destination_indication: %d " 431 "flow_idx: %d " 432 "fse_metadata: %d " 433 "cce_metadata: %d " 434 "sa_sw_peer_id: %d ", 435 msdu_end->rxpcu_mpdu_filter_in_category, 436 msdu_end->sw_frame_group_id, 437 msdu_end->phy_ppdu_id, 438 msdu_end->ip_hdr_chksum, 439 msdu_end->reported_mpdu_length, 440 msdu_end->key_id_octet, 441 msdu_end->cce_super_rule, 442 msdu_end->cce_classify_not_done_truncate, 443 msdu_end->cce_classify_not_done_cce_dis, 444 msdu_end->rule_indication_31_0, 445 msdu_end->rule_indication_63_32, 446 msdu_end->da_offset, 447 msdu_end->sa_offset, 448 msdu_end->da_offset_valid, 449 msdu_end->sa_offset_valid, 450 msdu_end->ipv6_options_crc, 451 msdu_end->tcp_seq_number, 452 msdu_end->tcp_ack_number, 453 msdu_end->tcp_flag, 454 msdu_end->lro_eligible, 455 msdu_end->window_size, 456 msdu_end->tcp_udp_chksum, 457 msdu_end->sa_idx_timeout, 458 msdu_end->da_idx_timeout, 459 msdu_end->msdu_limit_error, 460 msdu_end->flow_idx_timeout, 461 msdu_end->flow_idx_invalid, 462 msdu_end->wifi_parser_error, 463 msdu_end->amsdu_parser_error, 464 msdu_end->sa_is_valid, 465 msdu_end->da_is_valid, 466 msdu_end->da_is_mcbc, 467 msdu_end->l3_header_padding, 468 msdu_end->first_msdu, 469 msdu_end->last_msdu, 470 msdu_end->sa_idx, 471 msdu_end->msdu_drop, 472 msdu_end->reo_destination_indication, 473 msdu_end->flow_idx, 474 msdu_end->fse_metadata, 475 msdu_end->cce_metadata, 476 msdu_end->sa_sw_peer_id); 477 } 478 479 /** 480 * hal_rx_mpdu_start_tid_get_9000(): API to get tid 481 * from rx_msdu_start 482 * 483 * @buf: pointer to the start of RX PKT TLV header 484 * Return: uint32_t(tid value) 485 */ 486 static uint32_t hal_rx_mpdu_start_tid_get_9000(uint8_t *buf) 487 { 488 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 489 struct rx_mpdu_start *mpdu_start = 490 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 491 uint32_t tid; 492 493 tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details); 494 495 return tid; 496 } 497 498 /** 499 * hal_rx_msdu_start_reception_type_get(): API to get the reception type 500 * Interval from rx_msdu_start 501 * 502 * @buf: pointer to the start of RX PKT TLV header 503 * Return: uint32_t(reception_type) 504 */ 505 static uint32_t hal_rx_msdu_start_reception_type_get_9000(uint8_t *buf) 506 { 507 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 508 struct rx_msdu_start *msdu_start = 509 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 510 uint32_t reception_type; 511 512 reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start); 513 514 return reception_type; 515 } 516 517 /** 518 * hal_rx_msdu_end_da_idx_get_9000: API to get da_idx 519 * from rx_msdu_end TLV 520 * 521 * @ buf: pointer to the start of RX PKT TLV headers 522 * Return: da index 523 */ 524 static uint16_t hal_rx_msdu_end_da_idx_get_9000(uint8_t *buf) 525 { 526 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 527 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 528 uint16_t da_idx; 529 530 da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 531 532 return da_idx; 533 } 534 535 /** 536 * hal_rx_get_rx_fragment_number_9000(): Function to retrieve rx fragment number 537 * 538 * @nbuf: Network buffer 539 * Returns: rx fragment number 540 */ 541 static 542 uint8_t hal_rx_get_rx_fragment_number_9000(uint8_t *buf) 543 { 544 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 545 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 546 547 /* Return first 4 bits as fragment number */ 548 return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & 549 DOT11_SEQ_FRAG_MASK); 550 } 551 552 /** 553 * hal_rx_msdu_end_da_is_mcbc_get_9000(): API to check if pkt is MCBC 554 * from rx_msdu_end TLV 555 * 556 * @ buf: pointer to the start of RX PKT TLV headers 557 * Return: da_is_mcbc 558 */ 559 static uint8_t 560 hal_rx_msdu_end_da_is_mcbc_get_9000(uint8_t *buf) 561 { 562 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 563 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 564 565 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); 566 } 567 568 /** 569 * hal_rx_msdu_end_sa_is_valid_get_9000(): API to get_9000 the 570 * sa_is_valid bit from rx_msdu_end TLV 571 * 572 * @ buf: pointer to the start of RX PKT TLV headers 573 * Return: sa_is_valid bit 574 */ 575 static uint8_t 576 hal_rx_msdu_end_sa_is_valid_get_9000(uint8_t *buf) 577 { 578 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 579 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 580 uint8_t sa_is_valid; 581 582 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); 583 584 return sa_is_valid; 585 } 586 587 /** 588 * hal_rx_msdu_end_sa_idx_get_9000(): API to get_9000 the 589 * sa_idx from rx_msdu_end TLV 590 * 591 * @ buf: pointer to the start of RX PKT TLV headers 592 * Return: sa_idx (SA AST index) 593 */ 594 static uint16_t hal_rx_msdu_end_sa_idx_get_9000(uint8_t *buf) 595 { 596 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 597 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 598 uint16_t sa_idx; 599 600 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 601 602 return sa_idx; 603 } 604 605 /** 606 * hal_rx_desc_is_first_msdu_9000() - Check if first msdu 607 * 608 * @hal_soc_hdl: hal_soc handle 609 * @hw_desc_addr: hardware descriptor address 610 * 611 * Return: 0 - success/ non-zero failure 612 */ 613 static uint32_t hal_rx_desc_is_first_msdu_9000(void *hw_desc_addr) 614 { 615 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; 616 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; 617 618 return HAL_RX_GET(msdu_end, RX_MSDU_END_10, FIRST_MSDU); 619 } 620 621 /** 622 * hal_rx_msdu_end_l3_hdr_padding_get_9000(): API to get_9000 the 623 * l3_header padding from rx_msdu_end TLV 624 * 625 * @ buf: pointer to the start of RX PKT TLV headers 626 * Return: number of l3 header padding bytes 627 */ 628 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_9000(uint8_t *buf) 629 { 630 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 631 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 632 uint32_t l3_header_padding; 633 634 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 635 636 return l3_header_padding; 637 } 638 639 /** 640 * @ hal_rx_encryption_info_valid_9000: Returns encryption type. 641 * 642 * @ buf: rx_tlv_hdr of the received packet 643 * @ Return: encryption type 644 */ 645 inline uint32_t hal_rx_encryption_info_valid_9000(uint8_t *buf) 646 { 647 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 648 struct rx_mpdu_start *mpdu_start = 649 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 650 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 651 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); 652 653 return encryption_info; 654 } 655 656 /* 657 * @ hal_rx_print_pn_9000: Prints the PN of rx packet. 658 * 659 * @ buf: rx_tlv_hdr of the received packet 660 * @ Return: void 661 */ 662 static void hal_rx_print_pn_9000(uint8_t *buf) 663 { 664 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 665 struct rx_mpdu_start *mpdu_start = 666 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 667 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 668 669 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); 670 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); 671 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); 672 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); 673 674 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ", 675 pn_127_96, pn_95_64, pn_63_32, pn_31_0); 676 } 677 678 /** 679 * hal_rx_msdu_end_first_msdu_get_9000: API to get first msdu status 680 * from rx_msdu_end TLV 681 * 682 * @ buf: pointer to the start of RX PKT TLV headers 683 * Return: first_msdu 684 */ 685 static uint8_t hal_rx_msdu_end_first_msdu_get_9000(uint8_t *buf) 686 { 687 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 688 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 689 uint8_t first_msdu; 690 691 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); 692 693 return first_msdu; 694 } 695 696 /** 697 * hal_rx_msdu_end_da_is_valid_get_9000: API to check if da is valid 698 * from rx_msdu_end TLV 699 * 700 * @ buf: pointer to the start of RX PKT TLV headers 701 * Return: da_is_valid 702 */ 703 static uint8_t hal_rx_msdu_end_da_is_valid_get_9000(uint8_t *buf) 704 { 705 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 706 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 707 uint8_t da_is_valid; 708 709 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); 710 711 return da_is_valid; 712 } 713 714 /** 715 * hal_rx_msdu_end_last_msdu_get_9000: API to get last msdu status 716 * from rx_msdu_end TLV 717 * 718 * @ buf: pointer to the start of RX PKT TLV headers 719 * Return: last_msdu 720 */ 721 static uint8_t hal_rx_msdu_end_last_msdu_get_9000(uint8_t *buf) 722 { 723 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 724 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 725 uint8_t last_msdu; 726 727 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); 728 729 return last_msdu; 730 } 731 732 /* 733 * hal_rx_get_mpdu_mac_ad4_valid(): Retrieves if mpdu 4th addr is valid 734 * 735 * @nbuf: Network buffer 736 * Returns: value of mpdu 4th address valid field 737 */ 738 inline bool hal_rx_get_mpdu_mac_ad4_valid_9000(uint8_t *buf) 739 { 740 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 741 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 742 bool ad4_valid = 0; 743 744 ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(rx_mpdu_info); 745 746 return ad4_valid; 747 } 748 749 /** 750 * hal_rx_mpdu_start_sw_peer_id_get_9000: Retrieve sw peer_id 751 * @buf: network buffer 752 * 753 * Return: sw peer_id 754 */ 755 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_9000(uint8_t *buf) 756 { 757 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 758 struct rx_mpdu_start *mpdu_start = 759 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 760 761 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET( 762 &mpdu_start->rx_mpdu_info_details); 763 } 764 765 /* 766 * hal_rx_mpdu_get_to_ds_9000(): API to get the tods info 767 * from rx_mpdu_start 768 * 769 * @buf: pointer to the start of RX PKT TLV header 770 * Return: uint32_t(to_ds) 771 */ 772 static uint32_t hal_rx_mpdu_get_to_ds_9000(uint8_t *buf) 773 { 774 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 775 struct rx_mpdu_start *mpdu_start = 776 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 777 778 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 779 780 return HAL_RX_MPDU_GET_TODS(mpdu_info); 781 } 782 783 /* 784 * hal_rx_mpdu_get_fr_ds_9000(): API to get the from ds info 785 * from rx_mpdu_start 786 * 787 * @buf: pointer to the start of RX PKT TLV header 788 * Return: uint32_t(fr_ds) 789 */ 790 static uint32_t hal_rx_mpdu_get_fr_ds_9000(uint8_t *buf) 791 { 792 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 793 struct rx_mpdu_start *mpdu_start = 794 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 795 796 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 797 798 return HAL_RX_MPDU_GET_FROMDS(mpdu_info); 799 } 800 801 /* 802 * hal_rx_get_mpdu_frame_control_valid_9000(): Retrieves mpdu 803 * frame control valid 804 * 805 * @nbuf: Network buffer 806 * Returns: value of frame control valid field 807 */ 808 static uint8_t hal_rx_get_mpdu_frame_control_valid_9000(uint8_t *buf) 809 { 810 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 811 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 812 813 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); 814 } 815 816 /* 817 * hal_rx_mpdu_get_addr1_9000(): API to check get address1 of the mpdu 818 * 819 * @buf: pointer to the start of RX PKT TLV headera 820 * @mac_addr: pointer to mac address 821 * Return: success/failure 822 */ 823 static QDF_STATUS hal_rx_mpdu_get_addr1_9000(uint8_t *buf, 824 uint8_t *mac_addr) 825 { 826 struct __attribute__((__packed__)) hal_addr1 { 827 uint32_t ad1_31_0; 828 uint16_t ad1_47_32; 829 }; 830 831 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 832 struct rx_mpdu_start *mpdu_start = 833 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 834 835 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 836 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; 837 uint32_t mac_addr_ad1_valid; 838 839 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); 840 841 if (mac_addr_ad1_valid) { 842 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); 843 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); 844 return QDF_STATUS_SUCCESS; 845 } 846 847 return QDF_STATUS_E_FAILURE; 848 } 849 850 /* 851 * hal_rx_mpdu_get_addr2_9000(): API to check get address2 of the mpdu 852 * in the packet 853 * 854 * @buf: pointer to the start of RX PKT TLV header 855 * @mac_addr: pointer to mac address 856 * Return: success/failure 857 */ 858 static QDF_STATUS hal_rx_mpdu_get_addr2_9000(uint8_t *buf, uint8_t *mac_addr) 859 { 860 struct __attribute__((__packed__)) hal_addr2 { 861 uint16_t ad2_15_0; 862 uint32_t ad2_47_16; 863 }; 864 865 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 866 struct rx_mpdu_start *mpdu_start = 867 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 868 869 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 870 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; 871 uint32_t mac_addr_ad2_valid; 872 873 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); 874 875 if (mac_addr_ad2_valid) { 876 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); 877 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); 878 return QDF_STATUS_SUCCESS; 879 } 880 881 return QDF_STATUS_E_FAILURE; 882 } 883 884 /* 885 * hal_rx_mpdu_get_addr3_9000(): API to get address3 of the mpdu 886 * in the packet 887 * 888 * @buf: pointer to the start of RX PKT TLV header 889 * @mac_addr: pointer to mac address 890 * Return: success/failure 891 */ 892 static QDF_STATUS hal_rx_mpdu_get_addr3_9000(uint8_t *buf, uint8_t *mac_addr) 893 { 894 struct __attribute__((__packed__)) hal_addr3 { 895 uint32_t ad3_31_0; 896 uint16_t ad3_47_32; 897 }; 898 899 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 900 struct rx_mpdu_start *mpdu_start = 901 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 902 903 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 904 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; 905 uint32_t mac_addr_ad3_valid; 906 907 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); 908 909 if (mac_addr_ad3_valid) { 910 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); 911 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); 912 return QDF_STATUS_SUCCESS; 913 } 914 915 return QDF_STATUS_E_FAILURE; 916 } 917 918 /* 919 * hal_rx_mpdu_get_addr4_9000(): API to get address4 of the mpdu 920 * in the packet 921 * 922 * @buf: pointer to the start of RX PKT TLV header 923 * @mac_addr: pointer to mac address 924 * Return: success/failure 925 */ 926 static QDF_STATUS hal_rx_mpdu_get_addr4_9000(uint8_t *buf, uint8_t *mac_addr) 927 { 928 struct __attribute__((__packed__)) hal_addr4 { 929 uint32_t ad4_31_0; 930 uint16_t ad4_47_32; 931 }; 932 933 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 934 struct rx_mpdu_start *mpdu_start = 935 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 936 937 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 938 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; 939 uint32_t mac_addr_ad4_valid; 940 941 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); 942 943 if (mac_addr_ad4_valid) { 944 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); 945 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); 946 return QDF_STATUS_SUCCESS; 947 } 948 949 return QDF_STATUS_E_FAILURE; 950 } 951 952 /* 953 * hal_rx_get_mpdu_sequence_control_valid_9000(): Get mpdu 954 * sequence control valid 955 * 956 * @nbuf: Network buffer 957 * Returns: value of sequence control valid field 958 */ 959 static uint8_t hal_rx_get_mpdu_sequence_control_valid_9000(uint8_t *buf) 960 { 961 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 962 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 963 964 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); 965 } 966 967 /** 968 * hal_rx_is_unicast_9000: check packet is unicast frame or not. 969 * 970 * @ buf: pointer to rx pkt TLV. 971 * 972 * Return: true on unicast. 973 */ 974 static bool hal_rx_is_unicast_9000(uint8_t *buf) 975 { 976 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 977 struct rx_mpdu_start *mpdu_start = 978 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 979 uint32_t grp_id; 980 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 981 982 grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 983 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_OFFSET)), 984 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_MASK, 985 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_LSB)); 986 987 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false; 988 } 989 990 /** 991 * hal_rx_tid_get_9000: get tid based on qos control valid. 992 * @hal_soc_hdl: hal soc handle 993 * @buf: pointer to rx pkt TLV. 994 * 995 * Return: tid 996 */ 997 static uint32_t hal_rx_tid_get_9000(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 998 { 999 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1000 struct rx_mpdu_start *mpdu_start = 1001 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1002 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 1003 uint8_t qos_control_valid = 1004 (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 1005 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_OFFSET)), 1006 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_MASK, 1007 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_LSB)); 1008 1009 if (qos_control_valid) 1010 return hal_rx_mpdu_start_tid_get_9000(buf); 1011 1012 return HAL_RX_NON_QOS_TID; 1013 } 1014 1015 /** 1016 * hal_rx_hw_desc_get_ppduid_get_9000(): retrieve ppdu id 1017 * @rx_tlv_hdr: rx tlv header 1018 * @rxdma_dst_ring_desc: rxdma HW descriptor 1019 * 1020 * Return: ppdu id 1021 */ 1022 static uint32_t hal_rx_hw_desc_get_ppduid_get_9000(void *rx_tlv_hdr, 1023 void *rxdma_dst_ring_desc) 1024 { 1025 struct reo_entrance_ring *reo_ent = rxdma_dst_ring_desc; 1026 1027 return reo_ent->phy_ppdu_id; 1028 } 1029 1030 /** 1031 * hal_reo_status_get_header_9000 - Process reo desc info 1032 * @d - Pointer to reo descriptior 1033 * @b - tlv type info 1034 * @h1 - Pointer to hal_reo_status_header where info to be stored 1035 * 1036 * Return - none. 1037 * 1038 */ 1039 static void hal_reo_status_get_header_9000(uint32_t *d, int b, void *h1) 1040 { 1041 uint32_t val1 = 0; 1042 struct hal_reo_status_header *h = 1043 (struct hal_reo_status_header *)h1; 1044 1045 switch (b) { 1046 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1047 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, 1048 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1049 break; 1050 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1051 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, 1052 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1053 break; 1054 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1055 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, 1056 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1057 break; 1058 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1059 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, 1060 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1061 break; 1062 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1063 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, 1064 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1065 break; 1066 case HAL_REO_DESC_THRES_STATUS_TLV: 1067 val1 = 1068 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, 1069 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1070 break; 1071 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1072 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, 1073 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1074 break; 1075 default: 1076 qdf_nofl_err("ERROR: Unknown tlv\n"); 1077 break; 1078 } 1079 h->cmd_num = 1080 HAL_GET_FIELD( 1081 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, 1082 val1); 1083 h->exec_time = 1084 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1085 CMD_EXECUTION_TIME, val1); 1086 h->status = 1087 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1088 REO_CMD_EXECUTION_STATUS, val1); 1089 switch (b) { 1090 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1091 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, 1092 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1093 break; 1094 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1095 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, 1096 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1097 break; 1098 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1099 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, 1100 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1101 break; 1102 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1103 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, 1104 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1105 break; 1106 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1107 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, 1108 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1109 break; 1110 case HAL_REO_DESC_THRES_STATUS_TLV: 1111 val1 = 1112 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, 1113 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1114 break; 1115 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1116 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, 1117 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1118 break; 1119 default: 1120 qdf_nofl_err("ERROR: Unknown tlv\n"); 1121 break; 1122 } 1123 h->tstamp = 1124 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); 1125 } 1126 1127 /** 1128 * hal_rx_mpdu_start_mpdu_qos_control_valid_get_9000(): 1129 * Retrieve qos control valid bit from the tlv. 1130 * @buf: pointer to rx pkt TLV. 1131 * 1132 * Return: qos control value. 1133 */ 1134 static inline uint32_t 1135 hal_rx_mpdu_start_mpdu_qos_control_valid_get_9000(uint8_t *buf) 1136 { 1137 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1138 struct rx_mpdu_start *mpdu_start = 1139 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1140 1141 return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET( 1142 &mpdu_start->rx_mpdu_info_details); 1143 } 1144 1145 /** 1146 * hal_rx_msdu_end_sa_sw_peer_id_get_9000(): API to get the 1147 * sa_sw_peer_id from rx_msdu_end TLV 1148 * @buf: pointer to the start of RX PKT TLV headers 1149 * 1150 * Return: sa_sw_peer_id index 1151 */ 1152 static inline uint32_t 1153 hal_rx_msdu_end_sa_sw_peer_id_get_9000(uint8_t *buf) 1154 { 1155 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1156 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1157 1158 return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 1159 } 1160 1161 /** 1162 * hal_tx_desc_set_mesh_en_9000 - Set mesh_enable flag in Tx descriptor 1163 * @desc: Handle to Tx Descriptor 1164 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 1165 * enabling the interpretation of the 'Mesh Control Present' bit 1166 * (bit 8) of QoS Control (otherwise this bit is ignored), 1167 * For native WiFi frames, this indicates that a 'Mesh Control' field 1168 * is present between the header and the LLC. 1169 * 1170 * Return: void 1171 */ 1172 static inline 1173 void hal_tx_desc_set_mesh_en_9000(void *desc, uint8_t en) 1174 { 1175 HAL_SET_FLD(desc, TCL_DATA_CMD_5, MESH_ENABLE) |= 1176 HAL_TX_SM(TCL_DATA_CMD_5, MESH_ENABLE, en); 1177 } 1178 1179 static 1180 void *hal_rx_msdu0_buffer_addr_lsb_9000(void *link_desc_va) 1181 { 1182 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 1183 } 1184 1185 static 1186 void *hal_rx_msdu_desc_info_ptr_get_9000(void *msdu0) 1187 { 1188 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 1189 } 1190 1191 static 1192 void *hal_ent_mpdu_desc_info_9000(void *ent_ring_desc) 1193 { 1194 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 1195 } 1196 1197 static 1198 void *hal_dst_mpdu_desc_info_9000(void *dst_ring_desc) 1199 { 1200 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 1201 } 1202 1203 static 1204 uint8_t hal_rx_get_fc_valid_9000(uint8_t *buf) 1205 { 1206 return HAL_RX_GET_FC_VALID(buf); 1207 } 1208 1209 static uint8_t hal_rx_get_to_ds_flag_9000(uint8_t *buf) 1210 { 1211 return HAL_RX_GET_TO_DS_FLAG(buf); 1212 } 1213 1214 static uint8_t hal_rx_get_mac_addr2_valid_9000(uint8_t *buf) 1215 { 1216 return HAL_RX_GET_MAC_ADDR2_VALID(buf); 1217 } 1218 1219 static uint8_t hal_rx_get_filter_category_9000(uint8_t *buf) 1220 { 1221 return HAL_RX_GET_FILTER_CATEGORY(buf); 1222 } 1223 1224 static uint32_t 1225 hal_rx_get_ppdu_id_9000(uint8_t *buf) 1226 { 1227 struct rx_mpdu_info *rx_mpdu_info; 1228 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)buf; 1229 1230 rx_mpdu_info = 1231 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 1232 1233 return HAL_RX_GET_PPDU_ID(rx_mpdu_info); 1234 } 1235 1236 /** 1237 * hal_reo_config_9000(): Set reo config parameters 1238 * @soc: hal soc handle 1239 * @reg_val: value to be set 1240 * @reo_params: reo parameters 1241 * 1242 * Return: void 1243 */ 1244 static void 1245 hal_reo_config_9000(struct hal_soc *soc, 1246 uint32_t reg_val, 1247 struct hal_reo_params *reo_params) 1248 { 1249 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 1250 } 1251 1252 /** 1253 * hal_rx_msdu_desc_info_get_ptr_9000() - Get msdu desc info ptr 1254 * @msdu_details_ptr - Pointer to msdu_details_ptr 1255 * 1256 * Return - Pointer to rx_msdu_desc_info structure. 1257 * 1258 */ 1259 static void *hal_rx_msdu_desc_info_get_ptr_9000(void *msdu_details_ptr) 1260 { 1261 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 1262 } 1263 1264 /** 1265 * hal_rx_link_desc_msdu0_ptr_9000 - Get pointer to rx_msdu details 1266 * @link_desc - Pointer to link desc 1267 * 1268 * Return - Pointer to rx_msdu_details structure 1269 * 1270 */ 1271 static void *hal_rx_link_desc_msdu0_ptr_9000(void *link_desc) 1272 { 1273 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 1274 } 1275 1276 /** 1277 * hal_rx_msdu_flow_idx_get_9000: API to get flow index 1278 * from rx_msdu_end TLV 1279 * @buf: pointer to the start of RX PKT TLV headers 1280 * 1281 * Return: flow index value from MSDU END TLV 1282 */ 1283 static inline uint32_t hal_rx_msdu_flow_idx_get_9000(uint8_t *buf) 1284 { 1285 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1286 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1287 1288 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 1289 } 1290 1291 /** 1292 * hal_rx_msdu_flow_idx_invalid_9000: API to get flow index invalid 1293 * from rx_msdu_end TLV 1294 * @buf: pointer to the start of RX PKT TLV headers 1295 * 1296 * Return: flow index invalid value from MSDU END TLV 1297 */ 1298 static bool hal_rx_msdu_flow_idx_invalid_9000(uint8_t *buf) 1299 { 1300 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1301 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1302 1303 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 1304 } 1305 1306 /** 1307 * hal_rx_msdu_flow_idx_timeout_9000: API to get flow index timeout 1308 * from rx_msdu_end TLV 1309 * @buf: pointer to the start of RX PKT TLV headers 1310 * 1311 * Return: flow index timeout value from MSDU END TLV 1312 */ 1313 static bool hal_rx_msdu_flow_idx_timeout_9000(uint8_t *buf) 1314 { 1315 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1316 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1317 1318 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 1319 } 1320 1321 /** 1322 * hal_rx_msdu_fse_metadata_get_9000: API to get FSE metadata 1323 * from rx_msdu_end TLV 1324 * @buf: pointer to the start of RX PKT TLV headers 1325 * 1326 * Return: fse metadata value from MSDU END TLV 1327 */ 1328 static uint32_t hal_rx_msdu_fse_metadata_get_9000(uint8_t *buf) 1329 { 1330 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1331 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1332 1333 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end); 1334 } 1335 1336 /** 1337 * hal_rx_msdu_cce_metadata_get_9000: API to get CCE metadata 1338 * from rx_msdu_end TLV 1339 * @buf: pointer to the start of RX PKT TLV headers 1340 * 1341 * Return: cce_metadata 1342 */ 1343 static uint16_t 1344 hal_rx_msdu_cce_metadata_get_9000(uint8_t *buf) 1345 { 1346 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1347 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1348 1349 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end); 1350 } 1351 1352 /** 1353 * hal_rx_msdu_get_flow_params_9000: API to get flow index, flow index invalid 1354 * and flow index timeout from rx_msdu_end TLV 1355 * @buf: pointer to the start of RX PKT TLV headers 1356 * @flow_invalid: pointer to return value of flow_idx_valid 1357 * @flow_timeout: pointer to return value of flow_idx_timeout 1358 * @flow_index: pointer to return value of flow_idx 1359 * 1360 * Return: none 1361 */ 1362 static inline void 1363 hal_rx_msdu_get_flow_params_9000(uint8_t *buf, 1364 bool *flow_invalid, 1365 bool *flow_timeout, 1366 uint32_t *flow_index) 1367 { 1368 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1369 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1370 1371 *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 1372 *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 1373 *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 1374 } 1375 1376 /** 1377 * hal_rx_tlv_get_tcp_chksum_9000() - API to get tcp checksum 1378 * @buf: rx_tlv_hdr 1379 * 1380 * Return: tcp checksum 1381 */ 1382 static uint16_t 1383 hal_rx_tlv_get_tcp_chksum_9000(uint8_t *buf) 1384 { 1385 return HAL_RX_TLV_GET_TCP_CHKSUM(buf); 1386 } 1387 1388 /** 1389 * hal_rx_get_rx_sequence_9000(): Function to retrieve rx sequence number 1390 * 1391 * @nbuf: Network buffer 1392 * Returns: rx sequence number 1393 */ 1394 static 1395 uint16_t hal_rx_get_rx_sequence_9000(uint8_t *buf) 1396 { 1397 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 1398 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 1399 1400 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info); 1401 } 1402 1403 /** 1404 * hal_get_window_address_9000(): Function to get hp/tp address 1405 * @hal_soc: Pointer to hal_soc 1406 * @addr: address offset of register 1407 * 1408 * Return: modified address offset of register 1409 */ 1410 static inline qdf_iomem_t hal_get_window_address_9000(struct hal_soc *hal_soc, 1411 qdf_iomem_t addr) 1412 { 1413 uint32_t offset = addr - hal_soc->dev_base_addr; 1414 qdf_iomem_t new_offset; 1415 1416 /* 1417 * If offset lies within DP register range, use 3rd window to write 1418 * into DP region. 1419 */ 1420 if ((offset ^ SEQ_WCSS_UMAC_OFFSET) < WINDOW_RANGE_MASK) { 1421 new_offset = (hal_soc->dev_base_addr + (3 * WINDOW_START) + 1422 (offset & WINDOW_RANGE_MASK)); 1423 /* 1424 * If offset lies within CE register range, use 2nd window to write 1425 * into CE region. 1426 */ 1427 } else if ((offset ^ CE_WFSS_CE_REG_BASE) < WINDOW_RANGE_MASK) { 1428 new_offset = (hal_soc->dev_base_addr + (2 * WINDOW_START) + 1429 (offset & WINDOW_RANGE_MASK)); 1430 } else { 1431 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 1432 "%s: ERROR: Accessing Wrong register\n", __func__); 1433 qdf_assert_always(0); 1434 return 0; 1435 } 1436 return new_offset; 1437 } 1438 1439 static inline void hal_write_window_register(struct hal_soc *hal_soc) 1440 { 1441 /* Write value into window configuration register */ 1442 qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_REG_ADDRESS, 1443 WINDOW_CONFIGURATION_VALUE_9000); 1444 } 1445 1446 /** 1447 * hal_rx_msdu_packet_metadata_get_9000(): API to get the 1448 * msdu information from rx_msdu_end TLV 1449 * 1450 * @ buf: pointer to the start of RX PKT TLV headers 1451 * @ hal_rx_msdu_metadata: pointer to the msdu info structure 1452 */ 1453 static void 1454 hal_rx_msdu_packet_metadata_get_9000(uint8_t *buf, 1455 void *msdu_pkt_metadata) 1456 { 1457 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1458 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1459 struct hal_rx_msdu_metadata *msdu_metadata = 1460 (struct hal_rx_msdu_metadata *)msdu_pkt_metadata; 1461 1462 msdu_metadata->l3_hdr_pad = 1463 HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 1464 msdu_metadata->sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 1465 msdu_metadata->da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 1466 msdu_metadata->sa_sw_peer_id = 1467 HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 1468 } 1469 1470 /** 1471 * hal_rx_flow_setup_fse_9000() - Setup a flow search entry in HW FST 1472 * @fst: Pointer to the Rx Flow Search Table 1473 * @table_offset: offset into the table where the flow is to be setup 1474 * @flow: Flow Parameters 1475 * 1476 * Return: Success/Failure 1477 */ 1478 static void * 1479 hal_rx_flow_setup_fse_9000(uint8_t *rx_fst, uint32_t table_offset, 1480 uint8_t *rx_flow) 1481 { 1482 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 1483 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 1484 uint8_t *fse; 1485 bool fse_valid; 1486 1487 if (table_offset >= fst->max_entries) { 1488 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 1489 "HAL FSE table offset %u exceeds max entries %u", 1490 table_offset, fst->max_entries); 1491 return NULL; 1492 } 1493 1494 fse = (uint8_t *)fst->base_vaddr + 1495 (table_offset * HAL_RX_FST_ENTRY_SIZE); 1496 1497 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1498 1499 if (fse_valid) { 1500 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 1501 "HAL FSE %pK already valid", fse); 1502 return NULL; 1503 } 1504 1505 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96) = 1506 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96, 1507 qdf_htonl(flow->tuple_info.src_ip_127_96)); 1508 1509 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64) = 1510 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64, 1511 qdf_htonl(flow->tuple_info.src_ip_95_64)); 1512 1513 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32) = 1514 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32, 1515 qdf_htonl(flow->tuple_info.src_ip_63_32)); 1516 1517 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0) = 1518 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0, 1519 qdf_htonl(flow->tuple_info.src_ip_31_0)); 1520 1521 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96) = 1522 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96, 1523 qdf_htonl(flow->tuple_info.dest_ip_127_96)); 1524 1525 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64) = 1526 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64, 1527 qdf_htonl(flow->tuple_info.dest_ip_95_64)); 1528 1529 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32) = 1530 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32, 1531 qdf_htonl(flow->tuple_info.dest_ip_63_32)); 1532 1533 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0) = 1534 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0, 1535 qdf_htonl(flow->tuple_info.dest_ip_31_0)); 1536 1537 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT); 1538 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT) |= 1539 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, DEST_PORT, 1540 (flow->tuple_info.dest_port)); 1541 1542 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT); 1543 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT) |= 1544 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, SRC_PORT, 1545 (flow->tuple_info.src_port)); 1546 1547 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL); 1548 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL) |= 1549 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL, 1550 flow->tuple_info.l4_protocol); 1551 1552 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER); 1553 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER) |= 1554 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER, 1555 flow->reo_destination_handler); 1556 1557 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1558 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID) |= 1559 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, VALID, 1); 1560 1561 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA); 1562 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA) = 1563 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_10, METADATA, 1564 flow->fse_metadata); 1565 1566 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION); 1567 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION) |= 1568 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, 1569 REO_DESTINATION_INDICATION, 1570 flow->reo_destination_indication); 1571 1572 /* Reset all the other fields in FSE */ 1573 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, RESERVED_9); 1574 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, MSDU_DROP); 1575 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_COUNT); 1576 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_12, MSDU_BYTE_COUNT); 1577 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_13, TIMESTAMP); 1578 1579 return fse; 1580 } 1581 1582 static 1583 void hal_compute_reo_remap_ix2_ix3_9000(uint32_t *ring, uint32_t num_rings, 1584 uint32_t *remap1, uint32_t *remap2) 1585 { 1586 switch (num_rings) { 1587 case 3: 1588 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1589 HAL_REO_REMAP_IX2(ring[1], 17) | 1590 HAL_REO_REMAP_IX2(ring[2], 18) | 1591 HAL_REO_REMAP_IX2(ring[0], 19) | 1592 HAL_REO_REMAP_IX2(ring[1], 20) | 1593 HAL_REO_REMAP_IX2(ring[2], 21) | 1594 HAL_REO_REMAP_IX2(ring[0], 22) | 1595 HAL_REO_REMAP_IX2(ring[1], 23); 1596 1597 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) | 1598 HAL_REO_REMAP_IX3(ring[0], 25) | 1599 HAL_REO_REMAP_IX3(ring[1], 26) | 1600 HAL_REO_REMAP_IX3(ring[2], 27) | 1601 HAL_REO_REMAP_IX3(ring[0], 28) | 1602 HAL_REO_REMAP_IX3(ring[1], 29) | 1603 HAL_REO_REMAP_IX3(ring[2], 30) | 1604 HAL_REO_REMAP_IX3(ring[0], 31); 1605 break; 1606 case 4: 1607 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1608 HAL_REO_REMAP_IX2(ring[1], 17) | 1609 HAL_REO_REMAP_IX2(ring[2], 18) | 1610 HAL_REO_REMAP_IX2(ring[3], 19) | 1611 HAL_REO_REMAP_IX2(ring[0], 20) | 1612 HAL_REO_REMAP_IX2(ring[1], 21) | 1613 HAL_REO_REMAP_IX2(ring[2], 22) | 1614 HAL_REO_REMAP_IX2(ring[3], 23); 1615 1616 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1617 HAL_REO_REMAP_IX3(ring[1], 25) | 1618 HAL_REO_REMAP_IX3(ring[2], 26) | 1619 HAL_REO_REMAP_IX3(ring[3], 27) | 1620 HAL_REO_REMAP_IX3(ring[0], 28) | 1621 HAL_REO_REMAP_IX3(ring[1], 29) | 1622 HAL_REO_REMAP_IX3(ring[2], 30) | 1623 HAL_REO_REMAP_IX3(ring[3], 31); 1624 break; 1625 } 1626 } 1627 struct hal_hw_txrx_ops qcn9000_hal_hw_txrx_ops = { 1628 1629 /* init and setup */ 1630 hal_srng_dst_hw_init_generic, 1631 hal_srng_src_hw_init_generic, 1632 hal_get_hw_hptp_generic, 1633 hal_reo_setup_generic, 1634 hal_setup_link_idle_list_generic, 1635 hal_get_window_address_9000, 1636 NULL, 1637 1638 /* tx */ 1639 hal_tx_desc_set_dscp_tid_table_id_9000, 1640 hal_tx_set_dscp_tid_map_9000, 1641 hal_tx_update_dscp_tid_9000, 1642 hal_tx_desc_set_lmac_id_9000, 1643 hal_tx_desc_set_buf_addr_generic, 1644 hal_tx_desc_set_search_type_generic, 1645 hal_tx_desc_set_search_index_generic, 1646 hal_tx_desc_set_cache_set_num_generic, 1647 hal_tx_comp_get_status_generic, 1648 hal_tx_comp_get_release_reason_generic, 1649 hal_get_wbm_internal_error_generic, 1650 hal_tx_desc_set_mesh_en_9000, 1651 hal_tx_init_cmd_credit_ring_9000, 1652 1653 /* rx */ 1654 hal_rx_msdu_start_nss_get_9000, 1655 hal_rx_mon_hw_desc_get_mpdu_status_9000, 1656 hal_rx_get_tlv_9000, 1657 hal_rx_proc_phyrx_other_receive_info_tlv_9000, 1658 hal_rx_dump_msdu_start_tlv_9000, 1659 hal_rx_dump_msdu_end_tlv_9000, 1660 hal_get_link_desc_size_9000, 1661 hal_rx_mpdu_start_tid_get_9000, 1662 hal_rx_msdu_start_reception_type_get_9000, 1663 hal_rx_msdu_end_da_idx_get_9000, 1664 hal_rx_msdu_desc_info_get_ptr_9000, 1665 hal_rx_link_desc_msdu0_ptr_9000, 1666 hal_reo_status_get_header_9000, 1667 hal_rx_status_get_tlv_info_generic, 1668 hal_rx_wbm_err_info_get_generic, 1669 hal_rx_dump_mpdu_start_tlv_generic, 1670 1671 hal_tx_set_pcp_tid_map_generic, 1672 hal_tx_update_pcp_tid_generic, 1673 hal_tx_update_tidmap_prty_generic, 1674 hal_rx_get_rx_fragment_number_9000, 1675 hal_rx_msdu_end_da_is_mcbc_get_9000, 1676 hal_rx_msdu_end_sa_is_valid_get_9000, 1677 hal_rx_msdu_end_sa_idx_get_9000, 1678 hal_rx_desc_is_first_msdu_9000, 1679 hal_rx_msdu_end_l3_hdr_padding_get_9000, 1680 hal_rx_encryption_info_valid_9000, 1681 hal_rx_print_pn_9000, 1682 hal_rx_msdu_end_first_msdu_get_9000, 1683 hal_rx_msdu_end_da_is_valid_get_9000, 1684 hal_rx_msdu_end_last_msdu_get_9000, 1685 hal_rx_get_mpdu_mac_ad4_valid_9000, 1686 hal_rx_mpdu_start_sw_peer_id_get_9000, 1687 hal_rx_mpdu_get_to_ds_9000, 1688 hal_rx_mpdu_get_fr_ds_9000, 1689 hal_rx_get_mpdu_frame_control_valid_9000, 1690 hal_rx_mpdu_get_addr1_9000, 1691 hal_rx_mpdu_get_addr2_9000, 1692 hal_rx_mpdu_get_addr3_9000, 1693 hal_rx_mpdu_get_addr4_9000, 1694 hal_rx_get_mpdu_sequence_control_valid_9000, 1695 hal_rx_is_unicast_9000, 1696 hal_rx_tid_get_9000, 1697 hal_rx_hw_desc_get_ppduid_get_9000, 1698 hal_rx_mpdu_start_mpdu_qos_control_valid_get_9000, 1699 hal_rx_msdu_end_sa_sw_peer_id_get_9000, 1700 hal_rx_msdu0_buffer_addr_lsb_9000, 1701 hal_rx_msdu_desc_info_ptr_get_9000, 1702 hal_ent_mpdu_desc_info_9000, 1703 hal_dst_mpdu_desc_info_9000, 1704 hal_rx_get_fc_valid_9000, 1705 hal_rx_get_to_ds_flag_9000, 1706 hal_rx_get_mac_addr2_valid_9000, 1707 hal_rx_get_filter_category_9000, 1708 hal_rx_get_ppdu_id_9000, 1709 hal_reo_config_9000, 1710 hal_rx_msdu_flow_idx_get_9000, 1711 hal_rx_msdu_flow_idx_invalid_9000, 1712 hal_rx_msdu_flow_idx_timeout_9000, 1713 hal_rx_msdu_fse_metadata_get_9000, 1714 hal_rx_msdu_cce_metadata_get_9000, 1715 hal_rx_msdu_get_flow_params_9000, 1716 hal_rx_tlv_get_tcp_chksum_9000, 1717 hal_rx_get_rx_sequence_9000, 1718 NULL, 1719 NULL, 1720 /* rx - msdu fast path info fields */ 1721 hal_rx_msdu_packet_metadata_get_9000, 1722 NULL, 1723 NULL, 1724 NULL, 1725 NULL, 1726 NULL, 1727 NULL, 1728 hal_rx_mpdu_start_tlv_tag_valid_9000, 1729 hal_rx_sw_mon_desc_info_get_9000, 1730 hal_rx_wbm_err_msdu_continuation_get_9000, 1731 1732 /* rx - TLV struct offsets */ 1733 hal_rx_msdu_end_offset_get_generic, 1734 hal_rx_attn_offset_get_generic, 1735 hal_rx_msdu_start_offset_get_generic, 1736 hal_rx_mpdu_start_offset_get_generic, 1737 hal_rx_mpdu_end_offset_get_generic, 1738 hal_rx_flow_setup_fse_9000, 1739 hal_compute_reo_remap_ix2_ix3_9000 1740 }; 1741 1742 struct hal_hw_srng_config hw_srng_table_9000[] = { 1743 /* TODO: max_rings can populated by querying HW capabilities */ 1744 { /* REO_DST */ 1745 .start_ring_id = HAL_SRNG_REO2SW1, 1746 .max_rings = 4, 1747 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1748 .lmac_ring = FALSE, 1749 .ring_dir = HAL_SRNG_DST_RING, 1750 .reg_start = { 1751 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 1752 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1753 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 1754 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1755 }, 1756 .reg_size = { 1757 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 1758 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 1759 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 1760 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 1761 }, 1762 .max_size = 1763 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 1764 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 1765 }, 1766 { /* REO_EXCEPTION */ 1767 /* Designating REO2TCL ring as exception ring. This ring is 1768 * similar to other REO2SW rings though it is named as REO2TCL. 1769 * Any of theREO2SW rings can be used as exception ring. 1770 */ 1771 .start_ring_id = HAL_SRNG_REO2TCL, 1772 .max_rings = 1, 1773 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1774 .lmac_ring = FALSE, 1775 .ring_dir = HAL_SRNG_DST_RING, 1776 .reg_start = { 1777 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 1778 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1779 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 1780 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1781 }, 1782 /* Single ring - provide ring size if multiple rings of this 1783 * type are supported 1784 */ 1785 .reg_size = {}, 1786 .max_size = 1787 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 1788 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 1789 }, 1790 { /* REO_REINJECT */ 1791 .start_ring_id = HAL_SRNG_SW2REO, 1792 .max_rings = 1, 1793 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1794 .lmac_ring = FALSE, 1795 .ring_dir = HAL_SRNG_SRC_RING, 1796 .reg_start = { 1797 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 1798 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1799 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 1800 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1801 }, 1802 /* Single ring - provide ring size if multiple rings of this 1803 * type are supported 1804 */ 1805 .reg_size = {}, 1806 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 1807 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 1808 }, 1809 { /* REO_CMD */ 1810 .start_ring_id = HAL_SRNG_REO_CMD, 1811 .max_rings = 1, 1812 .entry_size = (sizeof(struct tlv_32_hdr) + 1813 sizeof(struct reo_get_queue_stats)) >> 2, 1814 .lmac_ring = FALSE, 1815 .ring_dir = HAL_SRNG_SRC_RING, 1816 .reg_start = { 1817 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 1818 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1819 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 1820 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1821 }, 1822 /* Single ring - provide ring size if multiple rings of this 1823 * type are supported 1824 */ 1825 .reg_size = {}, 1826 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1827 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1828 }, 1829 { /* REO_STATUS */ 1830 .start_ring_id = HAL_SRNG_REO_STATUS, 1831 .max_rings = 1, 1832 .entry_size = (sizeof(struct tlv_32_hdr) + 1833 sizeof(struct reo_get_queue_stats_status)) >> 2, 1834 .lmac_ring = FALSE, 1835 .ring_dir = HAL_SRNG_DST_RING, 1836 .reg_start = { 1837 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 1838 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1839 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 1840 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1841 }, 1842 /* Single ring - provide ring size if multiple rings of this 1843 * type are supported 1844 */ 1845 .reg_size = {}, 1846 .max_size = 1847 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1848 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1849 }, 1850 { /* TCL_DATA */ 1851 .start_ring_id = HAL_SRNG_SW2TCL1, 1852 .max_rings = 3, 1853 .entry_size = (sizeof(struct tlv_32_hdr) + 1854 sizeof(struct tcl_data_cmd)) >> 2, 1855 .lmac_ring = FALSE, 1856 .ring_dir = HAL_SRNG_SRC_RING, 1857 .reg_start = { 1858 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 1859 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1860 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 1861 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1862 }, 1863 .reg_size = { 1864 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 1865 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 1866 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 1867 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 1868 }, 1869 .max_size = 1870 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 1871 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 1872 }, 1873 { /* TCL_CMD/CREDIT */ 1874 /* qca8074v2 and qcn9000 uses this ring for data commands */ 1875 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 1876 .max_rings = 1, 1877 .entry_size = (sizeof(struct tlv_32_hdr) + 1878 sizeof(struct tcl_data_cmd)) >> 2, 1879 .lmac_ring = FALSE, 1880 .ring_dir = HAL_SRNG_SRC_RING, 1881 .reg_start = { 1882 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR( 1883 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1884 HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR( 1885 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1886 }, 1887 /* Single ring - provide ring size if multiple rings of this 1888 * type are supported 1889 */ 1890 .reg_size = {}, 1891 .max_size = 1892 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >> 1893 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT, 1894 }, 1895 { /* TCL_STATUS */ 1896 .start_ring_id = HAL_SRNG_TCL_STATUS, 1897 .max_rings = 1, 1898 .entry_size = (sizeof(struct tlv_32_hdr) + 1899 sizeof(struct tcl_status_ring)) >> 2, 1900 .lmac_ring = FALSE, 1901 .ring_dir = HAL_SRNG_DST_RING, 1902 .reg_start = { 1903 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 1904 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1905 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 1906 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1907 }, 1908 /* Single ring - provide ring size if multiple rings of this 1909 * type are supported 1910 */ 1911 .reg_size = {}, 1912 .max_size = 1913 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 1914 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 1915 }, 1916 { /* CE_SRC */ 1917 .start_ring_id = HAL_SRNG_CE_0_SRC, 1918 .max_rings = 12, 1919 .entry_size = sizeof(struct ce_src_desc) >> 2, 1920 .lmac_ring = FALSE, 1921 .ring_dir = HAL_SRNG_SRC_RING, 1922 .reg_start = { 1923 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1924 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1925 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1926 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1927 }, 1928 .reg_size = { 1929 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1930 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1931 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1932 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1933 }, 1934 .max_size = 1935 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1936 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1937 }, 1938 { /* CE_DST */ 1939 .start_ring_id = HAL_SRNG_CE_0_DST, 1940 .max_rings = 12, 1941 .entry_size = 8 >> 2, 1942 /*TODO: entry_size above should actually be 1943 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 1944 * of struct ce_dst_desc in HW header files 1945 */ 1946 .lmac_ring = FALSE, 1947 .ring_dir = HAL_SRNG_SRC_RING, 1948 .reg_start = { 1949 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1950 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1951 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1952 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1953 }, 1954 .reg_size = { 1955 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1956 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1957 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1958 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1959 }, 1960 .max_size = 1961 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1962 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1963 }, 1964 { /* CE_DST_STATUS */ 1965 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 1966 .max_rings = 12, 1967 .entry_size = sizeof(struct ce_stat_desc) >> 2, 1968 .lmac_ring = FALSE, 1969 .ring_dir = HAL_SRNG_DST_RING, 1970 .reg_start = { 1971 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 1972 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1973 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 1974 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1975 }, 1976 /* TODO: check destination status ring registers */ 1977 .reg_size = { 1978 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1979 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1980 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1981 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1982 }, 1983 .max_size = 1984 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1985 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1986 }, 1987 { /* WBM_IDLE_LINK */ 1988 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 1989 .max_rings = 1, 1990 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 1991 .lmac_ring = FALSE, 1992 .ring_dir = HAL_SRNG_SRC_RING, 1993 .reg_start = { 1994 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1995 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1996 }, 1997 /* Single ring - provide ring size if multiple rings of this 1998 * type are supported 1999 */ 2000 .reg_size = {}, 2001 .max_size = 2002 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 2003 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 2004 }, 2005 { /* SW2WBM_RELEASE */ 2006 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 2007 .max_rings = 1, 2008 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2009 .lmac_ring = FALSE, 2010 .ring_dir = HAL_SRNG_SRC_RING, 2011 .reg_start = { 2012 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2013 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2014 }, 2015 /* Single ring - provide ring size if multiple rings of this 2016 * type are supported 2017 */ 2018 .reg_size = {}, 2019 .max_size = 2020 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2021 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2022 }, 2023 { /* WBM2SW_RELEASE */ 2024 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 2025 .max_rings = 4, 2026 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2027 .lmac_ring = FALSE, 2028 .ring_dir = HAL_SRNG_DST_RING, 2029 .reg_start = { 2030 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2031 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2032 }, 2033 .reg_size = { 2034 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 2035 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2036 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 2037 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2038 }, 2039 .max_size = 2040 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2041 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2042 }, 2043 { /* RXDMA_BUF */ 2044 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 2045 #ifdef IPA_OFFLOAD 2046 .max_rings = 3, 2047 #else 2048 .max_rings = 2, 2049 #endif 2050 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2051 .lmac_ring = TRUE, 2052 .ring_dir = HAL_SRNG_SRC_RING, 2053 /* reg_start is not set because LMAC rings are not accessed 2054 * from host 2055 */ 2056 .reg_start = {}, 2057 .reg_size = {}, 2058 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2059 }, 2060 { /* RXDMA_DST */ 2061 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 2062 .max_rings = 1, 2063 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2064 .lmac_ring = TRUE, 2065 .ring_dir = HAL_SRNG_DST_RING, 2066 /* reg_start is not set because LMAC rings are not accessed 2067 * from host 2068 */ 2069 .reg_start = {}, 2070 .reg_size = {}, 2071 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2072 }, 2073 { /* RXDMA_MONITOR_BUF */ 2074 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 2075 .max_rings = 1, 2076 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2077 .lmac_ring = TRUE, 2078 .ring_dir = HAL_SRNG_SRC_RING, 2079 /* reg_start is not set because LMAC rings are not accessed 2080 * from host 2081 */ 2082 .reg_start = {}, 2083 .reg_size = {}, 2084 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2085 }, 2086 { /* RXDMA_MONITOR_STATUS */ 2087 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 2088 .max_rings = 1, 2089 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2090 .lmac_ring = TRUE, 2091 .ring_dir = HAL_SRNG_SRC_RING, 2092 /* reg_start is not set because LMAC rings are not accessed 2093 * from host 2094 */ 2095 .reg_start = {}, 2096 .reg_size = {}, 2097 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2098 }, 2099 { /* RXDMA_MONITOR_DST */ 2100 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 2101 .max_rings = 1, 2102 .entry_size = sizeof(struct sw_monitor_ring) >> 2, 2103 .lmac_ring = TRUE, 2104 .ring_dir = HAL_SRNG_DST_RING, 2105 /* reg_start is not set because LMAC rings are not accessed 2106 * from host 2107 */ 2108 .reg_start = {}, 2109 .reg_size = {}, 2110 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2111 }, 2112 { /* RXDMA_MONITOR_DESC */ 2113 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 2114 .max_rings = 1, 2115 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2116 .lmac_ring = TRUE, 2117 .ring_dir = HAL_SRNG_SRC_RING, 2118 /* reg_start is not set because LMAC rings are not accessed 2119 * from host 2120 */ 2121 .reg_start = {}, 2122 .reg_size = {}, 2123 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2124 }, 2125 { /* DIR_BUF_RX_DMA_SRC */ 2126 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 2127 /* one ring for spectral and one ring for cfr */ 2128 .max_rings = 2, 2129 .entry_size = 2, 2130 .lmac_ring = TRUE, 2131 .ring_dir = HAL_SRNG_SRC_RING, 2132 /* reg_start is not set because LMAC rings are not accessed 2133 * from host 2134 */ 2135 .reg_start = {}, 2136 .reg_size = {}, 2137 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2138 }, 2139 #ifdef WLAN_FEATURE_CIF_CFR 2140 { /* WIFI_POS_SRC */ 2141 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 2142 .max_rings = 1, 2143 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 2144 .lmac_ring = TRUE, 2145 .ring_dir = HAL_SRNG_SRC_RING, 2146 /* reg_start is not set because LMAC rings are not accessed 2147 * from host 2148 */ 2149 .reg_start = {}, 2150 .reg_size = {}, 2151 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2152 }, 2153 #endif 2154 }; 2155 2156 int32_t hal_hw_reg_offset_qcn9000[] = { 2157 /* dst */ 2158 REG_OFFSET(DST, HP), 2159 REG_OFFSET(DST, TP), 2160 REG_OFFSET(DST, ID), 2161 REG_OFFSET(DST, MISC), 2162 REG_OFFSET(DST, HP_ADDR_LSB), 2163 REG_OFFSET(DST, HP_ADDR_MSB), 2164 REG_OFFSET(DST, MSI1_BASE_LSB), 2165 REG_OFFSET(DST, MSI1_BASE_MSB), 2166 REG_OFFSET(DST, MSI1_DATA), 2167 REG_OFFSET(DST, BASE_LSB), 2168 REG_OFFSET(DST, BASE_MSB), 2169 REG_OFFSET(DST, PRODUCER_INT_SETUP), 2170 /* src */ 2171 REG_OFFSET(SRC, HP), 2172 REG_OFFSET(SRC, TP), 2173 REG_OFFSET(SRC, ID), 2174 REG_OFFSET(SRC, MISC), 2175 REG_OFFSET(SRC, TP_ADDR_LSB), 2176 REG_OFFSET(SRC, TP_ADDR_MSB), 2177 REG_OFFSET(SRC, MSI1_BASE_LSB), 2178 REG_OFFSET(SRC, MSI1_BASE_MSB), 2179 REG_OFFSET(SRC, MSI1_DATA), 2180 REG_OFFSET(SRC, BASE_LSB), 2181 REG_OFFSET(SRC, BASE_MSB), 2182 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX0), 2183 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX1), 2184 }; 2185 2186 /** 2187 * hal_qcn9000_attach()- Attach 9000 target specific hal_soc ops, 2188 * offset and srng table 2189 * Return: void 2190 */ 2191 void hal_qcn9000_attach(struct hal_soc *hal_soc) 2192 { 2193 hal_soc->hw_srng_table = hw_srng_table_9000; 2194 hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qcn9000; 2195 hal_soc->ops = &qcn9000_hal_hw_txrx_ops; 2196 if (hal_soc->static_window_map) 2197 hal_write_window_register(hal_soc); 2198 } 2199