1 /* 2 * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #include "hal_hw_headers.h" 19 #include "hal_internal.h" 20 #include "hal_api.h" 21 #include "target_type.h" 22 #include "wcss_version.h" 23 #include "qdf_module.h" 24 #include "hal_9000_rx.h" 25 #include "hal_api_mon.h" 26 #include "hal_flow.h" 27 #include "rx_flow_search_entry.h" 28 #include "hal_rx_flow_info.h" 29 30 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 31 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET 32 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 33 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK 34 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 35 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB 36 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 37 PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 38 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 39 PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 40 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 41 PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 42 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 43 PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 44 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 45 PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 46 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 47 PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 48 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 49 PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 50 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 51 PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 52 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 53 PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 54 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 55 PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 56 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 57 PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 58 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 59 RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 60 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 61 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 62 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 63 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 64 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 65 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 66 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 67 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 68 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER \ 69 STATUS_HEADER_REO_STATUS_NUMBER 70 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 71 STATUS_HEADER_TIMESTAMP 72 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 73 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 74 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 75 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 76 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 77 TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 78 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 79 TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 80 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 81 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 82 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 83 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 84 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 85 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 86 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 87 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 88 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 89 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 90 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 91 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 92 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 93 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 94 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 95 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 96 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 97 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 98 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 99 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 100 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 101 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 102 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 103 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 104 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 105 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 106 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 107 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 108 109 #define CE_WINDOW_ADDRESS_9000 \ 110 ((CE_WFSS_CE_REG_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) 111 112 #define UMAC_WINDOW_ADDRESS_9000 \ 113 ((SEQ_WCSS_UMAC_OFFSET >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) 114 115 #define WINDOW_CONFIGURATION_VALUE_9000 \ 116 ((CE_WINDOW_ADDRESS_9000 << 6) |\ 117 (UMAC_WINDOW_ADDRESS_9000 << 12) | \ 118 WINDOW_ENABLE_BIT) 119 120 #include <hal_9000_tx.h> 121 #include <hal_9000_rx.h> 122 #include <hal_generic_api.h> 123 #include <hal_wbm.h> 124 125 /** 126 * hal_rx_sw_mon_desc_info_get_9000(): API to read the 127 * sw monitor ring descriptor 128 * 129 * @rxdma_dst_ring_desc: sw monitor ring descriptor 130 * @desc_info_buf: Descriptor info buffer to which 131 * sw monitor ring descriptor is populated to 132 * 133 * Return: void 134 */ 135 static void 136 hal_rx_sw_mon_desc_info_get_9000(hal_ring_desc_t rxdma_dst_ring_desc, 137 hal_rx_mon_desc_info_t desc_info_buf) 138 { 139 struct sw_monitor_ring *sw_mon_ring = 140 (struct sw_monitor_ring *)rxdma_dst_ring_desc; 141 struct buffer_addr_info *buf_addr_info; 142 uint32_t *mpdu_info; 143 uint32_t loop_cnt; 144 struct hal_rx_mon_desc_info *desc_info; 145 146 desc_info = (struct hal_rx_mon_desc_info *)desc_info_buf; 147 mpdu_info = (uint32_t *)&sw_mon_ring-> 148 reo_level_mpdu_frame_info.rx_mpdu_desc_info_details; 149 150 loop_cnt = HAL_RX_GET(sw_mon_ring, SW_MONITOR_RING_7, LOOPING_COUNT); 151 desc_info->msdu_count = HAL_RX_MPDU_MSDU_COUNT_GET(mpdu_info); 152 153 /* Get msdu link descriptor buf_addr_info */ 154 buf_addr_info = &sw_mon_ring-> 155 reo_level_mpdu_frame_info.msdu_link_desc_addr_info; 156 desc_info->link_desc.paddr = HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) 157 | ((uint64_t)(HAL_RX_BUFFER_ADDR_39_32_GET( 158 buf_addr_info)) << 32); 159 desc_info->link_desc.sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info); 160 buf_addr_info = &sw_mon_ring->status_buff_addr_info; 161 desc_info->status_buf.paddr = HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) 162 | ((uint64_t) 163 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32); 164 desc_info->status_buf.sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info); 165 desc_info->end_of_ppdu = HAL_RX_GET(sw_mon_ring, 166 SW_MONITOR_RING_6, 167 END_OF_PPDU); 168 desc_info->status_buf_count = HAL_RX_GET(sw_mon_ring, 169 SW_MONITOR_RING_6, 170 STATUS_BUF_COUNT); 171 desc_info->rxdma_push_reason = HAL_RX_GET(sw_mon_ring, 172 SW_MONITOR_RING_6, 173 RXDMA_PUSH_REASON); 174 desc_info->ppdu_id = HAL_RX_GET(sw_mon_ring, 175 SW_MONITOR_RING_7, 176 PHY_PPDU_ID); 177 } 178 179 /** 180 * hal_rx_msdu_start_nss_get_9000(): API to get the NSS 181 * Interval from rx_msdu_start 182 * 183 * @buf: pointer to the start of RX PKT TLV header 184 * Return: uint32_t(nss) 185 */ 186 static uint32_t hal_rx_msdu_start_nss_get_9000(uint8_t *buf) 187 { 188 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 189 struct rx_msdu_start *msdu_start = 190 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 191 uint8_t mimo_ss_bitmap; 192 193 mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start); 194 195 return qdf_get_hweight8(mimo_ss_bitmap); 196 } 197 198 /** 199 * hal_rx_mon_hw_desc_get_mpdu_status_9000(): Retrieve MPDU status 200 * 201 * @ hw_desc_addr: Start address of Rx HW TLVs 202 * @ rs: Status for monitor mode 203 * 204 * Return: void 205 */ 206 static void hal_rx_mon_hw_desc_get_mpdu_status_9000(void *hw_desc_addr, 207 struct mon_rx_status *rs) 208 { 209 struct rx_msdu_start *rx_msdu_start; 210 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 211 uint32_t reg_value; 212 const uint32_t sgi_hw_to_cdp[] = { 213 CDP_SGI_0_8_US, 214 CDP_SGI_0_4_US, 215 CDP_SGI_1_6_US, 216 CDP_SGI_3_2_US, 217 }; 218 219 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 220 221 HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs); 222 223 rs->ant_signal_db = HAL_RX_GET(rx_msdu_start, 224 RX_MSDU_START_5, USER_RSSI); 225 rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC); 226 227 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI); 228 rs->sgi = sgi_hw_to_cdp[reg_value]; 229 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE); 230 rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0; 231 /* TODO: rs->beamformed should be set for SU beamforming also */ 232 } 233 234 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 235 /** 236 * hal_get_link_desc_size_9000(): API to get the link desc size 237 * 238 * Return: uint32_t 239 */ 240 static uint32_t hal_get_link_desc_size_9000(void) 241 { 242 return LINK_DESC_SIZE; 243 } 244 245 /** 246 * hal_rx_get_tlv_9000(): API to get the tlv 247 * 248 * @rx_tlv: TLV data extracted from the rx packet 249 * Return: uint8_t 250 */ 251 static uint8_t hal_rx_get_tlv_9000(void *rx_tlv) 252 { 253 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH); 254 } 255 256 /** 257 * hal_rx_mpdu_start_tlv_tag_valid_9000 () - API to check if RX_MPDU_START 258 * tlv tag is valid 259 * 260 *@rx_tlv_hdr: start address of rx_pkt_tlvs 261 * 262 * Return: true if RX_MPDU_START is valied, else false. 263 */ 264 uint8_t hal_rx_mpdu_start_tlv_tag_valid_9000(void *rx_tlv_hdr) 265 { 266 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 267 uint32_t tlv_tag; 268 269 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(&rx_desc->mpdu_start_tlv); 270 271 return tlv_tag == WIFIRX_MPDU_START_E ? true : false; 272 } 273 274 /** 275 * hal_rx_wbm_err_msdu_continuation_get_9000 () - API to check if WBM 276 * msdu continuation bit is set 277 * 278 *@wbm_desc: wbm release ring descriptor 279 * 280 * Return: true if msdu continuation bit is set. 281 */ 282 uint8_t hal_rx_wbm_err_msdu_continuation_get_9000(void *wbm_desc) 283 { 284 uint32_t comp_desc = 285 *(uint32_t *)(((uint8_t *)wbm_desc) + 286 WBM_RELEASE_RING_3_MSDU_CONTINUATION_OFFSET); 287 288 return (comp_desc & WBM_RELEASE_RING_3_MSDU_CONTINUATION_MASK) >> 289 WBM_RELEASE_RING_3_MSDU_CONTINUATION_LSB; 290 } 291 292 /** 293 * hal_rx_proc_phyrx_other_receive_info_tlv_9000(): API to get tlv info 294 * 295 * Return: uint32_t 296 */ 297 static inline 298 void hal_rx_proc_phyrx_other_receive_info_tlv_9000(void *rx_tlv_hdr, 299 void *ppdu_info_hdl) 300 { 301 } 302 303 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) 304 static inline 305 void hal_rx_get_bb_info_9000(void *rx_tlv, void *ppdu_info_hdl) 306 { 307 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 308 309 ppdu_info->cfr_info.bb_captured_channel = 310 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_CHANNEL); 311 312 ppdu_info->cfr_info.bb_captured_timeout = 313 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_TIMEOUT); 314 315 ppdu_info->cfr_info.bb_captured_reason = 316 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_REASON); 317 } 318 319 static inline 320 void hal_rx_get_rtt_info_9000(void *rx_tlv, void *ppdu_info_hdl) 321 { 322 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 323 324 ppdu_info->cfr_info.rx_location_info_valid = 325 HAL_RX_GET(rx_tlv, PHYRX_PKT_END_13_RX_PKT_END_DETAILS, 326 RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID); 327 328 ppdu_info->cfr_info.rtt_che_buffer_pointer_low32 = 329 HAL_RX_GET(rx_tlv, 330 PHYRX_PKT_END_12_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 331 RTT_CHE_BUFFER_POINTER_LOW32); 332 333 ppdu_info->cfr_info.rtt_che_buffer_pointer_high8 = 334 HAL_RX_GET(rx_tlv, 335 PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 336 RTT_CHE_BUFFER_POINTER_HIGH8); 337 338 ppdu_info->cfr_info.chan_capture_status = 339 GET_RX_LOCATION_INFO_CHAN_CAPTURE_STATUS(rx_tlv); 340 } 341 #endif 342 /** 343 * hal_rx_dump_msdu_start_tlv_9000() : dump RX msdu_start TLV in structured 344 * human readable format. 345 * @ msdu_start: pointer the msdu_start TLV in pkt. 346 * @ dbg_level: log level. 347 * 348 * Return: void 349 */ 350 static void hal_rx_dump_msdu_start_tlv_9000(void *msdustart, 351 uint8_t dbg_level) 352 { 353 struct rx_msdu_start *msdu_start = (struct rx_msdu_start *)msdustart; 354 355 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 356 "rx_msdu_start tlv - " 357 "rxpcu_mpdu_filter_in_category: %d " 358 "sw_frame_group_id: %d " 359 "phy_ppdu_id: %d " 360 "msdu_length: %d " 361 "ipsec_esp: %d " 362 "l3_offset: %d " 363 "ipsec_ah: %d " 364 "l4_offset: %d " 365 "msdu_number: %d " 366 "decap_format: %d " 367 "ipv4_proto: %d " 368 "ipv6_proto: %d " 369 "tcp_proto: %d " 370 "udp_proto: %d " 371 "ip_frag: %d " 372 "tcp_only_ack: %d " 373 "da_is_bcast_mcast: %d " 374 "ip4_protocol_ip6_next_header: %d " 375 "toeplitz_hash_2_or_4: %d " 376 "flow_id_toeplitz: %d " 377 "user_rssi: %d " 378 "pkt_type: %d " 379 "stbc: %d " 380 "sgi: %d " 381 "rate_mcs: %d " 382 "receive_bandwidth: %d " 383 "reception_type: %d " 384 "ppdu_start_timestamp: %d " 385 "sw_phy_meta_data: %d ", 386 msdu_start->rxpcu_mpdu_filter_in_category, 387 msdu_start->sw_frame_group_id, 388 msdu_start->phy_ppdu_id, 389 msdu_start->msdu_length, 390 msdu_start->ipsec_esp, 391 msdu_start->l3_offset, 392 msdu_start->ipsec_ah, 393 msdu_start->l4_offset, 394 msdu_start->msdu_number, 395 msdu_start->decap_format, 396 msdu_start->ipv4_proto, 397 msdu_start->ipv6_proto, 398 msdu_start->tcp_proto, 399 msdu_start->udp_proto, 400 msdu_start->ip_frag, 401 msdu_start->tcp_only_ack, 402 msdu_start->da_is_bcast_mcast, 403 msdu_start->ip4_protocol_ip6_next_header, 404 msdu_start->toeplitz_hash_2_or_4, 405 msdu_start->flow_id_toeplitz, 406 msdu_start->user_rssi, 407 msdu_start->pkt_type, 408 msdu_start->stbc, 409 msdu_start->sgi, 410 msdu_start->rate_mcs, 411 msdu_start->receive_bandwidth, 412 msdu_start->reception_type, 413 msdu_start->ppdu_start_timestamp, 414 msdu_start->sw_phy_meta_data); 415 } 416 417 /** 418 * hal_rx_dump_msdu_end_tlv_9000: dump RX msdu_end TLV in structured 419 * human readable format. 420 * @ msdu_end: pointer the msdu_end TLV in pkt. 421 * @ dbg_level: log level. 422 * 423 * Return: void 424 */ 425 static void hal_rx_dump_msdu_end_tlv_9000(void *msduend, 426 uint8_t dbg_level) 427 { 428 struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend; 429 430 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 431 "rx_msdu_end tlv - " 432 "rxpcu_mpdu_filter_in_category: %d " 433 "sw_frame_group_id: %d " 434 "phy_ppdu_id: %d " 435 "ip_hdr_chksum: %d " 436 "reported_mpdu_length: %d " 437 "key_id_octet: %d " 438 "cce_super_rule: %d " 439 "cce_classify_not_done_truncat: %d " 440 "cce_classify_not_done_cce_dis: %d " 441 "rule_indication_31_0: %d " 442 "rule_indication_63_32: %d " 443 "da_offset: %d " 444 "sa_offset: %d " 445 "da_offset_valid: %d " 446 "sa_offset_valid: %d " 447 "ipv6_options_crc: %d " 448 "tcp_seq_number: %d " 449 "tcp_ack_number: %d " 450 "tcp_flag: %d " 451 "lro_eligible: %d " 452 "window_size: %d " 453 "tcp_udp_chksum: %d " 454 "sa_idx_timeout: %d " 455 "da_idx_timeout: %d " 456 "msdu_limit_error: %d " 457 "flow_idx_timeout: %d " 458 "flow_idx_invalid: %d " 459 "wifi_parser_error: %d " 460 "amsdu_parser_error: %d " 461 "sa_is_valid: %d " 462 "da_is_valid: %d " 463 "da_is_mcbc: %d " 464 "l3_header_padding: %d " 465 "first_msdu: %d " 466 "last_msdu: %d " 467 "sa_idx: %d " 468 "msdu_drop: %d " 469 "reo_destination_indication: %d " 470 "flow_idx: %d " 471 "fse_metadata: %d " 472 "cce_metadata: %d " 473 "sa_sw_peer_id: %d ", 474 msdu_end->rxpcu_mpdu_filter_in_category, 475 msdu_end->sw_frame_group_id, 476 msdu_end->phy_ppdu_id, 477 msdu_end->ip_hdr_chksum, 478 msdu_end->reported_mpdu_length, 479 msdu_end->key_id_octet, 480 msdu_end->cce_super_rule, 481 msdu_end->cce_classify_not_done_truncate, 482 msdu_end->cce_classify_not_done_cce_dis, 483 msdu_end->rule_indication_31_0, 484 msdu_end->rule_indication_63_32, 485 msdu_end->da_offset, 486 msdu_end->sa_offset, 487 msdu_end->da_offset_valid, 488 msdu_end->sa_offset_valid, 489 msdu_end->ipv6_options_crc, 490 msdu_end->tcp_seq_number, 491 msdu_end->tcp_ack_number, 492 msdu_end->tcp_flag, 493 msdu_end->lro_eligible, 494 msdu_end->window_size, 495 msdu_end->tcp_udp_chksum, 496 msdu_end->sa_idx_timeout, 497 msdu_end->da_idx_timeout, 498 msdu_end->msdu_limit_error, 499 msdu_end->flow_idx_timeout, 500 msdu_end->flow_idx_invalid, 501 msdu_end->wifi_parser_error, 502 msdu_end->amsdu_parser_error, 503 msdu_end->sa_is_valid, 504 msdu_end->da_is_valid, 505 msdu_end->da_is_mcbc, 506 msdu_end->l3_header_padding, 507 msdu_end->first_msdu, 508 msdu_end->last_msdu, 509 msdu_end->sa_idx, 510 msdu_end->msdu_drop, 511 msdu_end->reo_destination_indication, 512 msdu_end->flow_idx, 513 msdu_end->fse_metadata, 514 msdu_end->cce_metadata, 515 msdu_end->sa_sw_peer_id); 516 } 517 518 /** 519 * hal_rx_mpdu_start_tid_get_9000(): API to get tid 520 * from rx_msdu_start 521 * 522 * @buf: pointer to the start of RX PKT TLV header 523 * Return: uint32_t(tid value) 524 */ 525 static uint32_t hal_rx_mpdu_start_tid_get_9000(uint8_t *buf) 526 { 527 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 528 struct rx_mpdu_start *mpdu_start = 529 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 530 uint32_t tid; 531 532 tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details); 533 534 return tid; 535 } 536 537 /** 538 * hal_rx_msdu_start_reception_type_get(): API to get the reception type 539 * Interval from rx_msdu_start 540 * 541 * @buf: pointer to the start of RX PKT TLV header 542 * Return: uint32_t(reception_type) 543 */ 544 static uint32_t hal_rx_msdu_start_reception_type_get_9000(uint8_t *buf) 545 { 546 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 547 struct rx_msdu_start *msdu_start = 548 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 549 uint32_t reception_type; 550 551 reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start); 552 553 return reception_type; 554 } 555 556 /** 557 * hal_rx_msdu_end_da_idx_get_9000: API to get da_idx 558 * from rx_msdu_end TLV 559 * 560 * @ buf: pointer to the start of RX PKT TLV headers 561 * Return: da index 562 */ 563 static uint16_t hal_rx_msdu_end_da_idx_get_9000(uint8_t *buf) 564 { 565 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 566 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 567 uint16_t da_idx; 568 569 da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 570 571 return da_idx; 572 } 573 574 /** 575 * hal_rx_get_rx_fragment_number_9000(): Function to retrieve rx fragment number 576 * 577 * @nbuf: Network buffer 578 * Returns: rx fragment number 579 */ 580 static 581 uint8_t hal_rx_get_rx_fragment_number_9000(uint8_t *buf) 582 { 583 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 584 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 585 586 /* Return first 4 bits as fragment number */ 587 return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & 588 DOT11_SEQ_FRAG_MASK); 589 } 590 591 /** 592 * hal_rx_msdu_end_da_is_mcbc_get_9000(): API to check if pkt is MCBC 593 * from rx_msdu_end TLV 594 * 595 * @ buf: pointer to the start of RX PKT TLV headers 596 * Return: da_is_mcbc 597 */ 598 static uint8_t 599 hal_rx_msdu_end_da_is_mcbc_get_9000(uint8_t *buf) 600 { 601 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 602 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 603 604 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); 605 } 606 607 /** 608 * hal_rx_msdu_end_sa_is_valid_get_9000(): API to get_9000 the 609 * sa_is_valid bit from rx_msdu_end TLV 610 * 611 * @ buf: pointer to the start of RX PKT TLV headers 612 * Return: sa_is_valid bit 613 */ 614 static uint8_t 615 hal_rx_msdu_end_sa_is_valid_get_9000(uint8_t *buf) 616 { 617 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 618 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 619 uint8_t sa_is_valid; 620 621 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); 622 623 return sa_is_valid; 624 } 625 626 /** 627 * hal_rx_msdu_end_sa_idx_get_9000(): API to get_9000 the 628 * sa_idx from rx_msdu_end TLV 629 * 630 * @ buf: pointer to the start of RX PKT TLV headers 631 * Return: sa_idx (SA AST index) 632 */ 633 static uint16_t hal_rx_msdu_end_sa_idx_get_9000(uint8_t *buf) 634 { 635 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 636 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 637 uint16_t sa_idx; 638 639 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 640 641 return sa_idx; 642 } 643 644 /** 645 * hal_rx_desc_is_first_msdu_9000() - Check if first msdu 646 * 647 * @hal_soc_hdl: hal_soc handle 648 * @hw_desc_addr: hardware descriptor address 649 * 650 * Return: 0 - success/ non-zero failure 651 */ 652 static uint32_t hal_rx_desc_is_first_msdu_9000(void *hw_desc_addr) 653 { 654 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; 655 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; 656 657 return HAL_RX_GET(msdu_end, RX_MSDU_END_10, FIRST_MSDU); 658 } 659 660 /** 661 * hal_rx_msdu_end_l3_hdr_padding_get_9000(): API to get_9000 the 662 * l3_header padding from rx_msdu_end TLV 663 * 664 * @ buf: pointer to the start of RX PKT TLV headers 665 * Return: number of l3 header padding bytes 666 */ 667 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_9000(uint8_t *buf) 668 { 669 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 670 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 671 uint32_t l3_header_padding; 672 673 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 674 675 return l3_header_padding; 676 } 677 678 /** 679 * @ hal_rx_encryption_info_valid_9000: Returns encryption type. 680 * 681 * @ buf: rx_tlv_hdr of the received packet 682 * @ Return: encryption type 683 */ 684 inline uint32_t hal_rx_encryption_info_valid_9000(uint8_t *buf) 685 { 686 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 687 struct rx_mpdu_start *mpdu_start = 688 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 689 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 690 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); 691 692 return encryption_info; 693 } 694 695 /* 696 * @ hal_rx_print_pn_9000: Prints the PN of rx packet. 697 * 698 * @ buf: rx_tlv_hdr of the received packet 699 * @ Return: void 700 */ 701 static void hal_rx_print_pn_9000(uint8_t *buf) 702 { 703 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 704 struct rx_mpdu_start *mpdu_start = 705 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 706 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 707 708 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); 709 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); 710 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); 711 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); 712 713 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ", 714 pn_127_96, pn_95_64, pn_63_32, pn_31_0); 715 } 716 717 /** 718 * hal_rx_msdu_end_first_msdu_get_9000: API to get first msdu status 719 * from rx_msdu_end TLV 720 * 721 * @ buf: pointer to the start of RX PKT TLV headers 722 * Return: first_msdu 723 */ 724 static uint8_t hal_rx_msdu_end_first_msdu_get_9000(uint8_t *buf) 725 { 726 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 727 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 728 uint8_t first_msdu; 729 730 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); 731 732 return first_msdu; 733 } 734 735 /** 736 * hal_rx_msdu_end_da_is_valid_get_9000: API to check if da is valid 737 * from rx_msdu_end TLV 738 * 739 * @ buf: pointer to the start of RX PKT TLV headers 740 * Return: da_is_valid 741 */ 742 static uint8_t hal_rx_msdu_end_da_is_valid_get_9000(uint8_t *buf) 743 { 744 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 745 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 746 uint8_t da_is_valid; 747 748 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); 749 750 return da_is_valid; 751 } 752 753 /** 754 * hal_rx_msdu_end_last_msdu_get_9000: API to get last msdu status 755 * from rx_msdu_end TLV 756 * 757 * @ buf: pointer to the start of RX PKT TLV headers 758 * Return: last_msdu 759 */ 760 static uint8_t hal_rx_msdu_end_last_msdu_get_9000(uint8_t *buf) 761 { 762 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 763 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 764 uint8_t last_msdu; 765 766 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); 767 768 return last_msdu; 769 } 770 771 /* 772 * hal_rx_get_mpdu_mac_ad4_valid(): Retrieves if mpdu 4th addr is valid 773 * 774 * @nbuf: Network buffer 775 * Returns: value of mpdu 4th address valid field 776 */ 777 inline bool hal_rx_get_mpdu_mac_ad4_valid_9000(uint8_t *buf) 778 { 779 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 780 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 781 bool ad4_valid = 0; 782 783 ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(rx_mpdu_info); 784 785 return ad4_valid; 786 } 787 788 /** 789 * hal_rx_mpdu_start_sw_peer_id_get_9000: Retrieve sw peer_id 790 * @buf: network buffer 791 * 792 * Return: sw peer_id 793 */ 794 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_9000(uint8_t *buf) 795 { 796 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 797 struct rx_mpdu_start *mpdu_start = 798 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 799 800 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET( 801 &mpdu_start->rx_mpdu_info_details); 802 } 803 804 /* 805 * hal_rx_mpdu_get_to_ds_9000(): API to get the tods info 806 * from rx_mpdu_start 807 * 808 * @buf: pointer to the start of RX PKT TLV header 809 * Return: uint32_t(to_ds) 810 */ 811 static uint32_t hal_rx_mpdu_get_to_ds_9000(uint8_t *buf) 812 { 813 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 814 struct rx_mpdu_start *mpdu_start = 815 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 816 817 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 818 819 return HAL_RX_MPDU_GET_TODS(mpdu_info); 820 } 821 822 /* 823 * hal_rx_mpdu_get_fr_ds_9000(): API to get the from ds info 824 * from rx_mpdu_start 825 * 826 * @buf: pointer to the start of RX PKT TLV header 827 * Return: uint32_t(fr_ds) 828 */ 829 static uint32_t hal_rx_mpdu_get_fr_ds_9000(uint8_t *buf) 830 { 831 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 832 struct rx_mpdu_start *mpdu_start = 833 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 834 835 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 836 837 return HAL_RX_MPDU_GET_FROMDS(mpdu_info); 838 } 839 840 /* 841 * hal_rx_get_mpdu_frame_control_valid_9000(): Retrieves mpdu 842 * frame control valid 843 * 844 * @nbuf: Network buffer 845 * Returns: value of frame control valid field 846 */ 847 static uint8_t hal_rx_get_mpdu_frame_control_valid_9000(uint8_t *buf) 848 { 849 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 850 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 851 852 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); 853 } 854 855 /* 856 * hal_rx_mpdu_get_addr1_9000(): API to check get address1 of the mpdu 857 * 858 * @buf: pointer to the start of RX PKT TLV headera 859 * @mac_addr: pointer to mac address 860 * Return: success/failure 861 */ 862 static QDF_STATUS hal_rx_mpdu_get_addr1_9000(uint8_t *buf, 863 uint8_t *mac_addr) 864 { 865 struct __attribute__((__packed__)) hal_addr1 { 866 uint32_t ad1_31_0; 867 uint16_t ad1_47_32; 868 }; 869 870 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 871 struct rx_mpdu_start *mpdu_start = 872 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 873 874 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 875 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; 876 uint32_t mac_addr_ad1_valid; 877 878 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); 879 880 if (mac_addr_ad1_valid) { 881 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); 882 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); 883 return QDF_STATUS_SUCCESS; 884 } 885 886 return QDF_STATUS_E_FAILURE; 887 } 888 889 /* 890 * hal_rx_mpdu_get_addr2_9000(): API to check get address2 of the mpdu 891 * in the packet 892 * 893 * @buf: pointer to the start of RX PKT TLV header 894 * @mac_addr: pointer to mac address 895 * Return: success/failure 896 */ 897 static QDF_STATUS hal_rx_mpdu_get_addr2_9000(uint8_t *buf, uint8_t *mac_addr) 898 { 899 struct __attribute__((__packed__)) hal_addr2 { 900 uint16_t ad2_15_0; 901 uint32_t ad2_47_16; 902 }; 903 904 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 905 struct rx_mpdu_start *mpdu_start = 906 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 907 908 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 909 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; 910 uint32_t mac_addr_ad2_valid; 911 912 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); 913 914 if (mac_addr_ad2_valid) { 915 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); 916 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); 917 return QDF_STATUS_SUCCESS; 918 } 919 920 return QDF_STATUS_E_FAILURE; 921 } 922 923 /* 924 * hal_rx_mpdu_get_addr3_9000(): API to get address3 of the mpdu 925 * in the packet 926 * 927 * @buf: pointer to the start of RX PKT TLV header 928 * @mac_addr: pointer to mac address 929 * Return: success/failure 930 */ 931 static QDF_STATUS hal_rx_mpdu_get_addr3_9000(uint8_t *buf, uint8_t *mac_addr) 932 { 933 struct __attribute__((__packed__)) hal_addr3 { 934 uint32_t ad3_31_0; 935 uint16_t ad3_47_32; 936 }; 937 938 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 939 struct rx_mpdu_start *mpdu_start = 940 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 941 942 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 943 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; 944 uint32_t mac_addr_ad3_valid; 945 946 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); 947 948 if (mac_addr_ad3_valid) { 949 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); 950 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); 951 return QDF_STATUS_SUCCESS; 952 } 953 954 return QDF_STATUS_E_FAILURE; 955 } 956 957 /* 958 * hal_rx_mpdu_get_addr4_9000(): API to get address4 of the mpdu 959 * in the packet 960 * 961 * @buf: pointer to the start of RX PKT TLV header 962 * @mac_addr: pointer to mac address 963 * Return: success/failure 964 */ 965 static QDF_STATUS hal_rx_mpdu_get_addr4_9000(uint8_t *buf, uint8_t *mac_addr) 966 { 967 struct __attribute__((__packed__)) hal_addr4 { 968 uint32_t ad4_31_0; 969 uint16_t ad4_47_32; 970 }; 971 972 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 973 struct rx_mpdu_start *mpdu_start = 974 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 975 976 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 977 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; 978 uint32_t mac_addr_ad4_valid; 979 980 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); 981 982 if (mac_addr_ad4_valid) { 983 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); 984 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); 985 return QDF_STATUS_SUCCESS; 986 } 987 988 return QDF_STATUS_E_FAILURE; 989 } 990 991 /* 992 * hal_rx_get_mpdu_sequence_control_valid_9000(): Get mpdu 993 * sequence control valid 994 * 995 * @nbuf: Network buffer 996 * Returns: value of sequence control valid field 997 */ 998 static uint8_t hal_rx_get_mpdu_sequence_control_valid_9000(uint8_t *buf) 999 { 1000 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 1001 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 1002 1003 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); 1004 } 1005 1006 /** 1007 * hal_rx_is_unicast_9000: check packet is unicast frame or not. 1008 * 1009 * @ buf: pointer to rx pkt TLV. 1010 * 1011 * Return: true on unicast. 1012 */ 1013 static bool hal_rx_is_unicast_9000(uint8_t *buf) 1014 { 1015 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1016 struct rx_mpdu_start *mpdu_start = 1017 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1018 uint32_t grp_id; 1019 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 1020 1021 grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 1022 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_OFFSET)), 1023 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_MASK, 1024 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_LSB)); 1025 1026 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false; 1027 } 1028 1029 /** 1030 * hal_rx_tid_get_9000: get tid based on qos control valid. 1031 * @hal_soc_hdl: hal soc handle 1032 * @buf: pointer to rx pkt TLV. 1033 * 1034 * Return: tid 1035 */ 1036 static uint32_t hal_rx_tid_get_9000(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1037 { 1038 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1039 struct rx_mpdu_start *mpdu_start = 1040 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1041 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 1042 uint8_t qos_control_valid = 1043 (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 1044 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_OFFSET)), 1045 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_MASK, 1046 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_LSB)); 1047 1048 if (qos_control_valid) 1049 return hal_rx_mpdu_start_tid_get_9000(buf); 1050 1051 return HAL_RX_NON_QOS_TID; 1052 } 1053 1054 /** 1055 * hal_rx_hw_desc_get_ppduid_get_9000(): retrieve ppdu id 1056 * @rx_tlv_hdr: rx tlv header 1057 * @rxdma_dst_ring_desc: rxdma HW descriptor 1058 * 1059 * Return: ppdu id 1060 */ 1061 static uint32_t hal_rx_hw_desc_get_ppduid_get_9000(void *rx_tlv_hdr, 1062 void *rxdma_dst_ring_desc) 1063 { 1064 struct reo_entrance_ring *reo_ent = rxdma_dst_ring_desc; 1065 1066 return reo_ent->phy_ppdu_id; 1067 } 1068 1069 /** 1070 * hal_reo_status_get_header_9000 - Process reo desc info 1071 * @d - Pointer to reo descriptior 1072 * @b - tlv type info 1073 * @h1 - Pointer to hal_reo_status_header where info to be stored 1074 * 1075 * Return - none. 1076 * 1077 */ 1078 static void hal_reo_status_get_header_9000(uint32_t *d, int b, void *h1) 1079 { 1080 uint32_t val1 = 0; 1081 struct hal_reo_status_header *h = 1082 (struct hal_reo_status_header *)h1; 1083 1084 switch (b) { 1085 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1086 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, 1087 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1088 break; 1089 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1090 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, 1091 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1092 break; 1093 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1094 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, 1095 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1096 break; 1097 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1098 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, 1099 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1100 break; 1101 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1102 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, 1103 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1104 break; 1105 case HAL_REO_DESC_THRES_STATUS_TLV: 1106 val1 = 1107 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, 1108 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1109 break; 1110 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1111 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, 1112 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1113 break; 1114 default: 1115 qdf_nofl_err("ERROR: Unknown tlv\n"); 1116 break; 1117 } 1118 h->cmd_num = 1119 HAL_GET_FIELD( 1120 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, 1121 val1); 1122 h->exec_time = 1123 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1124 CMD_EXECUTION_TIME, val1); 1125 h->status = 1126 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1127 REO_CMD_EXECUTION_STATUS, val1); 1128 switch (b) { 1129 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1130 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, 1131 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1132 break; 1133 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1134 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, 1135 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1136 break; 1137 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1138 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, 1139 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1140 break; 1141 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1142 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, 1143 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1144 break; 1145 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1146 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, 1147 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1148 break; 1149 case HAL_REO_DESC_THRES_STATUS_TLV: 1150 val1 = 1151 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, 1152 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1153 break; 1154 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1155 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, 1156 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1157 break; 1158 default: 1159 qdf_nofl_err("ERROR: Unknown tlv\n"); 1160 break; 1161 } 1162 h->tstamp = 1163 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); 1164 } 1165 1166 /** 1167 * hal_rx_mpdu_start_mpdu_qos_control_valid_get_9000(): 1168 * Retrieve qos control valid bit from the tlv. 1169 * @buf: pointer to rx pkt TLV. 1170 * 1171 * Return: qos control value. 1172 */ 1173 static inline uint32_t 1174 hal_rx_mpdu_start_mpdu_qos_control_valid_get_9000(uint8_t *buf) 1175 { 1176 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1177 struct rx_mpdu_start *mpdu_start = 1178 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1179 1180 return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET( 1181 &mpdu_start->rx_mpdu_info_details); 1182 } 1183 1184 /** 1185 * hal_rx_msdu_end_sa_sw_peer_id_get_9000(): API to get the 1186 * sa_sw_peer_id from rx_msdu_end TLV 1187 * @buf: pointer to the start of RX PKT TLV headers 1188 * 1189 * Return: sa_sw_peer_id index 1190 */ 1191 static inline uint32_t 1192 hal_rx_msdu_end_sa_sw_peer_id_get_9000(uint8_t *buf) 1193 { 1194 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1195 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1196 1197 return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 1198 } 1199 1200 /** 1201 * hal_tx_desc_set_mesh_en_9000 - Set mesh_enable flag in Tx descriptor 1202 * @desc: Handle to Tx Descriptor 1203 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 1204 * enabling the interpretation of the 'Mesh Control Present' bit 1205 * (bit 8) of QoS Control (otherwise this bit is ignored), 1206 * For native WiFi frames, this indicates that a 'Mesh Control' field 1207 * is present between the header and the LLC. 1208 * 1209 * Return: void 1210 */ 1211 static inline 1212 void hal_tx_desc_set_mesh_en_9000(void *desc, uint8_t en) 1213 { 1214 HAL_SET_FLD(desc, TCL_DATA_CMD_5, MESH_ENABLE) |= 1215 HAL_TX_SM(TCL_DATA_CMD_5, MESH_ENABLE, en); 1216 } 1217 1218 static 1219 void *hal_rx_msdu0_buffer_addr_lsb_9000(void *link_desc_va) 1220 { 1221 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 1222 } 1223 1224 static 1225 void *hal_rx_msdu_desc_info_ptr_get_9000(void *msdu0) 1226 { 1227 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 1228 } 1229 1230 static 1231 void *hal_ent_mpdu_desc_info_9000(void *ent_ring_desc) 1232 { 1233 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 1234 } 1235 1236 static 1237 void *hal_dst_mpdu_desc_info_9000(void *dst_ring_desc) 1238 { 1239 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 1240 } 1241 1242 static 1243 uint8_t hal_rx_get_fc_valid_9000(uint8_t *buf) 1244 { 1245 return HAL_RX_GET_FC_VALID(buf); 1246 } 1247 1248 static uint8_t hal_rx_get_to_ds_flag_9000(uint8_t *buf) 1249 { 1250 return HAL_RX_GET_TO_DS_FLAG(buf); 1251 } 1252 1253 static uint8_t hal_rx_get_mac_addr2_valid_9000(uint8_t *buf) 1254 { 1255 return HAL_RX_GET_MAC_ADDR2_VALID(buf); 1256 } 1257 1258 static uint8_t hal_rx_get_filter_category_9000(uint8_t *buf) 1259 { 1260 return HAL_RX_GET_FILTER_CATEGORY(buf); 1261 } 1262 1263 static uint32_t 1264 hal_rx_get_ppdu_id_9000(uint8_t *buf) 1265 { 1266 struct rx_mpdu_info *rx_mpdu_info; 1267 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)buf; 1268 1269 rx_mpdu_info = 1270 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 1271 1272 return HAL_RX_GET_PPDU_ID(rx_mpdu_info); 1273 } 1274 1275 /** 1276 * hal_reo_config_9000(): Set reo config parameters 1277 * @soc: hal soc handle 1278 * @reg_val: value to be set 1279 * @reo_params: reo parameters 1280 * 1281 * Return: void 1282 */ 1283 static void 1284 hal_reo_config_9000(struct hal_soc *soc, 1285 uint32_t reg_val, 1286 struct hal_reo_params *reo_params) 1287 { 1288 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 1289 } 1290 1291 /** 1292 * hal_rx_msdu_desc_info_get_ptr_9000() - Get msdu desc info ptr 1293 * @msdu_details_ptr - Pointer to msdu_details_ptr 1294 * 1295 * Return - Pointer to rx_msdu_desc_info structure. 1296 * 1297 */ 1298 static void *hal_rx_msdu_desc_info_get_ptr_9000(void *msdu_details_ptr) 1299 { 1300 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 1301 } 1302 1303 /** 1304 * hal_rx_link_desc_msdu0_ptr_9000 - Get pointer to rx_msdu details 1305 * @link_desc - Pointer to link desc 1306 * 1307 * Return - Pointer to rx_msdu_details structure 1308 * 1309 */ 1310 static void *hal_rx_link_desc_msdu0_ptr_9000(void *link_desc) 1311 { 1312 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 1313 } 1314 1315 /** 1316 * hal_rx_msdu_flow_idx_get_9000: API to get flow index 1317 * from rx_msdu_end TLV 1318 * @buf: pointer to the start of RX PKT TLV headers 1319 * 1320 * Return: flow index value from MSDU END TLV 1321 */ 1322 static inline uint32_t hal_rx_msdu_flow_idx_get_9000(uint8_t *buf) 1323 { 1324 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1325 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1326 1327 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 1328 } 1329 1330 /** 1331 * hal_rx_msdu_flow_idx_invalid_9000: API to get flow index invalid 1332 * from rx_msdu_end TLV 1333 * @buf: pointer to the start of RX PKT TLV headers 1334 * 1335 * Return: flow index invalid value from MSDU END TLV 1336 */ 1337 static bool hal_rx_msdu_flow_idx_invalid_9000(uint8_t *buf) 1338 { 1339 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1340 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1341 1342 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 1343 } 1344 1345 /** 1346 * hal_rx_msdu_flow_idx_timeout_9000: API to get flow index timeout 1347 * from rx_msdu_end TLV 1348 * @buf: pointer to the start of RX PKT TLV headers 1349 * 1350 * Return: flow index timeout value from MSDU END TLV 1351 */ 1352 static bool hal_rx_msdu_flow_idx_timeout_9000(uint8_t *buf) 1353 { 1354 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1355 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1356 1357 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 1358 } 1359 1360 /** 1361 * hal_rx_msdu_fse_metadata_get_9000: API to get FSE metadata 1362 * from rx_msdu_end TLV 1363 * @buf: pointer to the start of RX PKT TLV headers 1364 * 1365 * Return: fse metadata value from MSDU END TLV 1366 */ 1367 static uint32_t hal_rx_msdu_fse_metadata_get_9000(uint8_t *buf) 1368 { 1369 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1370 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1371 1372 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end); 1373 } 1374 1375 /** 1376 * hal_rx_msdu_cce_metadata_get_9000: API to get CCE metadata 1377 * from rx_msdu_end TLV 1378 * @buf: pointer to the start of RX PKT TLV headers 1379 * 1380 * Return: cce_metadata 1381 */ 1382 static uint16_t 1383 hal_rx_msdu_cce_metadata_get_9000(uint8_t *buf) 1384 { 1385 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1386 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1387 1388 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end); 1389 } 1390 1391 /** 1392 * hal_rx_msdu_get_flow_params_9000: API to get flow index, flow index invalid 1393 * and flow index timeout from rx_msdu_end TLV 1394 * @buf: pointer to the start of RX PKT TLV headers 1395 * @flow_invalid: pointer to return value of flow_idx_valid 1396 * @flow_timeout: pointer to return value of flow_idx_timeout 1397 * @flow_index: pointer to return value of flow_idx 1398 * 1399 * Return: none 1400 */ 1401 static inline void 1402 hal_rx_msdu_get_flow_params_9000(uint8_t *buf, 1403 bool *flow_invalid, 1404 bool *flow_timeout, 1405 uint32_t *flow_index) 1406 { 1407 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1408 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1409 1410 *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 1411 *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 1412 *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 1413 } 1414 1415 /** 1416 * hal_rx_tlv_get_tcp_chksum_9000() - API to get tcp checksum 1417 * @buf: rx_tlv_hdr 1418 * 1419 * Return: tcp checksum 1420 */ 1421 static uint16_t 1422 hal_rx_tlv_get_tcp_chksum_9000(uint8_t *buf) 1423 { 1424 return HAL_RX_TLV_GET_TCP_CHKSUM(buf); 1425 } 1426 1427 /** 1428 * hal_rx_get_rx_sequence_9000(): Function to retrieve rx sequence number 1429 * 1430 * @nbuf: Network buffer 1431 * Returns: rx sequence number 1432 */ 1433 static 1434 uint16_t hal_rx_get_rx_sequence_9000(uint8_t *buf) 1435 { 1436 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 1437 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 1438 1439 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info); 1440 } 1441 1442 /** 1443 * hal_get_window_address_9000(): Function to get hp/tp address 1444 * @hal_soc: Pointer to hal_soc 1445 * @addr: address offset of register 1446 * 1447 * Return: modified address offset of register 1448 */ 1449 static inline qdf_iomem_t hal_get_window_address_9000(struct hal_soc *hal_soc, 1450 qdf_iomem_t addr) 1451 { 1452 uint32_t offset = addr - hal_soc->dev_base_addr; 1453 qdf_iomem_t new_offset; 1454 1455 /* 1456 * If offset lies within DP register range, use 3rd window to write 1457 * into DP region. 1458 */ 1459 if ((offset ^ SEQ_WCSS_UMAC_OFFSET) < WINDOW_RANGE_MASK) { 1460 new_offset = (hal_soc->dev_base_addr + (3 * WINDOW_START) + 1461 (offset & WINDOW_RANGE_MASK)); 1462 /* 1463 * If offset lies within CE register range, use 2nd window to write 1464 * into CE region. 1465 */ 1466 } else if ((offset ^ CE_WFSS_CE_REG_BASE) < WINDOW_RANGE_MASK) { 1467 new_offset = (hal_soc->dev_base_addr + (2 * WINDOW_START) + 1468 (offset & WINDOW_RANGE_MASK)); 1469 } else { 1470 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 1471 "%s: ERROR: Accessing Wrong register\n", __func__); 1472 qdf_assert_always(0); 1473 return 0; 1474 } 1475 return new_offset; 1476 } 1477 1478 static inline void hal_write_window_register(struct hal_soc *hal_soc) 1479 { 1480 /* Write value into window configuration register */ 1481 qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_REG_ADDRESS, 1482 WINDOW_CONFIGURATION_VALUE_9000); 1483 } 1484 1485 /** 1486 * hal_rx_msdu_packet_metadata_get_9000(): API to get the 1487 * msdu information from rx_msdu_end TLV 1488 * 1489 * @ buf: pointer to the start of RX PKT TLV headers 1490 * @ hal_rx_msdu_metadata: pointer to the msdu info structure 1491 */ 1492 static void 1493 hal_rx_msdu_packet_metadata_get_9000(uint8_t *buf, 1494 void *msdu_pkt_metadata) 1495 { 1496 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1497 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1498 struct hal_rx_msdu_metadata *msdu_metadata = 1499 (struct hal_rx_msdu_metadata *)msdu_pkt_metadata; 1500 1501 msdu_metadata->l3_hdr_pad = 1502 HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 1503 msdu_metadata->sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 1504 msdu_metadata->da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 1505 msdu_metadata->sa_sw_peer_id = 1506 HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 1507 } 1508 1509 /** 1510 * hal_rx_flow_setup_fse_9000() - Setup a flow search entry in HW FST 1511 * @fst: Pointer to the Rx Flow Search Table 1512 * @table_offset: offset into the table where the flow is to be setup 1513 * @flow: Flow Parameters 1514 * 1515 * Return: Success/Failure 1516 */ 1517 static void * 1518 hal_rx_flow_setup_fse_9000(uint8_t *rx_fst, uint32_t table_offset, 1519 uint8_t *rx_flow) 1520 { 1521 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 1522 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 1523 uint8_t *fse; 1524 bool fse_valid; 1525 1526 if (table_offset >= fst->max_entries) { 1527 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 1528 "HAL FSE table offset %u exceeds max entries %u", 1529 table_offset, fst->max_entries); 1530 return NULL; 1531 } 1532 1533 fse = (uint8_t *)fst->base_vaddr + 1534 (table_offset * HAL_RX_FST_ENTRY_SIZE); 1535 1536 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1537 1538 if (fse_valid) { 1539 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 1540 "HAL FSE %pK already valid", fse); 1541 return NULL; 1542 } 1543 1544 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96) = 1545 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96, 1546 qdf_htonl(flow->tuple_info.src_ip_127_96)); 1547 1548 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64) = 1549 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64, 1550 qdf_htonl(flow->tuple_info.src_ip_95_64)); 1551 1552 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32) = 1553 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32, 1554 qdf_htonl(flow->tuple_info.src_ip_63_32)); 1555 1556 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0) = 1557 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0, 1558 qdf_htonl(flow->tuple_info.src_ip_31_0)); 1559 1560 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96) = 1561 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96, 1562 qdf_htonl(flow->tuple_info.dest_ip_127_96)); 1563 1564 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64) = 1565 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64, 1566 qdf_htonl(flow->tuple_info.dest_ip_95_64)); 1567 1568 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32) = 1569 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32, 1570 qdf_htonl(flow->tuple_info.dest_ip_63_32)); 1571 1572 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0) = 1573 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0, 1574 qdf_htonl(flow->tuple_info.dest_ip_31_0)); 1575 1576 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT); 1577 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT) |= 1578 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, DEST_PORT, 1579 (flow->tuple_info.dest_port)); 1580 1581 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT); 1582 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT) |= 1583 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, SRC_PORT, 1584 (flow->tuple_info.src_port)); 1585 1586 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL); 1587 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL) |= 1588 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL, 1589 flow->tuple_info.l4_protocol); 1590 1591 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER); 1592 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER) |= 1593 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER, 1594 flow->reo_destination_handler); 1595 1596 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1597 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID) |= 1598 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, VALID, 1); 1599 1600 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA); 1601 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA) = 1602 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_10, METADATA, 1603 flow->fse_metadata); 1604 1605 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION); 1606 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION) |= 1607 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, 1608 REO_DESTINATION_INDICATION, 1609 flow->reo_destination_indication); 1610 1611 /* Reset all the other fields in FSE */ 1612 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, RESERVED_9); 1613 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, MSDU_DROP); 1614 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_COUNT); 1615 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_12, MSDU_BYTE_COUNT); 1616 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_13, TIMESTAMP); 1617 1618 return fse; 1619 } 1620 1621 static 1622 void hal_compute_reo_remap_ix2_ix3_9000(uint32_t *ring, uint32_t num_rings, 1623 uint32_t *remap1, uint32_t *remap2) 1624 { 1625 switch (num_rings) { 1626 case 1: 1627 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1628 HAL_REO_REMAP_IX2(ring[0], 17) | 1629 HAL_REO_REMAP_IX2(ring[0], 18) | 1630 HAL_REO_REMAP_IX2(ring[0], 19) | 1631 HAL_REO_REMAP_IX2(ring[0], 20) | 1632 HAL_REO_REMAP_IX2(ring[0], 21) | 1633 HAL_REO_REMAP_IX2(ring[0], 22) | 1634 HAL_REO_REMAP_IX2(ring[0], 23); 1635 1636 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1637 HAL_REO_REMAP_IX3(ring[0], 25) | 1638 HAL_REO_REMAP_IX3(ring[0], 26) | 1639 HAL_REO_REMAP_IX3(ring[0], 27) | 1640 HAL_REO_REMAP_IX3(ring[0], 28) | 1641 HAL_REO_REMAP_IX3(ring[0], 29) | 1642 HAL_REO_REMAP_IX3(ring[0], 30) | 1643 HAL_REO_REMAP_IX3(ring[0], 31); 1644 break; 1645 case 2: 1646 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1647 HAL_REO_REMAP_IX2(ring[0], 17) | 1648 HAL_REO_REMAP_IX2(ring[1], 18) | 1649 HAL_REO_REMAP_IX2(ring[1], 19) | 1650 HAL_REO_REMAP_IX2(ring[0], 20) | 1651 HAL_REO_REMAP_IX2(ring[0], 21) | 1652 HAL_REO_REMAP_IX2(ring[1], 22) | 1653 HAL_REO_REMAP_IX2(ring[1], 23); 1654 1655 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1656 HAL_REO_REMAP_IX3(ring[0], 25) | 1657 HAL_REO_REMAP_IX3(ring[1], 26) | 1658 HAL_REO_REMAP_IX3(ring[1], 27) | 1659 HAL_REO_REMAP_IX3(ring[0], 28) | 1660 HAL_REO_REMAP_IX3(ring[0], 29) | 1661 HAL_REO_REMAP_IX3(ring[1], 30) | 1662 HAL_REO_REMAP_IX3(ring[1], 31); 1663 break; 1664 case 3: 1665 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1666 HAL_REO_REMAP_IX2(ring[1], 17) | 1667 HAL_REO_REMAP_IX2(ring[2], 18) | 1668 HAL_REO_REMAP_IX2(ring[0], 19) | 1669 HAL_REO_REMAP_IX2(ring[1], 20) | 1670 HAL_REO_REMAP_IX2(ring[2], 21) | 1671 HAL_REO_REMAP_IX2(ring[0], 22) | 1672 HAL_REO_REMAP_IX2(ring[1], 23); 1673 1674 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) | 1675 HAL_REO_REMAP_IX3(ring[0], 25) | 1676 HAL_REO_REMAP_IX3(ring[1], 26) | 1677 HAL_REO_REMAP_IX3(ring[2], 27) | 1678 HAL_REO_REMAP_IX3(ring[0], 28) | 1679 HAL_REO_REMAP_IX3(ring[1], 29) | 1680 HAL_REO_REMAP_IX3(ring[2], 30) | 1681 HAL_REO_REMAP_IX3(ring[0], 31); 1682 break; 1683 case 4: 1684 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1685 HAL_REO_REMAP_IX2(ring[1], 17) | 1686 HAL_REO_REMAP_IX2(ring[2], 18) | 1687 HAL_REO_REMAP_IX2(ring[3], 19) | 1688 HAL_REO_REMAP_IX2(ring[0], 20) | 1689 HAL_REO_REMAP_IX2(ring[1], 21) | 1690 HAL_REO_REMAP_IX2(ring[2], 22) | 1691 HAL_REO_REMAP_IX2(ring[3], 23); 1692 1693 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1694 HAL_REO_REMAP_IX3(ring[1], 25) | 1695 HAL_REO_REMAP_IX3(ring[2], 26) | 1696 HAL_REO_REMAP_IX3(ring[3], 27) | 1697 HAL_REO_REMAP_IX3(ring[0], 28) | 1698 HAL_REO_REMAP_IX3(ring[1], 29) | 1699 HAL_REO_REMAP_IX3(ring[2], 30) | 1700 HAL_REO_REMAP_IX3(ring[3], 31); 1701 break; 1702 } 1703 } 1704 struct hal_hw_txrx_ops qcn9000_hal_hw_txrx_ops = { 1705 1706 /* init and setup */ 1707 hal_srng_dst_hw_init_generic, 1708 hal_srng_src_hw_init_generic, 1709 hal_get_hw_hptp_generic, 1710 hal_reo_setup_generic, 1711 hal_setup_link_idle_list_generic, 1712 hal_get_window_address_9000, 1713 NULL, 1714 1715 /* tx */ 1716 hal_tx_desc_set_dscp_tid_table_id_9000, 1717 hal_tx_set_dscp_tid_map_9000, 1718 hal_tx_update_dscp_tid_9000, 1719 hal_tx_desc_set_lmac_id_9000, 1720 hal_tx_desc_set_buf_addr_generic, 1721 hal_tx_desc_set_search_type_generic, 1722 hal_tx_desc_set_search_index_generic, 1723 hal_tx_desc_set_cache_set_num_generic, 1724 hal_tx_comp_get_status_generic, 1725 hal_tx_comp_get_release_reason_generic, 1726 hal_get_wbm_internal_error_generic, 1727 hal_tx_desc_set_mesh_en_9000, 1728 hal_tx_init_cmd_credit_ring_9000, 1729 1730 /* rx */ 1731 hal_rx_msdu_start_nss_get_9000, 1732 hal_rx_mon_hw_desc_get_mpdu_status_9000, 1733 hal_rx_get_tlv_9000, 1734 hal_rx_proc_phyrx_other_receive_info_tlv_9000, 1735 hal_rx_dump_msdu_start_tlv_9000, 1736 hal_rx_dump_msdu_end_tlv_9000, 1737 hal_get_link_desc_size_9000, 1738 hal_rx_mpdu_start_tid_get_9000, 1739 hal_rx_msdu_start_reception_type_get_9000, 1740 hal_rx_msdu_end_da_idx_get_9000, 1741 hal_rx_msdu_desc_info_get_ptr_9000, 1742 hal_rx_link_desc_msdu0_ptr_9000, 1743 hal_reo_status_get_header_9000, 1744 hal_rx_status_get_tlv_info_generic, 1745 hal_rx_wbm_err_info_get_generic, 1746 hal_rx_dump_mpdu_start_tlv_generic, 1747 1748 hal_tx_set_pcp_tid_map_generic, 1749 hal_tx_update_pcp_tid_generic, 1750 hal_tx_update_tidmap_prty_generic, 1751 hal_rx_get_rx_fragment_number_9000, 1752 hal_rx_msdu_end_da_is_mcbc_get_9000, 1753 hal_rx_msdu_end_sa_is_valid_get_9000, 1754 hal_rx_msdu_end_sa_idx_get_9000, 1755 hal_rx_desc_is_first_msdu_9000, 1756 hal_rx_msdu_end_l3_hdr_padding_get_9000, 1757 hal_rx_encryption_info_valid_9000, 1758 hal_rx_print_pn_9000, 1759 hal_rx_msdu_end_first_msdu_get_9000, 1760 hal_rx_msdu_end_da_is_valid_get_9000, 1761 hal_rx_msdu_end_last_msdu_get_9000, 1762 hal_rx_get_mpdu_mac_ad4_valid_9000, 1763 hal_rx_mpdu_start_sw_peer_id_get_9000, 1764 hal_rx_mpdu_get_to_ds_9000, 1765 hal_rx_mpdu_get_fr_ds_9000, 1766 hal_rx_get_mpdu_frame_control_valid_9000, 1767 hal_rx_mpdu_get_addr1_9000, 1768 hal_rx_mpdu_get_addr2_9000, 1769 hal_rx_mpdu_get_addr3_9000, 1770 hal_rx_mpdu_get_addr4_9000, 1771 hal_rx_get_mpdu_sequence_control_valid_9000, 1772 hal_rx_is_unicast_9000, 1773 hal_rx_tid_get_9000, 1774 hal_rx_hw_desc_get_ppduid_get_9000, 1775 hal_rx_mpdu_start_mpdu_qos_control_valid_get_9000, 1776 hal_rx_msdu_end_sa_sw_peer_id_get_9000, 1777 hal_rx_msdu0_buffer_addr_lsb_9000, 1778 hal_rx_msdu_desc_info_ptr_get_9000, 1779 hal_ent_mpdu_desc_info_9000, 1780 hal_dst_mpdu_desc_info_9000, 1781 hal_rx_get_fc_valid_9000, 1782 hal_rx_get_to_ds_flag_9000, 1783 hal_rx_get_mac_addr2_valid_9000, 1784 hal_rx_get_filter_category_9000, 1785 hal_rx_get_ppdu_id_9000, 1786 hal_reo_config_9000, 1787 hal_rx_msdu_flow_idx_get_9000, 1788 hal_rx_msdu_flow_idx_invalid_9000, 1789 hal_rx_msdu_flow_idx_timeout_9000, 1790 hal_rx_msdu_fse_metadata_get_9000, 1791 hal_rx_msdu_cce_metadata_get_9000, 1792 hal_rx_msdu_get_flow_params_9000, 1793 hal_rx_tlv_get_tcp_chksum_9000, 1794 hal_rx_get_rx_sequence_9000, 1795 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) 1796 hal_rx_get_bb_info_9000, 1797 hal_rx_get_rtt_info_9000, 1798 #else 1799 NULL, 1800 NULL, 1801 #endif 1802 /* rx - msdu fast path info fields */ 1803 hal_rx_msdu_packet_metadata_get_9000, 1804 NULL, 1805 NULL, 1806 NULL, 1807 NULL, 1808 NULL, 1809 NULL, 1810 hal_rx_mpdu_start_tlv_tag_valid_9000, 1811 hal_rx_sw_mon_desc_info_get_9000, 1812 hal_rx_wbm_err_msdu_continuation_get_9000, 1813 1814 /* rx - TLV struct offsets */ 1815 hal_rx_msdu_end_offset_get_generic, 1816 hal_rx_attn_offset_get_generic, 1817 hal_rx_msdu_start_offset_get_generic, 1818 hal_rx_mpdu_start_offset_get_generic, 1819 hal_rx_mpdu_end_offset_get_generic, 1820 hal_rx_flow_setup_fse_9000, 1821 hal_compute_reo_remap_ix2_ix3_9000, 1822 NULL, 1823 NULL, 1824 NULL, 1825 NULL 1826 }; 1827 1828 struct hal_hw_srng_config hw_srng_table_9000[] = { 1829 /* TODO: max_rings can populated by querying HW capabilities */ 1830 { /* REO_DST */ 1831 .start_ring_id = HAL_SRNG_REO2SW1, 1832 .max_rings = 4, 1833 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1834 .lmac_ring = FALSE, 1835 .ring_dir = HAL_SRNG_DST_RING, 1836 .reg_start = { 1837 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 1838 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1839 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 1840 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1841 }, 1842 .reg_size = { 1843 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 1844 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 1845 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 1846 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 1847 }, 1848 .max_size = 1849 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 1850 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 1851 }, 1852 { /* REO_EXCEPTION */ 1853 /* Designating REO2TCL ring as exception ring. This ring is 1854 * similar to other REO2SW rings though it is named as REO2TCL. 1855 * Any of theREO2SW rings can be used as exception ring. 1856 */ 1857 .start_ring_id = HAL_SRNG_REO2TCL, 1858 .max_rings = 1, 1859 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1860 .lmac_ring = FALSE, 1861 .ring_dir = HAL_SRNG_DST_RING, 1862 .reg_start = { 1863 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 1864 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1865 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 1866 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1867 }, 1868 /* Single ring - provide ring size if multiple rings of this 1869 * type are supported 1870 */ 1871 .reg_size = {}, 1872 .max_size = 1873 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 1874 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 1875 }, 1876 { /* REO_REINJECT */ 1877 .start_ring_id = HAL_SRNG_SW2REO, 1878 .max_rings = 1, 1879 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1880 .lmac_ring = FALSE, 1881 .ring_dir = HAL_SRNG_SRC_RING, 1882 .reg_start = { 1883 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 1884 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1885 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 1886 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1887 }, 1888 /* Single ring - provide ring size if multiple rings of this 1889 * type are supported 1890 */ 1891 .reg_size = {}, 1892 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 1893 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 1894 }, 1895 { /* REO_CMD */ 1896 .start_ring_id = HAL_SRNG_REO_CMD, 1897 .max_rings = 1, 1898 .entry_size = (sizeof(struct tlv_32_hdr) + 1899 sizeof(struct reo_get_queue_stats)) >> 2, 1900 .lmac_ring = FALSE, 1901 .ring_dir = HAL_SRNG_SRC_RING, 1902 .reg_start = { 1903 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 1904 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1905 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 1906 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1907 }, 1908 /* Single ring - provide ring size if multiple rings of this 1909 * type are supported 1910 */ 1911 .reg_size = {}, 1912 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1913 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1914 }, 1915 { /* REO_STATUS */ 1916 .start_ring_id = HAL_SRNG_REO_STATUS, 1917 .max_rings = 1, 1918 .entry_size = (sizeof(struct tlv_32_hdr) + 1919 sizeof(struct reo_get_queue_stats_status)) >> 2, 1920 .lmac_ring = FALSE, 1921 .ring_dir = HAL_SRNG_DST_RING, 1922 .reg_start = { 1923 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 1924 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1925 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 1926 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1927 }, 1928 /* Single ring - provide ring size if multiple rings of this 1929 * type are supported 1930 */ 1931 .reg_size = {}, 1932 .max_size = 1933 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1934 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1935 }, 1936 { /* TCL_DATA */ 1937 .start_ring_id = HAL_SRNG_SW2TCL1, 1938 .max_rings = 3, 1939 .entry_size = (sizeof(struct tlv_32_hdr) + 1940 sizeof(struct tcl_data_cmd)) >> 2, 1941 .lmac_ring = FALSE, 1942 .ring_dir = HAL_SRNG_SRC_RING, 1943 .reg_start = { 1944 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 1945 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1946 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 1947 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1948 }, 1949 .reg_size = { 1950 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 1951 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 1952 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 1953 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 1954 }, 1955 .max_size = 1956 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 1957 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 1958 }, 1959 { /* TCL_CMD/CREDIT */ 1960 /* qca8074v2 and qcn9000 uses this ring for data commands */ 1961 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 1962 .max_rings = 1, 1963 .entry_size = (sizeof(struct tlv_32_hdr) + 1964 sizeof(struct tcl_data_cmd)) >> 2, 1965 .lmac_ring = FALSE, 1966 .ring_dir = HAL_SRNG_SRC_RING, 1967 .reg_start = { 1968 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR( 1969 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1970 HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR( 1971 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1972 }, 1973 /* Single ring - provide ring size if multiple rings of this 1974 * type are supported 1975 */ 1976 .reg_size = {}, 1977 .max_size = 1978 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >> 1979 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT, 1980 }, 1981 { /* TCL_STATUS */ 1982 .start_ring_id = HAL_SRNG_TCL_STATUS, 1983 .max_rings = 1, 1984 .entry_size = (sizeof(struct tlv_32_hdr) + 1985 sizeof(struct tcl_status_ring)) >> 2, 1986 .lmac_ring = FALSE, 1987 .ring_dir = HAL_SRNG_DST_RING, 1988 .reg_start = { 1989 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 1990 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1991 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 1992 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1993 }, 1994 /* Single ring - provide ring size if multiple rings of this 1995 * type are supported 1996 */ 1997 .reg_size = {}, 1998 .max_size = 1999 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 2000 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 2001 }, 2002 { /* CE_SRC */ 2003 .start_ring_id = HAL_SRNG_CE_0_SRC, 2004 .max_rings = 12, 2005 .entry_size = sizeof(struct ce_src_desc) >> 2, 2006 .lmac_ring = FALSE, 2007 .ring_dir = HAL_SRNG_SRC_RING, 2008 .reg_start = { 2009 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 2010 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 2011 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 2012 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 2013 }, 2014 .reg_size = { 2015 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 2016 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 2017 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 2018 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 2019 }, 2020 .max_size = 2021 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 2022 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 2023 }, 2024 { /* CE_DST */ 2025 .start_ring_id = HAL_SRNG_CE_0_DST, 2026 .max_rings = 12, 2027 .entry_size = 8 >> 2, 2028 /*TODO: entry_size above should actually be 2029 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 2030 * of struct ce_dst_desc in HW header files 2031 */ 2032 .lmac_ring = FALSE, 2033 .ring_dir = HAL_SRNG_SRC_RING, 2034 .reg_start = { 2035 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 2036 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2037 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 2038 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2039 }, 2040 .reg_size = { 2041 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2042 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2043 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2044 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2045 }, 2046 .max_size = 2047 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 2048 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 2049 }, 2050 { /* CE_DST_STATUS */ 2051 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 2052 .max_rings = 12, 2053 .entry_size = sizeof(struct ce_stat_desc) >> 2, 2054 .lmac_ring = FALSE, 2055 .ring_dir = HAL_SRNG_DST_RING, 2056 .reg_start = { 2057 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 2058 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2059 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 2060 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2061 }, 2062 /* TODO: check destination status ring registers */ 2063 .reg_size = { 2064 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2065 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2066 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2067 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2068 }, 2069 .max_size = 2070 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 2071 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 2072 }, 2073 { /* WBM_IDLE_LINK */ 2074 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 2075 .max_rings = 1, 2076 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 2077 .lmac_ring = FALSE, 2078 .ring_dir = HAL_SRNG_SRC_RING, 2079 .reg_start = { 2080 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2081 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2082 }, 2083 /* Single ring - provide ring size if multiple rings of this 2084 * type are supported 2085 */ 2086 .reg_size = {}, 2087 .max_size = 2088 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 2089 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 2090 }, 2091 { /* SW2WBM_RELEASE */ 2092 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 2093 .max_rings = 1, 2094 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2095 .lmac_ring = FALSE, 2096 .ring_dir = HAL_SRNG_SRC_RING, 2097 .reg_start = { 2098 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2099 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2100 }, 2101 /* Single ring - provide ring size if multiple rings of this 2102 * type are supported 2103 */ 2104 .reg_size = {}, 2105 .max_size = 2106 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2107 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2108 }, 2109 { /* WBM2SW_RELEASE */ 2110 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 2111 .max_rings = 4, 2112 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2113 .lmac_ring = FALSE, 2114 .ring_dir = HAL_SRNG_DST_RING, 2115 .reg_start = { 2116 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2117 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2118 }, 2119 .reg_size = { 2120 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 2121 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2122 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 2123 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2124 }, 2125 .max_size = 2126 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2127 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2128 }, 2129 { /* RXDMA_BUF */ 2130 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 2131 #ifdef IPA_OFFLOAD 2132 .max_rings = 3, 2133 #else 2134 .max_rings = 2, 2135 #endif 2136 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2137 .lmac_ring = TRUE, 2138 .ring_dir = HAL_SRNG_SRC_RING, 2139 /* reg_start is not set because LMAC rings are not accessed 2140 * from host 2141 */ 2142 .reg_start = {}, 2143 .reg_size = {}, 2144 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2145 }, 2146 { /* RXDMA_DST */ 2147 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 2148 .max_rings = 1, 2149 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2150 .lmac_ring = TRUE, 2151 .ring_dir = HAL_SRNG_DST_RING, 2152 /* reg_start is not set because LMAC rings are not accessed 2153 * from host 2154 */ 2155 .reg_start = {}, 2156 .reg_size = {}, 2157 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2158 }, 2159 { /* RXDMA_MONITOR_BUF */ 2160 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 2161 .max_rings = 1, 2162 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2163 .lmac_ring = TRUE, 2164 .ring_dir = HAL_SRNG_SRC_RING, 2165 /* reg_start is not set because LMAC rings are not accessed 2166 * from host 2167 */ 2168 .reg_start = {}, 2169 .reg_size = {}, 2170 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2171 }, 2172 { /* RXDMA_MONITOR_STATUS */ 2173 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 2174 .max_rings = 1, 2175 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2176 .lmac_ring = TRUE, 2177 .ring_dir = HAL_SRNG_SRC_RING, 2178 /* reg_start is not set because LMAC rings are not accessed 2179 * from host 2180 */ 2181 .reg_start = {}, 2182 .reg_size = {}, 2183 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2184 }, 2185 { /* RXDMA_MONITOR_DST */ 2186 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 2187 .max_rings = 1, 2188 .entry_size = sizeof(struct sw_monitor_ring) >> 2, 2189 .lmac_ring = TRUE, 2190 .ring_dir = HAL_SRNG_DST_RING, 2191 /* reg_start is not set because LMAC rings are not accessed 2192 * from host 2193 */ 2194 .reg_start = {}, 2195 .reg_size = {}, 2196 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2197 }, 2198 { /* RXDMA_MONITOR_DESC */ 2199 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 2200 .max_rings = 1, 2201 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2202 .lmac_ring = TRUE, 2203 .ring_dir = HAL_SRNG_SRC_RING, 2204 /* reg_start is not set because LMAC rings are not accessed 2205 * from host 2206 */ 2207 .reg_start = {}, 2208 .reg_size = {}, 2209 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2210 }, 2211 { /* DIR_BUF_RX_DMA_SRC */ 2212 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 2213 /* one ring for spectral and one ring for cfr */ 2214 .max_rings = 2, 2215 .entry_size = 2, 2216 .lmac_ring = TRUE, 2217 .ring_dir = HAL_SRNG_SRC_RING, 2218 /* reg_start is not set because LMAC rings are not accessed 2219 * from host 2220 */ 2221 .reg_start = {}, 2222 .reg_size = {}, 2223 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2224 }, 2225 #ifdef WLAN_FEATURE_CIF_CFR 2226 { /* WIFI_POS_SRC */ 2227 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 2228 .max_rings = 1, 2229 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 2230 .lmac_ring = TRUE, 2231 .ring_dir = HAL_SRNG_SRC_RING, 2232 /* reg_start is not set because LMAC rings are not accessed 2233 * from host 2234 */ 2235 .reg_start = {}, 2236 .reg_size = {}, 2237 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2238 }, 2239 #endif 2240 }; 2241 2242 int32_t hal_hw_reg_offset_qcn9000[] = { 2243 /* dst */ 2244 REG_OFFSET(DST, HP), 2245 REG_OFFSET(DST, TP), 2246 REG_OFFSET(DST, ID), 2247 REG_OFFSET(DST, MISC), 2248 REG_OFFSET(DST, HP_ADDR_LSB), 2249 REG_OFFSET(DST, HP_ADDR_MSB), 2250 REG_OFFSET(DST, MSI1_BASE_LSB), 2251 REG_OFFSET(DST, MSI1_BASE_MSB), 2252 REG_OFFSET(DST, MSI1_DATA), 2253 REG_OFFSET(DST, BASE_LSB), 2254 REG_OFFSET(DST, BASE_MSB), 2255 REG_OFFSET(DST, PRODUCER_INT_SETUP), 2256 /* src */ 2257 REG_OFFSET(SRC, HP), 2258 REG_OFFSET(SRC, TP), 2259 REG_OFFSET(SRC, ID), 2260 REG_OFFSET(SRC, MISC), 2261 REG_OFFSET(SRC, TP_ADDR_LSB), 2262 REG_OFFSET(SRC, TP_ADDR_MSB), 2263 REG_OFFSET(SRC, MSI1_BASE_LSB), 2264 REG_OFFSET(SRC, MSI1_BASE_MSB), 2265 REG_OFFSET(SRC, MSI1_DATA), 2266 REG_OFFSET(SRC, BASE_LSB), 2267 REG_OFFSET(SRC, BASE_MSB), 2268 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX0), 2269 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX1), 2270 }; 2271 2272 /** 2273 * hal_qcn9000_attach()- Attach 9000 target specific hal_soc ops, 2274 * offset and srng table 2275 * Return: void 2276 */ 2277 void hal_qcn9000_attach(struct hal_soc *hal_soc) 2278 { 2279 hal_soc->hw_srng_table = hw_srng_table_9000; 2280 hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qcn9000; 2281 hal_soc->ops = &qcn9000_hal_hw_txrx_ops; 2282 if (hal_soc->static_window_map) 2283 hal_write_window_register(hal_soc); 2284 } 2285