1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 #include "hal_li_hw_headers.h" 20 #include "hal_internal.h" 21 #include "hal_api.h" 22 #include "target_type.h" 23 #include "wcss_version.h" 24 #include "qdf_module.h" 25 #include "hal_9000_rx.h" 26 #include "hal_api_mon.h" 27 #include "hal_flow.h" 28 #include "rx_flow_search_entry.h" 29 #include "hal_rx_flow_info.h" 30 31 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 32 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET 33 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 34 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK 35 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 36 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB 37 #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET \ 38 RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET 39 #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK \ 40 RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK 41 #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB \ 42 RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB 43 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 44 PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 45 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 46 PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 47 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 48 PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 49 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 50 PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 51 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 52 PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 53 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 54 PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 55 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 56 PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 57 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 58 PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 59 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 60 PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 61 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 62 PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 63 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 64 PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 65 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 66 RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 67 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 68 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 69 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 70 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 71 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 72 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 73 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 74 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 75 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER \ 76 STATUS_HEADER_REO_STATUS_NUMBER 77 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 78 STATUS_HEADER_TIMESTAMP 79 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 80 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 81 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 82 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 83 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 84 TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 85 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 86 TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 87 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 88 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 89 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 90 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 91 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 92 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 93 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 94 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 95 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 96 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 97 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 98 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 99 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 100 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 101 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 102 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 103 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 104 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 105 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 106 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 107 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 108 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 109 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 110 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 111 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 112 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 113 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 114 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 115 116 #define CE_WINDOW_ADDRESS_9000 \ 117 ((CE_WFSS_CE_REG_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) 118 119 #define UMAC_WINDOW_ADDRESS_9000 \ 120 ((SEQ_WCSS_UMAC_OFFSET >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) 121 122 #define WINDOW_CONFIGURATION_VALUE_9000 \ 123 ((CE_WINDOW_ADDRESS_9000 << 6) |\ 124 (UMAC_WINDOW_ADDRESS_9000 << 12) | \ 125 WINDOW_ENABLE_BIT) 126 127 #include "hal_9000_tx.h" 128 #include <hal_generic_api.h> 129 #include "hal_li_rx.h" 130 #include "hal_li_api.h" 131 #include "hal_li_generic_api.h" 132 133 /** 134 * hal_rx_sw_mon_desc_info_get_9000(): API to read the 135 * sw monitor ring descriptor 136 * 137 * @rxdma_dst_ring_desc: sw monitor ring descriptor 138 * @desc_info_buf: Descriptor info buffer to which 139 * sw monitor ring descriptor is populated to 140 * 141 * Return: void 142 */ 143 static void 144 hal_rx_sw_mon_desc_info_get_9000(hal_ring_desc_t rxdma_dst_ring_desc, 145 hal_rx_mon_desc_info_t desc_info_buf) 146 { 147 struct sw_monitor_ring *sw_mon_ring = 148 (struct sw_monitor_ring *)rxdma_dst_ring_desc; 149 struct buffer_addr_info *buf_addr_info; 150 uint32_t *mpdu_info; 151 uint32_t loop_cnt; 152 struct hal_rx_mon_desc_info *desc_info; 153 154 desc_info = (struct hal_rx_mon_desc_info *)desc_info_buf; 155 mpdu_info = (uint32_t *)&sw_mon_ring-> 156 reo_level_mpdu_frame_info.rx_mpdu_desc_info_details; 157 158 loop_cnt = HAL_RX_GET(sw_mon_ring, SW_MONITOR_RING_7, LOOPING_COUNT); 159 desc_info->msdu_count = HAL_RX_MPDU_MSDU_COUNT_GET(mpdu_info); 160 161 /* Get msdu link descriptor buf_addr_info */ 162 buf_addr_info = &sw_mon_ring-> 163 reo_level_mpdu_frame_info.msdu_link_desc_addr_info; 164 desc_info->link_desc.paddr = HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) 165 | ((uint64_t)(HAL_RX_BUFFER_ADDR_39_32_GET( 166 buf_addr_info)) << 32); 167 desc_info->link_desc.sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info); 168 buf_addr_info = &sw_mon_ring->status_buff_addr_info; 169 desc_info->status_buf.paddr = HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) 170 | ((uint64_t) 171 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32); 172 desc_info->status_buf.sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info); 173 desc_info->end_of_ppdu = HAL_RX_GET(sw_mon_ring, 174 SW_MONITOR_RING_6, 175 END_OF_PPDU); 176 desc_info->status_buf_count = HAL_RX_GET(sw_mon_ring, 177 SW_MONITOR_RING_6, 178 STATUS_BUF_COUNT); 179 desc_info->rxdma_push_reason = HAL_RX_GET(sw_mon_ring, 180 SW_MONITOR_RING_6, 181 RXDMA_PUSH_REASON); 182 desc_info->rxdma_error_code = HAL_RX_GET(sw_mon_ring, 183 SW_MONITOR_RING_6, 184 RXDMA_ERROR_CODE); 185 desc_info->ppdu_id = HAL_RX_GET(sw_mon_ring, 186 SW_MONITOR_RING_7, 187 PHY_PPDU_ID); 188 } 189 190 /** 191 * hal_rx_msdu_start_nss_get_9000(): API to get the NSS 192 * Interval from rx_msdu_start 193 * 194 * @buf: pointer to the start of RX PKT TLV header 195 * Return: uint32_t(nss) 196 */ 197 static uint32_t hal_rx_msdu_start_nss_get_9000(uint8_t *buf) 198 { 199 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 200 struct rx_msdu_start *msdu_start = 201 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 202 uint8_t mimo_ss_bitmap; 203 204 mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start); 205 206 return qdf_get_hweight8(mimo_ss_bitmap); 207 } 208 209 /** 210 * hal_rx_msdu_start_get_len_9000(): API to get the MSDU length 211 * from rx_msdu_start TLV 212 * 213 * @ buf: pointer to the start of RX PKT TLV headers 214 * Return: (uint32_t)msdu length 215 */ 216 static uint32_t hal_rx_msdu_start_get_len_9000(uint8_t *buf) 217 { 218 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 219 struct rx_msdu_start *msdu_start = 220 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 221 uint32_t msdu_len; 222 223 msdu_len = HAL_RX_MSDU_START_MSDU_LEN_GET(msdu_start); 224 225 return msdu_len; 226 } 227 228 /** 229 * hal_rx_mon_hw_desc_get_mpdu_status_9000(): Retrieve MPDU status 230 * 231 * @ hw_desc_addr: Start address of Rx HW TLVs 232 * @ rs: Status for monitor mode 233 * 234 * Return: void 235 */ 236 static void hal_rx_mon_hw_desc_get_mpdu_status_9000(void *hw_desc_addr, 237 struct mon_rx_status *rs) 238 { 239 struct rx_msdu_start *rx_msdu_start; 240 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 241 uint32_t reg_value; 242 const uint32_t sgi_hw_to_cdp[] = { 243 CDP_SGI_0_8_US, 244 CDP_SGI_0_4_US, 245 CDP_SGI_1_6_US, 246 CDP_SGI_3_2_US, 247 }; 248 249 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 250 251 HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs); 252 253 rs->ant_signal_db = HAL_RX_GET(rx_msdu_start, 254 RX_MSDU_START_5, USER_RSSI); 255 rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC); 256 257 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI); 258 rs->sgi = sgi_hw_to_cdp[reg_value]; 259 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE); 260 rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0; 261 /* TODO: rs->beamformed should be set for SU beamforming also */ 262 } 263 264 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 265 /** 266 * hal_get_link_desc_size_9000(): API to get the link desc size 267 * 268 * Return: uint32_t 269 */ 270 static uint32_t hal_get_link_desc_size_9000(void) 271 { 272 return LINK_DESC_SIZE; 273 } 274 275 /** 276 * hal_rx_get_tlv_9000(): API to get the tlv 277 * 278 * @rx_tlv: TLV data extracted from the rx packet 279 * Return: uint8_t 280 */ 281 static uint8_t hal_rx_get_tlv_9000(void *rx_tlv) 282 { 283 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH); 284 } 285 286 /** 287 * hal_rx_mpdu_start_tlv_tag_valid_9000 () - API to check if RX_MPDU_START 288 * tlv tag is valid 289 * 290 *@rx_tlv_hdr: start address of rx_pkt_tlvs 291 * 292 * Return: true if RX_MPDU_START is valid, else false. 293 */ 294 uint8_t hal_rx_mpdu_start_tlv_tag_valid_9000(void *rx_tlv_hdr) 295 { 296 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 297 uint32_t tlv_tag; 298 299 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(&rx_desc->mpdu_start_tlv); 300 301 return tlv_tag == WIFIRX_MPDU_START_E ? true : false; 302 } 303 304 /** 305 * hal_rx_wbm_err_msdu_continuation_get_9000 () - API to check if WBM 306 * msdu continuation bit is set 307 * 308 *@wbm_desc: wbm release ring descriptor 309 * 310 * Return: true if msdu continuation bit is set. 311 */ 312 uint8_t hal_rx_wbm_err_msdu_continuation_get_9000(void *wbm_desc) 313 { 314 uint32_t comp_desc = 315 *(uint32_t *)(((uint8_t *)wbm_desc) + 316 WBM_RELEASE_RING_3_MSDU_CONTINUATION_OFFSET); 317 318 return (comp_desc & WBM_RELEASE_RING_3_MSDU_CONTINUATION_MASK) >> 319 WBM_RELEASE_RING_3_MSDU_CONTINUATION_LSB; 320 } 321 322 /** 323 * hal_rx_proc_phyrx_other_receive_info_tlv_9000(): API to get tlv info 324 * 325 * Return: uint32_t 326 */ 327 static inline 328 void hal_rx_proc_phyrx_other_receive_info_tlv_9000(void *rx_tlv_hdr, 329 void *ppdu_info_hdl) 330 { 331 } 332 333 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) 334 static inline 335 void hal_rx_get_bb_info_9000(void *rx_tlv, void *ppdu_info_hdl) 336 { 337 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 338 339 ppdu_info->cfr_info.bb_captured_channel = 340 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_CHANNEL); 341 342 ppdu_info->cfr_info.bb_captured_timeout = 343 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_TIMEOUT); 344 345 ppdu_info->cfr_info.bb_captured_reason = 346 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_REASON); 347 } 348 349 static inline 350 void hal_rx_get_rtt_info_9000(void *rx_tlv, void *ppdu_info_hdl) 351 { 352 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 353 354 ppdu_info->cfr_info.rx_location_info_valid = 355 HAL_RX_GET(rx_tlv, PHYRX_PKT_END_13_RX_PKT_END_DETAILS, 356 RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID); 357 358 ppdu_info->cfr_info.rtt_che_buffer_pointer_low32 = 359 HAL_RX_GET(rx_tlv, 360 PHYRX_PKT_END_12_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 361 RTT_CHE_BUFFER_POINTER_LOW32); 362 363 ppdu_info->cfr_info.rtt_che_buffer_pointer_high8 = 364 HAL_RX_GET(rx_tlv, 365 PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 366 RTT_CHE_BUFFER_POINTER_HIGH8); 367 368 ppdu_info->cfr_info.chan_capture_status = 369 GET_RX_LOCATION_INFO_CHAN_CAPTURE_STATUS(rx_tlv); 370 371 ppdu_info->cfr_info.rx_start_ts = 372 HAL_RX_GET(rx_tlv, 373 PHYRX_PKT_END_9_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 374 RX_START_TS); 375 376 ppdu_info->cfr_info.rtt_cfo_measurement = (int16_t) 377 HAL_RX_GET(rx_tlv, 378 PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 379 RTT_CFO_MEASUREMENT); 380 381 ppdu_info->cfr_info.agc_gain_info0 = 382 HAL_RX_GET(rx_tlv, 383 PHYRX_PKT_END_1_RX_PKT_END_DETAILS, 384 PHY_TIMESTAMP_1_LOWER_32); 385 386 ppdu_info->cfr_info.agc_gain_info1 = 387 HAL_RX_GET(rx_tlv, 388 PHYRX_PKT_END_2_RX_PKT_END_DETAILS, 389 PHY_TIMESTAMP_1_UPPER_32); 390 391 ppdu_info->cfr_info.agc_gain_info2 = 392 HAL_RX_GET(rx_tlv, 393 PHYRX_PKT_END_3_RX_PKT_END_DETAILS, 394 PHY_TIMESTAMP_2_LOWER_32); 395 396 ppdu_info->cfr_info.agc_gain_info3 = 397 HAL_RX_GET(rx_tlv, 398 PHYRX_PKT_END_4_RX_PKT_END_DETAILS, 399 PHY_TIMESTAMP_2_UPPER_32); 400 401 ppdu_info->cfr_info.mcs_rate = 402 HAL_RX_GET(rx_tlv, 403 PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 404 RTT_MCS_RATE); 405 406 ppdu_info->cfr_info.gi_type = 407 HAL_RX_GET(rx_tlv, 408 PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 409 RTT_GI_TYPE); 410 } 411 #endif 412 /** 413 * hal_rx_dump_msdu_start_tlv_9000() : dump RX msdu_start TLV in structured 414 * human readable format. 415 * @ msdu_start: pointer the msdu_start TLV in pkt. 416 * @ dbg_level: log level. 417 * 418 * Return: void 419 */ 420 static void hal_rx_dump_msdu_start_tlv_9000(void *msdustart, 421 uint8_t dbg_level) 422 { 423 struct rx_msdu_start *msdu_start = (struct rx_msdu_start *)msdustart; 424 425 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 426 "rx_msdu_start tlv - " 427 "rxpcu_mpdu_filter_in_category: %d " 428 "sw_frame_group_id: %d " 429 "phy_ppdu_id: %d " 430 "msdu_length: %d " 431 "ipsec_esp: %d " 432 "l3_offset: %d " 433 "ipsec_ah: %d " 434 "l4_offset: %d " 435 "msdu_number: %d " 436 "decap_format: %d " 437 "ipv4_proto: %d " 438 "ipv6_proto: %d " 439 "tcp_proto: %d " 440 "udp_proto: %d " 441 "ip_frag: %d " 442 "tcp_only_ack: %d " 443 "da_is_bcast_mcast: %d " 444 "ip4_protocol_ip6_next_header: %d " 445 "toeplitz_hash_2_or_4: %d " 446 "flow_id_toeplitz: %d " 447 "user_rssi: %d " 448 "pkt_type: %d " 449 "stbc: %d " 450 "sgi: %d " 451 "rate_mcs: %d " 452 "receive_bandwidth: %d " 453 "reception_type: %d " 454 "ppdu_start_timestamp: %d " 455 "sw_phy_meta_data: %d ", 456 msdu_start->rxpcu_mpdu_filter_in_category, 457 msdu_start->sw_frame_group_id, 458 msdu_start->phy_ppdu_id, 459 msdu_start->msdu_length, 460 msdu_start->ipsec_esp, 461 msdu_start->l3_offset, 462 msdu_start->ipsec_ah, 463 msdu_start->l4_offset, 464 msdu_start->msdu_number, 465 msdu_start->decap_format, 466 msdu_start->ipv4_proto, 467 msdu_start->ipv6_proto, 468 msdu_start->tcp_proto, 469 msdu_start->udp_proto, 470 msdu_start->ip_frag, 471 msdu_start->tcp_only_ack, 472 msdu_start->da_is_bcast_mcast, 473 msdu_start->ip4_protocol_ip6_next_header, 474 msdu_start->toeplitz_hash_2_or_4, 475 msdu_start->flow_id_toeplitz, 476 msdu_start->user_rssi, 477 msdu_start->pkt_type, 478 msdu_start->stbc, 479 msdu_start->sgi, 480 msdu_start->rate_mcs, 481 msdu_start->receive_bandwidth, 482 msdu_start->reception_type, 483 msdu_start->ppdu_start_timestamp, 484 msdu_start->sw_phy_meta_data); 485 } 486 487 /** 488 * hal_rx_dump_msdu_end_tlv_9000: dump RX msdu_end TLV in structured 489 * human readable format. 490 * @ msdu_end: pointer the msdu_end TLV in pkt. 491 * @ dbg_level: log level. 492 * 493 * Return: void 494 */ 495 static void hal_rx_dump_msdu_end_tlv_9000(void *msduend, 496 uint8_t dbg_level) 497 { 498 struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend; 499 500 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 501 "rx_msdu_end tlv - " 502 "rxpcu_mpdu_filter_in_category: %d " 503 "sw_frame_group_id: %d " 504 "phy_ppdu_id: %d " 505 "ip_hdr_chksum: %d " 506 "reported_mpdu_length: %d " 507 "key_id_octet: %d " 508 "cce_super_rule: %d " 509 "cce_classify_not_done_truncat: %d " 510 "cce_classify_not_done_cce_dis: %d " 511 "rule_indication_31_0: %d " 512 "rule_indication_63_32: %d " 513 "da_offset: %d " 514 "sa_offset: %d " 515 "da_offset_valid: %d " 516 "sa_offset_valid: %d " 517 "ipv6_options_crc: %d " 518 "tcp_seq_number: %d " 519 "tcp_ack_number: %d " 520 "tcp_flag: %d " 521 "lro_eligible: %d " 522 "window_size: %d " 523 "tcp_udp_chksum: %d " 524 "sa_idx_timeout: %d " 525 "da_idx_timeout: %d " 526 "msdu_limit_error: %d " 527 "flow_idx_timeout: %d " 528 "flow_idx_invalid: %d " 529 "wifi_parser_error: %d " 530 "amsdu_parser_error: %d " 531 "sa_is_valid: %d " 532 "da_is_valid: %d " 533 "da_is_mcbc: %d " 534 "l3_header_padding: %d " 535 "first_msdu: %d " 536 "last_msdu: %d " 537 "sa_idx: %d " 538 "msdu_drop: %d " 539 "reo_destination_indication: %d " 540 "flow_idx: %d " 541 "fse_metadata: %d " 542 "cce_metadata: %d " 543 "sa_sw_peer_id: %d ", 544 msdu_end->rxpcu_mpdu_filter_in_category, 545 msdu_end->sw_frame_group_id, 546 msdu_end->phy_ppdu_id, 547 msdu_end->ip_hdr_chksum, 548 msdu_end->reported_mpdu_length, 549 msdu_end->key_id_octet, 550 msdu_end->cce_super_rule, 551 msdu_end->cce_classify_not_done_truncate, 552 msdu_end->cce_classify_not_done_cce_dis, 553 msdu_end->rule_indication_31_0, 554 msdu_end->rule_indication_63_32, 555 msdu_end->da_offset, 556 msdu_end->sa_offset, 557 msdu_end->da_offset_valid, 558 msdu_end->sa_offset_valid, 559 msdu_end->ipv6_options_crc, 560 msdu_end->tcp_seq_number, 561 msdu_end->tcp_ack_number, 562 msdu_end->tcp_flag, 563 msdu_end->lro_eligible, 564 msdu_end->window_size, 565 msdu_end->tcp_udp_chksum, 566 msdu_end->sa_idx_timeout, 567 msdu_end->da_idx_timeout, 568 msdu_end->msdu_limit_error, 569 msdu_end->flow_idx_timeout, 570 msdu_end->flow_idx_invalid, 571 msdu_end->wifi_parser_error, 572 msdu_end->amsdu_parser_error, 573 msdu_end->sa_is_valid, 574 msdu_end->da_is_valid, 575 msdu_end->da_is_mcbc, 576 msdu_end->l3_header_padding, 577 msdu_end->first_msdu, 578 msdu_end->last_msdu, 579 msdu_end->sa_idx, 580 msdu_end->msdu_drop, 581 msdu_end->reo_destination_indication, 582 msdu_end->flow_idx, 583 msdu_end->fse_metadata, 584 msdu_end->cce_metadata, 585 msdu_end->sa_sw_peer_id); 586 } 587 588 /** 589 * hal_rx_mpdu_start_tid_get_9000(): API to get tid 590 * from rx_msdu_start 591 * 592 * @buf: pointer to the start of RX PKT TLV header 593 * Return: uint32_t(tid value) 594 */ 595 static uint32_t hal_rx_mpdu_start_tid_get_9000(uint8_t *buf) 596 { 597 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 598 struct rx_mpdu_start *mpdu_start = 599 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 600 uint32_t tid; 601 602 tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details); 603 604 return tid; 605 } 606 607 /** 608 * hal_rx_msdu_start_reception_type_get(): API to get the reception type 609 * Interval from rx_msdu_start 610 * 611 * @buf: pointer to the start of RX PKT TLV header 612 * Return: uint32_t(reception_type) 613 */ 614 static uint32_t hal_rx_msdu_start_reception_type_get_9000(uint8_t *buf) 615 { 616 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 617 struct rx_msdu_start *msdu_start = 618 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 619 uint32_t reception_type; 620 621 reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start); 622 623 return reception_type; 624 } 625 626 /** 627 * hal_rx_msdu_end_da_idx_get_9000: API to get da_idx 628 * from rx_msdu_end TLV 629 * 630 * @ buf: pointer to the start of RX PKT TLV headers 631 * Return: da index 632 */ 633 static uint16_t hal_rx_msdu_end_da_idx_get_9000(uint8_t *buf) 634 { 635 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 636 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 637 uint16_t da_idx; 638 639 da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 640 641 return da_idx; 642 } 643 644 /** 645 * hal_rx_get_rx_fragment_number_9000(): Function to retrieve rx fragment number 646 * 647 * @nbuf: Network buffer 648 * Returns: rx fragment number 649 */ 650 static 651 uint8_t hal_rx_get_rx_fragment_number_9000(uint8_t *buf) 652 { 653 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 654 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 655 656 /* Return first 4 bits as fragment number */ 657 return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & 658 DOT11_SEQ_FRAG_MASK); 659 } 660 661 /** 662 * hal_rx_msdu_end_da_is_mcbc_get_9000(): API to check if pkt is MCBC 663 * from rx_msdu_end TLV 664 * 665 * @ buf: pointer to the start of RX PKT TLV headers 666 * Return: da_is_mcbc 667 */ 668 static uint8_t 669 hal_rx_msdu_end_da_is_mcbc_get_9000(uint8_t *buf) 670 { 671 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 672 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 673 674 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); 675 } 676 677 /** 678 * hal_rx_msdu_end_sa_is_valid_get_9000(): API to get_9000 the 679 * sa_is_valid bit from rx_msdu_end TLV 680 * 681 * @ buf: pointer to the start of RX PKT TLV headers 682 * Return: sa_is_valid bit 683 */ 684 static uint8_t 685 hal_rx_msdu_end_sa_is_valid_get_9000(uint8_t *buf) 686 { 687 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 688 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 689 uint8_t sa_is_valid; 690 691 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); 692 693 return sa_is_valid; 694 } 695 696 /** 697 * hal_rx_msdu_end_sa_idx_get_9000(): API to get_9000 the 698 * sa_idx from rx_msdu_end TLV 699 * 700 * @ buf: pointer to the start of RX PKT TLV headers 701 * Return: sa_idx (SA AST index) 702 */ 703 static uint16_t hal_rx_msdu_end_sa_idx_get_9000(uint8_t *buf) 704 { 705 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 706 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 707 uint16_t sa_idx; 708 709 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 710 711 return sa_idx; 712 } 713 714 /** 715 * hal_rx_desc_is_first_msdu_9000() - Check if first msdu 716 * 717 * @hal_soc_hdl: hal_soc handle 718 * @hw_desc_addr: hardware descriptor address 719 * 720 * Return: 0 - success/ non-zero failure 721 */ 722 static uint32_t hal_rx_desc_is_first_msdu_9000(void *hw_desc_addr) 723 { 724 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; 725 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; 726 727 return HAL_RX_GET(msdu_end, RX_MSDU_END_10, FIRST_MSDU); 728 } 729 730 /** 731 * hal_rx_msdu_end_l3_hdr_padding_get_9000(): API to get_9000 the 732 * l3_header padding from rx_msdu_end TLV 733 * 734 * @ buf: pointer to the start of RX PKT TLV headers 735 * Return: number of l3 header padding bytes 736 */ 737 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_9000(uint8_t *buf) 738 { 739 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 740 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 741 uint32_t l3_header_padding; 742 743 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 744 745 return l3_header_padding; 746 } 747 748 /** 749 * @ hal_rx_encryption_info_valid_9000: Returns encryption type. 750 * 751 * @ buf: rx_tlv_hdr of the received packet 752 * @ Return: encryption type 753 */ 754 inline uint32_t hal_rx_encryption_info_valid_9000(uint8_t *buf) 755 { 756 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 757 struct rx_mpdu_start *mpdu_start = 758 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 759 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 760 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); 761 762 return encryption_info; 763 } 764 765 /* 766 * @ hal_rx_print_pn_9000: Prints the PN of rx packet. 767 * 768 * @ buf: rx_tlv_hdr of the received packet 769 * @ Return: void 770 */ 771 static void hal_rx_print_pn_9000(uint8_t *buf) 772 { 773 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 774 struct rx_mpdu_start *mpdu_start = 775 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 776 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 777 778 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); 779 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); 780 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); 781 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); 782 783 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ", 784 pn_127_96, pn_95_64, pn_63_32, pn_31_0); 785 } 786 787 /** 788 * hal_rx_msdu_end_first_msdu_get_9000: API to get first msdu status 789 * from rx_msdu_end TLV 790 * 791 * @ buf: pointer to the start of RX PKT TLV headers 792 * Return: first_msdu 793 */ 794 static uint8_t hal_rx_msdu_end_first_msdu_get_9000(uint8_t *buf) 795 { 796 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 797 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 798 uint8_t first_msdu; 799 800 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); 801 802 return first_msdu; 803 } 804 805 /** 806 * hal_rx_msdu_end_da_is_valid_get_9000: API to check if da is valid 807 * from rx_msdu_end TLV 808 * 809 * @ buf: pointer to the start of RX PKT TLV headers 810 * Return: da_is_valid 811 */ 812 static uint8_t hal_rx_msdu_end_da_is_valid_get_9000(uint8_t *buf) 813 { 814 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 815 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 816 uint8_t da_is_valid; 817 818 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); 819 820 return da_is_valid; 821 } 822 823 /** 824 * hal_rx_msdu_end_last_msdu_get_9000: API to get last msdu status 825 * from rx_msdu_end TLV 826 * 827 * @ buf: pointer to the start of RX PKT TLV headers 828 * Return: last_msdu 829 */ 830 static uint8_t hal_rx_msdu_end_last_msdu_get_9000(uint8_t *buf) 831 { 832 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 833 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 834 uint8_t last_msdu; 835 836 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); 837 838 return last_msdu; 839 } 840 841 /* 842 * hal_rx_get_mpdu_mac_ad4_valid(): Retrieves if mpdu 4th addr is valid 843 * 844 * @nbuf: Network buffer 845 * Returns: value of mpdu 4th address valid field 846 */ 847 inline bool hal_rx_get_mpdu_mac_ad4_valid_9000(uint8_t *buf) 848 { 849 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 850 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 851 bool ad4_valid = 0; 852 853 ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(rx_mpdu_info); 854 855 return ad4_valid; 856 } 857 858 /** 859 * hal_rx_mpdu_start_sw_peer_id_get_9000: Retrieve sw peer_id 860 * @buf: network buffer 861 * 862 * Return: sw peer_id 863 */ 864 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_9000(uint8_t *buf) 865 { 866 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 867 struct rx_mpdu_start *mpdu_start = 868 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 869 870 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET( 871 &mpdu_start->rx_mpdu_info_details); 872 } 873 874 /* 875 * hal_rx_mpdu_get_to_ds_9000(): API to get the tods info 876 * from rx_mpdu_start 877 * 878 * @buf: pointer to the start of RX PKT TLV header 879 * Return: uint32_t(to_ds) 880 */ 881 static uint32_t hal_rx_mpdu_get_to_ds_9000(uint8_t *buf) 882 { 883 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 884 struct rx_mpdu_start *mpdu_start = 885 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 886 887 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 888 889 return HAL_RX_MPDU_GET_TODS(mpdu_info); 890 } 891 892 /* 893 * hal_rx_mpdu_get_fr_ds_9000(): API to get the from ds info 894 * from rx_mpdu_start 895 * 896 * @buf: pointer to the start of RX PKT TLV header 897 * Return: uint32_t(fr_ds) 898 */ 899 static uint32_t hal_rx_mpdu_get_fr_ds_9000(uint8_t *buf) 900 { 901 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 902 struct rx_mpdu_start *mpdu_start = 903 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 904 905 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 906 907 return HAL_RX_MPDU_GET_FROMDS(mpdu_info); 908 } 909 910 /* 911 * hal_rx_get_mpdu_frame_control_valid_9000(): Retrieves mpdu 912 * frame control valid 913 * 914 * @nbuf: Network buffer 915 * Returns: value of frame control valid field 916 */ 917 static uint8_t hal_rx_get_mpdu_frame_control_valid_9000(uint8_t *buf) 918 { 919 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 920 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 921 922 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); 923 } 924 925 /** 926 * hal_rx_get_mpdu_frame_control_field_9000(): Function 927 * to retrieve frame control field 928 * 929 * @nbuf: Network buffer 930 * Returns: value of frame control field 931 * 932 */ 933 static uint16_t hal_rx_get_mpdu_frame_control_field_9000(uint8_t *buf) 934 { 935 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 936 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 937 uint16_t frame_ctrl = 0; 938 939 frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info); 940 941 return frame_ctrl; 942 } 943 944 /* 945 * hal_rx_mpdu_get_addr1_9000(): API to check get address1 of the mpdu 946 * 947 * @buf: pointer to the start of RX PKT TLV headera 948 * @mac_addr: pointer to mac address 949 * Return: success/failure 950 */ 951 static QDF_STATUS hal_rx_mpdu_get_addr1_9000(uint8_t *buf, 952 uint8_t *mac_addr) 953 { 954 struct __attribute__((__packed__)) hal_addr1 { 955 uint32_t ad1_31_0; 956 uint16_t ad1_47_32; 957 }; 958 959 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 960 struct rx_mpdu_start *mpdu_start = 961 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 962 963 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 964 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; 965 uint32_t mac_addr_ad1_valid; 966 967 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); 968 969 if (mac_addr_ad1_valid) { 970 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); 971 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); 972 return QDF_STATUS_SUCCESS; 973 } 974 975 return QDF_STATUS_E_FAILURE; 976 } 977 978 /* 979 * hal_rx_mpdu_get_addr2_9000(): API to check get address2 of the mpdu 980 * in the packet 981 * 982 * @buf: pointer to the start of RX PKT TLV header 983 * @mac_addr: pointer to mac address 984 * Return: success/failure 985 */ 986 static QDF_STATUS hal_rx_mpdu_get_addr2_9000(uint8_t *buf, uint8_t *mac_addr) 987 { 988 struct __attribute__((__packed__)) hal_addr2 { 989 uint16_t ad2_15_0; 990 uint32_t ad2_47_16; 991 }; 992 993 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 994 struct rx_mpdu_start *mpdu_start = 995 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 996 997 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 998 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; 999 uint32_t mac_addr_ad2_valid; 1000 1001 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); 1002 1003 if (mac_addr_ad2_valid) { 1004 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); 1005 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); 1006 return QDF_STATUS_SUCCESS; 1007 } 1008 1009 return QDF_STATUS_E_FAILURE; 1010 } 1011 1012 /* 1013 * hal_rx_mpdu_get_addr3_9000(): API to get address3 of the mpdu 1014 * in the packet 1015 * 1016 * @buf: pointer to the start of RX PKT TLV header 1017 * @mac_addr: pointer to mac address 1018 * Return: success/failure 1019 */ 1020 static QDF_STATUS hal_rx_mpdu_get_addr3_9000(uint8_t *buf, uint8_t *mac_addr) 1021 { 1022 struct __attribute__((__packed__)) hal_addr3 { 1023 uint32_t ad3_31_0; 1024 uint16_t ad3_47_32; 1025 }; 1026 1027 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1028 struct rx_mpdu_start *mpdu_start = 1029 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1030 1031 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 1032 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; 1033 uint32_t mac_addr_ad3_valid; 1034 1035 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); 1036 1037 if (mac_addr_ad3_valid) { 1038 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); 1039 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); 1040 return QDF_STATUS_SUCCESS; 1041 } 1042 1043 return QDF_STATUS_E_FAILURE; 1044 } 1045 1046 /* 1047 * hal_rx_mpdu_get_addr4_9000(): API to get address4 of the mpdu 1048 * in the packet 1049 * 1050 * @buf: pointer to the start of RX PKT TLV header 1051 * @mac_addr: pointer to mac address 1052 * Return: success/failure 1053 */ 1054 static QDF_STATUS hal_rx_mpdu_get_addr4_9000(uint8_t *buf, uint8_t *mac_addr) 1055 { 1056 struct __attribute__((__packed__)) hal_addr4 { 1057 uint32_t ad4_31_0; 1058 uint16_t ad4_47_32; 1059 }; 1060 1061 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1062 struct rx_mpdu_start *mpdu_start = 1063 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1064 1065 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 1066 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; 1067 uint32_t mac_addr_ad4_valid; 1068 1069 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); 1070 1071 if (mac_addr_ad4_valid) { 1072 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); 1073 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); 1074 return QDF_STATUS_SUCCESS; 1075 } 1076 1077 return QDF_STATUS_E_FAILURE; 1078 } 1079 1080 /* 1081 * hal_rx_get_mpdu_sequence_control_valid_9000(): Get mpdu 1082 * sequence control valid 1083 * 1084 * @nbuf: Network buffer 1085 * Returns: value of sequence control valid field 1086 */ 1087 static uint8_t hal_rx_get_mpdu_sequence_control_valid_9000(uint8_t *buf) 1088 { 1089 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 1090 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 1091 1092 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); 1093 } 1094 1095 /** 1096 * hal_rx_is_unicast_9000: check packet is unicast frame or not. 1097 * 1098 * @ buf: pointer to rx pkt TLV. 1099 * 1100 * Return: true on unicast. 1101 */ 1102 static bool hal_rx_is_unicast_9000(uint8_t *buf) 1103 { 1104 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1105 struct rx_mpdu_start *mpdu_start = 1106 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1107 uint32_t grp_id; 1108 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 1109 1110 grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 1111 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_OFFSET)), 1112 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_MASK, 1113 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_LSB)); 1114 1115 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false; 1116 } 1117 1118 /** 1119 * hal_rx_tid_get_9000: get tid based on qos control valid. 1120 * @hal_soc_hdl: hal soc handle 1121 * @buf: pointer to rx pkt TLV. 1122 * 1123 * Return: tid 1124 */ 1125 static uint32_t hal_rx_tid_get_9000(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1126 { 1127 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1128 struct rx_mpdu_start *mpdu_start = 1129 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1130 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 1131 uint8_t qos_control_valid = 1132 (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 1133 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_OFFSET)), 1134 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_MASK, 1135 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_LSB)); 1136 1137 if (qos_control_valid) 1138 return hal_rx_mpdu_start_tid_get_9000(buf); 1139 1140 return HAL_RX_NON_QOS_TID; 1141 } 1142 1143 /** 1144 * hal_rx_hw_desc_get_ppduid_get_9000(): retrieve ppdu id 1145 * @rx_tlv_hdr: rx tlv header 1146 * @rxdma_dst_ring_desc: rxdma HW descriptor 1147 * 1148 * Return: ppdu id 1149 */ 1150 static uint32_t hal_rx_hw_desc_get_ppduid_get_9000(void *rx_tlv_hdr, 1151 void *rxdma_dst_ring_desc) 1152 { 1153 struct reo_entrance_ring *reo_ent = rxdma_dst_ring_desc; 1154 1155 return reo_ent->phy_ppdu_id; 1156 } 1157 1158 /** 1159 * hal_reo_status_get_header_9000 - Process reo desc info 1160 * @ring_desc: REO status ring descriptor 1161 * @b - tlv type info 1162 * @h1 - Pointer to hal_reo_status_header where info to be stored 1163 * 1164 * Return - none. 1165 * 1166 */ 1167 static void hal_reo_status_get_header_9000(hal_ring_desc_t ring_desc, int b, 1168 void *h1) 1169 { 1170 uint32_t *d = (uint32_t *)ring_desc; 1171 uint32_t val1 = 0; 1172 struct hal_reo_status_header *h = 1173 (struct hal_reo_status_header *)h1; 1174 1175 /* Offsets of descriptor fields defined in HW headers start 1176 * from the field after TLV header 1177 */ 1178 d += HAL_GET_NUM_DWORDS(sizeof(struct tlv_32_hdr)); 1179 1180 switch (b) { 1181 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1182 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, 1183 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1184 break; 1185 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1186 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, 1187 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1188 break; 1189 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1190 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, 1191 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1192 break; 1193 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1194 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, 1195 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1196 break; 1197 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1198 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, 1199 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1200 break; 1201 case HAL_REO_DESC_THRES_STATUS_TLV: 1202 val1 = 1203 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, 1204 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1205 break; 1206 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1207 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, 1208 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1209 break; 1210 default: 1211 qdf_nofl_err("ERROR: Unknown tlv\n"); 1212 break; 1213 } 1214 h->cmd_num = 1215 HAL_GET_FIELD( 1216 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, 1217 val1); 1218 h->exec_time = 1219 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1220 CMD_EXECUTION_TIME, val1); 1221 h->status = 1222 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1223 REO_CMD_EXECUTION_STATUS, val1); 1224 switch (b) { 1225 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1226 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, 1227 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1228 break; 1229 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1230 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, 1231 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1232 break; 1233 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1234 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, 1235 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1236 break; 1237 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1238 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, 1239 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1240 break; 1241 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1242 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, 1243 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1244 break; 1245 case HAL_REO_DESC_THRES_STATUS_TLV: 1246 val1 = 1247 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, 1248 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1249 break; 1250 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1251 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, 1252 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1253 break; 1254 default: 1255 qdf_nofl_err("ERROR: Unknown tlv\n"); 1256 break; 1257 } 1258 h->tstamp = 1259 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); 1260 } 1261 1262 /** 1263 * hal_rx_mpdu_start_mpdu_qos_control_valid_get_9000(): 1264 * Retrieve qos control valid bit from the tlv. 1265 * @buf: pointer to rx pkt TLV. 1266 * 1267 * Return: qos control value. 1268 */ 1269 static inline uint32_t 1270 hal_rx_mpdu_start_mpdu_qos_control_valid_get_9000(uint8_t *buf) 1271 { 1272 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1273 struct rx_mpdu_start *mpdu_start = 1274 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1275 1276 return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET( 1277 &mpdu_start->rx_mpdu_info_details); 1278 } 1279 1280 /** 1281 * hal_rx_msdu_end_sa_sw_peer_id_get_9000(): API to get the 1282 * sa_sw_peer_id from rx_msdu_end TLV 1283 * @buf: pointer to the start of RX PKT TLV headers 1284 * 1285 * Return: sa_sw_peer_id index 1286 */ 1287 static inline uint32_t 1288 hal_rx_msdu_end_sa_sw_peer_id_get_9000(uint8_t *buf) 1289 { 1290 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1291 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1292 1293 return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 1294 } 1295 1296 /** 1297 * hal_tx_desc_set_mesh_en_9000 - Set mesh_enable flag in Tx descriptor 1298 * @desc: Handle to Tx Descriptor 1299 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 1300 * enabling the interpretation of the 'Mesh Control Present' bit 1301 * (bit 8) of QoS Control (otherwise this bit is ignored), 1302 * For native WiFi frames, this indicates that a 'Mesh Control' field 1303 * is present between the header and the LLC. 1304 * 1305 * Return: void 1306 */ 1307 static inline 1308 void hal_tx_desc_set_mesh_en_9000(void *desc, uint8_t en) 1309 { 1310 HAL_SET_FLD(desc, TCL_DATA_CMD_5, MESH_ENABLE) |= 1311 HAL_TX_SM(TCL_DATA_CMD_5, MESH_ENABLE, en); 1312 } 1313 1314 static 1315 void *hal_rx_msdu0_buffer_addr_lsb_9000(void *link_desc_va) 1316 { 1317 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 1318 } 1319 1320 static 1321 void *hal_rx_msdu_desc_info_ptr_get_9000(void *msdu0) 1322 { 1323 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 1324 } 1325 1326 static 1327 void *hal_ent_mpdu_desc_info_9000(void *ent_ring_desc) 1328 { 1329 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 1330 } 1331 1332 static 1333 void *hal_dst_mpdu_desc_info_9000(void *dst_ring_desc) 1334 { 1335 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 1336 } 1337 1338 static 1339 uint8_t hal_rx_get_fc_valid_9000(uint8_t *buf) 1340 { 1341 return HAL_RX_GET_FC_VALID(buf); 1342 } 1343 1344 static uint8_t hal_rx_get_to_ds_flag_9000(uint8_t *buf) 1345 { 1346 return HAL_RX_GET_TO_DS_FLAG(buf); 1347 } 1348 1349 static uint8_t hal_rx_get_mac_addr2_valid_9000(uint8_t *buf) 1350 { 1351 return HAL_RX_GET_MAC_ADDR2_VALID(buf); 1352 } 1353 1354 static uint8_t hal_rx_get_filter_category_9000(uint8_t *buf) 1355 { 1356 return HAL_RX_GET_FILTER_CATEGORY(buf); 1357 } 1358 1359 static uint32_t 1360 hal_rx_get_ppdu_id_9000(uint8_t *buf) 1361 { 1362 struct rx_mpdu_info *rx_mpdu_info; 1363 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)buf; 1364 1365 rx_mpdu_info = 1366 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 1367 1368 return HAL_RX_GET_PPDU_ID(rx_mpdu_info); 1369 } 1370 1371 /** 1372 * hal_reo_config_9000(): Set reo config parameters 1373 * @soc: hal soc handle 1374 * @reg_val: value to be set 1375 * @reo_params: reo parameters 1376 * 1377 * Return: void 1378 */ 1379 static void 1380 hal_reo_config_9000(struct hal_soc *soc, 1381 uint32_t reg_val, 1382 struct hal_reo_params *reo_params) 1383 { 1384 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 1385 } 1386 1387 /** 1388 * hal_rx_msdu_desc_info_get_ptr_9000() - Get msdu desc info ptr 1389 * @msdu_details_ptr - Pointer to msdu_details_ptr 1390 * 1391 * Return - Pointer to rx_msdu_desc_info structure. 1392 * 1393 */ 1394 static void *hal_rx_msdu_desc_info_get_ptr_9000(void *msdu_details_ptr) 1395 { 1396 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 1397 } 1398 1399 /** 1400 * hal_rx_link_desc_msdu0_ptr_9000 - Get pointer to rx_msdu details 1401 * @link_desc - Pointer to link desc 1402 * 1403 * Return - Pointer to rx_msdu_details structure 1404 * 1405 */ 1406 static void *hal_rx_link_desc_msdu0_ptr_9000(void *link_desc) 1407 { 1408 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 1409 } 1410 1411 /** 1412 * hal_rx_msdu_flow_idx_get_9000: API to get flow index 1413 * from rx_msdu_end TLV 1414 * @buf: pointer to the start of RX PKT TLV headers 1415 * 1416 * Return: flow index value from MSDU END TLV 1417 */ 1418 static inline uint32_t hal_rx_msdu_flow_idx_get_9000(uint8_t *buf) 1419 { 1420 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1421 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1422 1423 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 1424 } 1425 1426 /** 1427 * hal_rx_msdu_flow_idx_invalid_9000: API to get flow index invalid 1428 * from rx_msdu_end TLV 1429 * @buf: pointer to the start of RX PKT TLV headers 1430 * 1431 * Return: flow index invalid value from MSDU END TLV 1432 */ 1433 static bool hal_rx_msdu_flow_idx_invalid_9000(uint8_t *buf) 1434 { 1435 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1436 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1437 1438 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 1439 } 1440 1441 /** 1442 * hal_rx_msdu_flow_idx_timeout_9000: API to get flow index timeout 1443 * from rx_msdu_end TLV 1444 * @buf: pointer to the start of RX PKT TLV headers 1445 * 1446 * Return: flow index timeout value from MSDU END TLV 1447 */ 1448 static bool hal_rx_msdu_flow_idx_timeout_9000(uint8_t *buf) 1449 { 1450 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1451 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1452 1453 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 1454 } 1455 1456 /** 1457 * hal_rx_msdu_fse_metadata_get_9000: API to get FSE metadata 1458 * from rx_msdu_end TLV 1459 * @buf: pointer to the start of RX PKT TLV headers 1460 * 1461 * Return: fse metadata value from MSDU END TLV 1462 */ 1463 static uint32_t hal_rx_msdu_fse_metadata_get_9000(uint8_t *buf) 1464 { 1465 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1466 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1467 1468 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end); 1469 } 1470 1471 /** 1472 * hal_rx_msdu_cce_metadata_get_9000: API to get CCE metadata 1473 * from rx_msdu_end TLV 1474 * @buf: pointer to the start of RX PKT TLV headers 1475 * 1476 * Return: cce_metadata 1477 */ 1478 static uint16_t 1479 hal_rx_msdu_cce_metadata_get_9000(uint8_t *buf) 1480 { 1481 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1482 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1483 1484 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end); 1485 } 1486 1487 /** 1488 * hal_rx_msdu_get_flow_params_9000: API to get flow index, flow index invalid 1489 * and flow index timeout from rx_msdu_end TLV 1490 * @buf: pointer to the start of RX PKT TLV headers 1491 * @flow_invalid: pointer to return value of flow_idx_valid 1492 * @flow_timeout: pointer to return value of flow_idx_timeout 1493 * @flow_index: pointer to return value of flow_idx 1494 * 1495 * Return: none 1496 */ 1497 static inline void 1498 hal_rx_msdu_get_flow_params_9000(uint8_t *buf, 1499 bool *flow_invalid, 1500 bool *flow_timeout, 1501 uint32_t *flow_index) 1502 { 1503 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1504 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1505 1506 *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 1507 *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 1508 *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 1509 } 1510 1511 /** 1512 * hal_rx_tlv_get_tcp_chksum_9000() - API to get tcp checksum 1513 * @buf: rx_tlv_hdr 1514 * 1515 * Return: tcp checksum 1516 */ 1517 static uint16_t 1518 hal_rx_tlv_get_tcp_chksum_9000(uint8_t *buf) 1519 { 1520 return HAL_RX_TLV_GET_TCP_CHKSUM(buf); 1521 } 1522 1523 /** 1524 * hal_rx_get_rx_sequence_9000(): Function to retrieve rx sequence number 1525 * 1526 * @nbuf: Network buffer 1527 * Returns: rx sequence number 1528 */ 1529 static 1530 uint16_t hal_rx_get_rx_sequence_9000(uint8_t *buf) 1531 { 1532 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 1533 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 1534 1535 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info); 1536 } 1537 1538 /** 1539 * hal_get_window_address_9000(): Function to get hp/tp address 1540 * @hal_soc: Pointer to hal_soc 1541 * @addr: address offset of register 1542 * 1543 * Return: modified address offset of register 1544 */ 1545 static inline qdf_iomem_t hal_get_window_address_9000(struct hal_soc *hal_soc, 1546 qdf_iomem_t addr) 1547 { 1548 uint32_t offset = addr - hal_soc->dev_base_addr; 1549 qdf_iomem_t new_offset; 1550 1551 /* 1552 * If offset lies within DP register range, use 3rd window to write 1553 * into DP region. 1554 */ 1555 if ((offset ^ SEQ_WCSS_UMAC_OFFSET) < WINDOW_RANGE_MASK) { 1556 new_offset = (hal_soc->dev_base_addr + (3 * WINDOW_START) + 1557 (offset & WINDOW_RANGE_MASK)); 1558 /* 1559 * If offset lies within CE register range, use 2nd window to write 1560 * into CE region. 1561 */ 1562 } else if ((offset ^ CE_WFSS_CE_REG_BASE) < WINDOW_RANGE_MASK) { 1563 new_offset = (hal_soc->dev_base_addr + (2 * WINDOW_START) + 1564 (offset & WINDOW_RANGE_MASK)); 1565 } else { 1566 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 1567 "%s: ERROR: Accessing Wrong register\n", __func__); 1568 qdf_assert_always(0); 1569 return 0; 1570 } 1571 return new_offset; 1572 } 1573 1574 static inline void hal_write_window_register(struct hal_soc *hal_soc) 1575 { 1576 /* Write value into window configuration register */ 1577 qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_REG_ADDRESS, 1578 WINDOW_CONFIGURATION_VALUE_9000); 1579 } 1580 1581 /** 1582 * hal_rx_msdu_packet_metadata_get_9000(): API to get the 1583 * msdu information from rx_msdu_end TLV 1584 * 1585 * @ buf: pointer to the start of RX PKT TLV headers 1586 * @ hal_rx_msdu_metadata: pointer to the msdu info structure 1587 */ 1588 static void 1589 hal_rx_msdu_packet_metadata_get_9000(uint8_t *buf, 1590 void *msdu_pkt_metadata) 1591 { 1592 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1593 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1594 struct hal_rx_msdu_metadata *msdu_metadata = 1595 (struct hal_rx_msdu_metadata *)msdu_pkt_metadata; 1596 1597 msdu_metadata->l3_hdr_pad = 1598 HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 1599 msdu_metadata->sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 1600 msdu_metadata->da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 1601 msdu_metadata->sa_sw_peer_id = 1602 HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 1603 } 1604 1605 /** 1606 * hal_rx_flow_setup_fse_9000() - Setup a flow search entry in HW FST 1607 * @fst: Pointer to the Rx Flow Search Table 1608 * @table_offset: offset into the table where the flow is to be setup 1609 * @flow: Flow Parameters 1610 * 1611 * Return: Success/Failure 1612 */ 1613 static void * 1614 hal_rx_flow_setup_fse_9000(uint8_t *rx_fst, uint32_t table_offset, 1615 uint8_t *rx_flow) 1616 { 1617 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 1618 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 1619 uint8_t *fse; 1620 bool fse_valid; 1621 1622 if (table_offset >= fst->max_entries) { 1623 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 1624 "HAL FSE table offset %u exceeds max entries %u", 1625 table_offset, fst->max_entries); 1626 return NULL; 1627 } 1628 1629 fse = (uint8_t *)fst->base_vaddr + 1630 (table_offset * HAL_RX_FST_ENTRY_SIZE); 1631 1632 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1633 1634 if (fse_valid) { 1635 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 1636 "HAL FSE %pK already valid", fse); 1637 return NULL; 1638 } 1639 1640 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96) = 1641 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96, 1642 qdf_htonl(flow->tuple_info.src_ip_127_96)); 1643 1644 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64) = 1645 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64, 1646 qdf_htonl(flow->tuple_info.src_ip_95_64)); 1647 1648 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32) = 1649 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32, 1650 qdf_htonl(flow->tuple_info.src_ip_63_32)); 1651 1652 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0) = 1653 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0, 1654 qdf_htonl(flow->tuple_info.src_ip_31_0)); 1655 1656 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96) = 1657 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96, 1658 qdf_htonl(flow->tuple_info.dest_ip_127_96)); 1659 1660 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64) = 1661 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64, 1662 qdf_htonl(flow->tuple_info.dest_ip_95_64)); 1663 1664 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32) = 1665 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32, 1666 qdf_htonl(flow->tuple_info.dest_ip_63_32)); 1667 1668 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0) = 1669 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0, 1670 qdf_htonl(flow->tuple_info.dest_ip_31_0)); 1671 1672 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT); 1673 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT) |= 1674 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, DEST_PORT, 1675 (flow->tuple_info.dest_port)); 1676 1677 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT); 1678 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT) |= 1679 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, SRC_PORT, 1680 (flow->tuple_info.src_port)); 1681 1682 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL); 1683 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL) |= 1684 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL, 1685 flow->tuple_info.l4_protocol); 1686 1687 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER); 1688 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER) |= 1689 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER, 1690 flow->reo_destination_handler); 1691 1692 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1693 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID) |= 1694 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, VALID, 1); 1695 1696 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA); 1697 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA) = 1698 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_10, METADATA, 1699 flow->fse_metadata); 1700 1701 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION); 1702 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION) |= 1703 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, 1704 REO_DESTINATION_INDICATION, 1705 flow->reo_destination_indication); 1706 1707 /* Reset all the other fields in FSE */ 1708 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, RESERVED_9); 1709 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, MSDU_DROP); 1710 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_COUNT); 1711 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_12, MSDU_BYTE_COUNT); 1712 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_13, TIMESTAMP); 1713 1714 return fse; 1715 } 1716 1717 static 1718 void hal_compute_reo_remap_ix2_ix3_9000(uint32_t *ring, uint32_t num_rings, 1719 uint32_t *remap1, uint32_t *remap2) 1720 { 1721 switch (num_rings) { 1722 case 1: 1723 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1724 HAL_REO_REMAP_IX2(ring[0], 17) | 1725 HAL_REO_REMAP_IX2(ring[0], 18) | 1726 HAL_REO_REMAP_IX2(ring[0], 19) | 1727 HAL_REO_REMAP_IX2(ring[0], 20) | 1728 HAL_REO_REMAP_IX2(ring[0], 21) | 1729 HAL_REO_REMAP_IX2(ring[0], 22) | 1730 HAL_REO_REMAP_IX2(ring[0], 23); 1731 1732 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1733 HAL_REO_REMAP_IX3(ring[0], 25) | 1734 HAL_REO_REMAP_IX3(ring[0], 26) | 1735 HAL_REO_REMAP_IX3(ring[0], 27) | 1736 HAL_REO_REMAP_IX3(ring[0], 28) | 1737 HAL_REO_REMAP_IX3(ring[0], 29) | 1738 HAL_REO_REMAP_IX3(ring[0], 30) | 1739 HAL_REO_REMAP_IX3(ring[0], 31); 1740 break; 1741 case 2: 1742 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1743 HAL_REO_REMAP_IX2(ring[0], 17) | 1744 HAL_REO_REMAP_IX2(ring[1], 18) | 1745 HAL_REO_REMAP_IX2(ring[1], 19) | 1746 HAL_REO_REMAP_IX2(ring[0], 20) | 1747 HAL_REO_REMAP_IX2(ring[0], 21) | 1748 HAL_REO_REMAP_IX2(ring[1], 22) | 1749 HAL_REO_REMAP_IX2(ring[1], 23); 1750 1751 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1752 HAL_REO_REMAP_IX3(ring[0], 25) | 1753 HAL_REO_REMAP_IX3(ring[1], 26) | 1754 HAL_REO_REMAP_IX3(ring[1], 27) | 1755 HAL_REO_REMAP_IX3(ring[0], 28) | 1756 HAL_REO_REMAP_IX3(ring[0], 29) | 1757 HAL_REO_REMAP_IX3(ring[1], 30) | 1758 HAL_REO_REMAP_IX3(ring[1], 31); 1759 break; 1760 case 3: 1761 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1762 HAL_REO_REMAP_IX2(ring[1], 17) | 1763 HAL_REO_REMAP_IX2(ring[2], 18) | 1764 HAL_REO_REMAP_IX2(ring[0], 19) | 1765 HAL_REO_REMAP_IX2(ring[1], 20) | 1766 HAL_REO_REMAP_IX2(ring[2], 21) | 1767 HAL_REO_REMAP_IX2(ring[0], 22) | 1768 HAL_REO_REMAP_IX2(ring[1], 23); 1769 1770 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) | 1771 HAL_REO_REMAP_IX3(ring[0], 25) | 1772 HAL_REO_REMAP_IX3(ring[1], 26) | 1773 HAL_REO_REMAP_IX3(ring[2], 27) | 1774 HAL_REO_REMAP_IX3(ring[0], 28) | 1775 HAL_REO_REMAP_IX3(ring[1], 29) | 1776 HAL_REO_REMAP_IX3(ring[2], 30) | 1777 HAL_REO_REMAP_IX3(ring[0], 31); 1778 break; 1779 case 4: 1780 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1781 HAL_REO_REMAP_IX2(ring[1], 17) | 1782 HAL_REO_REMAP_IX2(ring[2], 18) | 1783 HAL_REO_REMAP_IX2(ring[3], 19) | 1784 HAL_REO_REMAP_IX2(ring[0], 20) | 1785 HAL_REO_REMAP_IX2(ring[1], 21) | 1786 HAL_REO_REMAP_IX2(ring[2], 22) | 1787 HAL_REO_REMAP_IX2(ring[3], 23); 1788 1789 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1790 HAL_REO_REMAP_IX3(ring[1], 25) | 1791 HAL_REO_REMAP_IX3(ring[2], 26) | 1792 HAL_REO_REMAP_IX3(ring[3], 27) | 1793 HAL_REO_REMAP_IX3(ring[0], 28) | 1794 HAL_REO_REMAP_IX3(ring[1], 29) | 1795 HAL_REO_REMAP_IX3(ring[2], 30) | 1796 HAL_REO_REMAP_IX3(ring[3], 31); 1797 break; 1798 } 1799 } 1800 1801 static void hal_hw_txrx_ops_attach_qcn9000(struct hal_soc *hal_soc) 1802 { 1803 1804 /* init and setup */ 1805 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic; 1806 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic; 1807 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic; 1808 hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_li; 1809 hal_soc->ops->hal_get_window_address = hal_get_window_address_9000; 1810 1811 /* tx */ 1812 hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id = 1813 hal_tx_desc_set_dscp_tid_table_id_9000; 1814 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_9000; 1815 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_9000; 1816 hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_9000; 1817 hal_soc->ops->hal_tx_desc_set_buf_addr = 1818 hal_tx_desc_set_buf_addr_generic_li; 1819 hal_soc->ops->hal_tx_desc_set_search_type = 1820 hal_tx_desc_set_search_type_generic_li; 1821 hal_soc->ops->hal_tx_desc_set_search_index = 1822 hal_tx_desc_set_search_index_generic_li; 1823 hal_soc->ops->hal_tx_desc_set_cache_set_num = 1824 hal_tx_desc_set_cache_set_num_generic_li; 1825 hal_soc->ops->hal_tx_comp_get_status = 1826 hal_tx_comp_get_status_generic_li; 1827 hal_soc->ops->hal_tx_comp_get_release_reason = 1828 hal_tx_comp_get_release_reason_generic_li; 1829 hal_soc->ops->hal_get_wbm_internal_error = 1830 hal_get_wbm_internal_error_generic_li; 1831 hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_9000; 1832 hal_soc->ops->hal_tx_init_cmd_credit_ring = 1833 hal_tx_init_cmd_credit_ring_9000; 1834 1835 /* rx */ 1836 hal_soc->ops->hal_rx_msdu_start_nss_get = 1837 hal_rx_msdu_start_nss_get_9000; 1838 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status = 1839 hal_rx_mon_hw_desc_get_mpdu_status_9000; 1840 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_9000; 1841 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv = 1842 hal_rx_proc_phyrx_other_receive_info_tlv_9000; 1843 hal_soc->ops->hal_rx_dump_msdu_start_tlv = 1844 hal_rx_dump_msdu_start_tlv_9000; 1845 hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_9000; 1846 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_9000; 1847 hal_soc->ops->hal_rx_mpdu_start_tid_get = 1848 hal_rx_mpdu_start_tid_get_9000; 1849 hal_soc->ops->hal_rx_msdu_start_reception_type_get = 1850 hal_rx_msdu_start_reception_type_get_9000; 1851 hal_soc->ops->hal_rx_msdu_end_da_idx_get = 1852 hal_rx_msdu_end_da_idx_get_9000; 1853 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = 1854 hal_rx_msdu_desc_info_get_ptr_9000; 1855 hal_soc->ops->hal_rx_link_desc_msdu0_ptr = 1856 hal_rx_link_desc_msdu0_ptr_9000; 1857 hal_soc->ops->hal_reo_status_get_header = 1858 hal_reo_status_get_header_9000; 1859 hal_soc->ops->hal_rx_status_get_tlv_info = 1860 hal_rx_status_get_tlv_info_generic_li; 1861 hal_soc->ops->hal_rx_wbm_err_info_get = 1862 hal_rx_wbm_err_info_get_generic_li; 1863 hal_soc->ops->hal_rx_dump_mpdu_start_tlv = 1864 hal_rx_dump_mpdu_start_tlv_generic_li; 1865 1866 hal_soc->ops->hal_tx_set_pcp_tid_map = 1867 hal_tx_set_pcp_tid_map_generic_li; 1868 hal_soc->ops->hal_tx_update_pcp_tid_map = 1869 hal_tx_update_pcp_tid_generic_li; 1870 hal_soc->ops->hal_tx_set_tidmap_prty = 1871 hal_tx_update_tidmap_prty_generic_li; 1872 hal_soc->ops->hal_rx_get_rx_fragment_number = 1873 hal_rx_get_rx_fragment_number_9000; 1874 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = 1875 hal_rx_msdu_end_da_is_mcbc_get_9000; 1876 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = 1877 hal_rx_msdu_end_sa_is_valid_get_9000; 1878 hal_soc->ops->hal_rx_msdu_end_sa_idx_get = 1879 hal_rx_msdu_end_sa_idx_get_9000; 1880 hal_soc->ops->hal_rx_desc_is_first_msdu = 1881 hal_rx_desc_is_first_msdu_9000; 1882 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get = 1883 hal_rx_msdu_end_l3_hdr_padding_get_9000; 1884 hal_soc->ops->hal_rx_encryption_info_valid = 1885 hal_rx_encryption_info_valid_9000; 1886 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_9000; 1887 hal_soc->ops->hal_rx_msdu_end_first_msdu_get = 1888 hal_rx_msdu_end_first_msdu_get_9000; 1889 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = 1890 hal_rx_msdu_end_da_is_valid_get_9000; 1891 hal_soc->ops->hal_rx_msdu_end_last_msdu_get = 1892 hal_rx_msdu_end_last_msdu_get_9000; 1893 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = 1894 hal_rx_get_mpdu_mac_ad4_valid_9000; 1895 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get = 1896 hal_rx_mpdu_start_sw_peer_id_get_9000; 1897 hal_soc->ops->hal_rx_tlv_peer_meta_data_get = 1898 hal_rx_mpdu_peer_meta_data_get_li; 1899 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_9000; 1900 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_9000; 1901 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid = 1902 hal_rx_get_mpdu_frame_control_valid_9000; 1903 hal_soc->ops->hal_rx_get_frame_ctrl_field = 1904 hal_rx_get_mpdu_frame_control_field_9000; 1905 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_9000; 1906 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_9000; 1907 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_9000; 1908 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_9000; 1909 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid = 1910 hal_rx_get_mpdu_sequence_control_valid_9000; 1911 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_9000; 1912 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_9000; 1913 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = 1914 hal_rx_hw_desc_get_ppduid_get_9000; 1915 hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get = 1916 hal_rx_mpdu_start_mpdu_qos_control_valid_get_9000; 1917 hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get = 1918 hal_rx_msdu_end_sa_sw_peer_id_get_9000; 1919 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = 1920 hal_rx_msdu0_buffer_addr_lsb_9000; 1921 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = 1922 hal_rx_msdu_desc_info_ptr_get_9000; 1923 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_9000; 1924 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_9000; 1925 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_9000; 1926 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_9000; 1927 hal_soc->ops->hal_rx_get_mac_addr2_valid = 1928 hal_rx_get_mac_addr2_valid_9000; 1929 hal_soc->ops->hal_rx_get_filter_category = 1930 hal_rx_get_filter_category_9000; 1931 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_9000; 1932 hal_soc->ops->hal_reo_config = hal_reo_config_9000; 1933 hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_9000; 1934 hal_soc->ops->hal_rx_msdu_flow_idx_invalid = 1935 hal_rx_msdu_flow_idx_invalid_9000; 1936 hal_soc->ops->hal_rx_msdu_flow_idx_timeout = 1937 hal_rx_msdu_flow_idx_timeout_9000; 1938 hal_soc->ops->hal_rx_msdu_fse_metadata_get = 1939 hal_rx_msdu_fse_metadata_get_9000; 1940 hal_soc->ops->hal_rx_msdu_cce_match_get = 1941 hal_rx_msdu_cce_match_get_li; 1942 hal_soc->ops->hal_rx_msdu_cce_metadata_get = 1943 hal_rx_msdu_cce_metadata_get_9000; 1944 hal_soc->ops->hal_rx_msdu_get_flow_params = 1945 hal_rx_msdu_get_flow_params_9000; 1946 hal_soc->ops->hal_rx_tlv_get_tcp_chksum = 1947 hal_rx_tlv_get_tcp_chksum_9000; 1948 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_9000; 1949 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) 1950 hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_9000; 1951 hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_9000; 1952 #endif 1953 /* rx - msdu fast path info fields */ 1954 hal_soc->ops->hal_rx_msdu_packet_metadata_get = 1955 hal_rx_msdu_packet_metadata_get_9000; 1956 hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid = 1957 hal_rx_mpdu_start_tlv_tag_valid_9000; 1958 hal_soc->ops->hal_rx_sw_mon_desc_info_get = 1959 hal_rx_sw_mon_desc_info_get_9000; 1960 hal_soc->ops->hal_rx_wbm_err_msdu_continuation_get = 1961 hal_rx_wbm_err_msdu_continuation_get_9000; 1962 1963 /* rx - TLV struct offsets */ 1964 hal_soc->ops->hal_rx_msdu_end_offset_get = 1965 hal_rx_msdu_end_offset_get_generic; 1966 hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic; 1967 hal_soc->ops->hal_rx_msdu_start_offset_get = 1968 hal_rx_msdu_start_offset_get_generic; 1969 hal_soc->ops->hal_rx_mpdu_start_offset_get = 1970 hal_rx_mpdu_start_offset_get_generic; 1971 hal_soc->ops->hal_rx_mpdu_end_offset_get = 1972 hal_rx_mpdu_end_offset_get_generic; 1973 #ifndef NO_RX_PKT_HDR_TLV 1974 hal_soc->ops->hal_rx_pkt_tlv_offset_get = 1975 hal_rx_pkt_tlv_offset_get_generic; 1976 #endif 1977 hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_9000; 1978 1979 hal_soc->ops->hal_rx_flow_get_tuple_info = 1980 hal_rx_flow_get_tuple_info_li; 1981 hal_soc->ops->hal_rx_flow_delete_entry = 1982 hal_rx_flow_delete_entry_li; 1983 hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_li; 1984 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = 1985 hal_compute_reo_remap_ix2_ix3_9000; 1986 hal_soc->ops->hal_setup_link_idle_list = 1987 hal_setup_link_idle_list_generic_li; 1988 hal_soc->ops->hal_compute_reo_remap_ix0 = NULL; 1989 hal_soc->ops->hal_rx_tlv_msdu_len_get = 1990 hal_rx_msdu_start_get_len_9000; 1991 }; 1992 1993 struct hal_hw_srng_config hw_srng_table_9000[] = { 1994 /* TODO: max_rings can populated by querying HW capabilities */ 1995 { /* REO_DST */ 1996 .start_ring_id = HAL_SRNG_REO2SW1, 1997 .max_rings = 4, 1998 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1999 .lmac_ring = FALSE, 2000 .ring_dir = HAL_SRNG_DST_RING, 2001 .reg_start = { 2002 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 2003 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2004 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 2005 SEQ_WCSS_UMAC_REO_REG_OFFSET) 2006 }, 2007 .reg_size = { 2008 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 2009 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 2010 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 2011 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 2012 }, 2013 .max_size = 2014 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 2015 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 2016 }, 2017 { /* REO_EXCEPTION */ 2018 /* Designating REO2TCL ring as exception ring. This ring is 2019 * similar to other REO2SW rings though it is named as REO2TCL. 2020 * Any of theREO2SW rings can be used as exception ring. 2021 */ 2022 .start_ring_id = HAL_SRNG_REO2TCL, 2023 .max_rings = 1, 2024 .entry_size = sizeof(struct reo_destination_ring) >> 2, 2025 .lmac_ring = FALSE, 2026 .ring_dir = HAL_SRNG_DST_RING, 2027 .reg_start = { 2028 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 2029 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2030 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 2031 SEQ_WCSS_UMAC_REO_REG_OFFSET) 2032 }, 2033 /* Single ring - provide ring size if multiple rings of this 2034 * type are supported 2035 */ 2036 .reg_size = {}, 2037 .max_size = 2038 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 2039 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 2040 }, 2041 { /* REO_REINJECT */ 2042 .start_ring_id = HAL_SRNG_SW2REO, 2043 .max_rings = 1, 2044 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2045 .lmac_ring = FALSE, 2046 .ring_dir = HAL_SRNG_SRC_RING, 2047 .reg_start = { 2048 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 2049 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2050 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 2051 SEQ_WCSS_UMAC_REO_REG_OFFSET) 2052 }, 2053 /* Single ring - provide ring size if multiple rings of this 2054 * type are supported 2055 */ 2056 .reg_size = {}, 2057 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 2058 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 2059 }, 2060 { /* REO_CMD */ 2061 .start_ring_id = HAL_SRNG_REO_CMD, 2062 .max_rings = 1, 2063 .entry_size = (sizeof(struct tlv_32_hdr) + 2064 sizeof(struct reo_get_queue_stats)) >> 2, 2065 .lmac_ring = FALSE, 2066 .ring_dir = HAL_SRNG_SRC_RING, 2067 .reg_start = { 2068 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 2069 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2070 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 2071 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2072 }, 2073 /* Single ring - provide ring size if multiple rings of this 2074 * type are supported 2075 */ 2076 .reg_size = {}, 2077 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 2078 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 2079 }, 2080 { /* REO_STATUS */ 2081 .start_ring_id = HAL_SRNG_REO_STATUS, 2082 .max_rings = 1, 2083 .entry_size = (sizeof(struct tlv_32_hdr) + 2084 sizeof(struct reo_get_queue_stats_status)) >> 2, 2085 .lmac_ring = FALSE, 2086 .ring_dir = HAL_SRNG_DST_RING, 2087 .reg_start = { 2088 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 2089 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2090 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 2091 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2092 }, 2093 /* Single ring - provide ring size if multiple rings of this 2094 * type are supported 2095 */ 2096 .reg_size = {}, 2097 .max_size = 2098 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 2099 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 2100 }, 2101 { /* TCL_DATA */ 2102 .start_ring_id = HAL_SRNG_SW2TCL1, 2103 .max_rings = 3, 2104 .entry_size = (sizeof(struct tlv_32_hdr) + 2105 sizeof(struct tcl_data_cmd)) >> 2, 2106 .lmac_ring = FALSE, 2107 .ring_dir = HAL_SRNG_SRC_RING, 2108 .reg_start = { 2109 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 2110 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2111 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 2112 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2113 }, 2114 .reg_size = { 2115 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 2116 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 2117 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 2118 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 2119 }, 2120 .max_size = 2121 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 2122 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 2123 }, 2124 { /* TCL_CMD/CREDIT */ 2125 /* qca8074v2 and qcn9000 uses this ring for data commands */ 2126 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 2127 .max_rings = 1, 2128 .entry_size = (sizeof(struct tlv_32_hdr) + 2129 sizeof(struct tcl_data_cmd)) >> 2, 2130 .lmac_ring = FALSE, 2131 .ring_dir = HAL_SRNG_SRC_RING, 2132 .reg_start = { 2133 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR( 2134 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2135 HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR( 2136 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2137 }, 2138 /* Single ring - provide ring size if multiple rings of this 2139 * type are supported 2140 */ 2141 .reg_size = {}, 2142 .max_size = 2143 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >> 2144 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT, 2145 }, 2146 { /* TCL_STATUS */ 2147 .start_ring_id = HAL_SRNG_TCL_STATUS, 2148 .max_rings = 1, 2149 .entry_size = (sizeof(struct tlv_32_hdr) + 2150 sizeof(struct tcl_status_ring)) >> 2, 2151 .lmac_ring = FALSE, 2152 .ring_dir = HAL_SRNG_DST_RING, 2153 .reg_start = { 2154 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 2155 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2156 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 2157 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2158 }, 2159 /* Single ring - provide ring size if multiple rings of this 2160 * type are supported 2161 */ 2162 .reg_size = {}, 2163 .max_size = 2164 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 2165 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 2166 }, 2167 { /* CE_SRC */ 2168 .start_ring_id = HAL_SRNG_CE_0_SRC, 2169 .max_rings = 12, 2170 .entry_size = sizeof(struct ce_src_desc) >> 2, 2171 .lmac_ring = FALSE, 2172 .ring_dir = HAL_SRNG_SRC_RING, 2173 .reg_start = { 2174 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 2175 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 2176 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 2177 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 2178 }, 2179 .reg_size = { 2180 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 2181 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 2182 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 2183 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 2184 }, 2185 .max_size = 2186 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 2187 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 2188 }, 2189 { /* CE_DST */ 2190 .start_ring_id = HAL_SRNG_CE_0_DST, 2191 .max_rings = 12, 2192 .entry_size = 8 >> 2, 2193 /*TODO: entry_size above should actually be 2194 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 2195 * of struct ce_dst_desc in HW header files 2196 */ 2197 .lmac_ring = FALSE, 2198 .ring_dir = HAL_SRNG_SRC_RING, 2199 .reg_start = { 2200 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 2201 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2202 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 2203 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2204 }, 2205 .reg_size = { 2206 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2207 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2208 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2209 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2210 }, 2211 .max_size = 2212 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 2213 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 2214 }, 2215 { /* CE_DST_STATUS */ 2216 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 2217 .max_rings = 12, 2218 .entry_size = sizeof(struct ce_stat_desc) >> 2, 2219 .lmac_ring = FALSE, 2220 .ring_dir = HAL_SRNG_DST_RING, 2221 .reg_start = { 2222 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 2223 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2224 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 2225 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2226 }, 2227 /* TODO: check destination status ring registers */ 2228 .reg_size = { 2229 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2230 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2231 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2232 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2233 }, 2234 .max_size = 2235 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 2236 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 2237 }, 2238 { /* WBM_IDLE_LINK */ 2239 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 2240 .max_rings = 1, 2241 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 2242 .lmac_ring = FALSE, 2243 .ring_dir = HAL_SRNG_SRC_RING, 2244 .reg_start = { 2245 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2246 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2247 }, 2248 /* Single ring - provide ring size if multiple rings of this 2249 * type are supported 2250 */ 2251 .reg_size = {}, 2252 .max_size = 2253 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 2254 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 2255 }, 2256 { /* SW2WBM_RELEASE */ 2257 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 2258 .max_rings = 1, 2259 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2260 .lmac_ring = FALSE, 2261 .ring_dir = HAL_SRNG_SRC_RING, 2262 .reg_start = { 2263 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2264 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2265 }, 2266 /* Single ring - provide ring size if multiple rings of this 2267 * type are supported 2268 */ 2269 .reg_size = {}, 2270 .max_size = 2271 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2272 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2273 }, 2274 { /* WBM2SW_RELEASE */ 2275 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 2276 .max_rings = 5, 2277 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2278 .lmac_ring = FALSE, 2279 .ring_dir = HAL_SRNG_DST_RING, 2280 .reg_start = { 2281 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2282 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2283 }, 2284 .reg_size = { 2285 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 2286 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2287 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 2288 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2289 }, 2290 .max_size = 2291 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2292 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2293 }, 2294 { /* RXDMA_BUF */ 2295 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 2296 #ifdef IPA_OFFLOAD 2297 #ifdef IPA_WDI3_VLAN_SUPPORT 2298 .max_rings = 4, 2299 #else 2300 .max_rings = 3, 2301 #endif 2302 #else 2303 .max_rings = 2, 2304 #endif 2305 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2306 .lmac_ring = TRUE, 2307 .ring_dir = HAL_SRNG_SRC_RING, 2308 /* reg_start is not set because LMAC rings are not accessed 2309 * from host 2310 */ 2311 .reg_start = {}, 2312 .reg_size = {}, 2313 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2314 }, 2315 { /* RXDMA_DST */ 2316 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 2317 .max_rings = 1, 2318 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2319 .lmac_ring = TRUE, 2320 .ring_dir = HAL_SRNG_DST_RING, 2321 /* reg_start is not set because LMAC rings are not accessed 2322 * from host 2323 */ 2324 .reg_start = {}, 2325 .reg_size = {}, 2326 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2327 }, 2328 { /* RXDMA_MONITOR_BUF */ 2329 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 2330 .max_rings = 1, 2331 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2332 .lmac_ring = TRUE, 2333 .ring_dir = HAL_SRNG_SRC_RING, 2334 /* reg_start is not set because LMAC rings are not accessed 2335 * from host 2336 */ 2337 .reg_start = {}, 2338 .reg_size = {}, 2339 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2340 }, 2341 { /* RXDMA_MONITOR_STATUS */ 2342 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 2343 .max_rings = 1, 2344 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2345 .lmac_ring = TRUE, 2346 .ring_dir = HAL_SRNG_SRC_RING, 2347 /* reg_start is not set because LMAC rings are not accessed 2348 * from host 2349 */ 2350 .reg_start = {}, 2351 .reg_size = {}, 2352 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2353 }, 2354 { /* RXDMA_MONITOR_DST */ 2355 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 2356 .max_rings = 1, 2357 .entry_size = sizeof(struct sw_monitor_ring) >> 2, 2358 .lmac_ring = TRUE, 2359 .ring_dir = HAL_SRNG_DST_RING, 2360 /* reg_start is not set because LMAC rings are not accessed 2361 * from host 2362 */ 2363 .reg_start = {}, 2364 .reg_size = {}, 2365 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2366 }, 2367 { /* RXDMA_MONITOR_DESC */ 2368 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 2369 .max_rings = 1, 2370 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2371 .lmac_ring = TRUE, 2372 .ring_dir = HAL_SRNG_SRC_RING, 2373 /* reg_start is not set because LMAC rings are not accessed 2374 * from host 2375 */ 2376 .reg_start = {}, 2377 .reg_size = {}, 2378 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2379 }, 2380 { /* DIR_BUF_RX_DMA_SRC */ 2381 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 2382 /* one ring for spectral and one ring for cfr */ 2383 .max_rings = 2, 2384 .entry_size = 2, 2385 .lmac_ring = TRUE, 2386 .ring_dir = HAL_SRNG_SRC_RING, 2387 /* reg_start is not set because LMAC rings are not accessed 2388 * from host 2389 */ 2390 .reg_start = {}, 2391 .reg_size = {}, 2392 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2393 }, 2394 #ifdef WLAN_FEATURE_CIF_CFR 2395 { /* WIFI_POS_SRC */ 2396 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 2397 .max_rings = 1, 2398 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 2399 .lmac_ring = TRUE, 2400 .ring_dir = HAL_SRNG_SRC_RING, 2401 /* reg_start is not set because LMAC rings are not accessed 2402 * from host 2403 */ 2404 .reg_start = {}, 2405 .reg_size = {}, 2406 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2407 }, 2408 #endif 2409 { /* REO2PPE */ 0}, 2410 { /* PPE2TCL */ 0}, 2411 { /* PPE_RELEASE */ 0}, 2412 { /* TX_MONITOR_BUF */ 0}, 2413 { /* TX_MONITOR_DST */ 0}, 2414 { /* SW2RXDMA_NEW */ 0}, 2415 }; 2416 2417 /** 2418 * hal_qcn9000_attach()- Attach 9000 target specific hal_soc ops, 2419 * offset and srng table 2420 * Return: void 2421 */ 2422 void hal_qcn9000_attach(struct hal_soc *hal_soc) 2423 { 2424 hal_soc->hw_srng_table = hw_srng_table_9000; 2425 hal_srng_hw_reg_offset_init_generic(hal_soc); 2426 hal_hw_txrx_default_ops_attach_li(hal_soc); 2427 hal_hw_txrx_ops_attach_qcn9000(hal_soc); 2428 if (hal_soc->static_window_map) 2429 hal_write_window_register(hal_soc); 2430 } 2431