1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #include "hal_li_hw_headers.h" 19 #include "hal_internal.h" 20 #include "hal_api.h" 21 #include "target_type.h" 22 #include "wcss_version.h" 23 #include "qdf_module.h" 24 #include "hal_9000_rx.h" 25 #include "hal_api_mon.h" 26 #include "hal_flow.h" 27 #include "rx_flow_search_entry.h" 28 #include "hal_rx_flow_info.h" 29 30 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 31 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET 32 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 33 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK 34 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 35 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB 36 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 37 PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 38 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 39 PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 40 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 41 PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 42 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 43 PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 44 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 45 PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 46 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 47 PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 48 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 49 PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 50 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 51 PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 52 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 53 PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 54 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 55 PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 56 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 57 PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 58 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 59 RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 60 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 61 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 62 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 63 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 64 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 65 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 66 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 67 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 68 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER \ 69 STATUS_HEADER_REO_STATUS_NUMBER 70 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 71 STATUS_HEADER_TIMESTAMP 72 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 73 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 74 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 75 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 76 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 77 TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 78 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 79 TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 80 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 81 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 82 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 83 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 84 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 85 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 86 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 87 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 88 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 89 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 90 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 91 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 92 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 93 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 94 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 95 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 96 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 97 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 98 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 99 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 100 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 101 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 102 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 103 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 104 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 105 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 106 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 107 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 108 109 #define CE_WINDOW_ADDRESS_9000 \ 110 ((CE_WFSS_CE_REG_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) 111 112 #define UMAC_WINDOW_ADDRESS_9000 \ 113 ((SEQ_WCSS_UMAC_OFFSET >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) 114 115 #define WINDOW_CONFIGURATION_VALUE_9000 \ 116 ((CE_WINDOW_ADDRESS_9000 << 6) |\ 117 (UMAC_WINDOW_ADDRESS_9000 << 12) | \ 118 WINDOW_ENABLE_BIT) 119 120 #include "hal_9000_tx.h" 121 #include <hal_generic_api.h> 122 #include "hal_li_rx.h" 123 #include "hal_li_api.h" 124 #include "hal_li_generic_api.h" 125 126 /** 127 * hal_rx_sw_mon_desc_info_get_9000(): API to read the 128 * sw monitor ring descriptor 129 * 130 * @rxdma_dst_ring_desc: sw monitor ring descriptor 131 * @desc_info_buf: Descriptor info buffer to which 132 * sw monitor ring descriptor is populated to 133 * 134 * Return: void 135 */ 136 static void 137 hal_rx_sw_mon_desc_info_get_9000(hal_ring_desc_t rxdma_dst_ring_desc, 138 hal_rx_mon_desc_info_t desc_info_buf) 139 { 140 struct sw_monitor_ring *sw_mon_ring = 141 (struct sw_monitor_ring *)rxdma_dst_ring_desc; 142 struct buffer_addr_info *buf_addr_info; 143 uint32_t *mpdu_info; 144 uint32_t loop_cnt; 145 struct hal_rx_mon_desc_info *desc_info; 146 147 desc_info = (struct hal_rx_mon_desc_info *)desc_info_buf; 148 mpdu_info = (uint32_t *)&sw_mon_ring-> 149 reo_level_mpdu_frame_info.rx_mpdu_desc_info_details; 150 151 loop_cnt = HAL_RX_GET(sw_mon_ring, SW_MONITOR_RING_7, LOOPING_COUNT); 152 desc_info->msdu_count = HAL_RX_MPDU_MSDU_COUNT_GET(mpdu_info); 153 154 /* Get msdu link descriptor buf_addr_info */ 155 buf_addr_info = &sw_mon_ring-> 156 reo_level_mpdu_frame_info.msdu_link_desc_addr_info; 157 desc_info->link_desc.paddr = HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) 158 | ((uint64_t)(HAL_RX_BUFFER_ADDR_39_32_GET( 159 buf_addr_info)) << 32); 160 desc_info->link_desc.sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info); 161 buf_addr_info = &sw_mon_ring->status_buff_addr_info; 162 desc_info->status_buf.paddr = HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) 163 | ((uint64_t) 164 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32); 165 desc_info->status_buf.sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info); 166 desc_info->end_of_ppdu = HAL_RX_GET(sw_mon_ring, 167 SW_MONITOR_RING_6, 168 END_OF_PPDU); 169 desc_info->status_buf_count = HAL_RX_GET(sw_mon_ring, 170 SW_MONITOR_RING_6, 171 STATUS_BUF_COUNT); 172 desc_info->rxdma_push_reason = HAL_RX_GET(sw_mon_ring, 173 SW_MONITOR_RING_6, 174 RXDMA_PUSH_REASON); 175 desc_info->ppdu_id = HAL_RX_GET(sw_mon_ring, 176 SW_MONITOR_RING_7, 177 PHY_PPDU_ID); 178 } 179 180 /** 181 * hal_rx_msdu_start_nss_get_9000(): API to get the NSS 182 * Interval from rx_msdu_start 183 * 184 * @buf: pointer to the start of RX PKT TLV header 185 * Return: uint32_t(nss) 186 */ 187 static uint32_t hal_rx_msdu_start_nss_get_9000(uint8_t *buf) 188 { 189 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 190 struct rx_msdu_start *msdu_start = 191 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 192 uint8_t mimo_ss_bitmap; 193 194 mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start); 195 196 return qdf_get_hweight8(mimo_ss_bitmap); 197 } 198 199 /** 200 * hal_rx_mon_hw_desc_get_mpdu_status_9000(): Retrieve MPDU status 201 * 202 * @ hw_desc_addr: Start address of Rx HW TLVs 203 * @ rs: Status for monitor mode 204 * 205 * Return: void 206 */ 207 static void hal_rx_mon_hw_desc_get_mpdu_status_9000(void *hw_desc_addr, 208 struct mon_rx_status *rs) 209 { 210 struct rx_msdu_start *rx_msdu_start; 211 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 212 uint32_t reg_value; 213 const uint32_t sgi_hw_to_cdp[] = { 214 CDP_SGI_0_8_US, 215 CDP_SGI_0_4_US, 216 CDP_SGI_1_6_US, 217 CDP_SGI_3_2_US, 218 }; 219 220 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 221 222 HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs); 223 224 rs->ant_signal_db = HAL_RX_GET(rx_msdu_start, 225 RX_MSDU_START_5, USER_RSSI); 226 rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC); 227 228 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI); 229 rs->sgi = sgi_hw_to_cdp[reg_value]; 230 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE); 231 rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0; 232 /* TODO: rs->beamformed should be set for SU beamforming also */ 233 } 234 235 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 236 /** 237 * hal_get_link_desc_size_9000(): API to get the link desc size 238 * 239 * Return: uint32_t 240 */ 241 static uint32_t hal_get_link_desc_size_9000(void) 242 { 243 return LINK_DESC_SIZE; 244 } 245 246 /** 247 * hal_rx_get_tlv_9000(): API to get the tlv 248 * 249 * @rx_tlv: TLV data extracted from the rx packet 250 * Return: uint8_t 251 */ 252 static uint8_t hal_rx_get_tlv_9000(void *rx_tlv) 253 { 254 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH); 255 } 256 257 /** 258 * hal_rx_mpdu_start_tlv_tag_valid_9000 () - API to check if RX_MPDU_START 259 * tlv tag is valid 260 * 261 *@rx_tlv_hdr: start address of rx_pkt_tlvs 262 * 263 * Return: true if RX_MPDU_START is valied, else false. 264 */ 265 uint8_t hal_rx_mpdu_start_tlv_tag_valid_9000(void *rx_tlv_hdr) 266 { 267 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 268 uint32_t tlv_tag; 269 270 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(&rx_desc->mpdu_start_tlv); 271 272 return tlv_tag == WIFIRX_MPDU_START_E ? true : false; 273 } 274 275 /** 276 * hal_rx_wbm_err_msdu_continuation_get_9000 () - API to check if WBM 277 * msdu continuation bit is set 278 * 279 *@wbm_desc: wbm release ring descriptor 280 * 281 * Return: true if msdu continuation bit is set. 282 */ 283 uint8_t hal_rx_wbm_err_msdu_continuation_get_9000(void *wbm_desc) 284 { 285 uint32_t comp_desc = 286 *(uint32_t *)(((uint8_t *)wbm_desc) + 287 WBM_RELEASE_RING_3_MSDU_CONTINUATION_OFFSET); 288 289 return (comp_desc & WBM_RELEASE_RING_3_MSDU_CONTINUATION_MASK) >> 290 WBM_RELEASE_RING_3_MSDU_CONTINUATION_LSB; 291 } 292 293 /** 294 * hal_rx_proc_phyrx_other_receive_info_tlv_9000(): API to get tlv info 295 * 296 * Return: uint32_t 297 */ 298 static inline 299 void hal_rx_proc_phyrx_other_receive_info_tlv_9000(void *rx_tlv_hdr, 300 void *ppdu_info_hdl) 301 { 302 } 303 304 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) 305 static inline 306 void hal_rx_get_bb_info_9000(void *rx_tlv, void *ppdu_info_hdl) 307 { 308 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 309 310 ppdu_info->cfr_info.bb_captured_channel = 311 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_CHANNEL); 312 313 ppdu_info->cfr_info.bb_captured_timeout = 314 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_TIMEOUT); 315 316 ppdu_info->cfr_info.bb_captured_reason = 317 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_REASON); 318 } 319 320 static inline 321 void hal_rx_get_rtt_info_9000(void *rx_tlv, void *ppdu_info_hdl) 322 { 323 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 324 325 ppdu_info->cfr_info.rx_location_info_valid = 326 HAL_RX_GET(rx_tlv, PHYRX_PKT_END_13_RX_PKT_END_DETAILS, 327 RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID); 328 329 ppdu_info->cfr_info.rtt_che_buffer_pointer_low32 = 330 HAL_RX_GET(rx_tlv, 331 PHYRX_PKT_END_12_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 332 RTT_CHE_BUFFER_POINTER_LOW32); 333 334 ppdu_info->cfr_info.rtt_che_buffer_pointer_high8 = 335 HAL_RX_GET(rx_tlv, 336 PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 337 RTT_CHE_BUFFER_POINTER_HIGH8); 338 339 ppdu_info->cfr_info.chan_capture_status = 340 GET_RX_LOCATION_INFO_CHAN_CAPTURE_STATUS(rx_tlv); 341 342 ppdu_info->cfr_info.rx_start_ts = 343 HAL_RX_GET(rx_tlv, 344 PHYRX_PKT_END_9_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 345 RX_START_TS); 346 347 ppdu_info->cfr_info.rtt_cfo_measurement = (int16_t) 348 HAL_RX_GET(rx_tlv, 349 PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 350 RTT_CFO_MEASUREMENT); 351 352 ppdu_info->cfr_info.agc_gain_info0 = 353 HAL_RX_GET(rx_tlv, 354 PHYRX_PKT_END_1_RX_PKT_END_DETAILS, 355 PHY_TIMESTAMP_1_LOWER_32); 356 357 ppdu_info->cfr_info.agc_gain_info1 = 358 HAL_RX_GET(rx_tlv, 359 PHYRX_PKT_END_2_RX_PKT_END_DETAILS, 360 PHY_TIMESTAMP_1_UPPER_32); 361 362 ppdu_info->cfr_info.agc_gain_info2 = 363 HAL_RX_GET(rx_tlv, 364 PHYRX_PKT_END_3_RX_PKT_END_DETAILS, 365 PHY_TIMESTAMP_2_LOWER_32); 366 367 ppdu_info->cfr_info.agc_gain_info3 = 368 HAL_RX_GET(rx_tlv, 369 PHYRX_PKT_END_4_RX_PKT_END_DETAILS, 370 PHY_TIMESTAMP_2_UPPER_32); 371 372 ppdu_info->cfr_info.mcs_rate = 373 HAL_RX_GET(rx_tlv, 374 PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 375 RTT_MCS_RATE); 376 377 ppdu_info->cfr_info.gi_type = 378 HAL_RX_GET(rx_tlv, 379 PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 380 RTT_GI_TYPE); 381 } 382 #endif 383 /** 384 * hal_rx_dump_msdu_start_tlv_9000() : dump RX msdu_start TLV in structured 385 * human readable format. 386 * @ msdu_start: pointer the msdu_start TLV in pkt. 387 * @ dbg_level: log level. 388 * 389 * Return: void 390 */ 391 static void hal_rx_dump_msdu_start_tlv_9000(void *msdustart, 392 uint8_t dbg_level) 393 { 394 struct rx_msdu_start *msdu_start = (struct rx_msdu_start *)msdustart; 395 396 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 397 "rx_msdu_start tlv - " 398 "rxpcu_mpdu_filter_in_category: %d " 399 "sw_frame_group_id: %d " 400 "phy_ppdu_id: %d " 401 "msdu_length: %d " 402 "ipsec_esp: %d " 403 "l3_offset: %d " 404 "ipsec_ah: %d " 405 "l4_offset: %d " 406 "msdu_number: %d " 407 "decap_format: %d " 408 "ipv4_proto: %d " 409 "ipv6_proto: %d " 410 "tcp_proto: %d " 411 "udp_proto: %d " 412 "ip_frag: %d " 413 "tcp_only_ack: %d " 414 "da_is_bcast_mcast: %d " 415 "ip4_protocol_ip6_next_header: %d " 416 "toeplitz_hash_2_or_4: %d " 417 "flow_id_toeplitz: %d " 418 "user_rssi: %d " 419 "pkt_type: %d " 420 "stbc: %d " 421 "sgi: %d " 422 "rate_mcs: %d " 423 "receive_bandwidth: %d " 424 "reception_type: %d " 425 "ppdu_start_timestamp: %d " 426 "sw_phy_meta_data: %d ", 427 msdu_start->rxpcu_mpdu_filter_in_category, 428 msdu_start->sw_frame_group_id, 429 msdu_start->phy_ppdu_id, 430 msdu_start->msdu_length, 431 msdu_start->ipsec_esp, 432 msdu_start->l3_offset, 433 msdu_start->ipsec_ah, 434 msdu_start->l4_offset, 435 msdu_start->msdu_number, 436 msdu_start->decap_format, 437 msdu_start->ipv4_proto, 438 msdu_start->ipv6_proto, 439 msdu_start->tcp_proto, 440 msdu_start->udp_proto, 441 msdu_start->ip_frag, 442 msdu_start->tcp_only_ack, 443 msdu_start->da_is_bcast_mcast, 444 msdu_start->ip4_protocol_ip6_next_header, 445 msdu_start->toeplitz_hash_2_or_4, 446 msdu_start->flow_id_toeplitz, 447 msdu_start->user_rssi, 448 msdu_start->pkt_type, 449 msdu_start->stbc, 450 msdu_start->sgi, 451 msdu_start->rate_mcs, 452 msdu_start->receive_bandwidth, 453 msdu_start->reception_type, 454 msdu_start->ppdu_start_timestamp, 455 msdu_start->sw_phy_meta_data); 456 } 457 458 /** 459 * hal_rx_dump_msdu_end_tlv_9000: dump RX msdu_end TLV in structured 460 * human readable format. 461 * @ msdu_end: pointer the msdu_end TLV in pkt. 462 * @ dbg_level: log level. 463 * 464 * Return: void 465 */ 466 static void hal_rx_dump_msdu_end_tlv_9000(void *msduend, 467 uint8_t dbg_level) 468 { 469 struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend; 470 471 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 472 "rx_msdu_end tlv - " 473 "rxpcu_mpdu_filter_in_category: %d " 474 "sw_frame_group_id: %d " 475 "phy_ppdu_id: %d " 476 "ip_hdr_chksum: %d " 477 "reported_mpdu_length: %d " 478 "key_id_octet: %d " 479 "cce_super_rule: %d " 480 "cce_classify_not_done_truncat: %d " 481 "cce_classify_not_done_cce_dis: %d " 482 "rule_indication_31_0: %d " 483 "rule_indication_63_32: %d " 484 "da_offset: %d " 485 "sa_offset: %d " 486 "da_offset_valid: %d " 487 "sa_offset_valid: %d " 488 "ipv6_options_crc: %d " 489 "tcp_seq_number: %d " 490 "tcp_ack_number: %d " 491 "tcp_flag: %d " 492 "lro_eligible: %d " 493 "window_size: %d " 494 "tcp_udp_chksum: %d " 495 "sa_idx_timeout: %d " 496 "da_idx_timeout: %d " 497 "msdu_limit_error: %d " 498 "flow_idx_timeout: %d " 499 "flow_idx_invalid: %d " 500 "wifi_parser_error: %d " 501 "amsdu_parser_error: %d " 502 "sa_is_valid: %d " 503 "da_is_valid: %d " 504 "da_is_mcbc: %d " 505 "l3_header_padding: %d " 506 "first_msdu: %d " 507 "last_msdu: %d " 508 "sa_idx: %d " 509 "msdu_drop: %d " 510 "reo_destination_indication: %d " 511 "flow_idx: %d " 512 "fse_metadata: %d " 513 "cce_metadata: %d " 514 "sa_sw_peer_id: %d ", 515 msdu_end->rxpcu_mpdu_filter_in_category, 516 msdu_end->sw_frame_group_id, 517 msdu_end->phy_ppdu_id, 518 msdu_end->ip_hdr_chksum, 519 msdu_end->reported_mpdu_length, 520 msdu_end->key_id_octet, 521 msdu_end->cce_super_rule, 522 msdu_end->cce_classify_not_done_truncate, 523 msdu_end->cce_classify_not_done_cce_dis, 524 msdu_end->rule_indication_31_0, 525 msdu_end->rule_indication_63_32, 526 msdu_end->da_offset, 527 msdu_end->sa_offset, 528 msdu_end->da_offset_valid, 529 msdu_end->sa_offset_valid, 530 msdu_end->ipv6_options_crc, 531 msdu_end->tcp_seq_number, 532 msdu_end->tcp_ack_number, 533 msdu_end->tcp_flag, 534 msdu_end->lro_eligible, 535 msdu_end->window_size, 536 msdu_end->tcp_udp_chksum, 537 msdu_end->sa_idx_timeout, 538 msdu_end->da_idx_timeout, 539 msdu_end->msdu_limit_error, 540 msdu_end->flow_idx_timeout, 541 msdu_end->flow_idx_invalid, 542 msdu_end->wifi_parser_error, 543 msdu_end->amsdu_parser_error, 544 msdu_end->sa_is_valid, 545 msdu_end->da_is_valid, 546 msdu_end->da_is_mcbc, 547 msdu_end->l3_header_padding, 548 msdu_end->first_msdu, 549 msdu_end->last_msdu, 550 msdu_end->sa_idx, 551 msdu_end->msdu_drop, 552 msdu_end->reo_destination_indication, 553 msdu_end->flow_idx, 554 msdu_end->fse_metadata, 555 msdu_end->cce_metadata, 556 msdu_end->sa_sw_peer_id); 557 } 558 559 /** 560 * hal_rx_mpdu_start_tid_get_9000(): API to get tid 561 * from rx_msdu_start 562 * 563 * @buf: pointer to the start of RX PKT TLV header 564 * Return: uint32_t(tid value) 565 */ 566 static uint32_t hal_rx_mpdu_start_tid_get_9000(uint8_t *buf) 567 { 568 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 569 struct rx_mpdu_start *mpdu_start = 570 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 571 uint32_t tid; 572 573 tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details); 574 575 return tid; 576 } 577 578 /** 579 * hal_rx_msdu_start_reception_type_get(): API to get the reception type 580 * Interval from rx_msdu_start 581 * 582 * @buf: pointer to the start of RX PKT TLV header 583 * Return: uint32_t(reception_type) 584 */ 585 static uint32_t hal_rx_msdu_start_reception_type_get_9000(uint8_t *buf) 586 { 587 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 588 struct rx_msdu_start *msdu_start = 589 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 590 uint32_t reception_type; 591 592 reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start); 593 594 return reception_type; 595 } 596 597 /** 598 * hal_rx_msdu_end_da_idx_get_9000: API to get da_idx 599 * from rx_msdu_end TLV 600 * 601 * @ buf: pointer to the start of RX PKT TLV headers 602 * Return: da index 603 */ 604 static uint16_t hal_rx_msdu_end_da_idx_get_9000(uint8_t *buf) 605 { 606 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 607 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 608 uint16_t da_idx; 609 610 da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 611 612 return da_idx; 613 } 614 615 /** 616 * hal_rx_get_rx_fragment_number_9000(): Function to retrieve rx fragment number 617 * 618 * @nbuf: Network buffer 619 * Returns: rx fragment number 620 */ 621 static 622 uint8_t hal_rx_get_rx_fragment_number_9000(uint8_t *buf) 623 { 624 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 625 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 626 627 /* Return first 4 bits as fragment number */ 628 return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & 629 DOT11_SEQ_FRAG_MASK); 630 } 631 632 /** 633 * hal_rx_msdu_end_da_is_mcbc_get_9000(): API to check if pkt is MCBC 634 * from rx_msdu_end TLV 635 * 636 * @ buf: pointer to the start of RX PKT TLV headers 637 * Return: da_is_mcbc 638 */ 639 static uint8_t 640 hal_rx_msdu_end_da_is_mcbc_get_9000(uint8_t *buf) 641 { 642 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 643 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 644 645 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); 646 } 647 648 /** 649 * hal_rx_msdu_end_sa_is_valid_get_9000(): API to get_9000 the 650 * sa_is_valid bit from rx_msdu_end TLV 651 * 652 * @ buf: pointer to the start of RX PKT TLV headers 653 * Return: sa_is_valid bit 654 */ 655 static uint8_t 656 hal_rx_msdu_end_sa_is_valid_get_9000(uint8_t *buf) 657 { 658 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 659 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 660 uint8_t sa_is_valid; 661 662 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); 663 664 return sa_is_valid; 665 } 666 667 /** 668 * hal_rx_msdu_end_sa_idx_get_9000(): API to get_9000 the 669 * sa_idx from rx_msdu_end TLV 670 * 671 * @ buf: pointer to the start of RX PKT TLV headers 672 * Return: sa_idx (SA AST index) 673 */ 674 static uint16_t hal_rx_msdu_end_sa_idx_get_9000(uint8_t *buf) 675 { 676 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 677 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 678 uint16_t sa_idx; 679 680 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 681 682 return sa_idx; 683 } 684 685 /** 686 * hal_rx_desc_is_first_msdu_9000() - Check if first msdu 687 * 688 * @hal_soc_hdl: hal_soc handle 689 * @hw_desc_addr: hardware descriptor address 690 * 691 * Return: 0 - success/ non-zero failure 692 */ 693 static uint32_t hal_rx_desc_is_first_msdu_9000(void *hw_desc_addr) 694 { 695 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; 696 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; 697 698 return HAL_RX_GET(msdu_end, RX_MSDU_END_10, FIRST_MSDU); 699 } 700 701 /** 702 * hal_rx_msdu_end_l3_hdr_padding_get_9000(): API to get_9000 the 703 * l3_header padding from rx_msdu_end TLV 704 * 705 * @ buf: pointer to the start of RX PKT TLV headers 706 * Return: number of l3 header padding bytes 707 */ 708 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_9000(uint8_t *buf) 709 { 710 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 711 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 712 uint32_t l3_header_padding; 713 714 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 715 716 return l3_header_padding; 717 } 718 719 /** 720 * @ hal_rx_encryption_info_valid_9000: Returns encryption type. 721 * 722 * @ buf: rx_tlv_hdr of the received packet 723 * @ Return: encryption type 724 */ 725 inline uint32_t hal_rx_encryption_info_valid_9000(uint8_t *buf) 726 { 727 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 728 struct rx_mpdu_start *mpdu_start = 729 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 730 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 731 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); 732 733 return encryption_info; 734 } 735 736 /* 737 * @ hal_rx_print_pn_9000: Prints the PN of rx packet. 738 * 739 * @ buf: rx_tlv_hdr of the received packet 740 * @ Return: void 741 */ 742 static void hal_rx_print_pn_9000(uint8_t *buf) 743 { 744 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 745 struct rx_mpdu_start *mpdu_start = 746 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 747 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 748 749 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); 750 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); 751 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); 752 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); 753 754 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ", 755 pn_127_96, pn_95_64, pn_63_32, pn_31_0); 756 } 757 758 /** 759 * hal_rx_msdu_end_first_msdu_get_9000: API to get first msdu status 760 * from rx_msdu_end TLV 761 * 762 * @ buf: pointer to the start of RX PKT TLV headers 763 * Return: first_msdu 764 */ 765 static uint8_t hal_rx_msdu_end_first_msdu_get_9000(uint8_t *buf) 766 { 767 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 768 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 769 uint8_t first_msdu; 770 771 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); 772 773 return first_msdu; 774 } 775 776 /** 777 * hal_rx_msdu_end_da_is_valid_get_9000: API to check if da is valid 778 * from rx_msdu_end TLV 779 * 780 * @ buf: pointer to the start of RX PKT TLV headers 781 * Return: da_is_valid 782 */ 783 static uint8_t hal_rx_msdu_end_da_is_valid_get_9000(uint8_t *buf) 784 { 785 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 786 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 787 uint8_t da_is_valid; 788 789 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); 790 791 return da_is_valid; 792 } 793 794 /** 795 * hal_rx_msdu_end_last_msdu_get_9000: API to get last msdu status 796 * from rx_msdu_end TLV 797 * 798 * @ buf: pointer to the start of RX PKT TLV headers 799 * Return: last_msdu 800 */ 801 static uint8_t hal_rx_msdu_end_last_msdu_get_9000(uint8_t *buf) 802 { 803 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 804 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 805 uint8_t last_msdu; 806 807 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); 808 809 return last_msdu; 810 } 811 812 /* 813 * hal_rx_get_mpdu_mac_ad4_valid(): Retrieves if mpdu 4th addr is valid 814 * 815 * @nbuf: Network buffer 816 * Returns: value of mpdu 4th address valid field 817 */ 818 inline bool hal_rx_get_mpdu_mac_ad4_valid_9000(uint8_t *buf) 819 { 820 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 821 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 822 bool ad4_valid = 0; 823 824 ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(rx_mpdu_info); 825 826 return ad4_valid; 827 } 828 829 /** 830 * hal_rx_mpdu_start_sw_peer_id_get_9000: Retrieve sw peer_id 831 * @buf: network buffer 832 * 833 * Return: sw peer_id 834 */ 835 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_9000(uint8_t *buf) 836 { 837 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 838 struct rx_mpdu_start *mpdu_start = 839 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 840 841 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET( 842 &mpdu_start->rx_mpdu_info_details); 843 } 844 845 /* 846 * hal_rx_mpdu_get_to_ds_9000(): API to get the tods info 847 * from rx_mpdu_start 848 * 849 * @buf: pointer to the start of RX PKT TLV header 850 * Return: uint32_t(to_ds) 851 */ 852 static uint32_t hal_rx_mpdu_get_to_ds_9000(uint8_t *buf) 853 { 854 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 855 struct rx_mpdu_start *mpdu_start = 856 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 857 858 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 859 860 return HAL_RX_MPDU_GET_TODS(mpdu_info); 861 } 862 863 /* 864 * hal_rx_mpdu_get_fr_ds_9000(): API to get the from ds info 865 * from rx_mpdu_start 866 * 867 * @buf: pointer to the start of RX PKT TLV header 868 * Return: uint32_t(fr_ds) 869 */ 870 static uint32_t hal_rx_mpdu_get_fr_ds_9000(uint8_t *buf) 871 { 872 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 873 struct rx_mpdu_start *mpdu_start = 874 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 875 876 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 877 878 return HAL_RX_MPDU_GET_FROMDS(mpdu_info); 879 } 880 881 /* 882 * hal_rx_get_mpdu_frame_control_valid_9000(): Retrieves mpdu 883 * frame control valid 884 * 885 * @nbuf: Network buffer 886 * Returns: value of frame control valid field 887 */ 888 static uint8_t hal_rx_get_mpdu_frame_control_valid_9000(uint8_t *buf) 889 { 890 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 891 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 892 893 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); 894 } 895 896 /* 897 * hal_rx_mpdu_get_addr1_9000(): API to check get address1 of the mpdu 898 * 899 * @buf: pointer to the start of RX PKT TLV headera 900 * @mac_addr: pointer to mac address 901 * Return: success/failure 902 */ 903 static QDF_STATUS hal_rx_mpdu_get_addr1_9000(uint8_t *buf, 904 uint8_t *mac_addr) 905 { 906 struct __attribute__((__packed__)) hal_addr1 { 907 uint32_t ad1_31_0; 908 uint16_t ad1_47_32; 909 }; 910 911 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 912 struct rx_mpdu_start *mpdu_start = 913 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 914 915 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 916 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; 917 uint32_t mac_addr_ad1_valid; 918 919 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); 920 921 if (mac_addr_ad1_valid) { 922 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); 923 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); 924 return QDF_STATUS_SUCCESS; 925 } 926 927 return QDF_STATUS_E_FAILURE; 928 } 929 930 /* 931 * hal_rx_mpdu_get_addr2_9000(): API to check get address2 of the mpdu 932 * in the packet 933 * 934 * @buf: pointer to the start of RX PKT TLV header 935 * @mac_addr: pointer to mac address 936 * Return: success/failure 937 */ 938 static QDF_STATUS hal_rx_mpdu_get_addr2_9000(uint8_t *buf, uint8_t *mac_addr) 939 { 940 struct __attribute__((__packed__)) hal_addr2 { 941 uint16_t ad2_15_0; 942 uint32_t ad2_47_16; 943 }; 944 945 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 946 struct rx_mpdu_start *mpdu_start = 947 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 948 949 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 950 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; 951 uint32_t mac_addr_ad2_valid; 952 953 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); 954 955 if (mac_addr_ad2_valid) { 956 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); 957 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); 958 return QDF_STATUS_SUCCESS; 959 } 960 961 return QDF_STATUS_E_FAILURE; 962 } 963 964 /* 965 * hal_rx_mpdu_get_addr3_9000(): API to get address3 of the mpdu 966 * in the packet 967 * 968 * @buf: pointer to the start of RX PKT TLV header 969 * @mac_addr: pointer to mac address 970 * Return: success/failure 971 */ 972 static QDF_STATUS hal_rx_mpdu_get_addr3_9000(uint8_t *buf, uint8_t *mac_addr) 973 { 974 struct __attribute__((__packed__)) hal_addr3 { 975 uint32_t ad3_31_0; 976 uint16_t ad3_47_32; 977 }; 978 979 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 980 struct rx_mpdu_start *mpdu_start = 981 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 982 983 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 984 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; 985 uint32_t mac_addr_ad3_valid; 986 987 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); 988 989 if (mac_addr_ad3_valid) { 990 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); 991 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); 992 return QDF_STATUS_SUCCESS; 993 } 994 995 return QDF_STATUS_E_FAILURE; 996 } 997 998 /* 999 * hal_rx_mpdu_get_addr4_9000(): API to get address4 of the mpdu 1000 * in the packet 1001 * 1002 * @buf: pointer to the start of RX PKT TLV header 1003 * @mac_addr: pointer to mac address 1004 * Return: success/failure 1005 */ 1006 static QDF_STATUS hal_rx_mpdu_get_addr4_9000(uint8_t *buf, uint8_t *mac_addr) 1007 { 1008 struct __attribute__((__packed__)) hal_addr4 { 1009 uint32_t ad4_31_0; 1010 uint16_t ad4_47_32; 1011 }; 1012 1013 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1014 struct rx_mpdu_start *mpdu_start = 1015 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1016 1017 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 1018 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; 1019 uint32_t mac_addr_ad4_valid; 1020 1021 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); 1022 1023 if (mac_addr_ad4_valid) { 1024 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); 1025 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); 1026 return QDF_STATUS_SUCCESS; 1027 } 1028 1029 return QDF_STATUS_E_FAILURE; 1030 } 1031 1032 /* 1033 * hal_rx_get_mpdu_sequence_control_valid_9000(): Get mpdu 1034 * sequence control valid 1035 * 1036 * @nbuf: Network buffer 1037 * Returns: value of sequence control valid field 1038 */ 1039 static uint8_t hal_rx_get_mpdu_sequence_control_valid_9000(uint8_t *buf) 1040 { 1041 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 1042 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 1043 1044 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); 1045 } 1046 1047 /** 1048 * hal_rx_is_unicast_9000: check packet is unicast frame or not. 1049 * 1050 * @ buf: pointer to rx pkt TLV. 1051 * 1052 * Return: true on unicast. 1053 */ 1054 static bool hal_rx_is_unicast_9000(uint8_t *buf) 1055 { 1056 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1057 struct rx_mpdu_start *mpdu_start = 1058 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1059 uint32_t grp_id; 1060 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 1061 1062 grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 1063 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_OFFSET)), 1064 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_MASK, 1065 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_LSB)); 1066 1067 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false; 1068 } 1069 1070 /** 1071 * hal_rx_tid_get_9000: get tid based on qos control valid. 1072 * @hal_soc_hdl: hal soc handle 1073 * @buf: pointer to rx pkt TLV. 1074 * 1075 * Return: tid 1076 */ 1077 static uint32_t hal_rx_tid_get_9000(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1078 { 1079 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1080 struct rx_mpdu_start *mpdu_start = 1081 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1082 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 1083 uint8_t qos_control_valid = 1084 (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 1085 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_OFFSET)), 1086 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_MASK, 1087 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_LSB)); 1088 1089 if (qos_control_valid) 1090 return hal_rx_mpdu_start_tid_get_9000(buf); 1091 1092 return HAL_RX_NON_QOS_TID; 1093 } 1094 1095 /** 1096 * hal_rx_hw_desc_get_ppduid_get_9000(): retrieve ppdu id 1097 * @rx_tlv_hdr: rx tlv header 1098 * @rxdma_dst_ring_desc: rxdma HW descriptor 1099 * 1100 * Return: ppdu id 1101 */ 1102 static uint32_t hal_rx_hw_desc_get_ppduid_get_9000(void *rx_tlv_hdr, 1103 void *rxdma_dst_ring_desc) 1104 { 1105 struct reo_entrance_ring *reo_ent = rxdma_dst_ring_desc; 1106 1107 return reo_ent->phy_ppdu_id; 1108 } 1109 1110 /** 1111 * hal_reo_status_get_header_9000 - Process reo desc info 1112 * @ring_desc: REO status ring descriptor 1113 * @b - tlv type info 1114 * @h1 - Pointer to hal_reo_status_header where info to be stored 1115 * 1116 * Return - none. 1117 * 1118 */ 1119 static void hal_reo_status_get_header_9000(hal_ring_desc_t ring_desc, int b, 1120 void *h1) 1121 { 1122 uint32_t *d = (uint32_t *)ring_desc; 1123 uint32_t val1 = 0; 1124 struct hal_reo_status_header *h = 1125 (struct hal_reo_status_header *)h1; 1126 1127 /* Offsets of descriptor fields defined in HW headers start 1128 * from the field after TLV header 1129 */ 1130 d += HAL_GET_NUM_DWORDS(sizeof(struct tlv_32_hdr)); 1131 1132 switch (b) { 1133 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1134 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, 1135 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1136 break; 1137 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1138 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, 1139 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1140 break; 1141 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1142 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, 1143 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1144 break; 1145 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1146 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, 1147 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1148 break; 1149 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1150 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, 1151 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1152 break; 1153 case HAL_REO_DESC_THRES_STATUS_TLV: 1154 val1 = 1155 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, 1156 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1157 break; 1158 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1159 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, 1160 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1161 break; 1162 default: 1163 qdf_nofl_err("ERROR: Unknown tlv\n"); 1164 break; 1165 } 1166 h->cmd_num = 1167 HAL_GET_FIELD( 1168 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, 1169 val1); 1170 h->exec_time = 1171 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1172 CMD_EXECUTION_TIME, val1); 1173 h->status = 1174 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1175 REO_CMD_EXECUTION_STATUS, val1); 1176 switch (b) { 1177 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1178 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, 1179 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1180 break; 1181 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1182 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, 1183 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1184 break; 1185 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1186 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, 1187 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1188 break; 1189 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1190 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, 1191 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1192 break; 1193 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1194 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, 1195 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1196 break; 1197 case HAL_REO_DESC_THRES_STATUS_TLV: 1198 val1 = 1199 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, 1200 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1201 break; 1202 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1203 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, 1204 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1205 break; 1206 default: 1207 qdf_nofl_err("ERROR: Unknown tlv\n"); 1208 break; 1209 } 1210 h->tstamp = 1211 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); 1212 } 1213 1214 /** 1215 * hal_rx_mpdu_start_mpdu_qos_control_valid_get_9000(): 1216 * Retrieve qos control valid bit from the tlv. 1217 * @buf: pointer to rx pkt TLV. 1218 * 1219 * Return: qos control value. 1220 */ 1221 static inline uint32_t 1222 hal_rx_mpdu_start_mpdu_qos_control_valid_get_9000(uint8_t *buf) 1223 { 1224 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1225 struct rx_mpdu_start *mpdu_start = 1226 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1227 1228 return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET( 1229 &mpdu_start->rx_mpdu_info_details); 1230 } 1231 1232 /** 1233 * hal_rx_msdu_end_sa_sw_peer_id_get_9000(): API to get the 1234 * sa_sw_peer_id from rx_msdu_end TLV 1235 * @buf: pointer to the start of RX PKT TLV headers 1236 * 1237 * Return: sa_sw_peer_id index 1238 */ 1239 static inline uint32_t 1240 hal_rx_msdu_end_sa_sw_peer_id_get_9000(uint8_t *buf) 1241 { 1242 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1243 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1244 1245 return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 1246 } 1247 1248 /** 1249 * hal_tx_desc_set_mesh_en_9000 - Set mesh_enable flag in Tx descriptor 1250 * @desc: Handle to Tx Descriptor 1251 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 1252 * enabling the interpretation of the 'Mesh Control Present' bit 1253 * (bit 8) of QoS Control (otherwise this bit is ignored), 1254 * For native WiFi frames, this indicates that a 'Mesh Control' field 1255 * is present between the header and the LLC. 1256 * 1257 * Return: void 1258 */ 1259 static inline 1260 void hal_tx_desc_set_mesh_en_9000(void *desc, uint8_t en) 1261 { 1262 HAL_SET_FLD(desc, TCL_DATA_CMD_5, MESH_ENABLE) |= 1263 HAL_TX_SM(TCL_DATA_CMD_5, MESH_ENABLE, en); 1264 } 1265 1266 static 1267 void *hal_rx_msdu0_buffer_addr_lsb_9000(void *link_desc_va) 1268 { 1269 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 1270 } 1271 1272 static 1273 void *hal_rx_msdu_desc_info_ptr_get_9000(void *msdu0) 1274 { 1275 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 1276 } 1277 1278 static 1279 void *hal_ent_mpdu_desc_info_9000(void *ent_ring_desc) 1280 { 1281 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 1282 } 1283 1284 static 1285 void *hal_dst_mpdu_desc_info_9000(void *dst_ring_desc) 1286 { 1287 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 1288 } 1289 1290 static 1291 uint8_t hal_rx_get_fc_valid_9000(uint8_t *buf) 1292 { 1293 return HAL_RX_GET_FC_VALID(buf); 1294 } 1295 1296 static uint8_t hal_rx_get_to_ds_flag_9000(uint8_t *buf) 1297 { 1298 return HAL_RX_GET_TO_DS_FLAG(buf); 1299 } 1300 1301 static uint8_t hal_rx_get_mac_addr2_valid_9000(uint8_t *buf) 1302 { 1303 return HAL_RX_GET_MAC_ADDR2_VALID(buf); 1304 } 1305 1306 static uint8_t hal_rx_get_filter_category_9000(uint8_t *buf) 1307 { 1308 return HAL_RX_GET_FILTER_CATEGORY(buf); 1309 } 1310 1311 static uint32_t 1312 hal_rx_get_ppdu_id_9000(uint8_t *buf) 1313 { 1314 struct rx_mpdu_info *rx_mpdu_info; 1315 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)buf; 1316 1317 rx_mpdu_info = 1318 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 1319 1320 return HAL_RX_GET_PPDU_ID(rx_mpdu_info); 1321 } 1322 1323 /** 1324 * hal_reo_config_9000(): Set reo config parameters 1325 * @soc: hal soc handle 1326 * @reg_val: value to be set 1327 * @reo_params: reo parameters 1328 * 1329 * Return: void 1330 */ 1331 static void 1332 hal_reo_config_9000(struct hal_soc *soc, 1333 uint32_t reg_val, 1334 struct hal_reo_params *reo_params) 1335 { 1336 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 1337 } 1338 1339 /** 1340 * hal_rx_msdu_desc_info_get_ptr_9000() - Get msdu desc info ptr 1341 * @msdu_details_ptr - Pointer to msdu_details_ptr 1342 * 1343 * Return - Pointer to rx_msdu_desc_info structure. 1344 * 1345 */ 1346 static void *hal_rx_msdu_desc_info_get_ptr_9000(void *msdu_details_ptr) 1347 { 1348 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 1349 } 1350 1351 /** 1352 * hal_rx_link_desc_msdu0_ptr_9000 - Get pointer to rx_msdu details 1353 * @link_desc - Pointer to link desc 1354 * 1355 * Return - Pointer to rx_msdu_details structure 1356 * 1357 */ 1358 static void *hal_rx_link_desc_msdu0_ptr_9000(void *link_desc) 1359 { 1360 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 1361 } 1362 1363 /** 1364 * hal_rx_msdu_flow_idx_get_9000: API to get flow index 1365 * from rx_msdu_end TLV 1366 * @buf: pointer to the start of RX PKT TLV headers 1367 * 1368 * Return: flow index value from MSDU END TLV 1369 */ 1370 static inline uint32_t hal_rx_msdu_flow_idx_get_9000(uint8_t *buf) 1371 { 1372 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1373 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1374 1375 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 1376 } 1377 1378 /** 1379 * hal_rx_msdu_flow_idx_invalid_9000: API to get flow index invalid 1380 * from rx_msdu_end TLV 1381 * @buf: pointer to the start of RX PKT TLV headers 1382 * 1383 * Return: flow index invalid value from MSDU END TLV 1384 */ 1385 static bool hal_rx_msdu_flow_idx_invalid_9000(uint8_t *buf) 1386 { 1387 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1388 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1389 1390 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 1391 } 1392 1393 /** 1394 * hal_rx_msdu_flow_idx_timeout_9000: API to get flow index timeout 1395 * from rx_msdu_end TLV 1396 * @buf: pointer to the start of RX PKT TLV headers 1397 * 1398 * Return: flow index timeout value from MSDU END TLV 1399 */ 1400 static bool hal_rx_msdu_flow_idx_timeout_9000(uint8_t *buf) 1401 { 1402 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1403 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1404 1405 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 1406 } 1407 1408 /** 1409 * hal_rx_msdu_fse_metadata_get_9000: API to get FSE metadata 1410 * from rx_msdu_end TLV 1411 * @buf: pointer to the start of RX PKT TLV headers 1412 * 1413 * Return: fse metadata value from MSDU END TLV 1414 */ 1415 static uint32_t hal_rx_msdu_fse_metadata_get_9000(uint8_t *buf) 1416 { 1417 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1418 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1419 1420 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end); 1421 } 1422 1423 /** 1424 * hal_rx_msdu_cce_metadata_get_9000: API to get CCE metadata 1425 * from rx_msdu_end TLV 1426 * @buf: pointer to the start of RX PKT TLV headers 1427 * 1428 * Return: cce_metadata 1429 */ 1430 static uint16_t 1431 hal_rx_msdu_cce_metadata_get_9000(uint8_t *buf) 1432 { 1433 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1434 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1435 1436 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end); 1437 } 1438 1439 /** 1440 * hal_rx_msdu_get_flow_params_9000: API to get flow index, flow index invalid 1441 * and flow index timeout from rx_msdu_end TLV 1442 * @buf: pointer to the start of RX PKT TLV headers 1443 * @flow_invalid: pointer to return value of flow_idx_valid 1444 * @flow_timeout: pointer to return value of flow_idx_timeout 1445 * @flow_index: pointer to return value of flow_idx 1446 * 1447 * Return: none 1448 */ 1449 static inline void 1450 hal_rx_msdu_get_flow_params_9000(uint8_t *buf, 1451 bool *flow_invalid, 1452 bool *flow_timeout, 1453 uint32_t *flow_index) 1454 { 1455 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1456 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1457 1458 *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 1459 *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 1460 *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 1461 } 1462 1463 /** 1464 * hal_rx_tlv_get_tcp_chksum_9000() - API to get tcp checksum 1465 * @buf: rx_tlv_hdr 1466 * 1467 * Return: tcp checksum 1468 */ 1469 static uint16_t 1470 hal_rx_tlv_get_tcp_chksum_9000(uint8_t *buf) 1471 { 1472 return HAL_RX_TLV_GET_TCP_CHKSUM(buf); 1473 } 1474 1475 /** 1476 * hal_rx_get_rx_sequence_9000(): Function to retrieve rx sequence number 1477 * 1478 * @nbuf: Network buffer 1479 * Returns: rx sequence number 1480 */ 1481 static 1482 uint16_t hal_rx_get_rx_sequence_9000(uint8_t *buf) 1483 { 1484 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 1485 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 1486 1487 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info); 1488 } 1489 1490 /** 1491 * hal_get_window_address_9000(): Function to get hp/tp address 1492 * @hal_soc: Pointer to hal_soc 1493 * @addr: address offset of register 1494 * 1495 * Return: modified address offset of register 1496 */ 1497 static inline qdf_iomem_t hal_get_window_address_9000(struct hal_soc *hal_soc, 1498 qdf_iomem_t addr) 1499 { 1500 uint32_t offset = addr - hal_soc->dev_base_addr; 1501 qdf_iomem_t new_offset; 1502 1503 /* 1504 * If offset lies within DP register range, use 3rd window to write 1505 * into DP region. 1506 */ 1507 if ((offset ^ SEQ_WCSS_UMAC_OFFSET) < WINDOW_RANGE_MASK) { 1508 new_offset = (hal_soc->dev_base_addr + (3 * WINDOW_START) + 1509 (offset & WINDOW_RANGE_MASK)); 1510 /* 1511 * If offset lies within CE register range, use 2nd window to write 1512 * into CE region. 1513 */ 1514 } else if ((offset ^ CE_WFSS_CE_REG_BASE) < WINDOW_RANGE_MASK) { 1515 new_offset = (hal_soc->dev_base_addr + (2 * WINDOW_START) + 1516 (offset & WINDOW_RANGE_MASK)); 1517 } else { 1518 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 1519 "%s: ERROR: Accessing Wrong register\n", __func__); 1520 qdf_assert_always(0); 1521 return 0; 1522 } 1523 return new_offset; 1524 } 1525 1526 static inline void hal_write_window_register(struct hal_soc *hal_soc) 1527 { 1528 /* Write value into window configuration register */ 1529 qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_REG_ADDRESS, 1530 WINDOW_CONFIGURATION_VALUE_9000); 1531 } 1532 1533 /** 1534 * hal_rx_msdu_packet_metadata_get_9000(): API to get the 1535 * msdu information from rx_msdu_end TLV 1536 * 1537 * @ buf: pointer to the start of RX PKT TLV headers 1538 * @ hal_rx_msdu_metadata: pointer to the msdu info structure 1539 */ 1540 static void 1541 hal_rx_msdu_packet_metadata_get_9000(uint8_t *buf, 1542 void *msdu_pkt_metadata) 1543 { 1544 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1545 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1546 struct hal_rx_msdu_metadata *msdu_metadata = 1547 (struct hal_rx_msdu_metadata *)msdu_pkt_metadata; 1548 1549 msdu_metadata->l3_hdr_pad = 1550 HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 1551 msdu_metadata->sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 1552 msdu_metadata->da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 1553 msdu_metadata->sa_sw_peer_id = 1554 HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 1555 } 1556 1557 /** 1558 * hal_rx_flow_setup_fse_9000() - Setup a flow search entry in HW FST 1559 * @fst: Pointer to the Rx Flow Search Table 1560 * @table_offset: offset into the table where the flow is to be setup 1561 * @flow: Flow Parameters 1562 * 1563 * Return: Success/Failure 1564 */ 1565 static void * 1566 hal_rx_flow_setup_fse_9000(uint8_t *rx_fst, uint32_t table_offset, 1567 uint8_t *rx_flow) 1568 { 1569 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 1570 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 1571 uint8_t *fse; 1572 bool fse_valid; 1573 1574 if (table_offset >= fst->max_entries) { 1575 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 1576 "HAL FSE table offset %u exceeds max entries %u", 1577 table_offset, fst->max_entries); 1578 return NULL; 1579 } 1580 1581 fse = (uint8_t *)fst->base_vaddr + 1582 (table_offset * HAL_RX_FST_ENTRY_SIZE); 1583 1584 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1585 1586 if (fse_valid) { 1587 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 1588 "HAL FSE %pK already valid", fse); 1589 return NULL; 1590 } 1591 1592 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96) = 1593 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96, 1594 qdf_htonl(flow->tuple_info.src_ip_127_96)); 1595 1596 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64) = 1597 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64, 1598 qdf_htonl(flow->tuple_info.src_ip_95_64)); 1599 1600 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32) = 1601 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32, 1602 qdf_htonl(flow->tuple_info.src_ip_63_32)); 1603 1604 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0) = 1605 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0, 1606 qdf_htonl(flow->tuple_info.src_ip_31_0)); 1607 1608 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96) = 1609 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96, 1610 qdf_htonl(flow->tuple_info.dest_ip_127_96)); 1611 1612 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64) = 1613 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64, 1614 qdf_htonl(flow->tuple_info.dest_ip_95_64)); 1615 1616 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32) = 1617 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32, 1618 qdf_htonl(flow->tuple_info.dest_ip_63_32)); 1619 1620 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0) = 1621 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0, 1622 qdf_htonl(flow->tuple_info.dest_ip_31_0)); 1623 1624 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT); 1625 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT) |= 1626 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, DEST_PORT, 1627 (flow->tuple_info.dest_port)); 1628 1629 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT); 1630 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT) |= 1631 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, SRC_PORT, 1632 (flow->tuple_info.src_port)); 1633 1634 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL); 1635 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL) |= 1636 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL, 1637 flow->tuple_info.l4_protocol); 1638 1639 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER); 1640 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER) |= 1641 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER, 1642 flow->reo_destination_handler); 1643 1644 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1645 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID) |= 1646 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, VALID, 1); 1647 1648 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA); 1649 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA) = 1650 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_10, METADATA, 1651 flow->fse_metadata); 1652 1653 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION); 1654 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION) |= 1655 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, 1656 REO_DESTINATION_INDICATION, 1657 flow->reo_destination_indication); 1658 1659 /* Reset all the other fields in FSE */ 1660 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, RESERVED_9); 1661 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, MSDU_DROP); 1662 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_COUNT); 1663 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_12, MSDU_BYTE_COUNT); 1664 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_13, TIMESTAMP); 1665 1666 return fse; 1667 } 1668 1669 static 1670 void hal_compute_reo_remap_ix2_ix3_9000(uint32_t *ring, uint32_t num_rings, 1671 uint32_t *remap1, uint32_t *remap2) 1672 { 1673 switch (num_rings) { 1674 case 1: 1675 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1676 HAL_REO_REMAP_IX2(ring[0], 17) | 1677 HAL_REO_REMAP_IX2(ring[0], 18) | 1678 HAL_REO_REMAP_IX2(ring[0], 19) | 1679 HAL_REO_REMAP_IX2(ring[0], 20) | 1680 HAL_REO_REMAP_IX2(ring[0], 21) | 1681 HAL_REO_REMAP_IX2(ring[0], 22) | 1682 HAL_REO_REMAP_IX2(ring[0], 23); 1683 1684 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1685 HAL_REO_REMAP_IX3(ring[0], 25) | 1686 HAL_REO_REMAP_IX3(ring[0], 26) | 1687 HAL_REO_REMAP_IX3(ring[0], 27) | 1688 HAL_REO_REMAP_IX3(ring[0], 28) | 1689 HAL_REO_REMAP_IX3(ring[0], 29) | 1690 HAL_REO_REMAP_IX3(ring[0], 30) | 1691 HAL_REO_REMAP_IX3(ring[0], 31); 1692 break; 1693 case 2: 1694 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1695 HAL_REO_REMAP_IX2(ring[0], 17) | 1696 HAL_REO_REMAP_IX2(ring[1], 18) | 1697 HAL_REO_REMAP_IX2(ring[1], 19) | 1698 HAL_REO_REMAP_IX2(ring[0], 20) | 1699 HAL_REO_REMAP_IX2(ring[0], 21) | 1700 HAL_REO_REMAP_IX2(ring[1], 22) | 1701 HAL_REO_REMAP_IX2(ring[1], 23); 1702 1703 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1704 HAL_REO_REMAP_IX3(ring[0], 25) | 1705 HAL_REO_REMAP_IX3(ring[1], 26) | 1706 HAL_REO_REMAP_IX3(ring[1], 27) | 1707 HAL_REO_REMAP_IX3(ring[0], 28) | 1708 HAL_REO_REMAP_IX3(ring[0], 29) | 1709 HAL_REO_REMAP_IX3(ring[1], 30) | 1710 HAL_REO_REMAP_IX3(ring[1], 31); 1711 break; 1712 case 3: 1713 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1714 HAL_REO_REMAP_IX2(ring[1], 17) | 1715 HAL_REO_REMAP_IX2(ring[2], 18) | 1716 HAL_REO_REMAP_IX2(ring[0], 19) | 1717 HAL_REO_REMAP_IX2(ring[1], 20) | 1718 HAL_REO_REMAP_IX2(ring[2], 21) | 1719 HAL_REO_REMAP_IX2(ring[0], 22) | 1720 HAL_REO_REMAP_IX2(ring[1], 23); 1721 1722 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) | 1723 HAL_REO_REMAP_IX3(ring[0], 25) | 1724 HAL_REO_REMAP_IX3(ring[1], 26) | 1725 HAL_REO_REMAP_IX3(ring[2], 27) | 1726 HAL_REO_REMAP_IX3(ring[0], 28) | 1727 HAL_REO_REMAP_IX3(ring[1], 29) | 1728 HAL_REO_REMAP_IX3(ring[2], 30) | 1729 HAL_REO_REMAP_IX3(ring[0], 31); 1730 break; 1731 case 4: 1732 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1733 HAL_REO_REMAP_IX2(ring[1], 17) | 1734 HAL_REO_REMAP_IX2(ring[2], 18) | 1735 HAL_REO_REMAP_IX2(ring[3], 19) | 1736 HAL_REO_REMAP_IX2(ring[0], 20) | 1737 HAL_REO_REMAP_IX2(ring[1], 21) | 1738 HAL_REO_REMAP_IX2(ring[2], 22) | 1739 HAL_REO_REMAP_IX2(ring[3], 23); 1740 1741 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1742 HAL_REO_REMAP_IX3(ring[1], 25) | 1743 HAL_REO_REMAP_IX3(ring[2], 26) | 1744 HAL_REO_REMAP_IX3(ring[3], 27) | 1745 HAL_REO_REMAP_IX3(ring[0], 28) | 1746 HAL_REO_REMAP_IX3(ring[1], 29) | 1747 HAL_REO_REMAP_IX3(ring[2], 30) | 1748 HAL_REO_REMAP_IX3(ring[3], 31); 1749 break; 1750 } 1751 } 1752 1753 static void hal_hw_txrx_ops_attach_qcn9000(struct hal_soc *hal_soc) 1754 { 1755 1756 /* init and setup */ 1757 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic; 1758 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic; 1759 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic; 1760 hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_li; 1761 hal_soc->ops->hal_get_window_address = hal_get_window_address_9000; 1762 1763 /* tx */ 1764 hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id = 1765 hal_tx_desc_set_dscp_tid_table_id_9000; 1766 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_9000; 1767 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_9000; 1768 hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_9000; 1769 hal_soc->ops->hal_tx_desc_set_buf_addr = 1770 hal_tx_desc_set_buf_addr_generic_li; 1771 hal_soc->ops->hal_tx_desc_set_search_type = 1772 hal_tx_desc_set_search_type_generic_li; 1773 hal_soc->ops->hal_tx_desc_set_search_index = 1774 hal_tx_desc_set_search_index_generic_li; 1775 hal_soc->ops->hal_tx_desc_set_cache_set_num = 1776 hal_tx_desc_set_cache_set_num_generic_li; 1777 hal_soc->ops->hal_tx_comp_get_status = 1778 hal_tx_comp_get_status_generic_li; 1779 hal_soc->ops->hal_tx_comp_get_release_reason = 1780 hal_tx_comp_get_release_reason_generic_li; 1781 hal_soc->ops->hal_get_wbm_internal_error = 1782 hal_get_wbm_internal_error_generic_li; 1783 hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_9000; 1784 hal_soc->ops->hal_tx_init_cmd_credit_ring = 1785 hal_tx_init_cmd_credit_ring_9000; 1786 1787 /* rx */ 1788 hal_soc->ops->hal_rx_msdu_start_nss_get = 1789 hal_rx_msdu_start_nss_get_9000; 1790 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status = 1791 hal_rx_mon_hw_desc_get_mpdu_status_9000; 1792 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_9000; 1793 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv = 1794 hal_rx_proc_phyrx_other_receive_info_tlv_9000; 1795 hal_soc->ops->hal_rx_dump_msdu_start_tlv = 1796 hal_rx_dump_msdu_start_tlv_9000; 1797 hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_9000; 1798 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_9000; 1799 hal_soc->ops->hal_rx_mpdu_start_tid_get = 1800 hal_rx_mpdu_start_tid_get_9000; 1801 hal_soc->ops->hal_rx_msdu_start_reception_type_get = 1802 hal_rx_msdu_start_reception_type_get_9000; 1803 hal_soc->ops->hal_rx_msdu_end_da_idx_get = 1804 hal_rx_msdu_end_da_idx_get_9000; 1805 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = 1806 hal_rx_msdu_desc_info_get_ptr_9000; 1807 hal_soc->ops->hal_rx_link_desc_msdu0_ptr = 1808 hal_rx_link_desc_msdu0_ptr_9000; 1809 hal_soc->ops->hal_reo_status_get_header = 1810 hal_reo_status_get_header_9000; 1811 hal_soc->ops->hal_rx_status_get_tlv_info = 1812 hal_rx_status_get_tlv_info_generic_li; 1813 hal_soc->ops->hal_rx_wbm_err_info_get = 1814 hal_rx_wbm_err_info_get_generic_li; 1815 hal_soc->ops->hal_rx_dump_mpdu_start_tlv = 1816 hal_rx_dump_mpdu_start_tlv_generic_li; 1817 1818 hal_soc->ops->hal_tx_set_pcp_tid_map = 1819 hal_tx_set_pcp_tid_map_generic_li; 1820 hal_soc->ops->hal_tx_update_pcp_tid_map = 1821 hal_tx_update_pcp_tid_generic_li; 1822 hal_soc->ops->hal_tx_set_tidmap_prty = 1823 hal_tx_update_tidmap_prty_generic_li; 1824 hal_soc->ops->hal_rx_get_rx_fragment_number = 1825 hal_rx_get_rx_fragment_number_9000; 1826 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = 1827 hal_rx_msdu_end_da_is_mcbc_get_9000; 1828 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = 1829 hal_rx_msdu_end_sa_is_valid_get_9000; 1830 hal_soc->ops->hal_rx_msdu_end_sa_idx_get = 1831 hal_rx_msdu_end_sa_idx_get_9000; 1832 hal_soc->ops->hal_rx_desc_is_first_msdu = 1833 hal_rx_desc_is_first_msdu_9000; 1834 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get = 1835 hal_rx_msdu_end_l3_hdr_padding_get_9000; 1836 hal_soc->ops->hal_rx_encryption_info_valid = 1837 hal_rx_encryption_info_valid_9000; 1838 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_9000; 1839 hal_soc->ops->hal_rx_msdu_end_first_msdu_get = 1840 hal_rx_msdu_end_first_msdu_get_9000; 1841 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = 1842 hal_rx_msdu_end_da_is_valid_get_9000; 1843 hal_soc->ops->hal_rx_msdu_end_last_msdu_get = 1844 hal_rx_msdu_end_last_msdu_get_9000; 1845 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = 1846 hal_rx_get_mpdu_mac_ad4_valid_9000; 1847 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get = 1848 hal_rx_mpdu_start_sw_peer_id_get_9000; 1849 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_9000; 1850 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_9000; 1851 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid = 1852 hal_rx_get_mpdu_frame_control_valid_9000; 1853 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_9000; 1854 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_9000; 1855 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_9000; 1856 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_9000; 1857 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid = 1858 hal_rx_get_mpdu_sequence_control_valid_9000; 1859 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_9000; 1860 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_9000; 1861 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = 1862 hal_rx_hw_desc_get_ppduid_get_9000; 1863 hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get = 1864 hal_rx_mpdu_start_mpdu_qos_control_valid_get_9000; 1865 hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get = 1866 hal_rx_msdu_end_sa_sw_peer_id_get_9000; 1867 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = 1868 hal_rx_msdu0_buffer_addr_lsb_9000; 1869 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = 1870 hal_rx_msdu_desc_info_ptr_get_9000; 1871 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_9000; 1872 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_9000; 1873 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_9000; 1874 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_9000; 1875 hal_soc->ops->hal_rx_get_mac_addr2_valid = 1876 hal_rx_get_mac_addr2_valid_9000; 1877 hal_soc->ops->hal_rx_get_filter_category = 1878 hal_rx_get_filter_category_9000; 1879 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_9000; 1880 hal_soc->ops->hal_reo_config = hal_reo_config_9000; 1881 hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_9000; 1882 hal_soc->ops->hal_rx_msdu_flow_idx_invalid = 1883 hal_rx_msdu_flow_idx_invalid_9000; 1884 hal_soc->ops->hal_rx_msdu_flow_idx_timeout = 1885 hal_rx_msdu_flow_idx_timeout_9000; 1886 hal_soc->ops->hal_rx_msdu_fse_metadata_get = 1887 hal_rx_msdu_fse_metadata_get_9000; 1888 hal_soc->ops->hal_rx_msdu_cce_metadata_get = 1889 hal_rx_msdu_cce_metadata_get_9000; 1890 hal_soc->ops->hal_rx_msdu_get_flow_params = 1891 hal_rx_msdu_get_flow_params_9000; 1892 hal_soc->ops->hal_rx_tlv_get_tcp_chksum = 1893 hal_rx_tlv_get_tcp_chksum_9000; 1894 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_9000; 1895 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) 1896 hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_9000; 1897 hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_9000; 1898 #endif 1899 /* rx - msdu fast path info fields */ 1900 hal_soc->ops->hal_rx_msdu_packet_metadata_get = 1901 hal_rx_msdu_packet_metadata_get_9000; 1902 hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid = 1903 hal_rx_mpdu_start_tlv_tag_valid_9000; 1904 hal_soc->ops->hal_rx_sw_mon_desc_info_get = 1905 hal_rx_sw_mon_desc_info_get_9000; 1906 hal_soc->ops->hal_rx_wbm_err_msdu_continuation_get = 1907 hal_rx_wbm_err_msdu_continuation_get_9000; 1908 1909 /* rx - TLV struct offsets */ 1910 hal_soc->ops->hal_rx_msdu_end_offset_get = 1911 hal_rx_msdu_end_offset_get_generic; 1912 hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic; 1913 hal_soc->ops->hal_rx_msdu_start_offset_get = 1914 hal_rx_msdu_start_offset_get_generic; 1915 hal_soc->ops->hal_rx_mpdu_start_offset_get = 1916 hal_rx_mpdu_start_offset_get_generic; 1917 hal_soc->ops->hal_rx_mpdu_end_offset_get = 1918 hal_rx_mpdu_end_offset_get_generic; 1919 #ifndef NO_RX_PKT_HDR_TLV 1920 hal_soc->ops->hal_rx_pkt_tlv_offset_get = 1921 hal_rx_pkt_tlv_offset_get_generic; 1922 #endif 1923 hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_9000; 1924 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = 1925 hal_compute_reo_remap_ix2_ix3_9000; 1926 hal_soc->ops->hal_setup_link_idle_list = 1927 hal_setup_link_idle_list_generic_li; 1928 }; 1929 1930 struct hal_hw_srng_config hw_srng_table_9000[] = { 1931 /* TODO: max_rings can populated by querying HW capabilities */ 1932 { /* REO_DST */ 1933 .start_ring_id = HAL_SRNG_REO2SW1, 1934 .max_rings = 4, 1935 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1936 .lmac_ring = FALSE, 1937 .ring_dir = HAL_SRNG_DST_RING, 1938 .reg_start = { 1939 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 1940 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1941 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 1942 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1943 }, 1944 .reg_size = { 1945 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 1946 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 1947 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 1948 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 1949 }, 1950 .max_size = 1951 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 1952 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 1953 }, 1954 { /* REO_EXCEPTION */ 1955 /* Designating REO2TCL ring as exception ring. This ring is 1956 * similar to other REO2SW rings though it is named as REO2TCL. 1957 * Any of theREO2SW rings can be used as exception ring. 1958 */ 1959 .start_ring_id = HAL_SRNG_REO2TCL, 1960 .max_rings = 1, 1961 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1962 .lmac_ring = FALSE, 1963 .ring_dir = HAL_SRNG_DST_RING, 1964 .reg_start = { 1965 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 1966 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1967 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 1968 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1969 }, 1970 /* Single ring - provide ring size if multiple rings of this 1971 * type are supported 1972 */ 1973 .reg_size = {}, 1974 .max_size = 1975 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 1976 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 1977 }, 1978 { /* REO_REINJECT */ 1979 .start_ring_id = HAL_SRNG_SW2REO, 1980 .max_rings = 1, 1981 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1982 .lmac_ring = FALSE, 1983 .ring_dir = HAL_SRNG_SRC_RING, 1984 .reg_start = { 1985 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 1986 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1987 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 1988 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1989 }, 1990 /* Single ring - provide ring size if multiple rings of this 1991 * type are supported 1992 */ 1993 .reg_size = {}, 1994 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 1995 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 1996 }, 1997 { /* REO_CMD */ 1998 .start_ring_id = HAL_SRNG_REO_CMD, 1999 .max_rings = 1, 2000 .entry_size = (sizeof(struct tlv_32_hdr) + 2001 sizeof(struct reo_get_queue_stats)) >> 2, 2002 .lmac_ring = FALSE, 2003 .ring_dir = HAL_SRNG_SRC_RING, 2004 .reg_start = { 2005 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 2006 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2007 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 2008 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2009 }, 2010 /* Single ring - provide ring size if multiple rings of this 2011 * type are supported 2012 */ 2013 .reg_size = {}, 2014 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 2015 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 2016 }, 2017 { /* REO_STATUS */ 2018 .start_ring_id = HAL_SRNG_REO_STATUS, 2019 .max_rings = 1, 2020 .entry_size = (sizeof(struct tlv_32_hdr) + 2021 sizeof(struct reo_get_queue_stats_status)) >> 2, 2022 .lmac_ring = FALSE, 2023 .ring_dir = HAL_SRNG_DST_RING, 2024 .reg_start = { 2025 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 2026 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2027 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 2028 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2029 }, 2030 /* Single ring - provide ring size if multiple rings of this 2031 * type are supported 2032 */ 2033 .reg_size = {}, 2034 .max_size = 2035 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 2036 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 2037 }, 2038 { /* TCL_DATA */ 2039 .start_ring_id = HAL_SRNG_SW2TCL1, 2040 .max_rings = 3, 2041 .entry_size = (sizeof(struct tlv_32_hdr) + 2042 sizeof(struct tcl_data_cmd)) >> 2, 2043 .lmac_ring = FALSE, 2044 .ring_dir = HAL_SRNG_SRC_RING, 2045 .reg_start = { 2046 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 2047 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2048 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 2049 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2050 }, 2051 .reg_size = { 2052 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 2053 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 2054 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 2055 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 2056 }, 2057 .max_size = 2058 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 2059 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 2060 }, 2061 { /* TCL_CMD/CREDIT */ 2062 /* qca8074v2 and qcn9000 uses this ring for data commands */ 2063 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 2064 .max_rings = 1, 2065 .entry_size = (sizeof(struct tlv_32_hdr) + 2066 sizeof(struct tcl_data_cmd)) >> 2, 2067 .lmac_ring = FALSE, 2068 .ring_dir = HAL_SRNG_SRC_RING, 2069 .reg_start = { 2070 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR( 2071 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2072 HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR( 2073 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2074 }, 2075 /* Single ring - provide ring size if multiple rings of this 2076 * type are supported 2077 */ 2078 .reg_size = {}, 2079 .max_size = 2080 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >> 2081 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT, 2082 }, 2083 { /* TCL_STATUS */ 2084 .start_ring_id = HAL_SRNG_TCL_STATUS, 2085 .max_rings = 1, 2086 .entry_size = (sizeof(struct tlv_32_hdr) + 2087 sizeof(struct tcl_status_ring)) >> 2, 2088 .lmac_ring = FALSE, 2089 .ring_dir = HAL_SRNG_DST_RING, 2090 .reg_start = { 2091 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 2092 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2093 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 2094 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2095 }, 2096 /* Single ring - provide ring size if multiple rings of this 2097 * type are supported 2098 */ 2099 .reg_size = {}, 2100 .max_size = 2101 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 2102 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 2103 }, 2104 { /* CE_SRC */ 2105 .start_ring_id = HAL_SRNG_CE_0_SRC, 2106 .max_rings = 12, 2107 .entry_size = sizeof(struct ce_src_desc) >> 2, 2108 .lmac_ring = FALSE, 2109 .ring_dir = HAL_SRNG_SRC_RING, 2110 .reg_start = { 2111 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 2112 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 2113 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 2114 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 2115 }, 2116 .reg_size = { 2117 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 2118 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 2119 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 2120 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 2121 }, 2122 .max_size = 2123 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 2124 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 2125 }, 2126 { /* CE_DST */ 2127 .start_ring_id = HAL_SRNG_CE_0_DST, 2128 .max_rings = 12, 2129 .entry_size = 8 >> 2, 2130 /*TODO: entry_size above should actually be 2131 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 2132 * of struct ce_dst_desc in HW header files 2133 */ 2134 .lmac_ring = FALSE, 2135 .ring_dir = HAL_SRNG_SRC_RING, 2136 .reg_start = { 2137 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 2138 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2139 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 2140 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2141 }, 2142 .reg_size = { 2143 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2144 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2145 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2146 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2147 }, 2148 .max_size = 2149 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 2150 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 2151 }, 2152 { /* CE_DST_STATUS */ 2153 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 2154 .max_rings = 12, 2155 .entry_size = sizeof(struct ce_stat_desc) >> 2, 2156 .lmac_ring = FALSE, 2157 .ring_dir = HAL_SRNG_DST_RING, 2158 .reg_start = { 2159 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 2160 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2161 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 2162 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2163 }, 2164 /* TODO: check destination status ring registers */ 2165 .reg_size = { 2166 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2167 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2168 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2169 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2170 }, 2171 .max_size = 2172 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 2173 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 2174 }, 2175 { /* WBM_IDLE_LINK */ 2176 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 2177 .max_rings = 1, 2178 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 2179 .lmac_ring = FALSE, 2180 .ring_dir = HAL_SRNG_SRC_RING, 2181 .reg_start = { 2182 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2183 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2184 }, 2185 /* Single ring - provide ring size if multiple rings of this 2186 * type are supported 2187 */ 2188 .reg_size = {}, 2189 .max_size = 2190 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 2191 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 2192 }, 2193 { /* SW2WBM_RELEASE */ 2194 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 2195 .max_rings = 1, 2196 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2197 .lmac_ring = FALSE, 2198 .ring_dir = HAL_SRNG_SRC_RING, 2199 .reg_start = { 2200 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2201 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2202 }, 2203 /* Single ring - provide ring size if multiple rings of this 2204 * type are supported 2205 */ 2206 .reg_size = {}, 2207 .max_size = 2208 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2209 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2210 }, 2211 { /* WBM2SW_RELEASE */ 2212 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 2213 .max_rings = 4, 2214 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2215 .lmac_ring = FALSE, 2216 .ring_dir = HAL_SRNG_DST_RING, 2217 .reg_start = { 2218 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2219 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2220 }, 2221 .reg_size = { 2222 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 2223 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2224 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 2225 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2226 }, 2227 .max_size = 2228 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2229 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2230 }, 2231 { /* RXDMA_BUF */ 2232 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 2233 #ifdef IPA_OFFLOAD 2234 .max_rings = 3, 2235 #else 2236 .max_rings = 2, 2237 #endif 2238 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2239 .lmac_ring = TRUE, 2240 .ring_dir = HAL_SRNG_SRC_RING, 2241 /* reg_start is not set because LMAC rings are not accessed 2242 * from host 2243 */ 2244 .reg_start = {}, 2245 .reg_size = {}, 2246 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2247 }, 2248 { /* RXDMA_DST */ 2249 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 2250 .max_rings = 1, 2251 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2252 .lmac_ring = TRUE, 2253 .ring_dir = HAL_SRNG_DST_RING, 2254 /* reg_start is not set because LMAC rings are not accessed 2255 * from host 2256 */ 2257 .reg_start = {}, 2258 .reg_size = {}, 2259 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2260 }, 2261 { /* RXDMA_MONITOR_BUF */ 2262 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 2263 .max_rings = 1, 2264 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2265 .lmac_ring = TRUE, 2266 .ring_dir = HAL_SRNG_SRC_RING, 2267 /* reg_start is not set because LMAC rings are not accessed 2268 * from host 2269 */ 2270 .reg_start = {}, 2271 .reg_size = {}, 2272 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2273 }, 2274 { /* RXDMA_MONITOR_STATUS */ 2275 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 2276 .max_rings = 1, 2277 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2278 .lmac_ring = TRUE, 2279 .ring_dir = HAL_SRNG_SRC_RING, 2280 /* reg_start is not set because LMAC rings are not accessed 2281 * from host 2282 */ 2283 .reg_start = {}, 2284 .reg_size = {}, 2285 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2286 }, 2287 { /* RXDMA_MONITOR_DST */ 2288 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 2289 .max_rings = 1, 2290 .entry_size = sizeof(struct sw_monitor_ring) >> 2, 2291 .lmac_ring = TRUE, 2292 .ring_dir = HAL_SRNG_DST_RING, 2293 /* reg_start is not set because LMAC rings are not accessed 2294 * from host 2295 */ 2296 .reg_start = {}, 2297 .reg_size = {}, 2298 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2299 }, 2300 { /* RXDMA_MONITOR_DESC */ 2301 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 2302 .max_rings = 1, 2303 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2304 .lmac_ring = TRUE, 2305 .ring_dir = HAL_SRNG_SRC_RING, 2306 /* reg_start is not set because LMAC rings are not accessed 2307 * from host 2308 */ 2309 .reg_start = {}, 2310 .reg_size = {}, 2311 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2312 }, 2313 { /* DIR_BUF_RX_DMA_SRC */ 2314 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 2315 /* one ring for spectral and one ring for cfr */ 2316 .max_rings = 2, 2317 .entry_size = 2, 2318 .lmac_ring = TRUE, 2319 .ring_dir = HAL_SRNG_SRC_RING, 2320 /* reg_start is not set because LMAC rings are not accessed 2321 * from host 2322 */ 2323 .reg_start = {}, 2324 .reg_size = {}, 2325 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2326 }, 2327 #ifdef WLAN_FEATURE_CIF_CFR 2328 { /* WIFI_POS_SRC */ 2329 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 2330 .max_rings = 1, 2331 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 2332 .lmac_ring = TRUE, 2333 .ring_dir = HAL_SRNG_SRC_RING, 2334 /* reg_start is not set because LMAC rings are not accessed 2335 * from host 2336 */ 2337 .reg_start = {}, 2338 .reg_size = {}, 2339 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2340 }, 2341 #endif 2342 { /* REO2PPE */ 0}, 2343 { /* PPE2TCL */ 0}, 2344 { /* PPE_RELEASE */ 0}, 2345 { /* TX_MONITOR_BUF */ 0}, 2346 { /* TX_MONITOR_DST */ 0}, 2347 { /* SW2RXDMA_NEW */ 0}, 2348 }; 2349 2350 /** 2351 * hal_qcn9000_attach()- Attach 9000 target specific hal_soc ops, 2352 * offset and srng table 2353 * Return: void 2354 */ 2355 void hal_qcn9000_attach(struct hal_soc *hal_soc) 2356 { 2357 hal_soc->hw_srng_table = hw_srng_table_9000; 2358 hal_srng_hw_reg_offset_init_generic(hal_soc); 2359 hal_hw_txrx_default_ops_attach_li(hal_soc); 2360 hal_hw_txrx_ops_attach_qcn9000(hal_soc); 2361 if (hal_soc->static_window_map) 2362 hal_write_window_register(hal_soc); 2363 } 2364