1 /* 2 * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #include "hal_hw_headers.h" 19 #include "hal_internal.h" 20 #include "hal_api.h" 21 #include "target_type.h" 22 #include "wcss_version.h" 23 #include "qdf_module.h" 24 25 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 26 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET 27 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 28 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK 29 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 30 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB 31 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 32 PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 33 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 34 PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 35 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 36 PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 37 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 38 PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 39 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 40 PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 41 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 42 PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 43 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 44 PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 45 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 46 PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 47 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 48 PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 49 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 50 PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 51 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 52 PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 53 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 54 RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 55 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 56 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 57 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 58 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 59 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 60 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 61 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 62 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 63 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER \ 64 STATUS_HEADER_REO_STATUS_NUMBER 65 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 66 STATUS_HEADER_TIMESTAMP 67 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 68 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 69 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 70 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 71 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 72 TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 73 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 74 TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 75 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 76 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 77 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 78 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 79 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 80 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 81 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 82 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 83 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 84 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 85 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 86 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 87 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 88 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 89 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 90 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 91 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 92 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 93 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 94 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 95 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 96 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 97 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 98 WBM_RELEASE_RING_6_TX_RATE_STATS_TSF_DIRECTLY_AFTER_PPDU_TRANSMISSION_MASK 99 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 100 WBM_RELEASE_RING_6_TX_RATE_STATS_TSF_DIRECTLY_AFTER_PPDU_TRANSMISSION_OFFSET 101 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 102 WBM_RELEASE_RING_6_TX_RATE_STATS_TSF_DIRECTLY_AFTER_PPDU_TRANSMISSION_LSB 103 104 /* Including hkv2 files as the functions between hkv2 and pine are exactly 105 * similar 106 */ 107 #include <hal_8074v2_tx.h> 108 #include <hal_8074v2_rx.h> 109 #include <hal_generic_api.h> 110 #include <hal_wbm.h> 111 112 #define HAL_RX_MPDU_GET_SEQUENCE_NUMBER(_rx_mpdu_info) \ 113 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 114 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_OFFSET)), \ 115 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_MASK, \ 116 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_LSB)) 117 118 /** 119 * hal_rx_get_rx_fragment_number_9000(): Function to retrieve rx fragment number 120 * 121 * @nbuf: Network buffer 122 * Returns: rx fragment number 123 */ 124 static 125 uint8_t hal_rx_get_rx_fragment_number_9000(uint8_t *buf) 126 { 127 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 128 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 129 130 /* Return first 4 bits as fragment number */ 131 return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & 132 DOT11_SEQ_FRAG_MASK); 133 } 134 135 /** 136 * hal_rx_msdu_end_da_is_mcbc_get_9000(): API to check if pkt is MCBC 137 * from rx_msdu_end TLV 138 * 139 * @ buf: pointer to the start of RX PKT TLV headers 140 * Return: da_is_mcbc 141 */ 142 static uint8_t 143 hal_rx_msdu_end_da_is_mcbc_get_9000(uint8_t *buf) 144 { 145 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 146 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 147 148 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); 149 } 150 151 /** 152 * hal_rx_msdu_end_sa_is_valid_get_9000(): API to get_9000 the 153 * sa_is_valid bit from rx_msdu_end TLV 154 * 155 * @ buf: pointer to the start of RX PKT TLV headers 156 * Return: sa_is_valid bit 157 */ 158 static uint8_t 159 hal_rx_msdu_end_sa_is_valid_get_9000(uint8_t *buf) 160 { 161 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 162 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 163 uint8_t sa_is_valid; 164 165 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); 166 167 return sa_is_valid; 168 } 169 170 /** 171 * hal_rx_msdu_end_sa_idx_get_9000(): API to get_9000 the 172 * sa_idx from rx_msdu_end TLV 173 * 174 * @ buf: pointer to the start of RX PKT TLV headers 175 * Return: sa_idx (SA AST index) 176 */ 177 static uint16_t hal_rx_msdu_end_sa_idx_get_9000(uint8_t *buf) 178 { 179 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 180 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 181 uint16_t sa_idx; 182 183 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 184 185 return sa_idx; 186 } 187 188 /** 189 * hal_rx_desc_is_first_msdu_9000() - Check if first msdu 190 * 191 * @hal_soc_hdl: hal_soc handle 192 * @hw_desc_addr: hardware descriptor address 193 * 194 * Return: 0 - success/ non-zero failure 195 */ 196 static uint32_t hal_rx_desc_is_first_msdu_9000(void *hw_desc_addr) 197 { 198 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; 199 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; 200 201 return HAL_RX_GET(msdu_end, RX_MSDU_END_5, FIRST_MSDU); 202 } 203 204 /** 205 * hal_rx_msdu_end_l3_hdr_padding_get_9000(): API to get_9000 the 206 * l3_header padding from rx_msdu_end TLV 207 * 208 * @ buf: pointer to the start of RX PKT TLV headers 209 * Return: number of l3 header padding bytes 210 */ 211 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_9000(uint8_t *buf) 212 { 213 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 214 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 215 uint32_t l3_header_padding; 216 217 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 218 219 return l3_header_padding; 220 } 221 222 /** 223 * @ hal_rx_encryption_info_valid_9000: Returns encryption type. 224 * 225 * @ buf: rx_tlv_hdr of the received packet 226 * @ Return: encryption type 227 */ 228 inline uint32_t hal_rx_encryption_info_valid_9000(uint8_t *buf) 229 { 230 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 231 struct rx_mpdu_start *mpdu_start = 232 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 233 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 234 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); 235 236 return encryption_info; 237 } 238 239 /* 240 * @ hal_rx_print_pn_9000: Prints the PN of rx packet. 241 * 242 * @ buf: rx_tlv_hdr of the received packet 243 * @ Return: void 244 */ 245 static void hal_rx_print_pn_9000(uint8_t *buf) 246 { 247 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 248 struct rx_mpdu_start *mpdu_start = 249 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 250 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 251 252 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); 253 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); 254 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); 255 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); 256 257 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ", 258 pn_127_96, pn_95_64, pn_63_32, pn_31_0); 259 } 260 261 /** 262 * hal_rx_msdu_end_first_msdu_get_9000: API to get first msdu status 263 * from rx_msdu_end TLV 264 * 265 * @ buf: pointer to the start of RX PKT TLV headers 266 * Return: first_msdu 267 */ 268 static uint8_t hal_rx_msdu_end_first_msdu_get_9000(uint8_t *buf) 269 { 270 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 271 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 272 uint8_t first_msdu; 273 274 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); 275 276 return first_msdu; 277 } 278 279 /** 280 * hal_rx_msdu_end_da_is_valid_get_9000: API to check if da is valid 281 * from rx_msdu_end TLV 282 * 283 * @ buf: pointer to the start of RX PKT TLV headers 284 * Return: da_is_valid 285 */ 286 static uint8_t hal_rx_msdu_end_da_is_valid_get_9000(uint8_t *buf) 287 { 288 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 289 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 290 uint8_t da_is_valid; 291 292 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); 293 294 return da_is_valid; 295 } 296 297 /** 298 * hal_rx_msdu_end_last_msdu_get_9000: API to get last msdu status 299 * from rx_msdu_end TLV 300 * 301 * @ buf: pointer to the start of RX PKT TLV headers 302 * Return: last_msdu 303 */ 304 static uint8_t hal_rx_msdu_end_last_msdu_get_9000(uint8_t *buf) 305 { 306 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 307 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 308 uint8_t last_msdu; 309 310 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); 311 312 return last_msdu; 313 } 314 315 /* 316 * hal_rx_get_mpdu_mac_ad4_valid(): Retrieves if mpdu 4th addr is valid 317 * 318 * @nbuf: Network buffer 319 * Returns: value of mpdu 4th address valid field 320 */ 321 inline bool hal_rx_get_mpdu_mac_ad4_valid_9000(uint8_t *buf) 322 { 323 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 324 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 325 bool ad4_valid = 0; 326 327 ad4_valid = HAL_RX_MPDU_GET_MAC_AD4_VALID(rx_mpdu_info); 328 329 return ad4_valid; 330 } 331 332 /** 333 * hal_rx_mpdu_start_sw_peer_id_get_9000: Retrieve sw peer_id 334 * @buf: network buffer 335 * 336 * Return: sw peer_id 337 */ 338 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_9000(uint8_t *buf) 339 { 340 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 341 struct rx_mpdu_start *mpdu_start = 342 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 343 344 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET( 345 &mpdu_start->rx_mpdu_info_details); 346 } 347 348 /* 349 * hal_rx_mpdu_get_to_ds_9000(): API to get the tods info 350 * from rx_mpdu_start 351 * 352 * @buf: pointer to the start of RX PKT TLV header 353 * Return: uint32_t(to_ds) 354 */ 355 static uint32_t hal_rx_mpdu_get_to_ds_9000(uint8_t *buf) 356 { 357 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 358 struct rx_mpdu_start *mpdu_start = 359 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 360 361 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 362 363 return HAL_RX_MPDU_GET_TODS(mpdu_info); 364 } 365 366 /* 367 * hal_rx_mpdu_get_fr_ds_9000(): API to get the from ds info 368 * from rx_mpdu_start 369 * 370 * @buf: pointer to the start of RX PKT TLV header 371 * Return: uint32_t(fr_ds) 372 */ 373 static uint32_t hal_rx_mpdu_get_fr_ds_9000(uint8_t *buf) 374 { 375 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 376 struct rx_mpdu_start *mpdu_start = 377 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 378 379 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 380 381 return HAL_RX_MPDU_GET_FROMDS(mpdu_info); 382 } 383 384 /* 385 * hal_rx_get_mpdu_frame_control_valid_9000(): Retrieves mpdu 386 * frame control valid 387 * 388 * @nbuf: Network buffer 389 * Returns: value of frame control valid field 390 */ 391 static uint8_t hal_rx_get_mpdu_frame_control_valid_9000(uint8_t *buf) 392 { 393 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 394 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 395 396 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); 397 } 398 399 /* 400 * hal_rx_mpdu_get_addr1_9000(): API to check get address1 of the mpdu 401 * 402 * @buf: pointer to the start of RX PKT TLV headera 403 * @mac_addr: pointer to mac address 404 * Return: success/failure 405 */ 406 static QDF_STATUS hal_rx_mpdu_get_addr1_9000(uint8_t *buf, 407 uint8_t *mac_addr) 408 { 409 struct __attribute__((__packed__)) hal_addr1 { 410 uint32_t ad1_31_0; 411 uint16_t ad1_47_32; 412 }; 413 414 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 415 struct rx_mpdu_start *mpdu_start = 416 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 417 418 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 419 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; 420 uint32_t mac_addr_ad1_valid; 421 422 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); 423 424 if (mac_addr_ad1_valid) { 425 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); 426 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); 427 return QDF_STATUS_SUCCESS; 428 } 429 430 return QDF_STATUS_E_FAILURE; 431 } 432 433 /* 434 * hal_rx_mpdu_get_addr2_9000(): API to check get address2 of the mpdu 435 * in the packet 436 * 437 * @buf: pointer to the start of RX PKT TLV header 438 * @mac_addr: pointer to mac address 439 * Return: success/failure 440 */ 441 static QDF_STATUS hal_rx_mpdu_get_addr2_9000(uint8_t *buf, uint8_t *mac_addr) 442 { 443 struct __attribute__((__packed__)) hal_addr2 { 444 uint16_t ad2_15_0; 445 uint32_t ad2_47_16; 446 }; 447 448 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 449 struct rx_mpdu_start *mpdu_start = 450 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 451 452 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 453 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; 454 uint32_t mac_addr_ad2_valid; 455 456 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); 457 458 if (mac_addr_ad2_valid) { 459 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); 460 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); 461 return QDF_STATUS_SUCCESS; 462 } 463 464 return QDF_STATUS_E_FAILURE; 465 } 466 467 /* 468 * hal_rx_mpdu_get_addr3_9000(): API to get address3 of the mpdu 469 * in the packet 470 * 471 * @buf: pointer to the start of RX PKT TLV header 472 * @mac_addr: pointer to mac address 473 * Return: success/failure 474 */ 475 static QDF_STATUS hal_rx_mpdu_get_addr3_9000(uint8_t *buf, uint8_t *mac_addr) 476 { 477 struct __attribute__((__packed__)) hal_addr3 { 478 uint32_t ad3_31_0; 479 uint16_t ad3_47_32; 480 }; 481 482 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 483 struct rx_mpdu_start *mpdu_start = 484 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 485 486 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 487 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; 488 uint32_t mac_addr_ad3_valid; 489 490 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); 491 492 if (mac_addr_ad3_valid) { 493 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); 494 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); 495 return QDF_STATUS_SUCCESS; 496 } 497 498 return QDF_STATUS_E_FAILURE; 499 } 500 501 /* 502 * hal_rx_mpdu_get_addr4_9000(): API to get address4 of the mpdu 503 * in the packet 504 * 505 * @buf: pointer to the start of RX PKT TLV header 506 * @mac_addr: pointer to mac address 507 * Return: success/failure 508 */ 509 static QDF_STATUS hal_rx_mpdu_get_addr4_9000(uint8_t *buf, uint8_t *mac_addr) 510 { 511 struct __attribute__((__packed__)) hal_addr4 { 512 uint32_t ad4_31_0; 513 uint16_t ad4_47_32; 514 }; 515 516 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 517 struct rx_mpdu_start *mpdu_start = 518 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 519 520 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 521 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; 522 uint32_t mac_addr_ad4_valid; 523 524 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); 525 526 if (mac_addr_ad4_valid) { 527 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); 528 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); 529 return QDF_STATUS_SUCCESS; 530 } 531 532 return QDF_STATUS_E_FAILURE; 533 } 534 535 /* 536 * hal_rx_get_mpdu_sequence_control_valid_9000(): Get mpdu 537 * sequence control valid 538 * 539 * @nbuf: Network buffer 540 * Returns: value of sequence control valid field 541 */ 542 static uint8_t hal_rx_get_mpdu_sequence_control_valid_9000(uint8_t *buf) 543 { 544 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 545 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 546 547 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); 548 } 549 550 /** 551 * hal_rx_is_unicast_9000: check packet is unicast frame or not. 552 * 553 * @ buf: pointer to rx pkt TLV. 554 * 555 * Return: true on unicast. 556 */ 557 static bool hal_rx_is_unicast_9000(uint8_t *buf) 558 { 559 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 560 struct rx_mpdu_start *mpdu_start = 561 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 562 uint32_t grp_id; 563 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 564 565 grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 566 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_OFFSET)), 567 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_MASK, 568 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_LSB)); 569 570 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false; 571 } 572 573 /** 574 * hal_rx_tid_get_9000: get tid based on qos control valid. 575 * @hal_soc_hdl: hal soc handle 576 * @buf: pointer to rx pkt TLV. 577 * 578 * Return: tid 579 */ 580 static uint32_t hal_rx_tid_get_9000(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 581 { 582 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 583 struct rx_mpdu_start *mpdu_start = 584 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 585 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 586 uint8_t qos_control_valid = 587 (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 588 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)), 589 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK, 590 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB)); 591 592 if (qos_control_valid) 593 return hal_rx_mpdu_start_tid_get_8074v2(buf); 594 595 return HAL_RX_NON_QOS_TID; 596 } 597 598 /** 599 * hal_rx_hw_desc_get_ppduid_get_9000(): retrieve ppdu id 600 * @hw_desc_addr: hw addr 601 * 602 * Return: ppdu id 603 */ 604 static uint32_t hal_rx_hw_desc_get_ppduid_get_9000(void *hw_desc_addr) 605 { 606 struct rx_mpdu_info *rx_mpdu_info; 607 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 608 609 rx_mpdu_info = 610 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 611 612 return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_0, PHY_PPDU_ID); 613 } 614 615 /** 616 * hal_reo_status_get_header_9000 - Process reo desc info 617 * @d - Pointer to reo descriptior 618 * @b - tlv type info 619 * @h1 - Pointer to hal_reo_status_header where info to be stored 620 * 621 * Return - none. 622 * 623 */ 624 static void hal_reo_status_get_header_9000(uint32_t *d, int b, void *h1) 625 { 626 uint32_t val1 = 0; 627 struct hal_reo_status_header *h = 628 (struct hal_reo_status_header *)h1; 629 630 switch (b) { 631 case HAL_REO_QUEUE_STATS_STATUS_TLV: 632 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, 633 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 634 break; 635 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 636 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, 637 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 638 break; 639 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 640 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, 641 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 642 break; 643 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 644 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, 645 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 646 break; 647 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 648 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, 649 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 650 break; 651 case HAL_REO_DESC_THRES_STATUS_TLV: 652 val1 = 653 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, 654 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 655 break; 656 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 657 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, 658 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 659 break; 660 default: 661 qdf_nofl_err("ERROR: Unknown tlv\n"); 662 break; 663 } 664 h->cmd_num = 665 HAL_GET_FIELD( 666 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, 667 val1); 668 h->exec_time = 669 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 670 CMD_EXECUTION_TIME, val1); 671 h->status = 672 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 673 REO_CMD_EXECUTION_STATUS, val1); 674 switch (b) { 675 case HAL_REO_QUEUE_STATS_STATUS_TLV: 676 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, 677 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 678 break; 679 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 680 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, 681 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 682 break; 683 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 684 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, 685 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 686 break; 687 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 688 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, 689 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 690 break; 691 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 692 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, 693 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 694 break; 695 case HAL_REO_DESC_THRES_STATUS_TLV: 696 val1 = 697 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, 698 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 699 break; 700 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 701 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, 702 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 703 break; 704 default: 705 qdf_nofl_err("ERROR: Unknown tlv\n"); 706 break; 707 } 708 h->tstamp = 709 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); 710 } 711 712 /** 713 * hal_rx_mpdu_start_mpdu_qos_control_valid_get_9000(): 714 * Retrieve qos control valid bit from the tlv. 715 * @buf: pointer to rx pkt TLV. 716 * 717 * Return: qos control value. 718 */ 719 static inline uint32_t 720 hal_rx_mpdu_start_mpdu_qos_control_valid_get_9000(uint8_t *buf) 721 { 722 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 723 struct rx_mpdu_start *mpdu_start = 724 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 725 726 return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET( 727 &mpdu_start->rx_mpdu_info_details); 728 } 729 730 /** 731 * hal_rx_msdu_end_sa_sw_peer_id_get_9000(): API to get the 732 * sa_sw_peer_id from rx_msdu_end TLV 733 * @buf: pointer to the start of RX PKT TLV headers 734 * 735 * Return: sa_sw_peer_id index 736 */ 737 static inline uint32_t 738 hal_rx_msdu_end_sa_sw_peer_id_get_9000(uint8_t *buf) 739 { 740 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 741 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 742 743 return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 744 } 745 746 /** 747 * hal_tx_desc_set_mesh_en_9000 - Set mesh_enable flag in Tx descriptor 748 * @desc: Handle to Tx Descriptor 749 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 750 * enabling the interpretation of the 'Mesh Control Present' bit 751 * (bit 8) of QoS Control (otherwise this bit is ignored), 752 * For native WiFi frames, this indicates that a 'Mesh Control' field 753 * is present between the header and the LLC. 754 * 755 * Return: void 756 */ 757 static inline 758 void hal_tx_desc_set_mesh_en_9000(void *desc, uint8_t en) 759 { 760 HAL_SET_FLD(desc, TCL_DATA_CMD_4, MESH_ENABLE) |= 761 HAL_TX_SM(TCL_DATA_CMD_4, MESH_ENABLE, en); 762 } 763 764 static 765 void *hal_rx_msdu0_buffer_addr_lsb_9000(void *link_desc_va) 766 { 767 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 768 } 769 770 static 771 void *hal_rx_msdu_desc_info_ptr_get_9000(void *msdu0) 772 { 773 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 774 } 775 776 static 777 void *hal_ent_mpdu_desc_info_9000(void *ent_ring_desc) 778 { 779 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 780 } 781 782 static 783 void *hal_dst_mpdu_desc_info_9000(void *dst_ring_desc) 784 { 785 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 786 } 787 788 static 789 uint8_t hal_rx_get_fc_valid_9000(uint8_t *buf) 790 { 791 return HAL_RX_GET_FC_VALID(buf); 792 } 793 794 static uint8_t hal_rx_get_to_ds_flag_9000(uint8_t *buf) 795 { 796 return HAL_RX_GET_TO_DS_FLAG(buf); 797 } 798 799 static uint8_t hal_rx_get_mac_addr2_valid_9000(uint8_t *buf) 800 { 801 return HAL_RX_GET_MAC_ADDR2_VALID(buf); 802 } 803 804 static uint8_t hal_rx_get_filter_category_9000(uint8_t *buf) 805 { 806 return HAL_RX_GET_FILTER_CATEGORY(buf); 807 } 808 809 static uint32_t 810 hal_rx_get_ppdu_id_9000(uint8_t *buf) 811 { 812 return HAL_RX_GET_PPDU_ID(buf); 813 } 814 815 /** 816 * hal_reo_config_9000(): Set reo config parameters 817 * @soc: hal soc handle 818 * @reg_val: value to be set 819 * @reo_params: reo parameters 820 * 821 * Return: void 822 */ 823 static void 824 hal_reo_config_9000(struct hal_soc *soc, 825 uint32_t reg_val, 826 struct hal_reo_params *reo_params) 827 { 828 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 829 } 830 831 /** 832 * hal_rx_msdu_desc_info_get_ptr_9000() - Get msdu desc info ptr 833 * @msdu_details_ptr - Pointer to msdu_details_ptr 834 * 835 * Return - Pointer to rx_msdu_desc_info structure. 836 * 837 */ 838 static void *hal_rx_msdu_desc_info_get_ptr_9000(void *msdu_details_ptr) 839 { 840 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 841 } 842 843 /** 844 * hal_rx_link_desc_msdu0_ptr_9000 - Get pointer to rx_msdu details 845 * @link_desc - Pointer to link desc 846 * 847 * Return - Pointer to rx_msdu_details structure 848 * 849 */ 850 static void *hal_rx_link_desc_msdu0_ptr_9000(void *link_desc) 851 { 852 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 853 } 854 855 /** 856 * hal_rx_msdu_flow_idx_get_9000: API to get flow index 857 * from rx_msdu_end TLV 858 * @buf: pointer to the start of RX PKT TLV headers 859 * 860 * Return: flow index value from MSDU END TLV 861 */ 862 static inline uint32_t hal_rx_msdu_flow_idx_get_9000(uint8_t *buf) 863 { 864 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 865 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 866 867 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 868 } 869 870 /** 871 * hal_rx_msdu_flow_idx_invalid_9000: API to get flow index invalid 872 * from rx_msdu_end TLV 873 * @buf: pointer to the start of RX PKT TLV headers 874 * 875 * Return: flow index invalid value from MSDU END TLV 876 */ 877 static bool hal_rx_msdu_flow_idx_invalid_9000(uint8_t *buf) 878 { 879 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 880 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 881 882 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 883 } 884 885 /** 886 * hal_rx_msdu_flow_idx_timeout_9000: API to get flow index timeout 887 * from rx_msdu_end TLV 888 * @buf: pointer to the start of RX PKT TLV headers 889 * 890 * Return: flow index timeout value from MSDU END TLV 891 */ 892 static bool hal_rx_msdu_flow_idx_timeout_9000(uint8_t *buf) 893 { 894 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 895 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 896 897 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 898 } 899 900 /** 901 * hal_rx_msdu_fse_metadata_get_9000: API to get FSE metadata 902 * from rx_msdu_end TLV 903 * @buf: pointer to the start of RX PKT TLV headers 904 * 905 * Return: fse metadata value from MSDU END TLV 906 */ 907 static uint32_t hal_rx_msdu_fse_metadata_get_9000(uint8_t *buf) 908 { 909 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 910 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 911 912 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end); 913 } 914 915 /** 916 * hal_rx_msdu_cce_metadata_get_9000: API to get CCE metadata 917 * from rx_msdu_end TLV 918 * @buf: pointer to the start of RX PKT TLV headers 919 * 920 * Return: cce_metadata 921 */ 922 static uint16_t 923 hal_rx_msdu_cce_metadata_get_9000(uint8_t *buf) 924 { 925 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 926 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 927 928 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end); 929 } 930 931 /** 932 * hal_rx_msdu_get_flow_params_9000: API to get flow index, flow index invalid 933 * and flow index timeout from rx_msdu_end TLV 934 * @buf: pointer to the start of RX PKT TLV headers 935 * @flow_invalid: pointer to return value of flow_idx_valid 936 * @flow_timeout: pointer to return value of flow_idx_timeout 937 * @flow_index: pointer to return value of flow_idx 938 * 939 * Return: none 940 */ 941 static inline void 942 hal_rx_msdu_get_flow_params_9000(uint8_t *buf, 943 bool *flow_invalid, 944 bool *flow_timeout, 945 uint32_t *flow_index) 946 { 947 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 948 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 949 950 *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 951 *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 952 *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 953 } 954 955 /** 956 * hal_rx_tlv_get_tcp_chksum_9000() - API to get tcp checksum 957 * @buf: rx_tlv_hdr 958 * 959 * Return: tcp checksum 960 */ 961 static uint16_t 962 hal_rx_tlv_get_tcp_chksum_9000(uint8_t *buf) 963 { 964 return HAL_RX_TLV_GET_TCP_CHKSUM(buf); 965 } 966 967 /** 968 * hal_rx_get_rx_sequence_9000(): Function to retrieve rx sequence number 969 * 970 * @nbuf: Network buffer 971 * Returns: rx sequence number 972 */ 973 static 974 uint16_t hal_rx_get_rx_sequence_9000(uint8_t *buf) 975 { 976 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 977 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 978 979 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info); 980 } 981 982 struct hal_hw_txrx_ops qcn9000_hal_hw_txrx_ops = { 983 984 /* init and setup */ 985 hal_srng_dst_hw_init_generic, 986 hal_srng_src_hw_init_generic, 987 hal_get_hw_hptp_generic, 988 hal_reo_setup_generic, 989 hal_setup_link_idle_list_generic, 990 991 /* tx */ 992 hal_tx_desc_set_dscp_tid_table_id_8074v2, 993 hal_tx_set_dscp_tid_map_8074v2, 994 hal_tx_update_dscp_tid_8074v2, 995 hal_tx_desc_set_lmac_id_8074v2, 996 hal_tx_desc_set_buf_addr_generic, 997 hal_tx_desc_set_search_type_generic, 998 hal_tx_desc_set_search_index_generic, 999 hal_tx_desc_set_cache_set_num_generic, 1000 hal_tx_comp_get_status_generic, 1001 hal_tx_comp_get_release_reason_generic, 1002 hal_tx_desc_set_mesh_en_9000, 1003 1004 /* rx */ 1005 hal_rx_msdu_start_nss_get_8074v2, 1006 hal_rx_mon_hw_desc_get_mpdu_status_8074v2, 1007 hal_rx_get_tlv_8074v2, 1008 hal_rx_proc_phyrx_other_receive_info_tlv_8074v2, 1009 hal_rx_dump_msdu_start_tlv_8074v2, 1010 hal_rx_dump_msdu_end_tlv_8074v2, 1011 hal_get_link_desc_size_8074v2, 1012 hal_rx_mpdu_start_tid_get_8074v2, 1013 hal_rx_msdu_start_reception_type_get_8074v2, 1014 hal_rx_msdu_end_da_idx_get_8074v2, 1015 hal_rx_msdu_desc_info_get_ptr_9000, 1016 hal_rx_link_desc_msdu0_ptr_9000, 1017 hal_reo_status_get_header_9000, 1018 hal_rx_status_get_tlv_info_generic, 1019 hal_rx_wbm_err_info_get_generic, 1020 hal_rx_dump_mpdu_start_tlv_generic, 1021 1022 hal_tx_set_pcp_tid_map_generic, 1023 hal_tx_update_pcp_tid_generic, 1024 hal_tx_update_tidmap_prty_generic, 1025 hal_rx_get_rx_fragment_number_9000, 1026 hal_rx_msdu_end_da_is_mcbc_get_9000, 1027 hal_rx_msdu_end_sa_is_valid_get_9000, 1028 hal_rx_msdu_end_sa_idx_get_9000, 1029 hal_rx_desc_is_first_msdu_9000, 1030 hal_rx_msdu_end_l3_hdr_padding_get_9000, 1031 hal_rx_encryption_info_valid_9000, 1032 hal_rx_print_pn_9000, 1033 hal_rx_msdu_end_first_msdu_get_9000, 1034 hal_rx_msdu_end_da_is_valid_get_9000, 1035 hal_rx_msdu_end_last_msdu_get_9000, 1036 hal_rx_get_mpdu_mac_ad4_valid_9000, 1037 hal_rx_mpdu_start_sw_peer_id_get_9000, 1038 hal_rx_mpdu_get_to_ds_9000, 1039 hal_rx_mpdu_get_fr_ds_9000, 1040 hal_rx_get_mpdu_frame_control_valid_9000, 1041 hal_rx_mpdu_get_addr1_9000, 1042 hal_rx_mpdu_get_addr2_9000, 1043 hal_rx_mpdu_get_addr3_9000, 1044 hal_rx_mpdu_get_addr4_9000, 1045 hal_rx_get_mpdu_sequence_control_valid_9000, 1046 hal_rx_is_unicast_9000, 1047 hal_rx_tid_get_9000, 1048 hal_rx_hw_desc_get_ppduid_get_9000, 1049 hal_rx_mpdu_start_mpdu_qos_control_valid_9000, 1050 hal_rx_msdu_end_sa_sw_peer_id_get_9000, 1051 hal_rx_msdu0_buffer_addr_lsb_9000, 1052 hal_rx_msdu_desc_info_ptr_get_9000, 1053 hal_ent_mpdu_desc_info_9000, 1054 hal_dst_mpdu_desc_info_9000, 1055 hal_rx_get_fc_valid_9000, 1056 hal_rx_get_to_ds_flag_9000, 1057 hal_rx_get_mac_addr2_valid_9000, 1058 hal_rx_get_filter_category_9000, 1059 hal_rx_get_ppdu_id_9000, 1060 hal_reo_config_9000, 1061 hal_rx_msdu_flow_idx_get_9000, 1062 hal_rx_msdu_flow_idx_invalid_9000, 1063 hal_rx_msdu_flow_idx_timeout_9000, 1064 hal_rx_msdu_fse_metadata_get_9000, 1065 hal_rx_msdu_cce_metadata_get_9000, 1066 hal_rx_msdu_get_flow_params_9000, 1067 hal_rx_tlv_get_tcp_chksum_9000, 1068 hal_rx_get_rx_sequence_9000, 1069 }; 1070 1071 struct hal_hw_srng_config hw_srng_table_9000[] = { 1072 /* TODO: max_rings can populated by querying HW capabilities */ 1073 { /* REO_DST */ 1074 .start_ring_id = HAL_SRNG_REO2SW1, 1075 .max_rings = 4, 1076 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1077 .lmac_ring = FALSE, 1078 .ring_dir = HAL_SRNG_DST_RING, 1079 .reg_start = { 1080 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 1081 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1082 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 1083 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1084 }, 1085 .reg_size = { 1086 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 1087 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 1088 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 1089 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 1090 }, 1091 .max_size = 1092 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 1093 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 1094 }, 1095 { /* REO_EXCEPTION */ 1096 /* Designating REO2TCL ring as exception ring. This ring is 1097 * similar to other REO2SW rings though it is named as REO2TCL. 1098 * Any of theREO2SW rings can be used as exception ring. 1099 */ 1100 .start_ring_id = HAL_SRNG_REO2TCL, 1101 .max_rings = 1, 1102 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1103 .lmac_ring = FALSE, 1104 .ring_dir = HAL_SRNG_DST_RING, 1105 .reg_start = { 1106 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 1107 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1108 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 1109 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1110 }, 1111 /* Single ring - provide ring size if multiple rings of this 1112 * type are supported 1113 */ 1114 .reg_size = {}, 1115 .max_size = 1116 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 1117 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 1118 }, 1119 { /* REO_REINJECT */ 1120 .start_ring_id = HAL_SRNG_SW2REO, 1121 .max_rings = 1, 1122 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1123 .lmac_ring = FALSE, 1124 .ring_dir = HAL_SRNG_SRC_RING, 1125 .reg_start = { 1126 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 1127 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1128 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 1129 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1130 }, 1131 /* Single ring - provide ring size if multiple rings of this 1132 * type are supported 1133 */ 1134 .reg_size = {}, 1135 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 1136 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 1137 }, 1138 { /* REO_CMD */ 1139 .start_ring_id = HAL_SRNG_REO_CMD, 1140 .max_rings = 1, 1141 .entry_size = (sizeof(struct tlv_32_hdr) + 1142 sizeof(struct reo_get_queue_stats)) >> 2, 1143 .lmac_ring = FALSE, 1144 .ring_dir = HAL_SRNG_SRC_RING, 1145 .reg_start = { 1146 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 1147 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1148 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 1149 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1150 }, 1151 /* Single ring - provide ring size if multiple rings of this 1152 * type are supported 1153 */ 1154 .reg_size = {}, 1155 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1156 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1157 }, 1158 { /* REO_STATUS */ 1159 .start_ring_id = HAL_SRNG_REO_STATUS, 1160 .max_rings = 1, 1161 .entry_size = (sizeof(struct tlv_32_hdr) + 1162 sizeof(struct reo_get_queue_stats_status)) >> 2, 1163 .lmac_ring = FALSE, 1164 .ring_dir = HAL_SRNG_DST_RING, 1165 .reg_start = { 1166 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 1167 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1168 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 1169 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1170 }, 1171 /* Single ring - provide ring size if multiple rings of this 1172 * type are supported 1173 */ 1174 .reg_size = {}, 1175 .max_size = 1176 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1177 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1178 }, 1179 { /* TCL_DATA */ 1180 .start_ring_id = HAL_SRNG_SW2TCL1, 1181 .max_rings = 3, 1182 .entry_size = (sizeof(struct tlv_32_hdr) + 1183 sizeof(struct tcl_data_cmd)) >> 2, 1184 .lmac_ring = FALSE, 1185 .ring_dir = HAL_SRNG_SRC_RING, 1186 .reg_start = { 1187 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 1188 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1189 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 1190 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1191 }, 1192 .reg_size = { 1193 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 1194 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 1195 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 1196 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 1197 }, 1198 .max_size = 1199 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 1200 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 1201 }, 1202 { /* TCL_CMD */ 1203 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 1204 .max_rings = 1, 1205 .entry_size = (sizeof(struct tlv_32_hdr) + 1206 sizeof(struct tcl_gse_cmd)) >> 2, 1207 .lmac_ring = FALSE, 1208 .ring_dir = HAL_SRNG_SRC_RING, 1209 .reg_start = { 1210 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR( 1211 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1212 HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR( 1213 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1214 }, 1215 /* Single ring - provide ring size if multiple rings of this 1216 * type are supported 1217 */ 1218 .reg_size = {}, 1219 .max_size = 1220 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1221 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1222 }, 1223 { /* TCL_STATUS */ 1224 .start_ring_id = HAL_SRNG_TCL_STATUS, 1225 .max_rings = 1, 1226 .entry_size = (sizeof(struct tlv_32_hdr) + 1227 sizeof(struct tcl_status_ring)) >> 2, 1228 .lmac_ring = FALSE, 1229 .ring_dir = HAL_SRNG_DST_RING, 1230 .reg_start = { 1231 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 1232 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1233 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 1234 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1235 }, 1236 /* Single ring - provide ring size if multiple rings of this 1237 * type are supported 1238 */ 1239 .reg_size = {}, 1240 .max_size = 1241 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 1242 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 1243 }, 1244 { /* CE_SRC */ 1245 .start_ring_id = HAL_SRNG_CE_0_SRC, 1246 .max_rings = 12, 1247 .entry_size = sizeof(struct ce_src_desc) >> 2, 1248 .lmac_ring = FALSE, 1249 .ring_dir = HAL_SRNG_SRC_RING, 1250 .reg_start = { 1251 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1252 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1253 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1254 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1255 }, 1256 .reg_size = { 1257 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1258 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1259 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1260 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1261 }, 1262 .max_size = 1263 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1264 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1265 }, 1266 { /* CE_DST */ 1267 .start_ring_id = HAL_SRNG_CE_0_DST, 1268 .max_rings = 12, 1269 .entry_size = 8 >> 2, 1270 /*TODO: entry_size above should actually be 1271 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 1272 * of struct ce_dst_desc in HW header files 1273 */ 1274 .lmac_ring = FALSE, 1275 .ring_dir = HAL_SRNG_SRC_RING, 1276 .reg_start = { 1277 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1278 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1279 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1280 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1281 }, 1282 .reg_size = { 1283 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1284 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1285 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1286 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1287 }, 1288 .max_size = 1289 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1290 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1291 }, 1292 { /* CE_DST_STATUS */ 1293 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 1294 .max_rings = 12, 1295 .entry_size = sizeof(struct ce_stat_desc) >> 2, 1296 .lmac_ring = FALSE, 1297 .ring_dir = HAL_SRNG_DST_RING, 1298 .reg_start = { 1299 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 1300 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1301 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 1302 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1303 }, 1304 /* TODO: check destination status ring registers */ 1305 .reg_size = { 1306 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1307 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1308 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1309 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1310 }, 1311 .max_size = 1312 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1313 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1314 }, 1315 { /* WBM_IDLE_LINK */ 1316 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 1317 .max_rings = 1, 1318 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 1319 .lmac_ring = FALSE, 1320 .ring_dir = HAL_SRNG_SRC_RING, 1321 .reg_start = { 1322 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1323 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1324 }, 1325 /* Single ring - provide ring size if multiple rings of this 1326 * type are supported 1327 */ 1328 .reg_size = {}, 1329 .max_size = 1330 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 1331 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 1332 }, 1333 { /* SW2WBM_RELEASE */ 1334 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 1335 .max_rings = 1, 1336 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1337 .lmac_ring = FALSE, 1338 .ring_dir = HAL_SRNG_SRC_RING, 1339 .reg_start = { 1340 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1341 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1342 }, 1343 /* Single ring - provide ring size if multiple rings of this 1344 * type are supported 1345 */ 1346 .reg_size = {}, 1347 .max_size = 1348 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1349 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1350 }, 1351 { /* WBM2SW_RELEASE */ 1352 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 1353 .max_rings = 4, 1354 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1355 .lmac_ring = FALSE, 1356 .ring_dir = HAL_SRNG_DST_RING, 1357 .reg_start = { 1358 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1359 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1360 }, 1361 .reg_size = { 1362 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1363 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1364 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1365 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1366 }, 1367 .max_size = 1368 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1369 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1370 }, 1371 { /* RXDMA_BUF */ 1372 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 1373 #ifdef IPA_OFFLOAD 1374 .max_rings = 3, 1375 #else 1376 .max_rings = 2, 1377 #endif 1378 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1379 .lmac_ring = TRUE, 1380 .ring_dir = HAL_SRNG_SRC_RING, 1381 /* reg_start is not set because LMAC rings are not accessed 1382 * from host 1383 */ 1384 .reg_start = {}, 1385 .reg_size = {}, 1386 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1387 }, 1388 { /* RXDMA_DST */ 1389 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 1390 .max_rings = 1, 1391 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1392 .lmac_ring = TRUE, 1393 .ring_dir = HAL_SRNG_DST_RING, 1394 /* reg_start is not set because LMAC rings are not accessed 1395 * from host 1396 */ 1397 .reg_start = {}, 1398 .reg_size = {}, 1399 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1400 }, 1401 { /* RXDMA_MONITOR_BUF */ 1402 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 1403 .max_rings = 1, 1404 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1405 .lmac_ring = TRUE, 1406 .ring_dir = HAL_SRNG_SRC_RING, 1407 /* reg_start is not set because LMAC rings are not accessed 1408 * from host 1409 */ 1410 .reg_start = {}, 1411 .reg_size = {}, 1412 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1413 }, 1414 { /* RXDMA_MONITOR_STATUS */ 1415 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 1416 .max_rings = 1, 1417 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1418 .lmac_ring = TRUE, 1419 .ring_dir = HAL_SRNG_SRC_RING, 1420 /* reg_start is not set because LMAC rings are not accessed 1421 * from host 1422 */ 1423 .reg_start = {}, 1424 .reg_size = {}, 1425 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1426 }, 1427 { /* RXDMA_MONITOR_DST */ 1428 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 1429 .max_rings = 1, 1430 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1431 .lmac_ring = TRUE, 1432 .ring_dir = HAL_SRNG_DST_RING, 1433 /* reg_start is not set because LMAC rings are not accessed 1434 * from host 1435 */ 1436 .reg_start = {}, 1437 .reg_size = {}, 1438 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1439 }, 1440 { /* RXDMA_MONITOR_DESC */ 1441 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 1442 .max_rings = 1, 1443 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1444 .lmac_ring = TRUE, 1445 .ring_dir = HAL_SRNG_SRC_RING, 1446 /* reg_start is not set because LMAC rings are not accessed 1447 * from host 1448 */ 1449 .reg_start = {}, 1450 .reg_size = {}, 1451 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1452 }, 1453 { /* DIR_BUF_RX_DMA_SRC */ 1454 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 1455 /* one ring for spectral and one ring for cfr */ 1456 .max_rings = 2, 1457 .entry_size = 2, 1458 .lmac_ring = TRUE, 1459 .ring_dir = HAL_SRNG_SRC_RING, 1460 /* reg_start is not set because LMAC rings are not accessed 1461 * from host 1462 */ 1463 .reg_start = {}, 1464 .reg_size = {}, 1465 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1466 }, 1467 #ifdef WLAN_FEATURE_CIF_CFR 1468 { /* WIFI_POS_SRC */ 1469 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 1470 .max_rings = 1, 1471 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 1472 .lmac_ring = TRUE, 1473 .ring_dir = HAL_SRNG_SRC_RING, 1474 /* reg_start is not set because LMAC rings are not accessed 1475 * from host 1476 */ 1477 .reg_start = {}, 1478 .reg_size = {}, 1479 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1480 }, 1481 #endif 1482 }; 1483 1484 int32_t hal_hw_reg_offset_qcn9000[] = { 1485 /* dst */ 1486 REG_OFFSET(DST, HP), 1487 REG_OFFSET(DST, TP), 1488 REG_OFFSET(DST, ID), 1489 REG_OFFSET(DST, MISC), 1490 REG_OFFSET(DST, HP_ADDR_LSB), 1491 REG_OFFSET(DST, HP_ADDR_MSB), 1492 REG_OFFSET(DST, MSI1_BASE_LSB), 1493 REG_OFFSET(DST, MSI1_BASE_MSB), 1494 REG_OFFSET(DST, MSI1_DATA), 1495 REG_OFFSET(DST, BASE_LSB), 1496 REG_OFFSET(DST, BASE_MSB), 1497 REG_OFFSET(DST, PRODUCER_INT_SETUP), 1498 /* src */ 1499 REG_OFFSET(SRC, HP), 1500 REG_OFFSET(SRC, TP), 1501 REG_OFFSET(SRC, ID), 1502 REG_OFFSET(SRC, MISC), 1503 REG_OFFSET(SRC, TP_ADDR_LSB), 1504 REG_OFFSET(SRC, TP_ADDR_MSB), 1505 REG_OFFSET(SRC, MSI1_BASE_LSB), 1506 REG_OFFSET(SRC, MSI1_BASE_MSB), 1507 REG_OFFSET(SRC, MSI1_DATA), 1508 REG_OFFSET(SRC, BASE_LSB), 1509 REG_OFFSET(SRC, BASE_MSB), 1510 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX0), 1511 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX1), 1512 }; 1513 1514 1515 /** 1516 * hal_qcn9000_attach()- Attach 9000 target specific hal_soc ops, 1517 * offset and srng table 1518 * Return: void 1519 */ 1520 void hal_qcn9000_attach(struct hal_soc *hal_soc) 1521 { 1522 hal_soc->hw_srng_table = hw_srng_table_9000; 1523 hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qcn9000; 1524 hal_soc->ops = &qcn9000_hal_hw_txrx_ops; 1525 } 1526