1 /* 2 * Copyright (c) 2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE 16 */ 17 #include "qdf_types.h" 18 #include "qdf_util.h" 19 #include "qdf_mem.h" 20 #include "qdf_nbuf.h" 21 #include "qdf_module.h" 22 23 #include "target_type.h" 24 #include "wcss_version.h" 25 26 #include "hal_be_hw_headers.h" 27 #include "hal_internal.h" 28 #include "hal_api.h" 29 #include "hal_flow.h" 30 #include "rx_flow_search_entry.h" 31 #include "hal_rx_flow_info.h" 32 #include "hal_be_api.h" 33 #include "tcl_entrance_from_ppe_ring.h" 34 #include "sw_monitor_ring.h" 35 #include "wcss_seq_hwioreg_umac.h" 36 #include "wfss_ce_reg_seq_hwioreg.h" 37 #include <uniform_reo_status_header.h> 38 #include <wbm_release_ring_tx.h> 39 #include <phyrx_location.h> 40 #ifdef WLAN_PKT_CAPTURE_TX_2_0 41 #include <mon_ingress_ring.h> 42 #include <mon_destination_ring.h> 43 #endif 44 #include "rx_reo_queue_1k.h" 45 46 #include <hal_be_rx.h> 47 48 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 49 RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 50 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 51 RX_MSDU_LINK_MSDU_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 52 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 53 RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 54 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 55 RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 56 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 57 REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 58 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER \ 59 STATUS_HEADER_REO_STATUS_NUMBER 60 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 61 STATUS_HEADER_TIMESTAMP 62 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 63 RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 64 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 65 RX_MSDU_LINK_MSDU_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 66 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 67 TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 68 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 69 TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 70 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 71 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_OFFSET 72 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 73 BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 74 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 75 BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 76 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 77 BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB 78 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 79 BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK 80 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 81 BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 82 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 83 BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 84 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 85 BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB 86 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 87 BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK 88 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 89 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_LSB 90 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 91 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MASK 92 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 93 WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 94 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 95 WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 96 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 97 WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 98 99 #if defined(WLAN_PKT_CAPTURE_TX_2_0) || defined(WLAN_PKT_CAPTURE_RX_2_0) 100 #include "hal_be_api_mon.h" 101 #endif 102 103 #define CMEM_REG_BASE 0x00100000 104 105 #define CE_WINDOW_ADDRESS_6432 \ 106 ((SOC_WFSS_CE_REG_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) 107 108 #define UMAC_WINDOW_ADDRESS_6432 \ 109 ((UMAC_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) 110 111 #define WINDOW_CONFIGURATION_VALUE_6432 \ 112 ((CE_WINDOW_ADDRESS_6432 << 6) |\ 113 (UMAC_WINDOW_ADDRESS_6432 << 12) | \ 114 WINDOW_ENABLE_BIT) 115 116 /* For Berryllium sw2rxdma ring size increased to 20 bits */ 117 #define HAL_RXDMA_MAX_RING_SIZE_BE 0xFFFFF 118 119 #include "hal_6432_rx.h" 120 #include "hal_6432_tx.h" 121 #include "hal_be_rx_tlv.h" 122 #include <hal_be_generic_api.h> 123 124 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 125 #define PMM_REG_BASE_QCN6432 0xB500FC 126 127 /** 128 * hal_get_link_desc_size_6432(): API to get the link desc size 129 * 130 * Return: uint32_t 131 */ 132 static uint32_t hal_get_link_desc_size_6432(void) 133 { 134 return LINK_DESC_SIZE; 135 } 136 137 /** 138 * hal_rx_get_tlv_6432(): API to get the tlv 139 * 140 * @rx_tlv: TLV data extracted from the rx packet 141 * Return: uint8_t 142 */ 143 static uint8_t hal_rx_get_tlv_6432(void *rx_tlv) 144 { 145 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY, RECEIVE_BANDWIDTH); 146 } 147 148 /** 149 * hal_rx_wbm_err_msdu_continuation_get_6432 () - API to check if WBM 150 * msdu continuation bit is set 151 * 152 *@wbm_desc: wbm release ring descriptor 153 * 154 * Return: true if msdu continuation bit is set. 155 */ 156 uint8_t hal_rx_wbm_err_msdu_continuation_get_6432(void *wbm_desc) 157 { 158 uint32_t comp_desc = *(uint32_t *)(((uint8_t *)wbm_desc) + 159 WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET); 160 161 return (comp_desc & 162 WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK) >> 163 WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB; 164 } 165 166 #if 0 // check this registration for MLO 167 /** 168 * hal_read_pmm_scratch_reg_5332(): API to read PMM Scratch register 169 * 170 * @soc: HAL soc 171 * @reg_enum: Enum of the scratch register 172 * 173 * Return: uint32_t 174 */ 175 static inline 176 uint32_t hal_read_pmm_scratch_reg_5332(struct hal_soc *soc, 177 enum hal_scratch_reg_enum reg_enum) 178 { 179 uint32_t val = 0; 180 void __iomem *bar; 181 182 bar = ioremap_nocache(PMM_SCRATCH_BASE_QCA5332, PMM_SCRATCH_SIZE); 183 pld_reg_read(soc->qdf_dev->dev, (reg_enum * 4), &val, bar); 184 iounmap(bar); 185 return val; 186 } 187 188 /** 189 * hal_get_tsf2_scratch_reg_qca5332(): API to read tsf2 scratch register 190 * 191 * @hal_soc_hdl: HAL soc context 192 * @mac_id: mac id 193 * @value: Pointer to update tsf2 value 194 * 195 * Return: void 196 */ 197 static void hal_get_tsf2_scratch_reg_qca5332(hal_soc_handle_t hal_soc_hdl, 198 uint8_t mac_id, uint64_t *value) 199 { 200 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; 201 uint32_t offset_lo, offset_hi; 202 enum hal_scratch_reg_enum enum_lo, enum_hi; 203 204 hal_get_tsf_enum(DEFAULT_TSF_ID, mac_id, &enum_lo, &enum_hi); 205 206 offset_lo = hal_read_pmm_scratch_reg_5332(soc, enum_lo); 207 208 offset_hi = hal_read_pmm_scratch_reg_5332(soc, enum_hi); 209 210 *value = ((uint64_t)(offset_hi) << 32 | offset_lo); 211 } 212 213 /** 214 * hal_get_tqm_scratch_reg_qca5332(): API to read tqm scratch register 215 * 216 * @hal_soc_hdl: HAL soc context 217 * @value: Pointer to update tqm value 218 * 219 * Return: void 220 */ 221 static void hal_get_tqm_scratch_reg_qca5332(hal_soc_handle_t hal_soc_hdl, 222 uint64_t *value) 223 { 224 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; 225 uint32_t offset_lo, offset_hi; 226 227 offset_lo = hal_read_pmm_scratch_reg_5332(soc, 228 PMM_TQM_CLOCK_OFFSET_LO_US); 229 230 offset_hi = hal_read_pmm_scratch_reg_5332(soc, 231 PMM_TQM_CLOCK_OFFSET_HI_US); 232 233 *value = ((uint64_t)(offset_hi) << 32 | offset_lo); 234 } 235 #endif 236 /** 237 * hal_rx_proc_phyrx_other_receive_info_tlv_6432(): API to get tlv info 238 * 239 * @rx_tlv_hdr: start address of rx_pkt_tlvs 240 * @ppdu_info_hdl: PPDU info handle to fill 241 * 242 * Return: uint32_t 243 */ 244 static inline 245 void hal_rx_proc_phyrx_other_receive_info_tlv_6432(void *rx_tlv_hdr, 246 void *ppdu_info_hdl) 247 { 248 uint32_t tlv_tag, tlv_len; 249 uint32_t temp_len, other_tlv_len, other_tlv_tag; 250 void *rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 251 void *other_tlv_hdr = NULL; 252 void *other_tlv = NULL; 253 254 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 255 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 256 temp_len = 0; 257 258 other_tlv_hdr = rx_tlv + HAL_RX_TLV32_HDR_SIZE; 259 other_tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(other_tlv_hdr); 260 other_tlv_len = HAL_RX_GET_USER_TLV32_LEN(other_tlv_hdr); 261 262 temp_len += other_tlv_len; 263 other_tlv = other_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 264 265 switch (other_tlv_tag) { 266 default: 267 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 268 "%s unhandled TLV type: %d, TLV len:%d", 269 __func__, other_tlv_tag, other_tlv_len); 270 break; 271 } 272 } 273 274 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) 275 static inline 276 void hal_rx_get_bb_info_6432(void *rx_tlv, void *ppdu_info_hdl) 277 { 278 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 279 280 ppdu_info->cfr_info.bb_captured_channel = 281 HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_CHANNEL); 282 283 ppdu_info->cfr_info.bb_captured_timeout = 284 HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_TIMEOUT); 285 286 ppdu_info->cfr_info.bb_captured_reason = 287 HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_REASON); 288 } 289 290 static inline 291 void hal_rx_get_rtt_info_6432(void *rx_tlv, void *ppdu_info_hdl) 292 { 293 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 294 295 ppdu_info->cfr_info.rx_location_info_valid = 296 HAL_RX_GET_64(rx_tlv, PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 297 RX_LOCATION_INFO_VALID); 298 299 ppdu_info->cfr_info.rtt_che_buffer_pointer_low32 = 300 HAL_RX_GET_64(rx_tlv, 301 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 302 RTT_CHE_BUFFER_POINTER_LOW32); 303 304 ppdu_info->cfr_info.rtt_che_buffer_pointer_high8 = 305 HAL_RX_GET_64(rx_tlv, 306 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 307 RTT_CHE_BUFFER_POINTER_HIGH8); 308 309 ppdu_info->cfr_info.chan_capture_status = 310 HAL_GET_RX_LOCATION_INFO_CHAN_CAPTURE_STATUS(rx_tlv); 311 312 ppdu_info->cfr_info.rx_start_ts = 313 HAL_RX_GET_64(rx_tlv, 314 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 315 RX_START_TS); 316 317 ppdu_info->cfr_info.rtt_cfo_measurement = (int16_t) 318 HAL_RX_GET_64(rx_tlv, 319 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 320 RTT_CFO_MEASUREMENT); 321 322 ppdu_info->cfr_info.agc_gain_info0 = 323 HAL_RX_GET_64(rx_tlv, 324 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 325 GAIN_CHAIN0); 326 327 ppdu_info->cfr_info.agc_gain_info0 |= 328 (((uint32_t)HAL_RX_GET_64(rx_tlv, 329 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 330 GAIN_CHAIN1)) << 16); 331 332 ppdu_info->cfr_info.agc_gain_info1 = 333 HAL_RX_GET_64(rx_tlv, 334 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 335 GAIN_CHAIN2); 336 337 ppdu_info->cfr_info.agc_gain_info1 |= 338 (((uint32_t)HAL_RX_GET_64(rx_tlv, 339 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 340 GAIN_CHAIN3)) << 16); 341 342 ppdu_info->cfr_info.agc_gain_info2 = 0; 343 344 ppdu_info->cfr_info.agc_gain_info3 = 0; 345 346 ppdu_info->cfr_info.mcs_rate = 347 HAL_RX_GET_64(rx_tlv, 348 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 349 RTT_MCS_RATE); 350 351 ppdu_info->cfr_info.gi_type = 352 HAL_RX_GET_64(rx_tlv, 353 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 354 RTT_GI_TYPE); 355 } 356 #endif 357 #ifdef CONFIG_WORD_BASED_TLV 358 /** 359 * hal_rx_dump_mpdu_start_tlv_6432() - dump RX mpdu_start TLV in structured 360 * human readable format. 361 * @mpdustart: pointer the rx_attention TLV in pkt. 362 * @dbg_level: log level. 363 * 364 * Return: void 365 */ 366 static inline void hal_rx_dump_mpdu_start_tlv_6432(void *mpdustart, 367 uint8_t dbg_level) 368 { 369 struct rx_mpdu_start_compact *mpdu_info = 370 (struct rx_mpdu_start_compact *)mpdustart; 371 372 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 373 "rx_mpdu_start tlv (1/5) - " 374 "rx_reo_queue_desc_addr_39_32 :%x" 375 "receive_queue_number:%x " 376 "pre_delim_err_warning:%x " 377 "first_delim_err:%x " 378 "pn_31_0:%x " 379 "pn_63_32:%x " 380 "pn_95_64:%x ", 381 mpdu_info->rx_reo_queue_desc_addr_39_32, 382 mpdu_info->receive_queue_number, 383 mpdu_info->pre_delim_err_warning, 384 mpdu_info->first_delim_err, 385 mpdu_info->pn_31_0, 386 mpdu_info->pn_63_32, 387 mpdu_info->pn_95_64); 388 389 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 390 "rx_mpdu_start tlv (2/5) - " 391 "ast_index:%x " 392 "sw_peer_id:%x " 393 "mpdu_frame_control_valid:%x " 394 "mpdu_duration_valid:%x " 395 "mac_addr_ad1_valid:%x " 396 "mac_addr_ad2_valid:%x " 397 "mac_addr_ad3_valid:%x " 398 "mac_addr_ad4_valid:%x " 399 "mpdu_sequence_control_valid :%x" 400 "mpdu_qos_control_valid:%x " 401 "mpdu_ht_control_valid:%x " 402 "frame_encryption_info_valid :%x", 403 mpdu_info->ast_index, 404 mpdu_info->sw_peer_id, 405 mpdu_info->mpdu_frame_control_valid, 406 mpdu_info->mpdu_duration_valid, 407 mpdu_info->mac_addr_ad1_valid, 408 mpdu_info->mac_addr_ad2_valid, 409 mpdu_info->mac_addr_ad3_valid, 410 mpdu_info->mac_addr_ad4_valid, 411 mpdu_info->mpdu_sequence_control_valid, 412 mpdu_info->mpdu_qos_control_valid, 413 mpdu_info->mpdu_ht_control_valid, 414 mpdu_info->frame_encryption_info_valid); 415 416 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 417 "rx_mpdu_start tlv (3/5) - " 418 "mpdu_fragment_number:%x " 419 "more_fragment_flag:%x " 420 "fr_ds:%x " 421 "to_ds:%x " 422 "encrypted:%x " 423 "mpdu_retry:%x " 424 "mpdu_sequence_number:%x ", 425 mpdu_info->mpdu_fragment_number, 426 mpdu_info->more_fragment_flag, 427 mpdu_info->fr_ds, 428 mpdu_info->to_ds, 429 mpdu_info->encrypted, 430 mpdu_info->mpdu_retry, 431 mpdu_info->mpdu_sequence_number); 432 433 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 434 "rx_mpdu_start tlv (4/5) - " 435 "mpdu_frame_control_field:%x " 436 "mpdu_duration_field:%x ", 437 mpdu_info->mpdu_frame_control_field, 438 mpdu_info->mpdu_duration_field); 439 440 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 441 "rx_mpdu_start tlv (5/5) - " 442 "mac_addr_ad1_31_0:%x " 443 "mac_addr_ad1_47_32:%x " 444 "mac_addr_ad2_15_0:%x " 445 "mac_addr_ad2_47_16:%x " 446 "mac_addr_ad3_31_0:%x " 447 "mac_addr_ad3_47_32:%x " 448 "mpdu_sequence_control_field :%x", 449 mpdu_info->mac_addr_ad1_31_0, 450 mpdu_info->mac_addr_ad1_47_32, 451 mpdu_info->mac_addr_ad2_15_0, 452 mpdu_info->mac_addr_ad2_47_16, 453 mpdu_info->mac_addr_ad3_31_0, 454 mpdu_info->mac_addr_ad3_47_32, 455 mpdu_info->mpdu_sequence_control_field); 456 } 457 458 /** 459 * hal_rx_dump_msdu_end_tlv_6432() - dump RX msdu_end TLV in structured 460 * human readable format. 461 * @msduend: pointer the msdu_end TLV in pkt. 462 * @dbg_level: log level. 463 * 464 * Return: void 465 */ 466 static void hal_rx_dump_msdu_end_tlv_6432(void *msduend, 467 uint8_t dbg_level) 468 { 469 struct rx_msdu_end_compact *msdu_end = 470 (struct rx_msdu_end_compact *)msduend; 471 472 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 473 "rx_msdu_end tlv - " 474 "key_id_octet: %d " 475 "tcp_udp_chksum: %d " 476 "sa_idx_timeout: %d " 477 "da_idx_timeout: %d " 478 "msdu_limit_error: %d " 479 "flow_idx_timeout: %d " 480 "flow_idx_invalid: %d " 481 "wifi_parser_error: %d " 482 "sa_is_valid: %d " 483 "da_is_valid: %d " 484 "da_is_mcbc: %d " 485 "tkip_mic_err: %d " 486 "l3_header_padding: %d " 487 "first_msdu: %d " 488 "last_msdu: %d " 489 "sa_idx: %d " 490 "msdu_drop: %d " 491 "reo_destination_indication: %d " 492 "flow_idx: %d " 493 "fse_metadata: %d " 494 "cce_metadata: %d " 495 "sa_sw_peer_id: %d ", 496 msdu_end->key_id_octet, 497 msdu_end->tcp_udp_chksum, 498 msdu_end->sa_idx_timeout, 499 msdu_end->da_idx_timeout, 500 msdu_end->msdu_limit_error, 501 msdu_end->flow_idx_timeout, 502 msdu_end->flow_idx_invalid, 503 msdu_end->wifi_parser_error, 504 msdu_end->sa_is_valid, 505 msdu_end->da_is_valid, 506 msdu_end->da_is_mcbc, 507 msdu_end->tkip_mic_err, 508 msdu_end->l3_header_padding, 509 msdu_end->first_msdu, 510 msdu_end->last_msdu, 511 msdu_end->sa_idx, 512 msdu_end->msdu_drop, 513 msdu_end->reo_destination_indication, 514 msdu_end->flow_idx, 515 msdu_end->fse_metadata, 516 msdu_end->cce_metadata, 517 msdu_end->sa_sw_peer_id); 518 } 519 #else 520 static inline void hal_rx_dump_mpdu_start_tlv_6432(void *mpdustart, 521 uint8_t dbg_level) 522 { 523 struct rx_mpdu_start *mpdu_start = (struct rx_mpdu_start *)mpdustart; 524 struct rx_mpdu_info *mpdu_info = 525 (struct rx_mpdu_info *)&mpdu_start->rx_mpdu_info_details; 526 527 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 528 "rx_mpdu_start tlv (1/5) - " 529 "rx_reo_queue_desc_addr_31_0 :%x" 530 "rx_reo_queue_desc_addr_39_32 :%x" 531 "receive_queue_number:%x " 532 "pre_delim_err_warning:%x " 533 "first_delim_err:%x " 534 "reserved_2a:%x " 535 "pn_31_0:%x " 536 "pn_63_32:%x " 537 "pn_95_64:%x " 538 "pn_127_96:%x " 539 "epd_en:%x " 540 "all_frames_shall_be_encrypted :%x" 541 "encrypt_type:%x " 542 "wep_key_width_for_variable_key :%x" 543 "mesh_sta:%x " 544 "bssid_hit:%x " 545 "bssid_number:%x " 546 "tid:%x " 547 "reserved_7a:%x ", 548 mpdu_info->rx_reo_queue_desc_addr_31_0, 549 mpdu_info->rx_reo_queue_desc_addr_39_32, 550 mpdu_info->receive_queue_number, 551 mpdu_info->pre_delim_err_warning, 552 mpdu_info->first_delim_err, 553 mpdu_info->reserved_2a, 554 mpdu_info->pn_31_0, 555 mpdu_info->pn_63_32, 556 mpdu_info->pn_95_64, 557 mpdu_info->pn_127_96, 558 mpdu_info->epd_en, 559 mpdu_info->all_frames_shall_be_encrypted, 560 mpdu_info->encrypt_type, 561 mpdu_info->wep_key_width_for_variable_key, 562 mpdu_info->mesh_sta, 563 mpdu_info->bssid_hit, 564 mpdu_info->bssid_number, 565 mpdu_info->tid, 566 mpdu_info->reserved_7a); 567 568 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 569 "rx_mpdu_start tlv (2/5) - " 570 "ast_index:%x " 571 "sw_peer_id:%x " 572 "mpdu_frame_control_valid:%x " 573 "mpdu_duration_valid:%x " 574 "mac_addr_ad1_valid:%x " 575 "mac_addr_ad2_valid:%x " 576 "mac_addr_ad3_valid:%x " 577 "mac_addr_ad4_valid:%x " 578 "mpdu_sequence_control_valid :%x" 579 "mpdu_qos_control_valid:%x " 580 "mpdu_ht_control_valid:%x " 581 "frame_encryption_info_valid :%x", 582 mpdu_info->ast_index, 583 mpdu_info->sw_peer_id, 584 mpdu_info->mpdu_frame_control_valid, 585 mpdu_info->mpdu_duration_valid, 586 mpdu_info->mac_addr_ad1_valid, 587 mpdu_info->mac_addr_ad2_valid, 588 mpdu_info->mac_addr_ad3_valid, 589 mpdu_info->mac_addr_ad4_valid, 590 mpdu_info->mpdu_sequence_control_valid, 591 mpdu_info->mpdu_qos_control_valid, 592 mpdu_info->mpdu_ht_control_valid, 593 mpdu_info->frame_encryption_info_valid); 594 595 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 596 "rx_mpdu_start tlv (3/5) - " 597 "mpdu_fragment_number:%x " 598 "more_fragment_flag:%x " 599 "reserved_11a:%x " 600 "fr_ds:%x " 601 "to_ds:%x " 602 "encrypted:%x " 603 "mpdu_retry:%x " 604 "mpdu_sequence_number:%x ", 605 mpdu_info->mpdu_fragment_number, 606 mpdu_info->more_fragment_flag, 607 mpdu_info->reserved_11a, 608 mpdu_info->fr_ds, 609 mpdu_info->to_ds, 610 mpdu_info->encrypted, 611 mpdu_info->mpdu_retry, 612 mpdu_info->mpdu_sequence_number); 613 614 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 615 "rx_mpdu_start tlv (4/5) - " 616 "mpdu_frame_control_field:%x " 617 "mpdu_duration_field:%x ", 618 mpdu_info->mpdu_frame_control_field, 619 mpdu_info->mpdu_duration_field); 620 621 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 622 "rx_mpdu_start tlv (5/5) - " 623 "mac_addr_ad1_31_0:%x " 624 "mac_addr_ad1_47_32:%x " 625 "mac_addr_ad2_15_0:%x " 626 "mac_addr_ad2_47_16:%x " 627 "mac_addr_ad3_31_0:%x " 628 "mac_addr_ad3_47_32:%x " 629 "mpdu_sequence_control_field :%x" 630 "mac_addr_ad4_31_0:%x " 631 "mac_addr_ad4_47_32:%x " 632 "mpdu_qos_control_field:%x ", 633 mpdu_info->mac_addr_ad1_31_0, 634 mpdu_info->mac_addr_ad1_47_32, 635 mpdu_info->mac_addr_ad2_15_0, 636 mpdu_info->mac_addr_ad2_47_16, 637 mpdu_info->mac_addr_ad3_31_0, 638 mpdu_info->mac_addr_ad3_47_32, 639 mpdu_info->mpdu_sequence_control_field, 640 mpdu_info->mac_addr_ad4_31_0, 641 mpdu_info->mac_addr_ad4_47_32, 642 mpdu_info->mpdu_qos_control_field); 643 } 644 645 static void hal_rx_dump_msdu_end_tlv_6432(void *msduend, 646 uint8_t dbg_level) 647 { 648 struct rx_msdu_end *msdu_end = 649 (struct rx_msdu_end *)msduend; 650 651 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 652 "rx_msdu_end tlv - " 653 "key_id_octet: %d " 654 "cce_super_rule: %d " 655 "cce_classify_not_done_truncat: %d " 656 "cce_classify_not_done_cce_dis: %d " 657 "rule_indication_31_0: %d " 658 "tcp_udp_chksum: %d " 659 "sa_idx_timeout: %d " 660 "da_idx_timeout: %d " 661 "msdu_limit_error: %d " 662 "flow_idx_timeout: %d " 663 "flow_idx_invalid: %d " 664 "wifi_parser_error: %d " 665 "sa_is_valid: %d " 666 "da_is_valid: %d " 667 "da_is_mcbc: %d " 668 "tkip_mic_err: %d " 669 "l3_header_padding: %d " 670 "first_msdu: %d " 671 "last_msdu: %d " 672 "sa_idx: %d " 673 "msdu_drop: %d " 674 "reo_destination_indication: %d " 675 "flow_idx: %d " 676 "fse_metadata: %d " 677 "cce_metadata: %d " 678 "sa_sw_peer_id: %d ", 679 msdu_end->key_id_octet, 680 msdu_end->cce_super_rule, 681 msdu_end->cce_classify_not_done_truncate, 682 msdu_end->cce_classify_not_done_cce_dis, 683 msdu_end->rule_indication_31_0, 684 msdu_end->tcp_udp_chksum, 685 msdu_end->sa_idx_timeout, 686 msdu_end->da_idx_timeout, 687 msdu_end->msdu_limit_error, 688 msdu_end->flow_idx_timeout, 689 msdu_end->flow_idx_invalid, 690 msdu_end->wifi_parser_error, 691 msdu_end->sa_is_valid, 692 msdu_end->da_is_valid, 693 msdu_end->da_is_mcbc, 694 msdu_end->tkip_mic_err, 695 msdu_end->l3_header_padding, 696 msdu_end->first_msdu, 697 msdu_end->last_msdu, 698 msdu_end->sa_idx, 699 msdu_end->msdu_drop, 700 msdu_end->reo_destination_indication, 701 msdu_end->flow_idx, 702 msdu_end->fse_metadata, 703 msdu_end->cce_metadata, 704 msdu_end->sa_sw_peer_id); 705 } 706 #endif 707 708 /** 709 * hal_reo_status_get_header_6432() - Process reo desc info 710 * 711 * @ring_desc: Pointer to reo descriptor 712 * @b: tlv type info 713 * @h1: Pointer to hal_reo_status_header where info to be stored 714 * 715 * Return: none. 716 * 717 */ 718 static void hal_reo_status_get_header_6432(hal_ring_desc_t ring_desc, 719 int b, void *h1) 720 { 721 uint64_t *d = (uint64_t *)ring_desc; 722 uint64_t val1 = 0; 723 struct hal_reo_status_header *h = 724 (struct hal_reo_status_header *)h1; 725 726 /* Offsets of descriptor fields defined in HW headers start 727 * from the field after TLV header 728 */ 729 d += HAL_GET_NUM_QWORDS(sizeof(struct tlv_32_hdr)); 730 731 switch (b) { 732 case HAL_REO_QUEUE_STATS_STATUS_TLV: 733 val1 = d[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS, 734 STATUS_HEADER_REO_STATUS_NUMBER)]; 735 break; 736 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 737 val1 = d[HAL_OFFSET_QW(REO_FLUSH_QUEUE_STATUS, 738 STATUS_HEADER_REO_STATUS_NUMBER)]; 739 break; 740 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 741 val1 = d[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS, 742 STATUS_HEADER_REO_STATUS_NUMBER)]; 743 break; 744 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 745 val1 = d[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS, 746 STATUS_HEADER_REO_STATUS_NUMBER)]; 747 break; 748 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 749 val1 = d[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS, 750 STATUS_HEADER_REO_STATUS_NUMBER)]; 751 break; 752 case HAL_REO_DESC_THRES_STATUS_TLV: 753 val1 = 754 d[HAL_OFFSET_QW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS, 755 STATUS_HEADER_REO_STATUS_NUMBER)]; 756 break; 757 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 758 val1 = d[HAL_OFFSET_QW(REO_UPDATE_RX_REO_QUEUE_STATUS, 759 STATUS_HEADER_REO_STATUS_NUMBER)]; 760 break; 761 default: 762 qdf_nofl_err("ERROR: Unknown tlv\n"); 763 break; 764 } 765 h->cmd_num = 766 HAL_GET_FIELD( 767 UNIFORM_REO_STATUS_HEADER, REO_STATUS_NUMBER, 768 val1); 769 h->exec_time = 770 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, 771 CMD_EXECUTION_TIME, val1); 772 h->status = 773 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, 774 REO_CMD_EXECUTION_STATUS, val1); 775 switch (b) { 776 case HAL_REO_QUEUE_STATS_STATUS_TLV: 777 val1 = d[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS, 778 STATUS_HEADER_TIMESTAMP)]; 779 break; 780 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 781 val1 = d[HAL_OFFSET_QW(REO_FLUSH_QUEUE_STATUS, 782 STATUS_HEADER_TIMESTAMP)]; 783 break; 784 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 785 val1 = d[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS, 786 STATUS_HEADER_TIMESTAMP)]; 787 break; 788 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 789 val1 = d[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS, 790 STATUS_HEADER_TIMESTAMP)]; 791 break; 792 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 793 val1 = d[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS, 794 STATUS_HEADER_TIMESTAMP)]; 795 break; 796 case HAL_REO_DESC_THRES_STATUS_TLV: 797 val1 = 798 d[HAL_OFFSET_QW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS, 799 STATUS_HEADER_TIMESTAMP)]; 800 break; 801 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 802 val1 = d[HAL_OFFSET_QW(REO_UPDATE_RX_REO_QUEUE_STATUS, 803 STATUS_HEADER_TIMESTAMP)]; 804 break; 805 default: 806 qdf_nofl_err("ERROR: Unknown tlv\n"); 807 break; 808 } 809 h->tstamp = 810 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, TIMESTAMP, val1); 811 } 812 813 static 814 void *hal_rx_msdu0_buffer_addr_lsb_6432(void *link_desc_va) 815 { 816 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 817 } 818 819 static 820 void *hal_rx_msdu_desc_info_ptr_get_6432(void *msdu0) 821 { 822 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 823 } 824 825 static 826 void *hal_ent_mpdu_desc_info_6432(void *ent_ring_desc) 827 { 828 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 829 } 830 831 static 832 void *hal_dst_mpdu_desc_info_6432(void *dst_ring_desc) 833 { 834 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 835 } 836 837 /** 838 * hal_reo_config_6432(): Set reo config parameters 839 * @soc: hal soc handle 840 * @reg_val: value to be set 841 * @reo_params: reo parameters 842 * 843 * Return: void 844 */ 845 static void 846 hal_reo_config_6432(struct hal_soc *soc, 847 uint32_t reg_val, 848 struct hal_reo_params *reo_params) 849 { 850 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 851 } 852 853 /** 854 * hal_rx_msdu_desc_info_get_ptr_6432() - Get msdu desc info ptr 855 * @msdu_details_ptr: Pointer to msdu_details_ptr 856 * 857 * Return: Pointer to rx_msdu_desc_info structure. 858 * 859 */ 860 static void *hal_rx_msdu_desc_info_get_ptr_6432(void *msdu_details_ptr) 861 { 862 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 863 } 864 865 /** 866 * hal_rx_link_desc_msdu0_ptr_6432 - Get pointer to rx_msdu details 867 * @link_desc: Pointer to link desc 868 * 869 * Return: Pointer to rx_msdu_details structure 870 * 871 */ 872 static void *hal_rx_link_desc_msdu0_ptr_6432(void *link_desc) 873 { 874 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 875 } 876 877 /** 878 * hal_get_window_address_6432(): Function to get hp/tp address 879 * @hal_soc: Pointer to hal_soc 880 * @addr: address offset of register 881 * 882 * Return: modified address offset of register 883 */ 884 885 static inline qdf_iomem_t hal_get_window_address_6432(struct hal_soc *hal_soc, 886 qdf_iomem_t addr) 887 { 888 uint32_t offset = addr - hal_soc->dev_base_addr; 889 qdf_iomem_t new_offset; 890 891 /* 892 * If offset lies within DP register range, use 3rd window to write 893 * into DP region. 894 */ 895 if ((offset ^ UMAC_BASE) < WINDOW_RANGE_MASK) { 896 new_offset = (hal_soc->dev_base_addr + (3 * WINDOW_START) + 897 (offset & WINDOW_RANGE_MASK)); 898 /* 899 * If offset lies within CE register range, use 2nd window to write 900 * into CE region. 901 */ 902 } else if ((offset ^ SOC_WFSS_CE_REG_BASE) < WINDOW_RANGE_MASK) { 903 new_offset = (hal_soc->dev_base_addr + (2 * WINDOW_START) + 904 (offset & WINDOW_RANGE_MASK)); 905 } else { 906 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 907 "%s: ERROR: Accessing Wrong register\n", __func__); 908 qdf_assert_always(0); 909 return 0; 910 } 911 return new_offset; 912 } 913 914 static inline void hal_write_window_register(struct hal_soc *hal_soc) 915 { 916 /* Write value into window configuration register */ 917 qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_REG_ADDRESS, 918 WINDOW_CONFIGURATION_VALUE_6432); 919 } 920 921 static 922 void hal_compute_reo_remap_ix2_ix3_6432(uint32_t *ring, uint32_t num_rings, 923 uint32_t *remap1, uint32_t *remap2) 924 { 925 switch (num_rings) { 926 case 1: 927 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 928 HAL_REO_REMAP_IX2(ring[0], 17) | 929 HAL_REO_REMAP_IX2(ring[0], 18) | 930 HAL_REO_REMAP_IX2(ring[0], 19) | 931 HAL_REO_REMAP_IX2(ring[0], 20) | 932 HAL_REO_REMAP_IX2(ring[0], 21) | 933 HAL_REO_REMAP_IX2(ring[0], 22) | 934 HAL_REO_REMAP_IX2(ring[0], 23); 935 936 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 937 HAL_REO_REMAP_IX3(ring[0], 25) | 938 HAL_REO_REMAP_IX3(ring[0], 26) | 939 HAL_REO_REMAP_IX3(ring[0], 27) | 940 HAL_REO_REMAP_IX3(ring[0], 28) | 941 HAL_REO_REMAP_IX3(ring[0], 29) | 942 HAL_REO_REMAP_IX3(ring[0], 30) | 943 HAL_REO_REMAP_IX3(ring[0], 31); 944 break; 945 case 2: 946 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 947 HAL_REO_REMAP_IX2(ring[0], 17) | 948 HAL_REO_REMAP_IX2(ring[1], 18) | 949 HAL_REO_REMAP_IX2(ring[1], 19) | 950 HAL_REO_REMAP_IX2(ring[0], 20) | 951 HAL_REO_REMAP_IX2(ring[0], 21) | 952 HAL_REO_REMAP_IX2(ring[1], 22) | 953 HAL_REO_REMAP_IX2(ring[1], 23); 954 955 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 956 HAL_REO_REMAP_IX3(ring[0], 25) | 957 HAL_REO_REMAP_IX3(ring[1], 26) | 958 HAL_REO_REMAP_IX3(ring[1], 27) | 959 HAL_REO_REMAP_IX3(ring[0], 28) | 960 HAL_REO_REMAP_IX3(ring[0], 29) | 961 HAL_REO_REMAP_IX3(ring[1], 30) | 962 HAL_REO_REMAP_IX3(ring[1], 31); 963 break; 964 case 3: 965 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 966 HAL_REO_REMAP_IX2(ring[1], 17) | 967 HAL_REO_REMAP_IX2(ring[2], 18) | 968 HAL_REO_REMAP_IX2(ring[0], 19) | 969 HAL_REO_REMAP_IX2(ring[1], 20) | 970 HAL_REO_REMAP_IX2(ring[2], 21) | 971 HAL_REO_REMAP_IX2(ring[0], 22) | 972 HAL_REO_REMAP_IX2(ring[1], 23); 973 974 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) | 975 HAL_REO_REMAP_IX3(ring[0], 25) | 976 HAL_REO_REMAP_IX3(ring[1], 26) | 977 HAL_REO_REMAP_IX3(ring[2], 27) | 978 HAL_REO_REMAP_IX3(ring[0], 28) | 979 HAL_REO_REMAP_IX3(ring[1], 29) | 980 HAL_REO_REMAP_IX3(ring[2], 30) | 981 HAL_REO_REMAP_IX3(ring[0], 31); 982 break; 983 case 4: 984 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 985 HAL_REO_REMAP_IX2(ring[1], 17) | 986 HAL_REO_REMAP_IX2(ring[2], 18) | 987 HAL_REO_REMAP_IX2(ring[3], 19) | 988 HAL_REO_REMAP_IX2(ring[0], 20) | 989 HAL_REO_REMAP_IX2(ring[1], 21) | 990 HAL_REO_REMAP_IX2(ring[2], 22) | 991 HAL_REO_REMAP_IX2(ring[3], 23); 992 993 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 994 HAL_REO_REMAP_IX3(ring[1], 25) | 995 HAL_REO_REMAP_IX3(ring[2], 26) | 996 HAL_REO_REMAP_IX3(ring[3], 27) | 997 HAL_REO_REMAP_IX3(ring[0], 28) | 998 HAL_REO_REMAP_IX3(ring[1], 29) | 999 HAL_REO_REMAP_IX3(ring[2], 30) | 1000 HAL_REO_REMAP_IX3(ring[3], 31); 1001 break; 1002 } 1003 } 1004 1005 /** 1006 * hal_rx_flow_setup_fse_6432() - Setup a flow search entry in HW FST 1007 * @rx_fst: Pointer to the Rx Flow Search Table 1008 * @table_offset: offset into the table where the flow is to be setup 1009 * @rx_flow: Flow Parameters 1010 * 1011 * Return: Success/Failure 1012 */ 1013 static void * 1014 hal_rx_flow_setup_fse_6432(uint8_t *rx_fst, uint32_t table_offset, 1015 uint8_t *rx_flow) 1016 { 1017 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 1018 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 1019 uint8_t *fse; 1020 bool fse_valid; 1021 1022 if (table_offset >= fst->max_entries) { 1023 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 1024 "HAL FSE table offset %u exceeds max entries %u", 1025 table_offset, fst->max_entries); 1026 return NULL; 1027 } 1028 1029 fse = (uint8_t *)fst->base_vaddr + 1030 (table_offset * HAL_RX_FST_ENTRY_SIZE); 1031 1032 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID); 1033 1034 if (fse_valid) { 1035 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 1036 "HAL FSE %pK already valid", fse); 1037 return NULL; 1038 } 1039 1040 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96) = 1041 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96, 1042 qdf_htonl(flow->tuple_info.src_ip_127_96)); 1043 1044 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64) = 1045 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64, 1046 qdf_htonl(flow->tuple_info.src_ip_95_64)); 1047 1048 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32) = 1049 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32, 1050 qdf_htonl(flow->tuple_info.src_ip_63_32)); 1051 1052 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0) = 1053 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0, 1054 qdf_htonl(flow->tuple_info.src_ip_31_0)); 1055 1056 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96) = 1057 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96, 1058 qdf_htonl(flow->tuple_info.dest_ip_127_96)); 1059 1060 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64) = 1061 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64, 1062 qdf_htonl(flow->tuple_info.dest_ip_95_64)); 1063 1064 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32) = 1065 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32, 1066 qdf_htonl(flow->tuple_info.dest_ip_63_32)); 1067 1068 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0) = 1069 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0, 1070 qdf_htonl(flow->tuple_info.dest_ip_31_0)); 1071 1072 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_PORT); 1073 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_PORT) |= 1074 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_PORT, 1075 (flow->tuple_info.dest_port)); 1076 1077 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_PORT); 1078 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_PORT) |= 1079 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_PORT, 1080 (flow->tuple_info.src_port)); 1081 1082 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL); 1083 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL) |= 1084 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL, 1085 flow->tuple_info.l4_protocol); 1086 1087 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, USE_PPE); 1088 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, USE_PPE) |= 1089 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, USE_PPE, flow->use_ppe_ds); 1090 1091 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, PRIORITY_VALID); 1092 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, PRIORITY_VALID) |= 1093 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, PRIORITY_VALID, 1094 flow->priority_vld); 1095 1096 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, SERVICE_CODE); 1097 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SERVICE_CODE) |= 1098 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SERVICE_CODE, 1099 flow->service_code); 1100 1101 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER); 1102 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER) |= 1103 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER, 1104 flow->reo_destination_handler); 1105 1106 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID); 1107 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID) |= 1108 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, VALID, 1); 1109 1110 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, METADATA); 1111 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, METADATA) = 1112 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, METADATA, 1113 flow->fse_metadata); 1114 1115 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_INDICATION); 1116 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_INDICATION) |= 1117 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, 1118 REO_DESTINATION_INDICATION, 1119 flow->reo_destination_indication); 1120 1121 /* Reset all the other fields in FSE */ 1122 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, RESERVED_9); 1123 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_DROP); 1124 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_COUNT); 1125 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_BYTE_COUNT); 1126 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, TIMESTAMP); 1127 1128 return fse; 1129 } 1130 1131 #ifndef NO_RX_PKT_HDR_TLV 1132 /** 1133 * hal_rx_dump_pkt_hdr_tlv_6432(): dump RX pkt header TLV in hex format 1134 * @pkt_tlvs: pointer the pkt_hdr_tlv in pkt. 1135 * @dbg_level: log level. 1136 * 1137 * Return: void 1138 */ 1139 static inline void hal_rx_dump_pkt_hdr_tlv_6432(struct rx_pkt_tlvs *pkt_tlvs, 1140 uint8_t dbg_level) 1141 { 1142 struct rx_pkt_hdr_tlv *pkt_hdr_tlv = &pkt_tlvs->pkt_hdr_tlv; 1143 1144 hal_verbose_debug("\n---------------\n" 1145 "rx_pkt_hdr_tlv\n" 1146 "---------------\n" 1147 "phy_ppdu_id 0x%x ", 1148 pkt_hdr_tlv->phy_ppdu_id); 1149 1150 hal_verbose_hex_dump(pkt_hdr_tlv->rx_pkt_hdr, 1151 sizeof(pkt_hdr_tlv->rx_pkt_hdr)); 1152 } 1153 #else 1154 /** 1155 * hal_rx_dump_pkt_hdr_tlv_6432(): dump RX pkt header TLV in hex format 1156 * @pkt_tlvs: pointer the pkt_hdr_tlv in pkt. 1157 * @dbg_level: log level. 1158 * 1159 * Return: void 1160 */ 1161 static inline void hal_rx_dump_pkt_hdr_tlv_6432(struct rx_pkt_tlvs *pkt_tlvs, 1162 uint8_t dbg_level) 1163 { 1164 } 1165 #endif 1166 1167 /** 1168 * hal_rx_dump_pkt_tlvs_6432(): API to print RX Pkt TLVS qcn6432 1169 * @hal_soc_hdl: hal_soc handle 1170 * @buf: pointer the pkt buffer 1171 * @dbg_level: log level 1172 * 1173 * Return: void 1174 */ 1175 #ifdef CONFIG_WORD_BASED_TLV 1176 static void hal_rx_dump_pkt_tlvs_6432(hal_soc_handle_t hal_soc_hdl, 1177 uint8_t *buf, uint8_t dbg_level) 1178 { 1179 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1180 struct rx_msdu_end_compact *msdu_end = 1181 &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1182 struct rx_mpdu_start_compact *mpdu_start = 1183 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1184 1185 hal_rx_dump_msdu_end_tlv_6432(msdu_end, dbg_level); 1186 hal_rx_dump_mpdu_start_tlv_6432(mpdu_start, dbg_level); 1187 hal_rx_dump_pkt_hdr_tlv_6432(pkt_tlvs, dbg_level); 1188 } 1189 #else 1190 static void hal_rx_dump_pkt_tlvs_6432(hal_soc_handle_t hal_soc_hdl, 1191 uint8_t *buf, uint8_t dbg_level) 1192 { 1193 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1194 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1195 struct rx_mpdu_start *mpdu_start = 1196 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1197 1198 hal_rx_dump_msdu_end_tlv_6432(msdu_end, dbg_level); 1199 hal_rx_dump_mpdu_start_tlv_6432(mpdu_start, dbg_level); 1200 hal_rx_dump_pkt_hdr_tlv_6432(pkt_tlvs, dbg_level); 1201 } 1202 #endif 1203 1204 #define HAL_NUM_TCL_BANKS_6432 24 1205 1206 /** 1207 * hal_cmem_write_6432() - function for CMEM buffer writing 1208 * @hal_soc_hdl: HAL SOC handle 1209 * @offset: CMEM address 1210 * @value: value to write 1211 * 1212 * Return: None. 1213 */ 1214 static void hal_cmem_write_6432(hal_soc_handle_t hal_soc_hdl, 1215 uint32_t offset, 1216 uint32_t value) 1217 { 1218 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 1219 1220 pld_reg_write(hal->qdf_dev->dev, offset, value, 1221 hal->dev_base_addr_cmem); 1222 } 1223 1224 /** 1225 * hal_tx_get_num_tcl_banks_6432() - Get number of banks in target 1226 * 1227 * Returns: number of bank 1228 */ 1229 static uint8_t hal_tx_get_num_tcl_banks_6432(void) 1230 { 1231 return HAL_NUM_TCL_BANKS_6432; 1232 } 1233 1234 static 1235 void hal_compute_reo_remap_ix0_6432(struct hal_soc *soc) 1236 { 1237 uint32_t remap0; 1238 1239 remap0 = HAL_REG_READ(soc, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR 1240 (REO_REG_REG_BASE)); 1241 1242 remap0 &= ~(HAL_REO_REMAP_IX0(0xF, 6)); 1243 remap0 |= HAL_REO_REMAP_IX0(REO2PPE_DST_RING, 6); 1244 1245 HAL_REG_WRITE(soc, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR 1246 (REO_REG_REG_BASE), remap0); 1247 1248 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR 0x%x", 1249 HAL_REG_READ(soc, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR 1250 (REO_REG_REG_BASE))); 1251 } 1252 1253 static void hal_reo_setup_6432(struct hal_soc *soc, void *reoparams, 1254 int qref_reset) 1255 { 1256 uint32_t reg_val; 1257 struct hal_reo_params *reo_params = (struct hal_reo_params *)reoparams; 1258 1259 reg_val = HAL_REG_READ(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR( 1260 REO_REG_REG_BASE)); 1261 1262 hal_reo_config_6432(soc, reg_val, reo_params); 1263 /* Other ring enable bits and REO_ENABLE will be set by FW */ 1264 1265 /* TODO: Setup destination ring mapping if enabled */ 1266 1267 /* TODO: Error destination ring setting is left to default. 1268 * Default setting is to send all errors to release ring. 1269 */ 1270 1271 /* Set the reo descriptor swap bits in case of BIG endian platform */ 1272 hal_setup_reo_swap(soc); 1273 1274 HAL_REG_WRITE(soc, 1275 HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(REO_REG_REG_BASE), 1276 HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000); 1277 1278 HAL_REG_WRITE(soc, 1279 HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(REO_REG_REG_BASE), 1280 (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000)); 1281 1282 HAL_REG_WRITE(soc, 1283 HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(REO_REG_REG_BASE), 1284 (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000)); 1285 1286 HAL_REG_WRITE(soc, 1287 HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(REO_REG_REG_BASE), 1288 (HAL_DEFAULT_VO_REO_TIMEOUT_MS * 1000)); 1289 1290 /* 1291 * When hash based routing is enabled, routing of the rx packet 1292 * is done based on the following value: 1 _ _ _ _ The last 4 1293 * bits are based on hash[3:0]. This means the possible values 1294 * are 0x10 to 0x1f. This value is used to look-up the 1295 * ring ID configured in Destination_Ring_Ctrl_IX_* register. 1296 * The Destination_Ring_Ctrl_IX_2 and Destination_Ring_Ctrl_IX_3 1297 * registers need to be configured to set-up the 16 entries to 1298 * map the hash values to a ring number. There are 3 bits per 1299 * hash entry – which are mapped as follows: 1300 * 0: TCL, 1:SW1, 2:SW2, * 3:SW3, 4:SW4, 5:Release, 6:FW(WIFI), 1301 * 7: NOT_USED. 1302 */ 1303 if (reo_params->rx_hash_enabled) { 1304 hal_compute_reo_remap_ix0_6432(soc); 1305 HAL_REG_WRITE(soc, 1306 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR 1307 (REO_REG_REG_BASE), reo_params->remap0); 1308 1309 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x", 1310 HAL_REG_READ(soc, 1311 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR( 1312 REO_REG_REG_BASE))); 1313 1314 HAL_REG_WRITE(soc, 1315 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 1316 (REO_REG_REG_BASE), reo_params->remap1); 1317 1318 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x", 1319 HAL_REG_READ(soc, 1320 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR( 1321 REO_REG_REG_BASE))); 1322 1323 HAL_REG_WRITE(soc, 1324 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 1325 (REO_REG_REG_BASE), reo_params->remap2); 1326 1327 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 0x%x", 1328 HAL_REG_READ(soc, 1329 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR( 1330 REO_REG_REG_BASE))); 1331 } 1332 1333 /* TODO: Check if the following registers shoould be setup by host: 1334 * AGING_CONTROL 1335 * HIGH_MEMORY_THRESHOLD 1336 * GLOBAL_LINK_DESC_COUNT_THRESH_IX_0[1,2] 1337 * GLOBAL_LINK_DESC_COUNT_CTRL 1338 */ 1339 1340 soc->reo_qref = *reo_params->reo_qref; 1341 hal_reo_shared_qaddr_init((hal_soc_handle_t)soc, qref_reset); 1342 } 1343 1344 static uint16_t hal_get_rx_max_ba_window_qcn6432(int tid) 1345 { 1346 return HAL_RX_BA_WINDOW_1024; 1347 } 1348 1349 /** 1350 * hal_qcn6432_get_reo_qdesc_size()- Get the reo queue descriptor size 1351 * from the give Block-Ack window size 1352 * @ba_window_size: Block-Ack window size 1353 * @tid: TID 1354 * 1355 * Return: reo queue descriptor size 1356 */ 1357 static uint32_t hal_qcn6432_get_reo_qdesc_size(uint32_t ba_window_size, int tid) 1358 { 1359 /* Hardcode the ba_window_size to HAL_RX_MAX_BA_WINDOW for 1360 * NON_QOS_TID until HW issues are resolved. 1361 */ 1362 if (tid != HAL_NON_QOS_TID) 1363 ba_window_size = hal_get_rx_max_ba_window_qcn6432(tid); 1364 1365 /* Return descriptor size corresponding to window size of 2 since 1366 * we set ba_window_size to 2 while setting up REO descriptors as 1367 * a WAR to get 2k jump exception aggregates are received without 1368 * a BA session. 1369 */ 1370 if (ba_window_size <= 1) { 1371 if (tid != HAL_NON_QOS_TID) 1372 return sizeof(struct rx_reo_queue) + 1373 sizeof(struct rx_reo_queue_ext); 1374 else 1375 return sizeof(struct rx_reo_queue); 1376 } 1377 1378 if (ba_window_size <= 105) 1379 return sizeof(struct rx_reo_queue) + 1380 sizeof(struct rx_reo_queue_ext); 1381 1382 if (ba_window_size <= 210) 1383 return sizeof(struct rx_reo_queue) + 1384 (2 * sizeof(struct rx_reo_queue_ext)); 1385 1386 if (ba_window_size <= 256) 1387 return sizeof(struct rx_reo_queue) + 1388 (3 * sizeof(struct rx_reo_queue_ext)); 1389 1390 return sizeof(struct rx_reo_queue) + 1391 (10 * sizeof(struct rx_reo_queue_ext)) + 1392 sizeof(struct rx_reo_queue_1k); 1393 } 1394 /** 1395 * hal_rx_tlv_msdu_done_copy_get_6432() - Get msdu done copy bit from rx_tlv 1396 * 1397 * @buf: pointer the tx_tlv 1398 * 1399 * Returns: msdu done copy bit 1400 */ 1401 static inline uint32_t hal_rx_tlv_msdu_done_copy_get_6432(uint8_t *buf) 1402 { 1403 return HAL_RX_TLV_MSDU_DONE_COPY_GET(buf); 1404 } 1405 1406 /** 1407 * hal_read_pmm_scratch_reg_6432(): API to read PMM Scratch register 1408 * 1409 * @soc: HAL soc 1410 * @base_addr: BAR address 1411 * @reg_enum: Enum of the scratch register 1412 * 1413 * Return: uint32_t 1414 */ 1415 static inline 1416 uint32_t hal_read_pmm_scratch_reg_6432(struct hal_soc *soc, 1417 uint32_t base_addr, 1418 enum hal_scratch_reg_enum reg_enum) 1419 { 1420 uint32_t val = 0; 1421 1422 pld_reg_read(soc->qdf_dev->dev, base_addr + (reg_enum * 4), &val, NULL); 1423 return val; 1424 } 1425 1426 /** 1427 * hal_get_tsf2_scratch_reg_qcn6432(): API to read tsf2 scratch register 1428 * 1429 * @hal_soc_hdl: HAL soc context 1430 * @mac_id: mac id 1431 * @value: Pointer to update tsf2 value 1432 * 1433 * Return: void 1434 */ 1435 static void hal_get_tsf2_scratch_reg_qcn6432(hal_soc_handle_t hal_soc_hdl, 1436 uint8_t mac_id, uint64_t *value) 1437 { 1438 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; 1439 uint32_t offset_lo, offset_hi; 1440 enum hal_scratch_reg_enum enum_lo, enum_hi; 1441 1442 hal_get_tsf_enum(DEFAULT_TSF_ID, mac_id, &enum_lo, &enum_hi); 1443 1444 offset_lo = hal_read_pmm_scratch_reg_6432(soc, 1445 PMM_REG_BASE_QCN6432, 1446 enum_lo); 1447 1448 offset_hi = hal_read_pmm_scratch_reg_6432(soc, 1449 PMM_REG_BASE_QCN6432, 1450 enum_hi); 1451 1452 *value = ((uint64_t)(offset_hi) << 32 | offset_lo); 1453 } 1454 1455 /** 1456 * hal_get_tqm_scratch_reg_qcn6432(): API to read tqm scratch register 1457 * 1458 * @hal_soc_hdl: HAL soc context 1459 * @value: Pointer to update tqm value 1460 * 1461 * Return: void 1462 */ 1463 1464 static void hal_get_tqm_scratch_reg_qcn6432(hal_soc_handle_t hal_soc_hdl, 1465 uint64_t *value) 1466 { 1467 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; 1468 uint32_t offset_lo, offset_hi; 1469 1470 offset_lo = hal_read_pmm_scratch_reg_6432(soc, 1471 PMM_REG_BASE_QCN6432, 1472 PMM_TQM_CLOCK_OFFSET_LO_US); 1473 1474 offset_hi = hal_read_pmm_scratch_reg_6432(soc, 1475 PMM_REG_BASE_QCN6432, 1476 PMM_TQM_CLOCK_OFFSET_HI_US); 1477 1478 *value = ((uint64_t)(offset_hi) << 32 | offset_lo); 1479 } 1480 1481 static void hal_hw_txrx_ops_attach_qcn6432(struct hal_soc *hal_soc) 1482 { 1483 /* init and setup */ 1484 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic; 1485 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic; 1486 hal_soc->ops->hal_srng_hw_disable = hal_srng_hw_disable_generic; 1487 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic; 1488 hal_soc->ops->hal_get_window_address = hal_get_window_address_6432; 1489 hal_soc->ops->hal_cmem_write = hal_cmem_write_6432; 1490 1491 /* tx */ 1492 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_6432; 1493 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_6432; 1494 hal_soc->ops->hal_tx_comp_get_status = 1495 hal_tx_comp_get_status_generic_be; 1496 hal_soc->ops->hal_tx_init_cmd_credit_ring = 1497 hal_tx_init_cmd_credit_ring_6432; 1498 hal_soc->ops->hal_tx_set_ppe_cmn_cfg = hal_tx_set_ppe_cmn_config_6432; 1499 hal_soc->ops->hal_tx_set_ppe_vp_entry = hal_tx_set_ppe_vp_entry_6432; 1500 hal_soc->ops->hal_ppeds_cfg_ast_override_map_reg = 1501 hal_ppeds_cfg_ast_override_map_reg_6432; 1502 hal_soc->ops->hal_tx_set_ppe_pri2tid = hal_tx_set_ppe_pri2tid_map_6432; 1503 hal_soc->ops->hal_tx_update_ppe_pri2tid = 1504 hal_tx_update_ppe_pri2tid_6432; 1505 hal_soc->ops->hal_tx_dump_ppe_vp_entry = hal_tx_dump_ppe_vp_entry_6432; 1506 hal_soc->ops->hal_tx_get_num_ppe_vp_tbl_entries = 1507 hal_tx_get_num_ppe_vp_tbl_entries_6432; 1508 hal_soc->ops->hal_tx_enable_pri2tid_map = 1509 hal_tx_enable_pri2tid_map_6432; 1510 hal_soc->ops->hal_tx_config_rbm_mapping_be = 1511 hal_tx_config_rbm_mapping_be_6432; 1512 1513 /* rx */ 1514 hal_soc->ops->hal_rx_msdu_start_nss_get = hal_rx_tlv_nss_get_be; 1515 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status = 1516 hal_rx_mon_hw_desc_get_mpdu_status_be; 1517 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_6432; 1518 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv = 1519 hal_rx_proc_phyrx_other_receive_info_tlv_6432; 1520 1521 hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_6432; 1522 hal_soc->ops->hal_rx_dump_mpdu_start_tlv = 1523 hal_rx_dump_mpdu_start_tlv_6432; 1524 hal_soc->ops->hal_rx_dump_pkt_tlvs = hal_rx_dump_pkt_tlvs_6432; 1525 1526 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_6432; 1527 hal_soc->ops->hal_rx_mpdu_start_tid_get = hal_rx_tlv_tid_get_be; 1528 hal_soc->ops->hal_rx_msdu_start_reception_type_get = 1529 hal_rx_tlv_reception_type_get_be; 1530 hal_soc->ops->hal_rx_msdu_end_da_idx_get = 1531 hal_rx_msdu_end_da_idx_get_be; 1532 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = 1533 hal_rx_msdu_desc_info_get_ptr_6432; 1534 hal_soc->ops->hal_rx_link_desc_msdu0_ptr = 1535 hal_rx_link_desc_msdu0_ptr_6432; 1536 hal_soc->ops->hal_reo_status_get_header = 1537 hal_reo_status_get_header_6432; 1538 #ifdef WLAN_PKT_CAPTURE_RX_2_0 1539 hal_soc->ops->hal_rx_status_get_tlv_info = 1540 hal_rx_status_get_tlv_info_wrapper_be; 1541 #endif 1542 hal_soc->ops->hal_rx_wbm_err_info_get = 1543 hal_rx_wbm_err_info_get_generic_be; 1544 hal_soc->ops->hal_tx_set_pcp_tid_map = 1545 hal_tx_set_pcp_tid_map_generic_be; 1546 hal_soc->ops->hal_tx_update_pcp_tid_map = 1547 hal_tx_update_pcp_tid_generic_be; 1548 hal_soc->ops->hal_tx_set_tidmap_prty = 1549 hal_tx_update_tidmap_prty_generic_be; 1550 hal_soc->ops->hal_rx_get_rx_fragment_number = 1551 hal_rx_get_rx_fragment_number_be, 1552 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = 1553 hal_rx_tlv_da_is_mcbc_get_be; 1554 hal_soc->ops->hal_rx_msdu_end_is_tkip_mic_err = 1555 hal_rx_tlv_is_tkip_mic_err_get_be; 1556 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = 1557 hal_rx_tlv_sa_is_valid_get_be; 1558 hal_soc->ops->hal_rx_msdu_end_sa_idx_get = hal_rx_tlv_sa_idx_get_be; 1559 hal_soc->ops->hal_rx_desc_is_first_msdu = hal_rx_desc_is_first_msdu_be; 1560 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get = 1561 hal_rx_tlv_l3_hdr_padding_get_be; 1562 hal_soc->ops->hal_rx_encryption_info_valid = 1563 hal_rx_encryption_info_valid_be; 1564 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_be; 1565 hal_soc->ops->hal_rx_msdu_end_first_msdu_get = 1566 hal_rx_tlv_first_msdu_get_be; 1567 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = 1568 hal_rx_tlv_da_is_valid_get_be; 1569 hal_soc->ops->hal_rx_msdu_end_last_msdu_get = 1570 hal_rx_tlv_last_msdu_get_be; 1571 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = 1572 hal_rx_get_mpdu_mac_ad4_valid_be; 1573 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get = 1574 hal_rx_mpdu_start_sw_peer_id_get_be; 1575 hal_soc->ops->hal_rx_tlv_peer_meta_data_get = 1576 hal_rx_msdu_peer_meta_data_get_be; 1577 #ifndef CONFIG_WORD_BASED_TLV 1578 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_be; 1579 hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get = 1580 hal_rx_mpdu_info_ampdu_flag_get_be; 1581 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = 1582 hal_rx_hw_desc_get_ppduid_get_be; 1583 hal_soc->ops->hal_rx_tlv_phy_ppdu_id_get = 1584 hal_rx_attn_phy_ppdu_id_get_be; 1585 hal_soc->ops->hal_rx_get_filter_category = 1586 hal_rx_get_filter_category_be; 1587 #endif 1588 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_be; 1589 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_be; 1590 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_be; 1591 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid = 1592 hal_rx_get_mpdu_frame_control_valid_be; 1593 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_be; 1594 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_be; 1595 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_be; 1596 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid = 1597 hal_rx_get_mpdu_sequence_control_valid_be; 1598 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_be; 1599 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_be; 1600 hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get = 1601 hal_rx_mpdu_start_mpdu_qos_control_valid_get_be; 1602 hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get = 1603 hal_rx_msdu_end_sa_sw_peer_id_get_be; 1604 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = 1605 hal_rx_msdu0_buffer_addr_lsb_6432; 1606 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = 1607 hal_rx_msdu_desc_info_ptr_get_6432; 1608 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_6432; 1609 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_6432; 1610 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_be; 1611 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_be; 1612 hal_soc->ops->hal_rx_get_mac_addr2_valid = 1613 hal_rx_get_mac_addr2_valid_be; 1614 hal_soc->ops->hal_reo_config = hal_reo_config_6432; 1615 hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_be; 1616 hal_soc->ops->hal_rx_msdu_flow_idx_invalid = 1617 hal_rx_msdu_flow_idx_invalid_be; 1618 hal_soc->ops->hal_rx_msdu_flow_idx_timeout = 1619 hal_rx_msdu_flow_idx_timeout_be; 1620 hal_soc->ops->hal_rx_msdu_fse_metadata_get = 1621 hal_rx_msdu_fse_metadata_get_be; 1622 hal_soc->ops->hal_rx_msdu_cce_match_get = 1623 hal_rx_msdu_cce_match_get_be; 1624 hal_soc->ops->hal_rx_msdu_cce_metadata_get = 1625 hal_rx_msdu_cce_metadata_get_be; 1626 hal_soc->ops->hal_rx_msdu_get_flow_params = 1627 hal_rx_msdu_get_flow_params_be; 1628 hal_soc->ops->hal_rx_tlv_get_tcp_chksum = hal_rx_tlv_get_tcp_chksum_be; 1629 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_be; 1630 #if defined(QCA_WIFI_QCA6432) && defined(WLAN_CFR_ENABLE) && \ 1631 defined(WLAN_ENH_CFR_ENABLE) 1632 hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_6432; 1633 hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_6432; 1634 #else 1635 hal_soc->ops->hal_rx_get_bb_info = NULL; 1636 hal_soc->ops->hal_rx_get_rtt_info = NULL; 1637 #endif 1638 /* rx - msdu fast path info fields */ 1639 hal_soc->ops->hal_rx_msdu_packet_metadata_get = 1640 hal_rx_msdu_packet_metadata_get_generic_be; 1641 hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid = 1642 hal_rx_mpdu_start_tlv_tag_valid_be; 1643 hal_soc->ops->hal_rx_wbm_err_msdu_continuation_get = 1644 hal_rx_wbm_err_msdu_continuation_get_6432; 1645 1646 /* rx - TLV struct offsets */ 1647 hal_soc->ops->hal_rx_msdu_end_offset_get = 1648 hal_rx_msdu_end_offset_get_generic; 1649 hal_soc->ops->hal_rx_mpdu_start_offset_get = 1650 hal_rx_mpdu_start_offset_get_generic; 1651 #ifndef NO_RX_PKT_HDR_TLV 1652 hal_soc->ops->hal_rx_pkt_tlv_offset_get = 1653 hal_rx_pkt_tlv_offset_get_generic; 1654 #endif 1655 hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_6432; 1656 1657 hal_soc->ops->hal_rx_flow_get_tuple_info = 1658 hal_rx_flow_get_tuple_info_be; 1659 hal_soc->ops->hal_rx_flow_delete_entry = 1660 hal_rx_flow_delete_entry_be; 1661 hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_be; 1662 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = 1663 hal_compute_reo_remap_ix2_ix3_6432; 1664 1665 hal_soc->ops->hal_rx_msdu_get_reo_destination_indication = 1666 hal_rx_msdu_get_reo_destination_indication_be; 1667 hal_soc->ops->hal_rx_get_tlv_size = hal_rx_get_tlv_size_generic_be; 1668 hal_soc->ops->hal_rx_msdu_is_wlan_mcast = 1669 hal_rx_msdu_is_wlan_mcast_generic_be; 1670 hal_soc->ops->hal_tx_get_num_tcl_banks = hal_tx_get_num_tcl_banks_6432; 1671 hal_soc->ops->hal_rx_tlv_decap_format_get = 1672 hal_rx_tlv_decap_format_get_be; 1673 #ifdef RECEIVE_OFFLOAD 1674 hal_soc->ops->hal_rx_tlv_get_offload_info = 1675 hal_rx_tlv_get_offload_info_be; 1676 hal_soc->ops->hal_rx_get_proto_params = hal_rx_get_proto_params_be; 1677 hal_soc->ops->hal_rx_get_l3_l4_offsets = hal_rx_get_l3_l4_offsets_be; 1678 #endif 1679 hal_soc->ops->hal_rx_tlv_msdu_done_get = 1680 hal_rx_tlv_msdu_done_copy_get_6432; 1681 hal_soc->ops->hal_rx_tlv_msdu_len_get = 1682 hal_rx_msdu_start_msdu_len_get_be; 1683 hal_soc->ops->hal_rx_get_frame_ctrl_field = 1684 hal_rx_get_frame_ctrl_field_be; 1685 hal_soc->ops->hal_rx_tlv_csum_err_get = hal_rx_tlv_csum_err_get_be; 1686 hal_soc->ops->hal_rx_tlv_msdu_len_set = 1687 hal_rx_msdu_start_msdu_len_set_be; 1688 hal_soc->ops->hal_rx_tlv_sgi_get = hal_rx_tlv_sgi_get_be; 1689 hal_soc->ops->hal_rx_tlv_rate_mcs_get = hal_rx_tlv_rate_mcs_get_be; 1690 hal_soc->ops->hal_rx_tlv_bw_get = hal_rx_tlv_bw_get_be; 1691 hal_soc->ops->hal_rx_tlv_get_pkt_type = hal_rx_tlv_get_pkt_type_be; 1692 hal_soc->ops->hal_rx_tlv_mic_err_get = hal_rx_tlv_mic_err_get_be; 1693 hal_soc->ops->hal_rx_tlv_decrypt_err_get = 1694 hal_rx_tlv_decrypt_err_get_be; 1695 hal_soc->ops->hal_rx_tlv_first_mpdu_get = hal_rx_tlv_first_mpdu_get_be; 1696 hal_soc->ops->hal_rx_tlv_get_is_decrypted = 1697 hal_rx_tlv_get_is_decrypted_be; 1698 hal_soc->ops->hal_rx_msdu_get_keyid = hal_rx_msdu_get_keyid_be; 1699 hal_soc->ops->hal_rx_tlv_get_freq = hal_rx_tlv_get_freq_be; 1700 hal_soc->ops->hal_rx_priv_info_set_in_tlv = 1701 hal_rx_priv_info_set_in_tlv_be; 1702 hal_soc->ops->hal_rx_priv_info_get_from_tlv = 1703 hal_rx_priv_info_get_from_tlv_be; 1704 hal_soc->ops->hal_rx_pkt_hdr_get = hal_rx_pkt_hdr_get_be; 1705 hal_soc->ops->hal_reo_setup = hal_reo_setup_6432; 1706 hal_soc->ops->hal_reo_config_reo2ppe_dest_info = NULL; 1707 #ifdef REO_SHARED_QREF_TABLE_EN 1708 hal_soc->ops->hal_reo_shared_qaddr_setup = hal_reo_shared_qaddr_setup_be; 1709 hal_soc->ops->hal_reo_shared_qaddr_init = hal_reo_shared_qaddr_init_be; 1710 hal_soc->ops->hal_reo_shared_qaddr_detach = hal_reo_shared_qaddr_detach_be; 1711 hal_soc->ops->hal_reo_shared_qaddr_write = hal_reo_shared_qaddr_write_be; 1712 hal_soc->ops->hal_reo_shared_qaddr_cache_clear = hal_reo_shared_qaddr_cache_clear_be; 1713 #endif 1714 /* Overwrite the default BE ops */ 1715 hal_soc->ops->hal_get_rx_max_ba_window = 1716 hal_get_rx_max_ba_window_qcn6432; 1717 hal_soc->ops->hal_get_reo_qdesc_size = hal_qcn6432_get_reo_qdesc_size; 1718 /* TX MONITOR */ 1719 #ifdef WLAN_PKT_CAPTURE_TX_2_0 1720 hal_soc->ops->hal_txmon_is_mon_buf_addr_tlv = 1721 hal_txmon_is_mon_buf_addr_tlv_generic_be; 1722 hal_soc->ops->hal_txmon_populate_packet_info = 1723 hal_txmon_populate_packet_info_generic_be; 1724 hal_soc->ops->hal_txmon_status_parse_tlv = 1725 hal_txmon_status_parse_tlv_generic_be; 1726 hal_soc->ops->hal_txmon_status_get_num_users = 1727 hal_txmon_status_get_num_users_generic_be; 1728 #if defined(TX_MONITOR_WORD_MASK) 1729 hal_soc->ops->hal_txmon_get_word_mask = 1730 hal_txmon_get_word_mask_qcn6432; 1731 #else 1732 hal_soc->ops->hal_txmon_get_word_mask = 1733 hal_txmon_get_word_mask_generic_be; 1734 #endif /* TX_MONITOR_WORD_MASK */ 1735 #endif /* WLAN_PKT_CAPTURE_TX_2_0 */ 1736 hal_soc->ops->hal_compute_reo_remap_ix0 = NULL; 1737 hal_soc->ops->hal_tx_vdev_mismatch_routing_set = 1738 hal_tx_vdev_mismatch_routing_set_generic_be; 1739 hal_soc->ops->hal_tx_mcast_mlo_reinject_routing_set = 1740 hal_tx_mcast_mlo_reinject_routing_set_generic_be; 1741 hal_soc->ops->hal_get_ba_aging_timeout = 1742 hal_get_ba_aging_timeout_be_generic; 1743 hal_soc->ops->hal_setup_link_idle_list = 1744 hal_setup_link_idle_list_generic_be; 1745 hal_soc->ops->hal_cookie_conversion_reg_cfg_be = 1746 hal_cookie_conversion_reg_cfg_generic_be; 1747 hal_soc->ops->hal_set_ba_aging_timeout = 1748 hal_set_ba_aging_timeout_be_generic; 1749 hal_soc->ops->hal_tx_populate_bank_register = 1750 hal_tx_populate_bank_register_be; 1751 hal_soc->ops->hal_tx_vdev_mcast_ctrl_set = 1752 hal_tx_vdev_mcast_ctrl_set_be; 1753 #ifdef CONFIG_WORD_BASED_TLV 1754 hal_soc->ops->hal_rx_mpdu_start_wmask_get = 1755 hal_rx_mpdu_start_wmask_get_be; 1756 hal_soc->ops->hal_rx_msdu_end_wmask_get = 1757 hal_rx_msdu_end_wmask_get_be; 1758 #endif 1759 hal_soc->ops->hal_get_tsf2_scratch_reg = 1760 hal_get_tsf2_scratch_reg_qcn6432; 1761 hal_soc->ops->hal_get_tqm_scratch_reg = 1762 hal_get_tqm_scratch_reg_qcn6432; 1763 hal_soc->ops->hal_tx_ring_halt_set = hal_tx_ppe2tcl_ring_halt_set_6432; 1764 hal_soc->ops->hal_tx_ring_halt_reset = 1765 hal_tx_ppe2tcl_ring_halt_reset_6432; 1766 hal_soc->ops->hal_tx_ring_halt_poll = 1767 hal_tx_ppe2tcl_ring_halt_done_6432; 1768 hal_soc->ops->hal_tx_get_num_ppe_vp_search_idx_tbl_entries = 1769 hal_tx_get_num_ppe_vp_search_idx_reg_entries_6432; 1770 }; 1771 1772 struct hal_hw_srng_config hw_srng_table_6432[] = { 1773 /* TODO: max_rings can populated by querying HW capabilities */ 1774 { /* REO_DST */ 1775 .start_ring_id = HAL_SRNG_REO2SW1, 1776 .max_rings = 8, 1777 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1778 .lmac_ring = FALSE, 1779 .ring_dir = HAL_SRNG_DST_RING, 1780 .reg_start = { 1781 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 1782 REO_REG_REG_BASE), 1783 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 1784 REO_REG_REG_BASE) 1785 }, 1786 .reg_size = { 1787 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 1788 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 1789 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 1790 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 1791 }, 1792 .max_size = 1793 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 1794 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 1795 }, 1796 { /* REO_EXCEPTION */ 1797 /* Designating REO2SW0 ring as exception ring. This ring is 1798 * similar to other REO2SW rings though it is named as REO2SW0. 1799 * Any of theREO2SW rings can be used as exception ring. 1800 */ 1801 .start_ring_id = HAL_SRNG_REO2SW0, 1802 .max_rings = 1, 1803 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1804 .lmac_ring = FALSE, 1805 .ring_dir = HAL_SRNG_DST_RING, 1806 .reg_start = { 1807 HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR( 1808 REO_REG_REG_BASE), 1809 HWIO_REO_R2_REO2SW0_RING_HP_ADDR( 1810 REO_REG_REG_BASE) 1811 }, 1812 /* Single ring - provide ring size if multiple rings of this 1813 * type are supported 1814 */ 1815 .reg_size = {}, 1816 .max_size = 1817 HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_BMSK >> 1818 HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_SHFT, 1819 }, 1820 { /* REO_REINJECT */ 1821 .start_ring_id = HAL_SRNG_SW2REO, 1822 .max_rings = 4, 1823 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1824 .lmac_ring = FALSE, 1825 .ring_dir = HAL_SRNG_SRC_RING, 1826 .reg_start = { 1827 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 1828 REO_REG_REG_BASE), 1829 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 1830 REO_REG_REG_BASE) 1831 }, 1832 /* Single ring - provide ring size if multiple rings of this 1833 * type are supported 1834 */ 1835 .reg_size = { 1836 HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(0) - 1837 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(0), 1838 HWIO_REO_R2_SW2REO1_RING_HP_ADDR(0) - 1839 HWIO_REO_R2_SW2REO_RING_HP_ADDR(0) 1840 }, 1841 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 1842 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 1843 }, 1844 { /* REO_CMD */ 1845 .start_ring_id = HAL_SRNG_REO_CMD, 1846 .max_rings = 1, 1847 .entry_size = (sizeof(struct tlv_32_hdr) + 1848 sizeof(struct reo_get_queue_stats)) >> 2, 1849 .lmac_ring = FALSE, 1850 .ring_dir = HAL_SRNG_SRC_RING, 1851 .reg_start = { 1852 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 1853 REO_REG_REG_BASE), 1854 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 1855 REO_REG_REG_BASE), 1856 }, 1857 /* Single ring - provide ring size if multiple rings of this 1858 * type are supported 1859 */ 1860 .reg_size = {}, 1861 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1862 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1863 }, 1864 { /* REO_STATUS */ 1865 .start_ring_id = HAL_SRNG_REO_STATUS, 1866 .max_rings = 1, 1867 .entry_size = (sizeof(struct tlv_32_hdr) + 1868 sizeof(struct reo_get_queue_stats_status)) >> 2, 1869 .lmac_ring = FALSE, 1870 .ring_dir = HAL_SRNG_DST_RING, 1871 .reg_start = { 1872 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 1873 REO_REG_REG_BASE), 1874 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 1875 REO_REG_REG_BASE), 1876 }, 1877 /* Single ring - provide ring size if multiple rings of this 1878 * type are supported 1879 */ 1880 .reg_size = {}, 1881 .max_size = 1882 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1883 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1884 }, 1885 { /* TCL_DATA */ 1886 .start_ring_id = HAL_SRNG_SW2TCL1, 1887 .max_rings = 6, 1888 .entry_size = sizeof(struct tcl_data_cmd) >> 2, 1889 .lmac_ring = FALSE, 1890 .ring_dir = HAL_SRNG_SRC_RING, 1891 .reg_start = { 1892 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 1893 MAC_TCL_REG_REG_BASE), 1894 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 1895 MAC_TCL_REG_REG_BASE), 1896 }, 1897 .reg_size = { 1898 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 1899 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 1900 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 1901 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 1902 }, 1903 .max_size = 1904 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 1905 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 1906 }, 1907 { /* TCL_CMD/CREDIT */ 1908 /* qca8074v2 and qcn6432 uses this ring for data commands */ 1909 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 1910 .max_rings = 1, 1911 .entry_size = sizeof(struct tcl_data_cmd) >> 2, 1912 .lmac_ring = FALSE, 1913 .ring_dir = HAL_SRNG_SRC_RING, 1914 .reg_start = { 1915 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR( 1916 MAC_TCL_REG_REG_BASE), 1917 HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR( 1918 MAC_TCL_REG_REG_BASE), 1919 }, 1920 /* Single ring - provide ring size if multiple rings of this 1921 * type are supported 1922 */ 1923 .reg_size = {}, 1924 .max_size = 1925 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >> 1926 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT, 1927 }, 1928 { /* TCL_STATUS */ 1929 .start_ring_id = HAL_SRNG_TCL_STATUS, 1930 .max_rings = 1, 1931 .entry_size = (sizeof(struct tlv_32_hdr) + 1932 sizeof(struct tcl_status_ring)) >> 2, 1933 .lmac_ring = FALSE, 1934 .ring_dir = HAL_SRNG_DST_RING, 1935 .reg_start = { 1936 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 1937 MAC_TCL_REG_REG_BASE), 1938 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 1939 MAC_TCL_REG_REG_BASE), 1940 }, 1941 /* Single ring - provide ring size if multiple rings of this 1942 * type are supported 1943 */ 1944 .reg_size = {}, 1945 .max_size = 1946 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 1947 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 1948 }, 1949 { /* CE_SRC */ 1950 .start_ring_id = HAL_SRNG_CE_0_SRC, 1951 .max_rings = 16, 1952 .entry_size = sizeof(struct ce_src_desc) >> 2, 1953 .lmac_ring = FALSE, 1954 .ring_dir = HAL_SRNG_SRC_RING, 1955 .reg_start = { 1956 HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR( 1957 WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE), 1958 HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR( 1959 WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE), 1960 }, 1961 .reg_size = { 1962 WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE - 1963 WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE, 1964 WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE - 1965 WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE, 1966 }, 1967 .max_size = 1968 HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK >> 1969 HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT, 1970 }, 1971 { /* CE_DST */ 1972 .start_ring_id = HAL_SRNG_CE_0_DST, 1973 .max_rings = 16, 1974 .entry_size = 8 >> 2, 1975 /*TODO: entry_size above should actually be 1976 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 1977 * of struct ce_dst_desc in HW header files 1978 */ 1979 .lmac_ring = FALSE, 1980 .ring_dir = HAL_SRNG_SRC_RING, 1981 .reg_start = { 1982 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1983 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE), 1984 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1985 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE), 1986 }, 1987 .reg_size = { 1988 WFSS_CE_1_CHANNEL_DST_REG_REG_BASE - 1989 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE, 1990 WFSS_CE_1_CHANNEL_DST_REG_REG_BASE - 1991 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE, 1992 }, 1993 .max_size = 1994 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1995 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1996 }, 1997 { /* CE_DST_STATUS */ 1998 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 1999 .max_rings = 16, 2000 .entry_size = sizeof(struct ce_stat_desc) >> 2, 2001 .lmac_ring = FALSE, 2002 .ring_dir = HAL_SRNG_DST_RING, 2003 .reg_start = { 2004 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 2005 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE), 2006 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 2007 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE), 2008 }, 2009 /* TODO: check destination status ring registers */ 2010 .reg_size = { 2011 WFSS_CE_1_CHANNEL_DST_REG_REG_BASE - 2012 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE, 2013 WFSS_CE_1_CHANNEL_DST_REG_REG_BASE - 2014 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE, 2015 }, 2016 .max_size = 2017 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 2018 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 2019 }, 2020 { /* WBM_IDLE_LINK */ 2021 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 2022 .max_rings = 1, 2023 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 2024 .lmac_ring = FALSE, 2025 .ring_dir = HAL_SRNG_SRC_RING, 2026 .reg_start = { 2027 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE), 2028 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(WBM_REG_REG_BASE), 2029 }, 2030 /* Single ring - provide ring size if multiple rings of this 2031 * type are supported 2032 */ 2033 .reg_size = {}, 2034 .max_size = 2035 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 2036 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 2037 }, 2038 { /* SW2WBM_RELEASE */ 2039 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 2040 .max_rings = 1, 2041 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2042 .lmac_ring = FALSE, 2043 .ring_dir = HAL_SRNG_SRC_RING, 2044 .reg_start = { 2045 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE), 2046 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE), 2047 }, 2048 /* Single ring - provide ring size if multiple rings of this 2049 * type are supported 2050 */ 2051 .reg_size = {}, 2052 .max_size = 2053 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2054 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2055 }, 2056 { /* WBM2SW_RELEASE */ 2057 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 2058 .max_rings = 8, 2059 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2060 .lmac_ring = FALSE, 2061 .ring_dir = HAL_SRNG_DST_RING, 2062 .reg_start = { 2063 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR( 2064 WBM_REG_REG_BASE), 2065 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR( 2066 WBM_REG_REG_BASE), 2067 }, 2068 .reg_size = { 2069 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR( 2070 WBM_REG_REG_BASE) - 2071 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR( 2072 WBM_REG_REG_BASE), 2073 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR( 2074 WBM_REG_REG_BASE) - 2075 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR( 2076 WBM_REG_REG_BASE), 2077 }, 2078 .max_size = 2079 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2080 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2081 }, 2082 { /* RXDMA_BUF */ 2083 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 2084 #ifdef IPA_OFFLOAD 2085 .max_rings = 3, 2086 #else 2087 .max_rings = 3, 2088 #endif 2089 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2090 .lmac_ring = TRUE, 2091 .ring_dir = HAL_SRNG_SRC_RING, 2092 /* reg_start is not set because LMAC rings are not accessed 2093 * from host 2094 */ 2095 .reg_start = {}, 2096 .reg_size = {}, 2097 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2098 }, 2099 { /* RXDMA_DST */ 2100 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 2101 .max_rings = 0, 2102 .entry_size = 0/*sizeof(struct reo_entrance_ring) >> 2*/, 2103 .lmac_ring = TRUE, 2104 .ring_dir = HAL_SRNG_DST_RING, 2105 /* reg_start is not set because LMAC rings are not accessed 2106 * from host 2107 */ 2108 .reg_start = {}, 2109 .reg_size = {}, 2110 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2111 }, 2112 #ifdef WLAN_PKT_CAPTURE_RX_2_0 2113 { /* RXDMA_MONITOR_BUF */ 2114 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 2115 .max_rings = 1, 2116 .entry_size = sizeof(struct mon_ingress_ring) >> 2, 2117 .lmac_ring = TRUE, 2118 .ring_dir = HAL_SRNG_SRC_RING, 2119 /* reg_start is not set because LMAC rings are not accessed 2120 * from host 2121 */ 2122 .reg_start = {}, 2123 .reg_size = {}, 2124 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 2125 }, 2126 #else 2127 {}, 2128 #endif 2129 { /* RXDMA_MONITOR_STATUS */ 2130 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 2131 .max_rings = 0, 2132 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2133 .lmac_ring = TRUE, 2134 .ring_dir = HAL_SRNG_SRC_RING, 2135 /* reg_start is not set because LMAC rings are not accessed 2136 * from host 2137 */ 2138 .reg_start = {}, 2139 .reg_size = {}, 2140 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2141 }, 2142 #ifdef WLAN_PKT_CAPTURE_RX_2_0 2143 { /* RXDMA_MONITOR_DST */ 2144 .start_ring_id = HAL_SRNG_WMAC1_RXMON2SW0, 2145 .max_rings = 2, 2146 .entry_size = sizeof(struct mon_destination_ring) >> 2, 2147 .lmac_ring = TRUE, 2148 .ring_dir = HAL_SRNG_DST_RING, 2149 /* reg_start is not set because LMAC rings are not accessed 2150 * from host 2151 */ 2152 .reg_start = {}, 2153 .reg_size = {}, 2154 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 2155 }, 2156 #else 2157 {}, 2158 #endif 2159 { /* RXDMA_MONITOR_DESC */ 2160 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 2161 .max_rings = 0, 2162 .entry_size = 0/*sizeof(struct sw_monitor_ring) >> 2*/, 2163 .lmac_ring = TRUE, 2164 .ring_dir = HAL_SRNG_DST_RING, 2165 /* reg_start is not set because LMAC rings are not accessed 2166 * from host 2167 */ 2168 .reg_start = {}, 2169 .reg_size = {}, 2170 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 2171 }, 2172 2173 { /* DIR_BUF_RX_DMA_SRC */ 2174 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 2175 /* one ring for spectral and one ring for cfr */ 2176 .max_rings = 2, 2177 .entry_size = 2, 2178 .lmac_ring = TRUE, 2179 .ring_dir = HAL_SRNG_SRC_RING, 2180 /* reg_start is not set because LMAC rings are not accessed 2181 * from host 2182 */ 2183 .reg_start = {}, 2184 .reg_size = {}, 2185 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2186 }, 2187 #ifdef WLAN_FEATURE_CIF_CFR 2188 { /* WIFI_POS_SRC */ 2189 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 2190 .max_rings = 1, 2191 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 2192 .lmac_ring = TRUE, 2193 .ring_dir = HAL_SRNG_SRC_RING, 2194 /* reg_start is not set because LMAC rings are not accessed 2195 * from host 2196 */ 2197 .reg_start = {}, 2198 .reg_size = {}, 2199 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 2200 }, 2201 #endif 2202 { /* REO2PPE */ 2203 .start_ring_id = HAL_SRNG_REO2PPE, 2204 .max_rings = 1, 2205 .entry_size = sizeof(struct reo_destination_ring) >> 2, 2206 .lmac_ring = FALSE, 2207 .ring_dir = HAL_SRNG_DST_RING, 2208 .reg_start = { 2209 HWIO_REO_R0_REO2PPE_RING_BASE_LSB_ADDR( 2210 REO_REG_REG_BASE), 2211 HWIO_REO_R2_REO2PPE_RING_HP_ADDR( 2212 REO_REG_REG_BASE), 2213 }, 2214 /* Single ring - provide ring size if multiple rings of this 2215 * type are supported 2216 */ 2217 .reg_size = {}, 2218 .max_size = 2219 HWIO_REO_R0_REO2PPE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK >> 2220 HWIO_REO_R0_REO2PPE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT, 2221 }, 2222 { /* PPE2TCL */ 2223 .start_ring_id = HAL_SRNG_PPE2TCL1, 2224 .max_rings = 1, 2225 .entry_size = sizeof(struct tcl_entrance_from_ppe_ring) >> 2, 2226 .lmac_ring = FALSE, 2227 .ring_dir = HAL_SRNG_SRC_RING, 2228 .reg_start = { 2229 HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_ADDR( 2230 MAC_TCL_REG_REG_BASE), 2231 HWIO_TCL_R2_PPE2TCL1_RING_HP_ADDR( 2232 MAC_TCL_REG_REG_BASE), 2233 }, 2234 .reg_size = {}, 2235 .max_size = 2236 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 2237 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 2238 }, 2239 { /* PPE_RELEASE */ 2240 .start_ring_id = HAL_SRNG_WBM_PPE_RELEASE, 2241 .max_rings = 1, 2242 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2243 .lmac_ring = FALSE, 2244 .ring_dir = HAL_SRNG_SRC_RING, 2245 }, 2246 #ifdef WLAN_PKT_CAPTURE_TX_2_0 2247 { /* TX_MONITOR_BUF */ 2248 .start_ring_id = HAL_SRNG_SW2TXMON_BUF0, 2249 .max_rings = 1, 2250 .entry_size = sizeof(struct mon_ingress_ring) >> 2, 2251 .lmac_ring = TRUE, 2252 .ring_dir = HAL_SRNG_SRC_RING, 2253 /* reg_start is not set because LMAC rings are not accessed 2254 * from host 2255 */ 2256 .reg_start = {}, 2257 .reg_size = {}, 2258 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 2259 }, 2260 { /* TX_MONITOR_DST */ 2261 .start_ring_id = HAL_SRNG_WMAC1_TXMON2SW0, 2262 .max_rings = 2, 2263 .entry_size = sizeof(struct mon_destination_ring) >> 2, 2264 .lmac_ring = TRUE, 2265 .ring_dir = HAL_SRNG_DST_RING, 2266 /* reg_start is not set because LMAC rings are not accessed 2267 * from host 2268 */ 2269 .reg_start = {}, 2270 .reg_size = {}, 2271 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 2272 }, 2273 #else 2274 {}, 2275 {}, 2276 #endif 2277 { /* SW2RXDMA */ 2278 .start_ring_id = HAL_SRNG_SW2RXDMA_BUF0, 2279 .max_rings = 3, 2280 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2281 .lmac_ring = TRUE, 2282 .ring_dir = HAL_SRNG_SRC_RING, 2283 /* reg_start is not set because LMAC rings are not accessed 2284 * from host 2285 */ 2286 .reg_start = {}, 2287 .reg_size = {}, 2288 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 2289 .dmac_cmn_ring = TRUE, 2290 }, 2291 { /* SW2RXDMA_LINK_RELEASE */ 0}, 2292 }; 2293 2294 /** 2295 * hal_srng_hw_reg_offset_init_qcn6432() - Initialize the HW srng reg offset 2296 * applicable only for qcn6432 2297 * @hal_soc: HAL Soc handle 2298 * 2299 * Return: None 2300 */ 2301 static inline void hal_srng_hw_reg_offset_init_qcn6432(struct hal_soc *hal_soc) 2302 { 2303 int32_t *hw_reg_offset = hal_soc->hal_hw_reg_offset; 2304 2305 hw_reg_offset[DST_MSI2_BASE_LSB] = REG_OFFSET(DST, MSI2_BASE_LSB), 2306 hw_reg_offset[DST_MSI2_BASE_MSB] = REG_OFFSET(DST, MSI2_BASE_MSB), 2307 hw_reg_offset[DST_MSI2_DATA] = REG_OFFSET(DST, MSI2_DATA), 2308 hw_reg_offset[DST_PRODUCER_INT2_SETUP] = 2309 REG_OFFSET(DST, PRODUCER_INT2_SETUP); 2310 } 2311 2312 /* 2313 * hal_reo_config_reo2ppe_dest_info_6432() - Configure reo2ppe dest info 2314 * @hal_soc_hdl: HAL SoC Context 2315 * 2316 * Return: None. 2317 */ 2318 static inline 2319 void hal_reo_config_reo2ppe_dest_info_6432(hal_soc_handle_t hal_soc_hdl) 2320 { 2321 HAL_REG_WRITE((struct hal_soc *)hal_soc_hdl, 2322 HWIO_REO_R0_REO2PPE_DEST_INFO_ADDR(REO_REG_REG_BASE), 2323 REO2PPE_RULE_FAIL_FB); 2324 } 2325 2326 static void hal_hw_txrx_ops_override_qcn6432(struct hal_soc *hal_soc) 2327 { 2328 hal_soc->ops->hal_reo_config_reo2ppe_dest_info = 2329 hal_reo_config_reo2ppe_dest_info_6432; 2330 2331 hal_soc->ops->hal_get_tsf2_scratch_reg = 2332 hal_get_tsf2_scratch_reg_qcn6432; 2333 hal_soc->ops->hal_get_tqm_scratch_reg = 2334 hal_get_tqm_scratch_reg_qcn6432; 2335 } 2336 2337 /** 2338 * hal_qcn6432_attach()- Attach 6432 target specific hal_soc ops, 2339 * offset and srng table 2340 * @hal_soc: hal_soc handle 2341 * 2342 * Return: void 2343 */ 2344 void hal_qcn6432_attach(struct hal_soc *hal_soc) 2345 { 2346 hal_soc->hw_srng_table = hw_srng_table_6432; 2347 2348 hal_srng_hw_reg_offset_init_generic(hal_soc); 2349 hal_srng_hw_reg_offset_init_qcn6432(hal_soc); 2350 2351 hal_hw_txrx_default_ops_attach_be(hal_soc); 2352 hal_hw_txrx_ops_attach_qcn6432(hal_soc); 2353 hal_soc->dmac_cmn_src_rxbuf_ring = true; 2354 if (hal_soc->static_window_map) 2355 hal_write_window_register(hal_soc); 2356 hal_hw_txrx_ops_override_qcn6432(hal_soc); 2357 } 2358