1 /* 2 * Copyright (c) 2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE 16 */ 17 #include "qdf_types.h" 18 #include "qdf_util.h" 19 #include "qdf_mem.h" 20 #include "qdf_nbuf.h" 21 #include "qdf_module.h" 22 23 #include "target_type.h" 24 #include "wcss_version.h" 25 26 #include "hal_be_hw_headers.h" 27 #include "hal_internal.h" 28 #include "hal_api.h" 29 #include "hal_flow.h" 30 #include "rx_flow_search_entry.h" 31 #include "hal_rx_flow_info.h" 32 #include "hal_be_api.h" 33 #include "tcl_entrance_from_ppe_ring.h" 34 #include "sw_monitor_ring.h" 35 #include "wcss_seq_hwioreg_umac.h" 36 #include "wfss_ce_reg_seq_hwioreg.h" 37 #include <uniform_reo_status_header.h> 38 #include <wbm_release_ring_tx.h> 39 #include <phyrx_location.h> 40 #if defined(WLAN_PKT_CAPTURE_TX_2_0) || \ 41 defined(WLAN_PKT_CAPTURE_RX_2_0) 42 #include <mon_ingress_ring.h> 43 #include <mon_destination_ring.h> 44 #endif 45 #include "rx_reo_queue_1k.h" 46 47 #include <hal_be_rx.h> 48 49 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 50 RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 51 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 52 RX_MSDU_LINK_MSDU_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 53 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 54 RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 55 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 56 RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 57 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 58 REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 59 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER \ 60 STATUS_HEADER_REO_STATUS_NUMBER 61 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 62 STATUS_HEADER_TIMESTAMP 63 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 64 RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 65 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 66 RX_MSDU_LINK_MSDU_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 67 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 68 TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 69 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 70 TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 71 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 72 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_OFFSET 73 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 74 BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 75 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 76 BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 77 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 78 BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB 79 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 80 BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK 81 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 82 BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 83 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 84 BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 85 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 86 BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB 87 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 88 BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK 89 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 90 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_LSB 91 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 92 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MASK 93 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 94 WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 95 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 96 WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 97 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 98 WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 99 100 #if defined(WLAN_PKT_CAPTURE_TX_2_0) || defined(WLAN_PKT_CAPTURE_RX_2_0) 101 #include "hal_be_api_mon.h" 102 #endif 103 104 #define CMEM_REG_BASE 0x00100000 105 106 #define CE_WINDOW_ADDRESS_6432 \ 107 ((SOC_WFSS_CE_REG_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) 108 109 #define UMAC_WINDOW_ADDRESS_6432 \ 110 ((UMAC_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) 111 112 #define WINDOW_CONFIGURATION_VALUE_6432 \ 113 ((CE_WINDOW_ADDRESS_6432 << 6) |\ 114 (UMAC_WINDOW_ADDRESS_6432 << 12) | \ 115 WINDOW_ENABLE_BIT) 116 117 /* For Berryllium sw2rxdma ring size increased to 20 bits */ 118 #define HAL_RXDMA_MAX_RING_SIZE_BE 0xFFFFF 119 120 #include "hal_6432_rx.h" 121 #include "hal_6432_tx.h" 122 #include "hal_be_rx_tlv.h" 123 #include <hal_be_generic_api.h> 124 125 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 126 #define PMM_REG_BASE_QCN6432 0xB500FC 127 128 /** 129 * hal_get_link_desc_size_6432(): API to get the link desc size 130 * 131 * Return: uint32_t 132 */ 133 static uint32_t hal_get_link_desc_size_6432(void) 134 { 135 return LINK_DESC_SIZE; 136 } 137 138 /** 139 * hal_rx_get_tlv_6432(): API to get the tlv 140 * 141 * @rx_tlv: TLV data extracted from the rx packet 142 * Return: uint8_t 143 */ 144 static uint8_t hal_rx_get_tlv_6432(void *rx_tlv) 145 { 146 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY, RECEIVE_BANDWIDTH); 147 } 148 149 /** 150 * hal_rx_wbm_err_msdu_continuation_get_6432 () - API to check if WBM 151 * msdu continuation bit is set 152 * 153 *@wbm_desc: wbm release ring descriptor 154 * 155 * Return: true if msdu continuation bit is set. 156 */ 157 uint8_t hal_rx_wbm_err_msdu_continuation_get_6432(void *wbm_desc) 158 { 159 uint32_t comp_desc = *(uint32_t *)(((uint8_t *)wbm_desc) + 160 WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET); 161 162 return (comp_desc & 163 WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK) >> 164 WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB; 165 } 166 167 #if 0 // check this registration for MLO 168 /** 169 * hal_read_pmm_scratch_reg_5332(): API to read PMM Scratch register 170 * 171 * @soc: HAL soc 172 * @reg_enum: Enum of the scratch register 173 * 174 * Return: uint32_t 175 */ 176 static inline 177 uint32_t hal_read_pmm_scratch_reg_5332(struct hal_soc *soc, 178 enum hal_scratch_reg_enum reg_enum) 179 { 180 uint32_t val = 0; 181 void __iomem *bar; 182 183 bar = ioremap_nocache(PMM_SCRATCH_BASE_QCA5332, PMM_SCRATCH_SIZE); 184 pld_reg_read(soc->qdf_dev->dev, (reg_enum * 4), &val, bar); 185 iounmap(bar); 186 return val; 187 } 188 189 /** 190 * hal_get_tsf2_scratch_reg_qca5332(): API to read tsf2 scratch register 191 * 192 * @hal_soc_hdl: HAL soc context 193 * @mac_id: mac id 194 * @value: Pointer to update tsf2 value 195 * 196 * Return: void 197 */ 198 static void hal_get_tsf2_scratch_reg_qca5332(hal_soc_handle_t hal_soc_hdl, 199 uint8_t mac_id, uint64_t *value) 200 { 201 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; 202 uint32_t offset_lo, offset_hi; 203 enum hal_scratch_reg_enum enum_lo, enum_hi; 204 205 hal_get_tsf_enum(DEFAULT_TSF_ID, mac_id, &enum_lo, &enum_hi); 206 207 offset_lo = hal_read_pmm_scratch_reg_5332(soc, enum_lo); 208 209 offset_hi = hal_read_pmm_scratch_reg_5332(soc, enum_hi); 210 211 *value = ((uint64_t)(offset_hi) << 32 | offset_lo); 212 } 213 214 /** 215 * hal_get_tqm_scratch_reg_qca5332(): API to read tqm scratch register 216 * 217 * @hal_soc_hdl: HAL soc context 218 * @value: Pointer to update tqm value 219 * 220 * Return: void 221 */ 222 static void hal_get_tqm_scratch_reg_qca5332(hal_soc_handle_t hal_soc_hdl, 223 uint64_t *value) 224 { 225 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; 226 uint32_t offset_lo, offset_hi; 227 228 offset_lo = hal_read_pmm_scratch_reg_5332(soc, 229 PMM_TQM_CLOCK_OFFSET_LO_US); 230 231 offset_hi = hal_read_pmm_scratch_reg_5332(soc, 232 PMM_TQM_CLOCK_OFFSET_HI_US); 233 234 *value = ((uint64_t)(offset_hi) << 32 | offset_lo); 235 } 236 #endif 237 /** 238 * hal_rx_proc_phyrx_other_receive_info_tlv_6432(): API to get tlv info 239 * 240 * @rx_tlv_hdr: start address of rx_pkt_tlvs 241 * @ppdu_info_hdl: PPDU info handle to fill 242 * 243 * Return: uint32_t 244 */ 245 static inline 246 void hal_rx_proc_phyrx_other_receive_info_tlv_6432(void *rx_tlv_hdr, 247 void *ppdu_info_hdl) 248 { 249 uint32_t tlv_tag, tlv_len; 250 uint32_t temp_len, other_tlv_len, other_tlv_tag; 251 void *rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 252 void *other_tlv_hdr = NULL; 253 void *other_tlv = NULL; 254 255 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 256 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 257 temp_len = 0; 258 259 other_tlv_hdr = rx_tlv + HAL_RX_TLV32_HDR_SIZE; 260 other_tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(other_tlv_hdr); 261 other_tlv_len = HAL_RX_GET_USER_TLV32_LEN(other_tlv_hdr); 262 263 temp_len += other_tlv_len; 264 other_tlv = other_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 265 266 switch (other_tlv_tag) { 267 default: 268 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 269 "%s unhandled TLV type: %d, TLV len:%d", 270 __func__, other_tlv_tag, other_tlv_len); 271 break; 272 } 273 } 274 275 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) 276 static inline 277 void hal_rx_get_bb_info_6432(void *rx_tlv, void *ppdu_info_hdl) 278 { 279 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 280 281 ppdu_info->cfr_info.bb_captured_channel = 282 HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_CHANNEL); 283 284 ppdu_info->cfr_info.bb_captured_timeout = 285 HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_TIMEOUT); 286 287 ppdu_info->cfr_info.bb_captured_reason = 288 HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_REASON); 289 } 290 291 static inline 292 void hal_rx_get_rtt_info_6432(void *rx_tlv, void *ppdu_info_hdl) 293 { 294 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 295 296 ppdu_info->cfr_info.rx_location_info_valid = 297 HAL_RX_GET_64(rx_tlv, PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 298 RX_LOCATION_INFO_VALID); 299 300 ppdu_info->cfr_info.rtt_che_buffer_pointer_low32 = 301 HAL_RX_GET_64(rx_tlv, 302 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 303 RTT_CHE_BUFFER_POINTER_LOW32); 304 305 ppdu_info->cfr_info.rtt_che_buffer_pointer_high8 = 306 HAL_RX_GET_64(rx_tlv, 307 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 308 RTT_CHE_BUFFER_POINTER_HIGH8); 309 310 ppdu_info->cfr_info.chan_capture_status = 311 HAL_GET_RX_LOCATION_INFO_CHAN_CAPTURE_STATUS(rx_tlv); 312 313 ppdu_info->cfr_info.rx_start_ts = 314 HAL_RX_GET_64(rx_tlv, 315 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 316 RX_START_TS); 317 318 ppdu_info->cfr_info.rtt_cfo_measurement = (int16_t) 319 HAL_RX_GET_64(rx_tlv, 320 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 321 RTT_CFO_MEASUREMENT); 322 323 ppdu_info->cfr_info.agc_gain_info0 = 324 HAL_RX_GET_64(rx_tlv, 325 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 326 GAIN_CHAIN0); 327 328 ppdu_info->cfr_info.agc_gain_info0 |= 329 (((uint32_t)HAL_RX_GET_64(rx_tlv, 330 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 331 GAIN_CHAIN1)) << 16); 332 333 ppdu_info->cfr_info.agc_gain_info1 = 334 HAL_RX_GET_64(rx_tlv, 335 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 336 GAIN_CHAIN2); 337 338 ppdu_info->cfr_info.agc_gain_info1 |= 339 (((uint32_t)HAL_RX_GET_64(rx_tlv, 340 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 341 GAIN_CHAIN3)) << 16); 342 343 ppdu_info->cfr_info.agc_gain_info2 = 0; 344 345 ppdu_info->cfr_info.agc_gain_info3 = 0; 346 347 ppdu_info->cfr_info.mcs_rate = 348 HAL_RX_GET_64(rx_tlv, 349 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 350 RTT_MCS_RATE); 351 352 ppdu_info->cfr_info.gi_type = 353 HAL_RX_GET_64(rx_tlv, 354 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 355 RTT_GI_TYPE); 356 } 357 #endif 358 #ifdef CONFIG_WORD_BASED_TLV 359 /** 360 * hal_rx_dump_mpdu_start_tlv_6432() - dump RX mpdu_start TLV in structured 361 * human readable format. 362 * @mpdustart: pointer the rx_attention TLV in pkt. 363 * @dbg_level: log level. 364 * 365 * Return: void 366 */ 367 static inline void hal_rx_dump_mpdu_start_tlv_6432(void *mpdustart, 368 uint8_t dbg_level) 369 { 370 struct rx_mpdu_start_compact *mpdu_info = 371 (struct rx_mpdu_start_compact *)mpdustart; 372 373 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 374 "rx_mpdu_start tlv (1/5) - " 375 "rx_reo_queue_desc_addr_39_32 :%x" 376 "receive_queue_number:%x " 377 "pre_delim_err_warning:%x " 378 "first_delim_err:%x " 379 "pn_31_0:%x " 380 "pn_63_32:%x " 381 "pn_95_64:%x ", 382 mpdu_info->rx_reo_queue_desc_addr_39_32, 383 mpdu_info->receive_queue_number, 384 mpdu_info->pre_delim_err_warning, 385 mpdu_info->first_delim_err, 386 mpdu_info->pn_31_0, 387 mpdu_info->pn_63_32, 388 mpdu_info->pn_95_64); 389 390 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 391 "rx_mpdu_start tlv (2/5) - " 392 "ast_index:%x " 393 "sw_peer_id:%x " 394 "mpdu_frame_control_valid:%x " 395 "mpdu_duration_valid:%x " 396 "mac_addr_ad1_valid:%x " 397 "mac_addr_ad2_valid:%x " 398 "mac_addr_ad3_valid:%x " 399 "mac_addr_ad4_valid:%x " 400 "mpdu_sequence_control_valid :%x" 401 "mpdu_qos_control_valid:%x " 402 "mpdu_ht_control_valid:%x " 403 "frame_encryption_info_valid :%x", 404 mpdu_info->ast_index, 405 mpdu_info->sw_peer_id, 406 mpdu_info->mpdu_frame_control_valid, 407 mpdu_info->mpdu_duration_valid, 408 mpdu_info->mac_addr_ad1_valid, 409 mpdu_info->mac_addr_ad2_valid, 410 mpdu_info->mac_addr_ad3_valid, 411 mpdu_info->mac_addr_ad4_valid, 412 mpdu_info->mpdu_sequence_control_valid, 413 mpdu_info->mpdu_qos_control_valid, 414 mpdu_info->mpdu_ht_control_valid, 415 mpdu_info->frame_encryption_info_valid); 416 417 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 418 "rx_mpdu_start tlv (3/5) - " 419 "mpdu_fragment_number:%x " 420 "more_fragment_flag:%x " 421 "fr_ds:%x " 422 "to_ds:%x " 423 "encrypted:%x " 424 "mpdu_retry:%x " 425 "mpdu_sequence_number:%x ", 426 mpdu_info->mpdu_fragment_number, 427 mpdu_info->more_fragment_flag, 428 mpdu_info->fr_ds, 429 mpdu_info->to_ds, 430 mpdu_info->encrypted, 431 mpdu_info->mpdu_retry, 432 mpdu_info->mpdu_sequence_number); 433 434 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 435 "rx_mpdu_start tlv (4/5) - " 436 "mpdu_frame_control_field:%x " 437 "mpdu_duration_field:%x ", 438 mpdu_info->mpdu_frame_control_field, 439 mpdu_info->mpdu_duration_field); 440 441 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 442 "rx_mpdu_start tlv (5/5) - " 443 "mac_addr_ad1_31_0:%x " 444 "mac_addr_ad1_47_32:%x " 445 "mac_addr_ad2_15_0:%x " 446 "mac_addr_ad2_47_16:%x " 447 "mac_addr_ad3_31_0:%x " 448 "mac_addr_ad3_47_32:%x " 449 "mpdu_sequence_control_field :%x", 450 mpdu_info->mac_addr_ad1_31_0, 451 mpdu_info->mac_addr_ad1_47_32, 452 mpdu_info->mac_addr_ad2_15_0, 453 mpdu_info->mac_addr_ad2_47_16, 454 mpdu_info->mac_addr_ad3_31_0, 455 mpdu_info->mac_addr_ad3_47_32, 456 mpdu_info->mpdu_sequence_control_field); 457 } 458 459 /** 460 * hal_rx_dump_msdu_end_tlv_6432() - dump RX msdu_end TLV in structured 461 * human readable format. 462 * @msduend: pointer the msdu_end TLV in pkt. 463 * @dbg_level: log level. 464 * 465 * Return: void 466 */ 467 static void hal_rx_dump_msdu_end_tlv_6432(void *msduend, 468 uint8_t dbg_level) 469 { 470 struct rx_msdu_end_compact *msdu_end = 471 (struct rx_msdu_end_compact *)msduend; 472 473 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 474 "rx_msdu_end tlv - " 475 "key_id_octet: %d " 476 "tcp_udp_chksum: %d " 477 "sa_idx_timeout: %d " 478 "da_idx_timeout: %d " 479 "msdu_limit_error: %d " 480 "flow_idx_timeout: %d " 481 "flow_idx_invalid: %d " 482 "wifi_parser_error: %d " 483 "sa_is_valid: %d " 484 "da_is_valid: %d " 485 "da_is_mcbc: %d " 486 "tkip_mic_err: %d " 487 "l3_header_padding: %d " 488 "first_msdu: %d " 489 "last_msdu: %d " 490 "sa_idx: %d " 491 "msdu_drop: %d " 492 "reo_destination_indication: %d " 493 "flow_idx: %d " 494 "fse_metadata: %d " 495 "cce_metadata: %d " 496 "sa_sw_peer_id: %d ", 497 msdu_end->key_id_octet, 498 msdu_end->tcp_udp_chksum, 499 msdu_end->sa_idx_timeout, 500 msdu_end->da_idx_timeout, 501 msdu_end->msdu_limit_error, 502 msdu_end->flow_idx_timeout, 503 msdu_end->flow_idx_invalid, 504 msdu_end->wifi_parser_error, 505 msdu_end->sa_is_valid, 506 msdu_end->da_is_valid, 507 msdu_end->da_is_mcbc, 508 msdu_end->tkip_mic_err, 509 msdu_end->l3_header_padding, 510 msdu_end->first_msdu, 511 msdu_end->last_msdu, 512 msdu_end->sa_idx, 513 msdu_end->msdu_drop, 514 msdu_end->reo_destination_indication, 515 msdu_end->flow_idx, 516 msdu_end->fse_metadata, 517 msdu_end->cce_metadata, 518 msdu_end->sa_sw_peer_id); 519 } 520 #else 521 static inline void hal_rx_dump_mpdu_start_tlv_6432(void *mpdustart, 522 uint8_t dbg_level) 523 { 524 struct rx_mpdu_start *mpdu_start = (struct rx_mpdu_start *)mpdustart; 525 struct rx_mpdu_info *mpdu_info = 526 (struct rx_mpdu_info *)&mpdu_start->rx_mpdu_info_details; 527 528 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 529 "rx_mpdu_start tlv (1/5) - " 530 "rx_reo_queue_desc_addr_31_0 :%x" 531 "rx_reo_queue_desc_addr_39_32 :%x" 532 "receive_queue_number:%x " 533 "pre_delim_err_warning:%x " 534 "first_delim_err:%x " 535 "reserved_2a:%x " 536 "pn_31_0:%x " 537 "pn_63_32:%x " 538 "pn_95_64:%x " 539 "pn_127_96:%x " 540 "epd_en:%x " 541 "all_frames_shall_be_encrypted :%x" 542 "encrypt_type:%x " 543 "wep_key_width_for_variable_key :%x" 544 "mesh_sta:%x " 545 "bssid_hit:%x " 546 "bssid_number:%x " 547 "tid:%x " 548 "reserved_7a:%x ", 549 mpdu_info->rx_reo_queue_desc_addr_31_0, 550 mpdu_info->rx_reo_queue_desc_addr_39_32, 551 mpdu_info->receive_queue_number, 552 mpdu_info->pre_delim_err_warning, 553 mpdu_info->first_delim_err, 554 mpdu_info->reserved_2a, 555 mpdu_info->pn_31_0, 556 mpdu_info->pn_63_32, 557 mpdu_info->pn_95_64, 558 mpdu_info->pn_127_96, 559 mpdu_info->epd_en, 560 mpdu_info->all_frames_shall_be_encrypted, 561 mpdu_info->encrypt_type, 562 mpdu_info->wep_key_width_for_variable_key, 563 mpdu_info->mesh_sta, 564 mpdu_info->bssid_hit, 565 mpdu_info->bssid_number, 566 mpdu_info->tid, 567 mpdu_info->reserved_7a); 568 569 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 570 "rx_mpdu_start tlv (2/5) - " 571 "ast_index:%x " 572 "sw_peer_id:%x " 573 "mpdu_frame_control_valid:%x " 574 "mpdu_duration_valid:%x " 575 "mac_addr_ad1_valid:%x " 576 "mac_addr_ad2_valid:%x " 577 "mac_addr_ad3_valid:%x " 578 "mac_addr_ad4_valid:%x " 579 "mpdu_sequence_control_valid :%x" 580 "mpdu_qos_control_valid:%x " 581 "mpdu_ht_control_valid:%x " 582 "frame_encryption_info_valid :%x", 583 mpdu_info->ast_index, 584 mpdu_info->sw_peer_id, 585 mpdu_info->mpdu_frame_control_valid, 586 mpdu_info->mpdu_duration_valid, 587 mpdu_info->mac_addr_ad1_valid, 588 mpdu_info->mac_addr_ad2_valid, 589 mpdu_info->mac_addr_ad3_valid, 590 mpdu_info->mac_addr_ad4_valid, 591 mpdu_info->mpdu_sequence_control_valid, 592 mpdu_info->mpdu_qos_control_valid, 593 mpdu_info->mpdu_ht_control_valid, 594 mpdu_info->frame_encryption_info_valid); 595 596 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 597 "rx_mpdu_start tlv (3/5) - " 598 "mpdu_fragment_number:%x " 599 "more_fragment_flag:%x " 600 "reserved_11a:%x " 601 "fr_ds:%x " 602 "to_ds:%x " 603 "encrypted:%x " 604 "mpdu_retry:%x " 605 "mpdu_sequence_number:%x ", 606 mpdu_info->mpdu_fragment_number, 607 mpdu_info->more_fragment_flag, 608 mpdu_info->reserved_11a, 609 mpdu_info->fr_ds, 610 mpdu_info->to_ds, 611 mpdu_info->encrypted, 612 mpdu_info->mpdu_retry, 613 mpdu_info->mpdu_sequence_number); 614 615 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 616 "rx_mpdu_start tlv (4/5) - " 617 "mpdu_frame_control_field:%x " 618 "mpdu_duration_field:%x ", 619 mpdu_info->mpdu_frame_control_field, 620 mpdu_info->mpdu_duration_field); 621 622 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 623 "rx_mpdu_start tlv (5/5) - " 624 "mac_addr_ad1_31_0:%x " 625 "mac_addr_ad1_47_32:%x " 626 "mac_addr_ad2_15_0:%x " 627 "mac_addr_ad2_47_16:%x " 628 "mac_addr_ad3_31_0:%x " 629 "mac_addr_ad3_47_32:%x " 630 "mpdu_sequence_control_field :%x" 631 "mac_addr_ad4_31_0:%x " 632 "mac_addr_ad4_47_32:%x " 633 "mpdu_qos_control_field:%x ", 634 mpdu_info->mac_addr_ad1_31_0, 635 mpdu_info->mac_addr_ad1_47_32, 636 mpdu_info->mac_addr_ad2_15_0, 637 mpdu_info->mac_addr_ad2_47_16, 638 mpdu_info->mac_addr_ad3_31_0, 639 mpdu_info->mac_addr_ad3_47_32, 640 mpdu_info->mpdu_sequence_control_field, 641 mpdu_info->mac_addr_ad4_31_0, 642 mpdu_info->mac_addr_ad4_47_32, 643 mpdu_info->mpdu_qos_control_field); 644 } 645 646 static void hal_rx_dump_msdu_end_tlv_6432(void *msduend, 647 uint8_t dbg_level) 648 { 649 struct rx_msdu_end *msdu_end = 650 (struct rx_msdu_end *)msduend; 651 652 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 653 "rx_msdu_end tlv - " 654 "key_id_octet: %d " 655 "cce_super_rule: %d " 656 "cce_classify_not_done_truncat: %d " 657 "cce_classify_not_done_cce_dis: %d " 658 "rule_indication_31_0: %d " 659 "tcp_udp_chksum: %d " 660 "sa_idx_timeout: %d " 661 "da_idx_timeout: %d " 662 "msdu_limit_error: %d " 663 "flow_idx_timeout: %d " 664 "flow_idx_invalid: %d " 665 "wifi_parser_error: %d " 666 "sa_is_valid: %d " 667 "da_is_valid: %d " 668 "da_is_mcbc: %d " 669 "tkip_mic_err: %d " 670 "l3_header_padding: %d " 671 "first_msdu: %d " 672 "last_msdu: %d " 673 "sa_idx: %d " 674 "msdu_drop: %d " 675 "reo_destination_indication: %d " 676 "flow_idx: %d " 677 "fse_metadata: %d " 678 "cce_metadata: %d " 679 "sa_sw_peer_id: %d ", 680 msdu_end->key_id_octet, 681 msdu_end->cce_super_rule, 682 msdu_end->cce_classify_not_done_truncate, 683 msdu_end->cce_classify_not_done_cce_dis, 684 msdu_end->rule_indication_31_0, 685 msdu_end->tcp_udp_chksum, 686 msdu_end->sa_idx_timeout, 687 msdu_end->da_idx_timeout, 688 msdu_end->msdu_limit_error, 689 msdu_end->flow_idx_timeout, 690 msdu_end->flow_idx_invalid, 691 msdu_end->wifi_parser_error, 692 msdu_end->sa_is_valid, 693 msdu_end->da_is_valid, 694 msdu_end->da_is_mcbc, 695 msdu_end->tkip_mic_err, 696 msdu_end->l3_header_padding, 697 msdu_end->first_msdu, 698 msdu_end->last_msdu, 699 msdu_end->sa_idx, 700 msdu_end->msdu_drop, 701 msdu_end->reo_destination_indication, 702 msdu_end->flow_idx, 703 msdu_end->fse_metadata, 704 msdu_end->cce_metadata, 705 msdu_end->sa_sw_peer_id); 706 } 707 #endif 708 709 /** 710 * hal_reo_status_get_header_6432() - Process reo desc info 711 * 712 * @ring_desc: Pointer to reo descriptor 713 * @b: tlv type info 714 * @h1: Pointer to hal_reo_status_header where info to be stored 715 * 716 * Return: none. 717 * 718 */ 719 static void hal_reo_status_get_header_6432(hal_ring_desc_t ring_desc, 720 int b, void *h1) 721 { 722 uint64_t *d = (uint64_t *)ring_desc; 723 uint64_t val1 = 0; 724 struct hal_reo_status_header *h = 725 (struct hal_reo_status_header *)h1; 726 727 /* Offsets of descriptor fields defined in HW headers start 728 * from the field after TLV header 729 */ 730 d += HAL_GET_NUM_QWORDS(sizeof(struct tlv_32_hdr)); 731 732 switch (b) { 733 case HAL_REO_QUEUE_STATS_STATUS_TLV: 734 val1 = d[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS, 735 STATUS_HEADER_REO_STATUS_NUMBER)]; 736 break; 737 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 738 val1 = d[HAL_OFFSET_QW(REO_FLUSH_QUEUE_STATUS, 739 STATUS_HEADER_REO_STATUS_NUMBER)]; 740 break; 741 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 742 val1 = d[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS, 743 STATUS_HEADER_REO_STATUS_NUMBER)]; 744 break; 745 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 746 val1 = d[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS, 747 STATUS_HEADER_REO_STATUS_NUMBER)]; 748 break; 749 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 750 val1 = d[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS, 751 STATUS_HEADER_REO_STATUS_NUMBER)]; 752 break; 753 case HAL_REO_DESC_THRES_STATUS_TLV: 754 val1 = 755 d[HAL_OFFSET_QW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS, 756 STATUS_HEADER_REO_STATUS_NUMBER)]; 757 break; 758 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 759 val1 = d[HAL_OFFSET_QW(REO_UPDATE_RX_REO_QUEUE_STATUS, 760 STATUS_HEADER_REO_STATUS_NUMBER)]; 761 break; 762 default: 763 qdf_nofl_err("ERROR: Unknown tlv\n"); 764 break; 765 } 766 h->cmd_num = 767 HAL_GET_FIELD( 768 UNIFORM_REO_STATUS_HEADER, REO_STATUS_NUMBER, 769 val1); 770 h->exec_time = 771 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, 772 CMD_EXECUTION_TIME, val1); 773 h->status = 774 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, 775 REO_CMD_EXECUTION_STATUS, val1); 776 switch (b) { 777 case HAL_REO_QUEUE_STATS_STATUS_TLV: 778 val1 = d[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS, 779 STATUS_HEADER_TIMESTAMP)]; 780 break; 781 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 782 val1 = d[HAL_OFFSET_QW(REO_FLUSH_QUEUE_STATUS, 783 STATUS_HEADER_TIMESTAMP)]; 784 break; 785 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 786 val1 = d[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS, 787 STATUS_HEADER_TIMESTAMP)]; 788 break; 789 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 790 val1 = d[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS, 791 STATUS_HEADER_TIMESTAMP)]; 792 break; 793 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 794 val1 = d[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS, 795 STATUS_HEADER_TIMESTAMP)]; 796 break; 797 case HAL_REO_DESC_THRES_STATUS_TLV: 798 val1 = 799 d[HAL_OFFSET_QW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS, 800 STATUS_HEADER_TIMESTAMP)]; 801 break; 802 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 803 val1 = d[HAL_OFFSET_QW(REO_UPDATE_RX_REO_QUEUE_STATUS, 804 STATUS_HEADER_TIMESTAMP)]; 805 break; 806 default: 807 qdf_nofl_err("ERROR: Unknown tlv\n"); 808 break; 809 } 810 h->tstamp = 811 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, TIMESTAMP, val1); 812 } 813 814 static 815 void *hal_rx_msdu0_buffer_addr_lsb_6432(void *link_desc_va) 816 { 817 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 818 } 819 820 static 821 void *hal_rx_msdu_desc_info_ptr_get_6432(void *msdu0) 822 { 823 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 824 } 825 826 static 827 void *hal_ent_mpdu_desc_info_6432(void *ent_ring_desc) 828 { 829 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 830 } 831 832 static 833 void *hal_dst_mpdu_desc_info_6432(void *dst_ring_desc) 834 { 835 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 836 } 837 838 /** 839 * hal_reo_config_6432(): Set reo config parameters 840 * @soc: hal soc handle 841 * @reg_val: value to be set 842 * @reo_params: reo parameters 843 * 844 * Return: void 845 */ 846 static void 847 hal_reo_config_6432(struct hal_soc *soc, 848 uint32_t reg_val, 849 struct hal_reo_params *reo_params) 850 { 851 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 852 } 853 854 /** 855 * hal_rx_msdu_desc_info_get_ptr_6432() - Get msdu desc info ptr 856 * @msdu_details_ptr: Pointer to msdu_details_ptr 857 * 858 * Return: Pointer to rx_msdu_desc_info structure. 859 * 860 */ 861 static void *hal_rx_msdu_desc_info_get_ptr_6432(void *msdu_details_ptr) 862 { 863 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 864 } 865 866 /** 867 * hal_rx_link_desc_msdu0_ptr_6432 - Get pointer to rx_msdu details 868 * @link_desc: Pointer to link desc 869 * 870 * Return: Pointer to rx_msdu_details structure 871 * 872 */ 873 static void *hal_rx_link_desc_msdu0_ptr_6432(void *link_desc) 874 { 875 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 876 } 877 878 /** 879 * hal_get_window_address_6432(): Function to get hp/tp address 880 * @hal_soc: Pointer to hal_soc 881 * @addr: address offset of register 882 * 883 * Return: modified address offset of register 884 */ 885 886 static inline qdf_iomem_t hal_get_window_address_6432(struct hal_soc *hal_soc, 887 qdf_iomem_t addr) 888 { 889 uint32_t offset = addr - hal_soc->dev_base_addr; 890 qdf_iomem_t new_offset; 891 892 /* 893 * If offset lies within DP register range, use 3rd window to write 894 * into DP region. 895 */ 896 if ((offset ^ UMAC_BASE) < WINDOW_RANGE_MASK) { 897 new_offset = (hal_soc->dev_base_addr + (3 * WINDOW_START) + 898 (offset & WINDOW_RANGE_MASK)); 899 /* 900 * If offset lies within CE register range, use 2nd window to write 901 * into CE region. 902 */ 903 } else if ((offset ^ SOC_WFSS_CE_REG_BASE) < WINDOW_RANGE_MASK) { 904 new_offset = (hal_soc->dev_base_addr + (2 * WINDOW_START) + 905 (offset & WINDOW_RANGE_MASK)); 906 } else { 907 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 908 "%s: ERROR: Accessing Wrong register\n", __func__); 909 qdf_assert_always(0); 910 return 0; 911 } 912 return new_offset; 913 } 914 915 static inline void hal_write_window_register(struct hal_soc *hal_soc) 916 { 917 /* Write value into window configuration register */ 918 qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_REG_ADDRESS, 919 WINDOW_CONFIGURATION_VALUE_6432); 920 } 921 922 static 923 void hal_compute_reo_remap_ix2_ix3_6432(uint32_t *ring, uint32_t num_rings, 924 uint32_t *remap1, uint32_t *remap2) 925 { 926 switch (num_rings) { 927 case 1: 928 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 929 HAL_REO_REMAP_IX2(ring[0], 17) | 930 HAL_REO_REMAP_IX2(ring[0], 18) | 931 HAL_REO_REMAP_IX2(ring[0], 19) | 932 HAL_REO_REMAP_IX2(ring[0], 20) | 933 HAL_REO_REMAP_IX2(ring[0], 21) | 934 HAL_REO_REMAP_IX2(ring[0], 22) | 935 HAL_REO_REMAP_IX2(ring[0], 23); 936 937 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 938 HAL_REO_REMAP_IX3(ring[0], 25) | 939 HAL_REO_REMAP_IX3(ring[0], 26) | 940 HAL_REO_REMAP_IX3(ring[0], 27) | 941 HAL_REO_REMAP_IX3(ring[0], 28) | 942 HAL_REO_REMAP_IX3(ring[0], 29) | 943 HAL_REO_REMAP_IX3(ring[0], 30) | 944 HAL_REO_REMAP_IX3(ring[0], 31); 945 break; 946 case 2: 947 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 948 HAL_REO_REMAP_IX2(ring[0], 17) | 949 HAL_REO_REMAP_IX2(ring[1], 18) | 950 HAL_REO_REMAP_IX2(ring[1], 19) | 951 HAL_REO_REMAP_IX2(ring[0], 20) | 952 HAL_REO_REMAP_IX2(ring[0], 21) | 953 HAL_REO_REMAP_IX2(ring[1], 22) | 954 HAL_REO_REMAP_IX2(ring[1], 23); 955 956 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 957 HAL_REO_REMAP_IX3(ring[0], 25) | 958 HAL_REO_REMAP_IX3(ring[1], 26) | 959 HAL_REO_REMAP_IX3(ring[1], 27) | 960 HAL_REO_REMAP_IX3(ring[0], 28) | 961 HAL_REO_REMAP_IX3(ring[0], 29) | 962 HAL_REO_REMAP_IX3(ring[1], 30) | 963 HAL_REO_REMAP_IX3(ring[1], 31); 964 break; 965 case 3: 966 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 967 HAL_REO_REMAP_IX2(ring[1], 17) | 968 HAL_REO_REMAP_IX2(ring[2], 18) | 969 HAL_REO_REMAP_IX2(ring[0], 19) | 970 HAL_REO_REMAP_IX2(ring[1], 20) | 971 HAL_REO_REMAP_IX2(ring[2], 21) | 972 HAL_REO_REMAP_IX2(ring[0], 22) | 973 HAL_REO_REMAP_IX2(ring[1], 23); 974 975 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) | 976 HAL_REO_REMAP_IX3(ring[0], 25) | 977 HAL_REO_REMAP_IX3(ring[1], 26) | 978 HAL_REO_REMAP_IX3(ring[2], 27) | 979 HAL_REO_REMAP_IX3(ring[0], 28) | 980 HAL_REO_REMAP_IX3(ring[1], 29) | 981 HAL_REO_REMAP_IX3(ring[2], 30) | 982 HAL_REO_REMAP_IX3(ring[0], 31); 983 break; 984 case 4: 985 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 986 HAL_REO_REMAP_IX2(ring[1], 17) | 987 HAL_REO_REMAP_IX2(ring[2], 18) | 988 HAL_REO_REMAP_IX2(ring[3], 19) | 989 HAL_REO_REMAP_IX2(ring[0], 20) | 990 HAL_REO_REMAP_IX2(ring[1], 21) | 991 HAL_REO_REMAP_IX2(ring[2], 22) | 992 HAL_REO_REMAP_IX2(ring[3], 23); 993 994 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 995 HAL_REO_REMAP_IX3(ring[1], 25) | 996 HAL_REO_REMAP_IX3(ring[2], 26) | 997 HAL_REO_REMAP_IX3(ring[3], 27) | 998 HAL_REO_REMAP_IX3(ring[0], 28) | 999 HAL_REO_REMAP_IX3(ring[1], 29) | 1000 HAL_REO_REMAP_IX3(ring[2], 30) | 1001 HAL_REO_REMAP_IX3(ring[3], 31); 1002 break; 1003 } 1004 } 1005 1006 /** 1007 * hal_rx_flow_setup_fse_6432() - Setup a flow search entry in HW FST 1008 * @rx_fst: Pointer to the Rx Flow Search Table 1009 * @table_offset: offset into the table where the flow is to be setup 1010 * @rx_flow: Flow Parameters 1011 * 1012 * Return: Success/Failure 1013 */ 1014 static void * 1015 hal_rx_flow_setup_fse_6432(uint8_t *rx_fst, uint32_t table_offset, 1016 uint8_t *rx_flow) 1017 { 1018 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 1019 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 1020 uint8_t *fse; 1021 bool fse_valid; 1022 1023 if (table_offset >= fst->max_entries) { 1024 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 1025 "HAL FSE table offset %u exceeds max entries %u", 1026 table_offset, fst->max_entries); 1027 return NULL; 1028 } 1029 1030 fse = (uint8_t *)fst->base_vaddr + 1031 (table_offset * HAL_RX_FST_ENTRY_SIZE); 1032 1033 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID); 1034 1035 if (fse_valid) { 1036 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 1037 "HAL FSE %pK already valid", fse); 1038 return NULL; 1039 } 1040 1041 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96) = 1042 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96, 1043 qdf_htonl(flow->tuple_info.src_ip_127_96)); 1044 1045 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64) = 1046 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64, 1047 qdf_htonl(flow->tuple_info.src_ip_95_64)); 1048 1049 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32) = 1050 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32, 1051 qdf_htonl(flow->tuple_info.src_ip_63_32)); 1052 1053 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0) = 1054 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0, 1055 qdf_htonl(flow->tuple_info.src_ip_31_0)); 1056 1057 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96) = 1058 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96, 1059 qdf_htonl(flow->tuple_info.dest_ip_127_96)); 1060 1061 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64) = 1062 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64, 1063 qdf_htonl(flow->tuple_info.dest_ip_95_64)); 1064 1065 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32) = 1066 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32, 1067 qdf_htonl(flow->tuple_info.dest_ip_63_32)); 1068 1069 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0) = 1070 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0, 1071 qdf_htonl(flow->tuple_info.dest_ip_31_0)); 1072 1073 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_PORT); 1074 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_PORT) |= 1075 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_PORT, 1076 (flow->tuple_info.dest_port)); 1077 1078 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_PORT); 1079 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_PORT) |= 1080 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_PORT, 1081 (flow->tuple_info.src_port)); 1082 1083 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL); 1084 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL) |= 1085 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL, 1086 flow->tuple_info.l4_protocol); 1087 1088 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, USE_PPE); 1089 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, USE_PPE) |= 1090 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, USE_PPE, flow->use_ppe_ds); 1091 1092 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, PRIORITY_VALID); 1093 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, PRIORITY_VALID) |= 1094 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, PRIORITY_VALID, 1095 flow->priority_vld); 1096 1097 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, SERVICE_CODE); 1098 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SERVICE_CODE) |= 1099 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SERVICE_CODE, 1100 flow->service_code); 1101 1102 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER); 1103 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER) |= 1104 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER, 1105 flow->reo_destination_handler); 1106 1107 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID); 1108 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID) |= 1109 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, VALID, 1); 1110 1111 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, METADATA); 1112 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, METADATA) = 1113 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, METADATA, 1114 flow->fse_metadata); 1115 1116 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_INDICATION); 1117 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_INDICATION) |= 1118 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, 1119 REO_DESTINATION_INDICATION, 1120 flow->reo_destination_indication); 1121 1122 /* Reset all the other fields in FSE */ 1123 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, RESERVED_9); 1124 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_DROP); 1125 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_COUNT); 1126 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_BYTE_COUNT); 1127 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, TIMESTAMP); 1128 1129 return fse; 1130 } 1131 1132 #ifndef NO_RX_PKT_HDR_TLV 1133 /** 1134 * hal_rx_dump_pkt_hdr_tlv_6432(): dump RX pkt header TLV in hex format 1135 * @pkt_tlvs: pointer the pkt_hdr_tlv in pkt. 1136 * @dbg_level: log level. 1137 * 1138 * Return: void 1139 */ 1140 static inline void hal_rx_dump_pkt_hdr_tlv_6432(struct rx_pkt_tlvs *pkt_tlvs, 1141 uint8_t dbg_level) 1142 { 1143 struct rx_pkt_hdr_tlv *pkt_hdr_tlv = &pkt_tlvs->pkt_hdr_tlv; 1144 1145 hal_verbose_debug("\n---------------\n" 1146 "rx_pkt_hdr_tlv\n" 1147 "---------------\n" 1148 "phy_ppdu_id 0x%x ", 1149 pkt_hdr_tlv->phy_ppdu_id); 1150 1151 hal_verbose_hex_dump(pkt_hdr_tlv->rx_pkt_hdr, 1152 sizeof(pkt_hdr_tlv->rx_pkt_hdr)); 1153 } 1154 #else 1155 /** 1156 * hal_rx_dump_pkt_hdr_tlv_6432(): dump RX pkt header TLV in hex format 1157 * @pkt_tlvs: pointer the pkt_hdr_tlv in pkt. 1158 * @dbg_level: log level. 1159 * 1160 * Return: void 1161 */ 1162 static inline void hal_rx_dump_pkt_hdr_tlv_6432(struct rx_pkt_tlvs *pkt_tlvs, 1163 uint8_t dbg_level) 1164 { 1165 } 1166 #endif 1167 1168 /** 1169 * hal_rx_dump_pkt_tlvs_6432(): API to print RX Pkt TLVS qcn6432 1170 * @hal_soc_hdl: hal_soc handle 1171 * @buf: pointer the pkt buffer 1172 * @dbg_level: log level 1173 * 1174 * Return: void 1175 */ 1176 #ifdef CONFIG_WORD_BASED_TLV 1177 static void hal_rx_dump_pkt_tlvs_6432(hal_soc_handle_t hal_soc_hdl, 1178 uint8_t *buf, uint8_t dbg_level) 1179 { 1180 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1181 struct rx_msdu_end_compact *msdu_end = 1182 &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1183 struct rx_mpdu_start_compact *mpdu_start = 1184 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1185 1186 hal_rx_dump_msdu_end_tlv_6432(msdu_end, dbg_level); 1187 hal_rx_dump_mpdu_start_tlv_6432(mpdu_start, dbg_level); 1188 hal_rx_dump_pkt_hdr_tlv_6432(pkt_tlvs, dbg_level); 1189 } 1190 #else 1191 static void hal_rx_dump_pkt_tlvs_6432(hal_soc_handle_t hal_soc_hdl, 1192 uint8_t *buf, uint8_t dbg_level) 1193 { 1194 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1195 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1196 struct rx_mpdu_start *mpdu_start = 1197 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1198 1199 hal_rx_dump_msdu_end_tlv_6432(msdu_end, dbg_level); 1200 hal_rx_dump_mpdu_start_tlv_6432(mpdu_start, dbg_level); 1201 hal_rx_dump_pkt_hdr_tlv_6432(pkt_tlvs, dbg_level); 1202 } 1203 #endif 1204 1205 #define HAL_NUM_TCL_BANKS_6432 24 1206 1207 /** 1208 * hal_cmem_write_6432() - function for CMEM buffer writing 1209 * @hal_soc_hdl: HAL SOC handle 1210 * @offset: CMEM address 1211 * @value: value to write 1212 * 1213 * Return: None. 1214 */ 1215 static void hal_cmem_write_6432(hal_soc_handle_t hal_soc_hdl, 1216 uint32_t offset, 1217 uint32_t value) 1218 { 1219 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 1220 1221 pld_reg_write(hal->qdf_dev->dev, offset, value, 1222 hal->dev_base_addr_cmem); 1223 } 1224 1225 /** 1226 * hal_tx_get_num_tcl_banks_6432() - Get number of banks in target 1227 * 1228 * Returns: number of bank 1229 */ 1230 static uint8_t hal_tx_get_num_tcl_banks_6432(void) 1231 { 1232 return HAL_NUM_TCL_BANKS_6432; 1233 } 1234 1235 static 1236 void hal_compute_reo_remap_ix0_6432(struct hal_soc *soc) 1237 { 1238 uint32_t remap0; 1239 1240 remap0 = HAL_REG_READ(soc, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR 1241 (REO_REG_REG_BASE)); 1242 1243 remap0 &= ~(HAL_REO_REMAP_IX0(0xF, 6)); 1244 remap0 |= HAL_REO_REMAP_IX0(REO2PPE_DST_RING, 6); 1245 1246 HAL_REG_WRITE(soc, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR 1247 (REO_REG_REG_BASE), remap0); 1248 1249 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR 0x%x", 1250 HAL_REG_READ(soc, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR 1251 (REO_REG_REG_BASE))); 1252 } 1253 1254 static void hal_reo_setup_6432(struct hal_soc *soc, void *reoparams, 1255 int qref_reset) 1256 { 1257 uint32_t reg_val; 1258 struct hal_reo_params *reo_params = (struct hal_reo_params *)reoparams; 1259 1260 reg_val = HAL_REG_READ(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR( 1261 REO_REG_REG_BASE)); 1262 1263 hal_reo_config_6432(soc, reg_val, reo_params); 1264 /* Other ring enable bits and REO_ENABLE will be set by FW */ 1265 1266 /* TODO: Setup destination ring mapping if enabled */ 1267 1268 /* TODO: Error destination ring setting is left to default. 1269 * Default setting is to send all errors to release ring. 1270 */ 1271 1272 /* Set the reo descriptor swap bits in case of BIG endian platform */ 1273 hal_setup_reo_swap(soc); 1274 1275 HAL_REG_WRITE(soc, 1276 HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(REO_REG_REG_BASE), 1277 HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000); 1278 1279 HAL_REG_WRITE(soc, 1280 HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(REO_REG_REG_BASE), 1281 (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000)); 1282 1283 HAL_REG_WRITE(soc, 1284 HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(REO_REG_REG_BASE), 1285 (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000)); 1286 1287 HAL_REG_WRITE(soc, 1288 HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(REO_REG_REG_BASE), 1289 (HAL_DEFAULT_VO_REO_TIMEOUT_MS * 1000)); 1290 1291 /* 1292 * When hash based routing is enabled, routing of the rx packet 1293 * is done based on the following value: 1 _ _ _ _ The last 4 1294 * bits are based on hash[3:0]. This means the possible values 1295 * are 0x10 to 0x1f. This value is used to look-up the 1296 * ring ID configured in Destination_Ring_Ctrl_IX_* register. 1297 * The Destination_Ring_Ctrl_IX_2 and Destination_Ring_Ctrl_IX_3 1298 * registers need to be configured to set-up the 16 entries to 1299 * map the hash values to a ring number. There are 3 bits per 1300 * hash entry which are mapped as follows: 1301 * 0: TCL, 1:SW1, 2:SW2, * 3:SW3, 4:SW4, 5:Release, 6:FW(WIFI), 1302 * 7: NOT_USED. 1303 */ 1304 if (reo_params->rx_hash_enabled) { 1305 hal_compute_reo_remap_ix0_6432(soc); 1306 HAL_REG_WRITE(soc, 1307 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR 1308 (REO_REG_REG_BASE), reo_params->remap0); 1309 1310 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x", 1311 HAL_REG_READ(soc, 1312 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR( 1313 REO_REG_REG_BASE))); 1314 1315 HAL_REG_WRITE(soc, 1316 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 1317 (REO_REG_REG_BASE), reo_params->remap1); 1318 1319 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x", 1320 HAL_REG_READ(soc, 1321 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR( 1322 REO_REG_REG_BASE))); 1323 1324 HAL_REG_WRITE(soc, 1325 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 1326 (REO_REG_REG_BASE), reo_params->remap2); 1327 1328 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 0x%x", 1329 HAL_REG_READ(soc, 1330 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR( 1331 REO_REG_REG_BASE))); 1332 } 1333 1334 /* TODO: Check if the following registers shoould be setup by host: 1335 * AGING_CONTROL 1336 * HIGH_MEMORY_THRESHOLD 1337 * GLOBAL_LINK_DESC_COUNT_THRESH_IX_0[1,2] 1338 * GLOBAL_LINK_DESC_COUNT_CTRL 1339 */ 1340 1341 soc->reo_qref = *reo_params->reo_qref; 1342 hal_reo_shared_qaddr_init((hal_soc_handle_t)soc, qref_reset); 1343 } 1344 1345 static uint16_t hal_get_rx_max_ba_window_qcn6432(int tid) 1346 { 1347 return HAL_RX_BA_WINDOW_1024; 1348 } 1349 1350 /** 1351 * hal_qcn6432_get_reo_qdesc_size()- Get the reo queue descriptor size 1352 * from the give Block-Ack window size 1353 * @ba_window_size: Block-Ack window size 1354 * @tid: TID 1355 * 1356 * Return: reo queue descriptor size 1357 */ 1358 static uint32_t hal_qcn6432_get_reo_qdesc_size(uint32_t ba_window_size, int tid) 1359 { 1360 /* Hardcode the ba_window_size to HAL_RX_MAX_BA_WINDOW for 1361 * NON_QOS_TID until HW issues are resolved. 1362 */ 1363 if (tid != HAL_NON_QOS_TID) 1364 ba_window_size = hal_get_rx_max_ba_window_qcn6432(tid); 1365 1366 /* Return descriptor size corresponding to window size of 2 since 1367 * we set ba_window_size to 2 while setting up REO descriptors as 1368 * a WAR to get 2k jump exception aggregates are received without 1369 * a BA session. 1370 */ 1371 if (ba_window_size <= 1) { 1372 if (tid != HAL_NON_QOS_TID) 1373 return sizeof(struct rx_reo_queue) + 1374 sizeof(struct rx_reo_queue_ext); 1375 else 1376 return sizeof(struct rx_reo_queue); 1377 } 1378 1379 if (ba_window_size <= 105) 1380 return sizeof(struct rx_reo_queue) + 1381 sizeof(struct rx_reo_queue_ext); 1382 1383 if (ba_window_size <= 210) 1384 return sizeof(struct rx_reo_queue) + 1385 (2 * sizeof(struct rx_reo_queue_ext)); 1386 1387 if (ba_window_size <= 256) 1388 return sizeof(struct rx_reo_queue) + 1389 (3 * sizeof(struct rx_reo_queue_ext)); 1390 1391 return sizeof(struct rx_reo_queue) + 1392 (10 * sizeof(struct rx_reo_queue_ext)) + 1393 sizeof(struct rx_reo_queue_1k); 1394 } 1395 /** 1396 * hal_rx_tlv_msdu_done_copy_get_6432() - Get msdu done copy bit from rx_tlv 1397 * 1398 * @buf: pointer the tx_tlv 1399 * 1400 * Returns: msdu done copy bit 1401 */ 1402 static inline uint32_t hal_rx_tlv_msdu_done_copy_get_6432(uint8_t *buf) 1403 { 1404 return HAL_RX_TLV_MSDU_DONE_COPY_GET(buf); 1405 } 1406 1407 /** 1408 * hal_read_pmm_scratch_reg_6432(): API to read PMM Scratch register 1409 * 1410 * @soc: HAL soc 1411 * @base_addr: BAR address 1412 * @reg_enum: Enum of the scratch register 1413 * 1414 * Return: uint32_t 1415 */ 1416 static inline 1417 uint32_t hal_read_pmm_scratch_reg_6432(struct hal_soc *soc, 1418 uint32_t base_addr, 1419 enum hal_scratch_reg_enum reg_enum) 1420 { 1421 uint32_t val = 0; 1422 1423 pld_reg_read(soc->qdf_dev->dev, base_addr + (reg_enum * 4), &val, NULL); 1424 return val; 1425 } 1426 1427 /** 1428 * hal_get_tsf2_scratch_reg_qcn6432(): API to read tsf2 scratch register 1429 * 1430 * @hal_soc_hdl: HAL soc context 1431 * @mac_id: mac id 1432 * @value: Pointer to update tsf2 value 1433 * 1434 * Return: void 1435 */ 1436 static void hal_get_tsf2_scratch_reg_qcn6432(hal_soc_handle_t hal_soc_hdl, 1437 uint8_t mac_id, uint64_t *value) 1438 { 1439 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; 1440 uint32_t offset_lo, offset_hi; 1441 enum hal_scratch_reg_enum enum_lo, enum_hi; 1442 1443 hal_get_tsf_enum(DEFAULT_TSF_ID, mac_id, &enum_lo, &enum_hi); 1444 1445 offset_lo = hal_read_pmm_scratch_reg_6432(soc, 1446 PMM_REG_BASE_QCN6432, 1447 enum_lo); 1448 1449 offset_hi = hal_read_pmm_scratch_reg_6432(soc, 1450 PMM_REG_BASE_QCN6432, 1451 enum_hi); 1452 1453 *value = ((uint64_t)(offset_hi) << 32 | offset_lo); 1454 } 1455 1456 /** 1457 * hal_get_tqm_scratch_reg_qcn6432(): API to read tqm scratch register 1458 * 1459 * @hal_soc_hdl: HAL soc context 1460 * @value: Pointer to update tqm value 1461 * 1462 * Return: void 1463 */ 1464 1465 static void hal_get_tqm_scratch_reg_qcn6432(hal_soc_handle_t hal_soc_hdl, 1466 uint64_t *value) 1467 { 1468 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; 1469 uint32_t offset_lo, offset_hi; 1470 1471 offset_lo = hal_read_pmm_scratch_reg_6432(soc, 1472 PMM_REG_BASE_QCN6432, 1473 PMM_TQM_CLOCK_OFFSET_LO_US); 1474 1475 offset_hi = hal_read_pmm_scratch_reg_6432(soc, 1476 PMM_REG_BASE_QCN6432, 1477 PMM_TQM_CLOCK_OFFSET_HI_US); 1478 1479 *value = ((uint64_t)(offset_hi) << 32 | offset_lo); 1480 } 1481 1482 static void hal_hw_txrx_ops_attach_qcn6432(struct hal_soc *hal_soc) 1483 { 1484 /* init and setup */ 1485 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic; 1486 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic; 1487 hal_soc->ops->hal_srng_hw_disable = hal_srng_hw_disable_generic; 1488 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic; 1489 hal_soc->ops->hal_get_window_address = hal_get_window_address_6432; 1490 hal_soc->ops->hal_cmem_write = hal_cmem_write_6432; 1491 1492 /* tx */ 1493 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_6432; 1494 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_6432; 1495 hal_soc->ops->hal_tx_comp_get_status = 1496 hal_tx_comp_get_status_generic_be; 1497 hal_soc->ops->hal_tx_init_cmd_credit_ring = 1498 hal_tx_init_cmd_credit_ring_6432; 1499 hal_soc->ops->hal_tx_set_ppe_cmn_cfg = hal_tx_set_ppe_cmn_config_6432; 1500 hal_soc->ops->hal_tx_set_ppe_vp_entry = hal_tx_set_ppe_vp_entry_6432; 1501 hal_soc->ops->hal_ppeds_cfg_ast_override_map_reg = 1502 hal_ppeds_cfg_ast_override_map_reg_6432; 1503 hal_soc->ops->hal_tx_set_ppe_pri2tid = hal_tx_set_ppe_pri2tid_map_6432; 1504 hal_soc->ops->hal_tx_update_ppe_pri2tid = 1505 hal_tx_update_ppe_pri2tid_6432; 1506 hal_soc->ops->hal_tx_dump_ppe_vp_entry = hal_tx_dump_ppe_vp_entry_6432; 1507 hal_soc->ops->hal_tx_get_num_ppe_vp_tbl_entries = 1508 hal_tx_get_num_ppe_vp_tbl_entries_6432; 1509 hal_soc->ops->hal_tx_enable_pri2tid_map = 1510 hal_tx_enable_pri2tid_map_6432; 1511 hal_soc->ops->hal_tx_config_rbm_mapping_be = 1512 hal_tx_config_rbm_mapping_be_6432; 1513 1514 /* rx */ 1515 hal_soc->ops->hal_rx_msdu_start_nss_get = hal_rx_tlv_nss_get_be; 1516 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status = 1517 hal_rx_mon_hw_desc_get_mpdu_status_be; 1518 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_6432; 1519 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv = 1520 hal_rx_proc_phyrx_other_receive_info_tlv_6432; 1521 1522 hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_6432; 1523 hal_soc->ops->hal_rx_dump_mpdu_start_tlv = 1524 hal_rx_dump_mpdu_start_tlv_6432; 1525 hal_soc->ops->hal_rx_dump_pkt_tlvs = hal_rx_dump_pkt_tlvs_6432; 1526 1527 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_6432; 1528 hal_soc->ops->hal_rx_mpdu_start_tid_get = hal_rx_tlv_tid_get_be; 1529 hal_soc->ops->hal_rx_msdu_start_reception_type_get = 1530 hal_rx_tlv_reception_type_get_be; 1531 hal_soc->ops->hal_rx_msdu_end_da_idx_get = 1532 hal_rx_msdu_end_da_idx_get_be; 1533 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = 1534 hal_rx_msdu_desc_info_get_ptr_6432; 1535 hal_soc->ops->hal_rx_link_desc_msdu0_ptr = 1536 hal_rx_link_desc_msdu0_ptr_6432; 1537 hal_soc->ops->hal_reo_status_get_header = 1538 hal_reo_status_get_header_6432; 1539 #ifdef WLAN_PKT_CAPTURE_RX_2_0 1540 hal_soc->ops->hal_rx_status_get_tlv_info = 1541 hal_rx_status_get_tlv_info_wrapper_be; 1542 #endif 1543 hal_soc->ops->hal_rx_wbm_err_info_get = 1544 hal_rx_wbm_err_info_get_generic_be; 1545 hal_soc->ops->hal_tx_set_pcp_tid_map = 1546 hal_tx_set_pcp_tid_map_generic_be; 1547 hal_soc->ops->hal_tx_update_pcp_tid_map = 1548 hal_tx_update_pcp_tid_generic_be; 1549 hal_soc->ops->hal_tx_set_tidmap_prty = 1550 hal_tx_update_tidmap_prty_generic_be; 1551 hal_soc->ops->hal_rx_get_rx_fragment_number = 1552 hal_rx_get_rx_fragment_number_be, 1553 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = 1554 hal_rx_tlv_da_is_mcbc_get_be; 1555 hal_soc->ops->hal_rx_msdu_end_is_tkip_mic_err = 1556 hal_rx_tlv_is_tkip_mic_err_get_be; 1557 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = 1558 hal_rx_tlv_sa_is_valid_get_be; 1559 hal_soc->ops->hal_rx_msdu_end_sa_idx_get = hal_rx_tlv_sa_idx_get_be; 1560 hal_soc->ops->hal_rx_desc_is_first_msdu = hal_rx_desc_is_first_msdu_be; 1561 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get = 1562 hal_rx_tlv_l3_hdr_padding_get_be; 1563 hal_soc->ops->hal_rx_encryption_info_valid = 1564 hal_rx_encryption_info_valid_be; 1565 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_be; 1566 hal_soc->ops->hal_rx_msdu_end_first_msdu_get = 1567 hal_rx_tlv_first_msdu_get_be; 1568 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = 1569 hal_rx_tlv_da_is_valid_get_be; 1570 hal_soc->ops->hal_rx_msdu_end_last_msdu_get = 1571 hal_rx_tlv_last_msdu_get_be; 1572 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = 1573 hal_rx_get_mpdu_mac_ad4_valid_be; 1574 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get = 1575 hal_rx_mpdu_start_sw_peer_id_get_be; 1576 hal_soc->ops->hal_rx_tlv_peer_meta_data_get = 1577 hal_rx_msdu_peer_meta_data_get_be; 1578 #ifndef CONFIG_WORD_BASED_TLV 1579 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_be; 1580 hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get = 1581 hal_rx_mpdu_info_ampdu_flag_get_be; 1582 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = 1583 hal_rx_hw_desc_get_ppduid_get_be; 1584 hal_soc->ops->hal_rx_tlv_phy_ppdu_id_get = 1585 hal_rx_attn_phy_ppdu_id_get_be; 1586 hal_soc->ops->hal_rx_get_filter_category = 1587 hal_rx_get_filter_category_be; 1588 #endif 1589 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_be; 1590 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_be; 1591 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_be; 1592 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid = 1593 hal_rx_get_mpdu_frame_control_valid_be; 1594 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_be; 1595 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_be; 1596 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_be; 1597 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid = 1598 hal_rx_get_mpdu_sequence_control_valid_be; 1599 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_be; 1600 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_be; 1601 hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get = 1602 hal_rx_mpdu_start_mpdu_qos_control_valid_get_be; 1603 hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get = 1604 hal_rx_msdu_end_sa_sw_peer_id_get_be; 1605 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = 1606 hal_rx_msdu0_buffer_addr_lsb_6432; 1607 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = 1608 hal_rx_msdu_desc_info_ptr_get_6432; 1609 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_6432; 1610 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_6432; 1611 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_be; 1612 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_be; 1613 hal_soc->ops->hal_rx_get_mac_addr2_valid = 1614 hal_rx_get_mac_addr2_valid_be; 1615 hal_soc->ops->hal_reo_config = hal_reo_config_6432; 1616 hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_be; 1617 hal_soc->ops->hal_rx_msdu_flow_idx_invalid = 1618 hal_rx_msdu_flow_idx_invalid_be; 1619 hal_soc->ops->hal_rx_msdu_flow_idx_timeout = 1620 hal_rx_msdu_flow_idx_timeout_be; 1621 hal_soc->ops->hal_rx_msdu_fse_metadata_get = 1622 hal_rx_msdu_fse_metadata_get_be; 1623 hal_soc->ops->hal_rx_msdu_cce_match_get = 1624 hal_rx_msdu_cce_match_get_be; 1625 hal_soc->ops->hal_rx_msdu_cce_metadata_get = 1626 hal_rx_msdu_cce_metadata_get_be; 1627 hal_soc->ops->hal_rx_msdu_get_flow_params = 1628 hal_rx_msdu_get_flow_params_be; 1629 hal_soc->ops->hal_rx_tlv_get_tcp_chksum = hal_rx_tlv_get_tcp_chksum_be; 1630 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_be; 1631 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) 1632 hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_6432; 1633 hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_6432; 1634 #else 1635 hal_soc->ops->hal_rx_get_bb_info = NULL; 1636 hal_soc->ops->hal_rx_get_rtt_info = NULL; 1637 #endif 1638 /* rx - msdu fast path info fields */ 1639 hal_soc->ops->hal_rx_msdu_packet_metadata_get = 1640 hal_rx_msdu_packet_metadata_get_generic_be; 1641 hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid = 1642 hal_rx_mpdu_start_tlv_tag_valid_be; 1643 hal_soc->ops->hal_rx_wbm_err_msdu_continuation_get = 1644 hal_rx_wbm_err_msdu_continuation_get_6432; 1645 1646 /* rx - TLV struct offsets */ 1647 hal_soc->ops->hal_rx_msdu_end_offset_get = 1648 hal_rx_msdu_end_offset_get_generic; 1649 hal_soc->ops->hal_rx_mpdu_start_offset_get = 1650 hal_rx_mpdu_start_offset_get_generic; 1651 #ifndef NO_RX_PKT_HDR_TLV 1652 hal_soc->ops->hal_rx_pkt_tlv_offset_get = 1653 hal_rx_pkt_tlv_offset_get_generic; 1654 #endif 1655 hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_6432; 1656 1657 hal_soc->ops->hal_rx_flow_get_tuple_info = 1658 hal_rx_flow_get_tuple_info_be; 1659 hal_soc->ops->hal_rx_flow_delete_entry = 1660 hal_rx_flow_delete_entry_be; 1661 hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_be; 1662 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = 1663 hal_compute_reo_remap_ix2_ix3_6432; 1664 1665 hal_soc->ops->hal_rx_msdu_get_reo_destination_indication = 1666 hal_rx_msdu_get_reo_destination_indication_be; 1667 hal_soc->ops->hal_rx_get_tlv_size = hal_rx_get_tlv_size_generic_be; 1668 hal_soc->ops->hal_rx_msdu_is_wlan_mcast = 1669 hal_rx_msdu_is_wlan_mcast_generic_be; 1670 hal_soc->ops->hal_tx_get_num_tcl_banks = hal_tx_get_num_tcl_banks_6432; 1671 hal_soc->ops->hal_rx_tlv_decap_format_get = 1672 hal_rx_tlv_decap_format_get_be; 1673 #ifdef RECEIVE_OFFLOAD 1674 hal_soc->ops->hal_rx_tlv_get_offload_info = 1675 hal_rx_tlv_get_offload_info_be; 1676 hal_soc->ops->hal_rx_get_proto_params = hal_rx_get_proto_params_be; 1677 hal_soc->ops->hal_rx_get_l3_l4_offsets = hal_rx_get_l3_l4_offsets_be; 1678 #endif 1679 hal_soc->ops->hal_rx_tlv_msdu_done_get = 1680 hal_rx_tlv_msdu_done_copy_get_6432; 1681 hal_soc->ops->hal_rx_tlv_msdu_len_get = 1682 hal_rx_msdu_start_msdu_len_get_be; 1683 hal_soc->ops->hal_rx_get_frame_ctrl_field = 1684 hal_rx_get_frame_ctrl_field_be; 1685 hal_soc->ops->hal_rx_tlv_csum_err_get = hal_rx_tlv_csum_err_get_be; 1686 hal_soc->ops->hal_rx_tlv_msdu_len_set = 1687 hal_rx_msdu_start_msdu_len_set_be; 1688 hal_soc->ops->hal_rx_tlv_sgi_get = hal_rx_tlv_sgi_get_be; 1689 hal_soc->ops->hal_rx_tlv_rate_mcs_get = hal_rx_tlv_rate_mcs_get_be; 1690 hal_soc->ops->hal_rx_tlv_bw_get = hal_rx_tlv_bw_get_be; 1691 hal_soc->ops->hal_rx_tlv_get_pkt_type = hal_rx_tlv_get_pkt_type_be; 1692 hal_soc->ops->hal_rx_tlv_mic_err_get = hal_rx_tlv_mic_err_get_be; 1693 hal_soc->ops->hal_rx_tlv_decrypt_err_get = 1694 hal_rx_tlv_decrypt_err_get_be; 1695 hal_soc->ops->hal_rx_tlv_first_mpdu_get = hal_rx_tlv_first_mpdu_get_be; 1696 hal_soc->ops->hal_rx_tlv_get_is_decrypted = 1697 hal_rx_tlv_get_is_decrypted_be; 1698 hal_soc->ops->hal_rx_msdu_get_keyid = hal_rx_msdu_get_keyid_be; 1699 hal_soc->ops->hal_rx_tlv_get_freq = hal_rx_tlv_get_freq_be; 1700 hal_soc->ops->hal_rx_priv_info_set_in_tlv = 1701 hal_rx_priv_info_set_in_tlv_be; 1702 hal_soc->ops->hal_rx_priv_info_get_from_tlv = 1703 hal_rx_priv_info_get_from_tlv_be; 1704 hal_soc->ops->hal_rx_pkt_hdr_get = hal_rx_pkt_hdr_get_be; 1705 hal_soc->ops->hal_reo_setup = hal_reo_setup_6432; 1706 hal_soc->ops->hal_reo_config_reo2ppe_dest_info = NULL; 1707 #ifdef REO_SHARED_QREF_TABLE_EN 1708 hal_soc->ops->hal_reo_shared_qaddr_setup = hal_reo_shared_qaddr_setup_be; 1709 hal_soc->ops->hal_reo_shared_qaddr_init = hal_reo_shared_qaddr_init_be; 1710 hal_soc->ops->hal_reo_shared_qaddr_detach = hal_reo_shared_qaddr_detach_be; 1711 hal_soc->ops->hal_reo_shared_qaddr_write = hal_reo_shared_qaddr_write_be; 1712 hal_soc->ops->hal_reo_shared_qaddr_cache_clear = hal_reo_shared_qaddr_cache_clear_be; 1713 #endif 1714 /* Overwrite the default BE ops */ 1715 hal_soc->ops->hal_get_rx_max_ba_window = 1716 hal_get_rx_max_ba_window_qcn6432; 1717 hal_soc->ops->hal_get_reo_qdesc_size = hal_qcn6432_get_reo_qdesc_size; 1718 /* TX MONITOR */ 1719 #ifdef WLAN_PKT_CAPTURE_TX_2_0 1720 hal_soc->ops->hal_txmon_is_mon_buf_addr_tlv = 1721 hal_txmon_is_mon_buf_addr_tlv_generic_be; 1722 hal_soc->ops->hal_txmon_populate_packet_info = 1723 hal_txmon_populate_packet_info_generic_be; 1724 hal_soc->ops->hal_txmon_status_parse_tlv = 1725 hal_txmon_status_parse_tlv_generic_be; 1726 hal_soc->ops->hal_txmon_status_get_num_users = 1727 hal_txmon_status_get_num_users_generic_be; 1728 #if defined(TX_MONITOR_WORD_MASK) 1729 hal_soc->ops->hal_txmon_get_word_mask = 1730 hal_txmon_get_word_mask_qcn6432; 1731 #else 1732 hal_soc->ops->hal_txmon_get_word_mask = 1733 hal_txmon_get_word_mask_generic_be; 1734 #endif /* TX_MONITOR_WORD_MASK */ 1735 #endif /* WLAN_PKT_CAPTURE_TX_2_0 */ 1736 hal_soc->ops->hal_compute_reo_remap_ix0 = NULL; 1737 hal_soc->ops->hal_tx_vdev_mismatch_routing_set = 1738 hal_tx_vdev_mismatch_routing_set_generic_be; 1739 hal_soc->ops->hal_tx_mcast_mlo_reinject_routing_set = 1740 hal_tx_mcast_mlo_reinject_routing_set_generic_be; 1741 hal_soc->ops->hal_get_ba_aging_timeout = 1742 hal_get_ba_aging_timeout_be_generic; 1743 hal_soc->ops->hal_setup_link_idle_list = 1744 hal_setup_link_idle_list_generic_be; 1745 hal_soc->ops->hal_cookie_conversion_reg_cfg_be = 1746 hal_cookie_conversion_reg_cfg_generic_be; 1747 hal_soc->ops->hal_set_ba_aging_timeout = 1748 hal_set_ba_aging_timeout_be_generic; 1749 hal_soc->ops->hal_tx_populate_bank_register = 1750 hal_tx_populate_bank_register_be; 1751 hal_soc->ops->hal_tx_vdev_mcast_ctrl_set = 1752 hal_tx_vdev_mcast_ctrl_set_be; 1753 #ifdef CONFIG_WORD_BASED_TLV 1754 hal_soc->ops->hal_rx_mpdu_start_wmask_get = 1755 hal_rx_mpdu_start_wmask_get_be; 1756 hal_soc->ops->hal_rx_msdu_end_wmask_get = 1757 hal_rx_msdu_end_wmask_get_be; 1758 #endif 1759 hal_soc->ops->hal_get_tsf2_scratch_reg = 1760 hal_get_tsf2_scratch_reg_qcn6432; 1761 hal_soc->ops->hal_get_tqm_scratch_reg = 1762 hal_get_tqm_scratch_reg_qcn6432; 1763 hal_soc->ops->hal_tx_ring_halt_set = hal_tx_ppe2tcl_ring_halt_set_6432; 1764 hal_soc->ops->hal_tx_ring_halt_reset = 1765 hal_tx_ppe2tcl_ring_halt_reset_6432; 1766 hal_soc->ops->hal_tx_ring_halt_poll = 1767 hal_tx_ppe2tcl_ring_halt_done_6432; 1768 hal_soc->ops->hal_tx_get_num_ppe_vp_search_idx_tbl_entries = 1769 hal_tx_get_num_ppe_vp_search_idx_reg_entries_6432; 1770 }; 1771 1772 struct hal_hw_srng_config hw_srng_table_6432[] = { 1773 /* TODO: max_rings can populated by querying HW capabilities */ 1774 { /* REO_DST */ 1775 .start_ring_id = HAL_SRNG_REO2SW1, 1776 .max_rings = 8, 1777 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1778 .lmac_ring = FALSE, 1779 .ring_dir = HAL_SRNG_DST_RING, 1780 .reg_start = { 1781 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 1782 REO_REG_REG_BASE), 1783 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 1784 REO_REG_REG_BASE) 1785 }, 1786 .reg_size = { 1787 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 1788 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 1789 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 1790 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 1791 }, 1792 .max_size = 1793 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 1794 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 1795 }, 1796 { /* REO_EXCEPTION */ 1797 /* Designating REO2SW0 ring as exception ring. This ring is 1798 * similar to other REO2SW rings though it is named as REO2SW0. 1799 * Any of theREO2SW rings can be used as exception ring. 1800 */ 1801 .start_ring_id = HAL_SRNG_REO2SW0, 1802 .max_rings = 1, 1803 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1804 .lmac_ring = FALSE, 1805 .ring_dir = HAL_SRNG_DST_RING, 1806 .reg_start = { 1807 HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR( 1808 REO_REG_REG_BASE), 1809 HWIO_REO_R2_REO2SW0_RING_HP_ADDR( 1810 REO_REG_REG_BASE) 1811 }, 1812 /* Single ring - provide ring size if multiple rings of this 1813 * type are supported 1814 */ 1815 .reg_size = {}, 1816 .max_size = 1817 HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_BMSK >> 1818 HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_SHFT, 1819 }, 1820 { /* REO_REINJECT */ 1821 .start_ring_id = HAL_SRNG_SW2REO, 1822 .max_rings = 4, 1823 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1824 .lmac_ring = FALSE, 1825 .ring_dir = HAL_SRNG_SRC_RING, 1826 .reg_start = { 1827 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 1828 REO_REG_REG_BASE), 1829 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 1830 REO_REG_REG_BASE) 1831 }, 1832 /* Single ring - provide ring size if multiple rings of this 1833 * type are supported 1834 */ 1835 .reg_size = { 1836 HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(0) - 1837 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(0), 1838 HWIO_REO_R2_SW2REO1_RING_HP_ADDR(0) - 1839 HWIO_REO_R2_SW2REO_RING_HP_ADDR(0) 1840 }, 1841 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 1842 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 1843 }, 1844 { /* REO_CMD */ 1845 .start_ring_id = HAL_SRNG_REO_CMD, 1846 .max_rings = 1, 1847 .entry_size = (sizeof(struct tlv_32_hdr) + 1848 sizeof(struct reo_get_queue_stats)) >> 2, 1849 .lmac_ring = FALSE, 1850 .ring_dir = HAL_SRNG_SRC_RING, 1851 .reg_start = { 1852 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 1853 REO_REG_REG_BASE), 1854 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 1855 REO_REG_REG_BASE), 1856 }, 1857 /* Single ring - provide ring size if multiple rings of this 1858 * type are supported 1859 */ 1860 .reg_size = {}, 1861 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1862 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1863 }, 1864 { /* REO_STATUS */ 1865 .start_ring_id = HAL_SRNG_REO_STATUS, 1866 .max_rings = 1, 1867 .entry_size = (sizeof(struct tlv_32_hdr) + 1868 sizeof(struct reo_get_queue_stats_status)) >> 2, 1869 .lmac_ring = FALSE, 1870 .ring_dir = HAL_SRNG_DST_RING, 1871 .reg_start = { 1872 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 1873 REO_REG_REG_BASE), 1874 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 1875 REO_REG_REG_BASE), 1876 }, 1877 /* Single ring - provide ring size if multiple rings of this 1878 * type are supported 1879 */ 1880 .reg_size = {}, 1881 .max_size = 1882 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1883 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1884 }, 1885 { /* TCL_DATA */ 1886 .start_ring_id = HAL_SRNG_SW2TCL1, 1887 .max_rings = 6, 1888 .entry_size = sizeof(struct tcl_data_cmd) >> 2, 1889 .lmac_ring = FALSE, 1890 .ring_dir = HAL_SRNG_SRC_RING, 1891 .reg_start = { 1892 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 1893 MAC_TCL_REG_REG_BASE), 1894 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 1895 MAC_TCL_REG_REG_BASE), 1896 }, 1897 .reg_size = { 1898 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 1899 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 1900 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 1901 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 1902 }, 1903 .max_size = 1904 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 1905 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 1906 }, 1907 { /* TCL_CMD/CREDIT */ 1908 /* qca8074v2 and qcn6432 uses this ring for data commands */ 1909 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 1910 .max_rings = 1, 1911 .entry_size = sizeof(struct tcl_data_cmd) >> 2, 1912 .lmac_ring = FALSE, 1913 .ring_dir = HAL_SRNG_SRC_RING, 1914 .reg_start = { 1915 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR( 1916 MAC_TCL_REG_REG_BASE), 1917 HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR( 1918 MAC_TCL_REG_REG_BASE), 1919 }, 1920 /* Single ring - provide ring size if multiple rings of this 1921 * type are supported 1922 */ 1923 .reg_size = {}, 1924 .max_size = 1925 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >> 1926 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT, 1927 }, 1928 { /* TCL_STATUS */ 1929 .start_ring_id = HAL_SRNG_TCL_STATUS, 1930 .max_rings = 1, 1931 .entry_size = (sizeof(struct tlv_32_hdr) + 1932 sizeof(struct tcl_status_ring)) >> 2, 1933 .lmac_ring = FALSE, 1934 .ring_dir = HAL_SRNG_DST_RING, 1935 .reg_start = { 1936 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 1937 MAC_TCL_REG_REG_BASE), 1938 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 1939 MAC_TCL_REG_REG_BASE), 1940 }, 1941 /* Single ring - provide ring size if multiple rings of this 1942 * type are supported 1943 */ 1944 .reg_size = {}, 1945 .max_size = 1946 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 1947 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 1948 }, 1949 { /* CE_SRC */ 1950 .start_ring_id = HAL_SRNG_CE_0_SRC, 1951 .max_rings = 16, 1952 .entry_size = sizeof(struct ce_src_desc) >> 2, 1953 .lmac_ring = FALSE, 1954 .ring_dir = HAL_SRNG_SRC_RING, 1955 .reg_start = { 1956 HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR( 1957 WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE), 1958 HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR( 1959 WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE), 1960 }, 1961 .reg_size = { 1962 WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE - 1963 WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE, 1964 WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE - 1965 WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE, 1966 }, 1967 .max_size = 1968 HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK >> 1969 HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT, 1970 }, 1971 { /* CE_DST */ 1972 .start_ring_id = HAL_SRNG_CE_0_DST, 1973 .max_rings = 16, 1974 .entry_size = 8 >> 2, 1975 /*TODO: entry_size above should actually be 1976 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 1977 * of struct ce_dst_desc in HW header files 1978 */ 1979 .lmac_ring = FALSE, 1980 .ring_dir = HAL_SRNG_SRC_RING, 1981 .reg_start = { 1982 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1983 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE), 1984 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1985 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE), 1986 }, 1987 .reg_size = { 1988 WFSS_CE_1_CHANNEL_DST_REG_REG_BASE - 1989 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE, 1990 WFSS_CE_1_CHANNEL_DST_REG_REG_BASE - 1991 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE, 1992 }, 1993 .max_size = 1994 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1995 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1996 }, 1997 { /* CE_DST_STATUS */ 1998 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 1999 .max_rings = 16, 2000 .entry_size = sizeof(struct ce_stat_desc) >> 2, 2001 .lmac_ring = FALSE, 2002 .ring_dir = HAL_SRNG_DST_RING, 2003 .reg_start = { 2004 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 2005 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE), 2006 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 2007 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE), 2008 }, 2009 /* TODO: check destination status ring registers */ 2010 .reg_size = { 2011 WFSS_CE_1_CHANNEL_DST_REG_REG_BASE - 2012 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE, 2013 WFSS_CE_1_CHANNEL_DST_REG_REG_BASE - 2014 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE, 2015 }, 2016 .max_size = 2017 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 2018 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 2019 }, 2020 { /* WBM_IDLE_LINK */ 2021 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 2022 .max_rings = 1, 2023 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 2024 .lmac_ring = FALSE, 2025 .ring_dir = HAL_SRNG_SRC_RING, 2026 .reg_start = { 2027 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE), 2028 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(WBM_REG_REG_BASE), 2029 }, 2030 /* Single ring - provide ring size if multiple rings of this 2031 * type are supported 2032 */ 2033 .reg_size = {}, 2034 .max_size = 2035 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 2036 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 2037 }, 2038 { /* SW2WBM_RELEASE */ 2039 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 2040 .max_rings = 1, 2041 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2042 .lmac_ring = FALSE, 2043 .ring_dir = HAL_SRNG_SRC_RING, 2044 .reg_start = { 2045 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE), 2046 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE), 2047 }, 2048 /* Single ring - provide ring size if multiple rings of this 2049 * type are supported 2050 */ 2051 .reg_size = {}, 2052 .max_size = 2053 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2054 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2055 }, 2056 { /* WBM2SW_RELEASE */ 2057 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 2058 .max_rings = 8, 2059 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2060 .lmac_ring = FALSE, 2061 .ring_dir = HAL_SRNG_DST_RING, 2062 .reg_start = { 2063 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR( 2064 WBM_REG_REG_BASE), 2065 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR( 2066 WBM_REG_REG_BASE), 2067 }, 2068 .reg_size = { 2069 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR( 2070 WBM_REG_REG_BASE) - 2071 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR( 2072 WBM_REG_REG_BASE), 2073 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR( 2074 WBM_REG_REG_BASE) - 2075 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR( 2076 WBM_REG_REG_BASE), 2077 }, 2078 .max_size = 2079 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2080 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2081 }, 2082 { /* RXDMA_BUF */ 2083 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 2084 #ifdef IPA_OFFLOAD 2085 .max_rings = 3, 2086 #else 2087 .max_rings = 3, 2088 #endif 2089 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2090 .lmac_ring = TRUE, 2091 .ring_dir = HAL_SRNG_SRC_RING, 2092 /* reg_start is not set because LMAC rings are not accessed 2093 * from host 2094 */ 2095 .reg_start = {}, 2096 .reg_size = {}, 2097 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2098 }, 2099 { /* RXDMA_DST */ 2100 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 2101 .max_rings = 0, 2102 .entry_size = 0/*sizeof(struct reo_entrance_ring) >> 2*/, 2103 .lmac_ring = TRUE, 2104 .ring_dir = HAL_SRNG_DST_RING, 2105 /* reg_start is not set because LMAC rings are not accessed 2106 * from host 2107 */ 2108 .reg_start = {}, 2109 .reg_size = {}, 2110 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2111 }, 2112 #ifdef WLAN_PKT_CAPTURE_RX_2_0 2113 { /* RXDMA_MONITOR_BUF */ 2114 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 2115 .max_rings = 1, 2116 .entry_size = sizeof(struct mon_ingress_ring) >> 2, 2117 .lmac_ring = TRUE, 2118 .ring_dir = HAL_SRNG_SRC_RING, 2119 /* reg_start is not set because LMAC rings are not accessed 2120 * from host 2121 */ 2122 .reg_start = {}, 2123 .reg_size = {}, 2124 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 2125 }, 2126 #else 2127 {}, 2128 #endif 2129 { /* RXDMA_MONITOR_STATUS */ 2130 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 2131 .max_rings = 0, 2132 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2133 .lmac_ring = TRUE, 2134 .ring_dir = HAL_SRNG_SRC_RING, 2135 /* reg_start is not set because LMAC rings are not accessed 2136 * from host 2137 */ 2138 .reg_start = {}, 2139 .reg_size = {}, 2140 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2141 }, 2142 #ifdef WLAN_PKT_CAPTURE_RX_2_0 2143 { /* RXDMA_MONITOR_DST */ 2144 .start_ring_id = HAL_SRNG_WMAC1_RXMON2SW0, 2145 .max_rings = 2, 2146 .entry_size = sizeof(struct mon_destination_ring) >> 2, 2147 .lmac_ring = TRUE, 2148 .ring_dir = HAL_SRNG_DST_RING, 2149 /* reg_start is not set because LMAC rings are not accessed 2150 * from host 2151 */ 2152 .reg_start = {}, 2153 .reg_size = {}, 2154 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 2155 }, 2156 #else 2157 {}, 2158 #endif 2159 { /* RXDMA_MONITOR_DESC */ 2160 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 2161 .max_rings = 0, 2162 .entry_size = 0/*sizeof(struct sw_monitor_ring) >> 2*/, 2163 .lmac_ring = TRUE, 2164 .ring_dir = HAL_SRNG_DST_RING, 2165 /* reg_start is not set because LMAC rings are not accessed 2166 * from host 2167 */ 2168 .reg_start = {}, 2169 .reg_size = {}, 2170 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 2171 }, 2172 2173 { /* DIR_BUF_RX_DMA_SRC */ 2174 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 2175 /* one ring for spectral and one ring for cfr */ 2176 .max_rings = 2, 2177 .entry_size = 2, 2178 .lmac_ring = TRUE, 2179 .ring_dir = HAL_SRNG_SRC_RING, 2180 /* reg_start is not set because LMAC rings are not accessed 2181 * from host 2182 */ 2183 .reg_start = {}, 2184 .reg_size = {}, 2185 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2186 }, 2187 #ifdef WLAN_FEATURE_CIF_CFR 2188 { /* WIFI_POS_SRC */ 2189 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 2190 .max_rings = 1, 2191 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 2192 .lmac_ring = TRUE, 2193 .ring_dir = HAL_SRNG_SRC_RING, 2194 /* reg_start is not set because LMAC rings are not accessed 2195 * from host 2196 */ 2197 .reg_start = {}, 2198 .reg_size = {}, 2199 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 2200 }, 2201 #endif 2202 { /* REO2PPE */ 2203 .start_ring_id = HAL_SRNG_REO2PPE, 2204 .max_rings = 1, 2205 .entry_size = sizeof(struct reo_destination_ring) >> 2, 2206 .lmac_ring = FALSE, 2207 .ring_dir = HAL_SRNG_DST_RING, 2208 .reg_start = { 2209 HWIO_REO_R0_REO2PPE_RING_BASE_LSB_ADDR( 2210 REO_REG_REG_BASE), 2211 HWIO_REO_R2_REO2PPE_RING_HP_ADDR( 2212 REO_REG_REG_BASE), 2213 }, 2214 /* Single ring - provide ring size if multiple rings of this 2215 * type are supported 2216 */ 2217 .reg_size = {}, 2218 .max_size = 2219 HWIO_REO_R0_REO2PPE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK >> 2220 HWIO_REO_R0_REO2PPE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT, 2221 }, 2222 { /* PPE2TCL */ 2223 .start_ring_id = HAL_SRNG_PPE2TCL1, 2224 .max_rings = 1, 2225 .entry_size = sizeof(struct tcl_entrance_from_ppe_ring) >> 2, 2226 .lmac_ring = FALSE, 2227 .ring_dir = HAL_SRNG_SRC_RING, 2228 .reg_start = { 2229 HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_ADDR( 2230 MAC_TCL_REG_REG_BASE), 2231 HWIO_TCL_R2_PPE2TCL1_RING_HP_ADDR( 2232 MAC_TCL_REG_REG_BASE), 2233 }, 2234 .reg_size = {}, 2235 .max_size = 2236 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 2237 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 2238 }, 2239 { /* PPE_RELEASE */ 2240 .start_ring_id = HAL_SRNG_WBM_PPE_RELEASE, 2241 .max_rings = 1, 2242 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2243 .lmac_ring = FALSE, 2244 .ring_dir = HAL_SRNG_SRC_RING, 2245 }, 2246 #ifdef WLAN_PKT_CAPTURE_TX_2_0 2247 { /* TX_MONITOR_BUF */ 2248 .start_ring_id = HAL_SRNG_SW2TXMON_BUF0, 2249 .max_rings = 1, 2250 .entry_size = sizeof(struct mon_ingress_ring) >> 2, 2251 .lmac_ring = TRUE, 2252 .ring_dir = HAL_SRNG_SRC_RING, 2253 /* reg_start is not set because LMAC rings are not accessed 2254 * from host 2255 */ 2256 .reg_start = {}, 2257 .reg_size = {}, 2258 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 2259 }, 2260 { /* TX_MONITOR_DST */ 2261 .start_ring_id = HAL_SRNG_WMAC1_TXMON2SW0, 2262 .max_rings = 2, 2263 .entry_size = sizeof(struct mon_destination_ring) >> 2, 2264 .lmac_ring = TRUE, 2265 .ring_dir = HAL_SRNG_DST_RING, 2266 /* reg_start is not set because LMAC rings are not accessed 2267 * from host 2268 */ 2269 .reg_start = {}, 2270 .reg_size = {}, 2271 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 2272 }, 2273 #else 2274 {}, 2275 {}, 2276 #endif 2277 { /* SW2RXDMA */ 2278 .start_ring_id = HAL_SRNG_SW2RXDMA_BUF0, 2279 .max_rings = 3, 2280 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2281 .lmac_ring = TRUE, 2282 .ring_dir = HAL_SRNG_SRC_RING, 2283 /* reg_start is not set because LMAC rings are not accessed 2284 * from host 2285 */ 2286 .reg_start = {}, 2287 .reg_size = {}, 2288 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 2289 .dmac_cmn_ring = TRUE, 2290 }, 2291 { /* SW2RXDMA_LINK_RELEASE */ 0}, 2292 }; 2293 2294 /** 2295 * hal_srng_hw_reg_offset_init_qcn6432() - Initialize the HW srng reg offset 2296 * applicable only for qcn6432 2297 * @hal_soc: HAL Soc handle 2298 * 2299 * Return: None 2300 */ 2301 static inline void hal_srng_hw_reg_offset_init_qcn6432(struct hal_soc *hal_soc) 2302 { 2303 int32_t *hw_reg_offset = hal_soc->hal_hw_reg_offset; 2304 2305 hw_reg_offset[DST_MSI2_BASE_LSB] = REG_OFFSET(DST, MSI2_BASE_LSB), 2306 hw_reg_offset[DST_MSI2_BASE_MSB] = REG_OFFSET(DST, MSI2_BASE_MSB), 2307 hw_reg_offset[DST_MSI2_DATA] = REG_OFFSET(DST, MSI2_DATA), 2308 hw_reg_offset[DST_PRODUCER_INT2_SETUP] = 2309 REG_OFFSET(DST, PRODUCER_INT2_SETUP); 2310 } 2311 2312 /* 2313 * hal_reo_config_reo2ppe_dest_info_6432() - Configure reo2ppe dest info 2314 * @hal_soc_hdl: HAL SoC Context 2315 * 2316 * Return: None. 2317 */ 2318 static inline 2319 void hal_reo_config_reo2ppe_dest_info_6432(hal_soc_handle_t hal_soc_hdl) 2320 { 2321 HAL_REG_WRITE((struct hal_soc *)hal_soc_hdl, 2322 HWIO_REO_R0_REO2PPE_DEST_INFO_ADDR(REO_REG_REG_BASE), 2323 REO2PPE_RULE_FAIL_FB); 2324 } 2325 2326 static void hal_hw_txrx_ops_override_qcn6432(struct hal_soc *hal_soc) 2327 { 2328 hal_soc->ops->hal_reo_config_reo2ppe_dest_info = 2329 hal_reo_config_reo2ppe_dest_info_6432; 2330 2331 hal_soc->ops->hal_get_tsf2_scratch_reg = 2332 hal_get_tsf2_scratch_reg_qcn6432; 2333 hal_soc->ops->hal_get_tqm_scratch_reg = 2334 hal_get_tqm_scratch_reg_qcn6432; 2335 } 2336 2337 /** 2338 * hal_qcn6432_attach()- Attach 6432 target specific hal_soc ops, 2339 * offset and srng table 2340 * @hal_soc: hal_soc handle 2341 * 2342 * Return: void 2343 */ 2344 void hal_qcn6432_attach(struct hal_soc *hal_soc) 2345 { 2346 hal_soc->hw_srng_table = hw_srng_table_6432; 2347 2348 hal_srng_hw_reg_offset_init_generic(hal_soc); 2349 hal_srng_hw_reg_offset_init_qcn6432(hal_soc); 2350 2351 hal_hw_txrx_default_ops_attach_be(hal_soc); 2352 hal_hw_txrx_ops_attach_qcn6432(hal_soc); 2353 hal_soc->dmac_cmn_src_rxbuf_ring = true; 2354 if (hal_soc->static_window_map) 2355 hal_write_window_register(hal_soc); 2356 hal_hw_txrx_ops_override_qcn6432(hal_soc); 2357 } 2358