1 /* 2 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #include "hal_li_hw_headers.h" 19 #include "hal_internal.h" 20 #include "hal_api.h" 21 #include "target_type.h" 22 #include "wcss_version.h" 23 #include "qdf_module.h" 24 #include "hal_qcn6122_rx.h" 25 #include "hal_api_mon.h" 26 #include "hal_flow.h" 27 #include "rx_flow_search_entry.h" 28 #include "hal_rx_flow_info.h" 29 30 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 31 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET 32 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 33 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK 34 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 35 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB 36 #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET \ 37 RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET 38 #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK \ 39 RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK 40 #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB \ 41 RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB 42 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 43 PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 44 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 45 PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 46 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 47 PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 48 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 49 PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 50 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 51 PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 52 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 53 PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 54 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 55 PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 56 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 57 PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 58 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 59 PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 60 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 61 PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 62 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 63 PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 64 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 65 RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 66 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 67 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 68 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 69 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 70 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 71 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 72 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 73 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 74 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER \ 75 STATUS_HEADER_REO_STATUS_NUMBER 76 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 77 STATUS_HEADER_TIMESTAMP 78 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 79 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 80 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 81 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 82 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 83 TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 84 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 85 TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 86 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 87 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 88 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 89 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 90 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 91 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 92 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 93 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 94 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 95 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 96 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 97 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 98 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 99 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 100 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 101 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 102 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 103 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 104 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 105 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 106 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 107 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 108 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 109 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 110 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 111 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 112 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 113 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 114 115 #define CE_WINDOW_ADDRESS_6122 \ 116 ((SOC_WFSS_CE_REG_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) 117 118 #define UMAC_WINDOW_ADDRESS_6122 \ 119 ((SEQ_WCSS_UMAC_OFFSET >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) 120 121 #define WINDOW_CONFIGURATION_VALUE_6122 \ 122 ((CE_WINDOW_ADDRESS_6122 << 6) |\ 123 (UMAC_WINDOW_ADDRESS_6122 << 12) | \ 124 WINDOW_ENABLE_BIT) 125 126 #include "hal_qcn6122_tx.h" 127 #include <hal_generic_api.h> 128 #include "hal_li_rx.h" 129 #include "hal_li_api.h" 130 #include "hal_li_generic_api.h" 131 132 /** 133 * hal_rx_sw_mon_desc_info_get_6122(): API to read the 134 * sw monitor ring descriptor 135 * 136 * @rxdma_dst_ring_desc: sw monitor ring descriptor 137 * @desc_info_buf: Descriptor info buffer to which 138 * sw monitor ring descriptor is populated to 139 * 140 * Return: void 141 */ 142 static void 143 hal_rx_sw_mon_desc_info_get_6122(hal_ring_desc_t rxdma_dst_ring_desc, 144 hal_rx_mon_desc_info_t desc_info_buf) 145 { 146 struct sw_monitor_ring *sw_mon_ring = 147 (struct sw_monitor_ring *)rxdma_dst_ring_desc; 148 struct buffer_addr_info *buf_addr_info; 149 uint32_t *mpdu_info; 150 uint32_t loop_cnt; 151 struct hal_rx_mon_desc_info *desc_info; 152 153 desc_info = (struct hal_rx_mon_desc_info *)desc_info_buf; 154 mpdu_info = (uint32_t *)&sw_mon_ring-> 155 reo_level_mpdu_frame_info.rx_mpdu_desc_info_details; 156 157 loop_cnt = HAL_RX_GET(sw_mon_ring, SW_MONITOR_RING_7, LOOPING_COUNT); 158 desc_info->msdu_count = HAL_RX_MPDU_MSDU_COUNT_GET(mpdu_info); 159 160 /* Get msdu link descriptor buf_addr_info */ 161 buf_addr_info = &sw_mon_ring-> 162 reo_level_mpdu_frame_info.msdu_link_desc_addr_info; 163 desc_info->link_desc.paddr = HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) 164 | ((uint64_t)(HAL_RX_BUFFER_ADDR_39_32_GET( 165 buf_addr_info)) << 32); 166 desc_info->link_desc.sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info); 167 buf_addr_info = &sw_mon_ring->status_buff_addr_info; 168 desc_info->status_buf.paddr = HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) 169 | ((uint64_t) 170 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32); 171 desc_info->status_buf.sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info); 172 desc_info->end_of_ppdu = HAL_RX_GET(sw_mon_ring, 173 SW_MONITOR_RING_6, 174 END_OF_PPDU); 175 desc_info->status_buf_count = HAL_RX_GET(sw_mon_ring, 176 SW_MONITOR_RING_6, 177 STATUS_BUF_COUNT); 178 desc_info->rxdma_push_reason = HAL_RX_GET(sw_mon_ring, 179 SW_MONITOR_RING_6, 180 RXDMA_PUSH_REASON); 181 desc_info->ppdu_id = HAL_RX_GET(sw_mon_ring, 182 SW_MONITOR_RING_7, 183 PHY_PPDU_ID); 184 } 185 186 /** 187 * hal_rx_msdu_start_nss_get_6122(): API to get the NSS 188 * Interval from rx_msdu_start 189 * 190 * @buf: pointer to the start of RX PKT TLV header 191 * Return: uint32_t(nss) 192 */ 193 static uint32_t hal_rx_msdu_start_nss_get_6122(uint8_t *buf) 194 { 195 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 196 struct rx_msdu_start *msdu_start = 197 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 198 uint8_t mimo_ss_bitmap; 199 200 mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start); 201 202 return qdf_get_hweight8(mimo_ss_bitmap); 203 } 204 205 /** 206 * hal_rx_msdu_start_get_len_6122(): API to get the MSDU length 207 * from rx_msdu_start TLV 208 * 209 * @ buf: pointer to the start of RX PKT TLV headers 210 * Return: (uint32_t)msdu length 211 */ 212 static uint32_t hal_rx_msdu_start_get_len_6122(uint8_t *buf) 213 { 214 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 215 struct rx_msdu_start *msdu_start = 216 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 217 uint32_t msdu_len; 218 219 msdu_len = HAL_RX_MSDU_START_MSDU_LEN_GET(msdu_start); 220 221 return msdu_len; 222 } 223 224 /** 225 * hal_rx_mon_hw_desc_get_mpdu_status_6122(): Retrieve MPDU status 226 * 227 * @ hw_desc_addr: Start address of Rx HW TLVs 228 * @ rs: Status for monitor mode 229 * 230 * Return: void 231 */ 232 static void hal_rx_mon_hw_desc_get_mpdu_status_6122(void *hw_desc_addr, 233 struct mon_rx_status *rs) 234 { 235 struct rx_msdu_start *rx_msdu_start; 236 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 237 uint32_t reg_value; 238 const uint32_t sgi_hw_to_cdp[] = { 239 CDP_SGI_0_8_US, 240 CDP_SGI_0_4_US, 241 CDP_SGI_1_6_US, 242 CDP_SGI_3_2_US, 243 }; 244 245 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 246 247 HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs); 248 249 rs->ant_signal_db = HAL_RX_GET(rx_msdu_start, 250 RX_MSDU_START_5, USER_RSSI); 251 rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC); 252 253 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI); 254 rs->sgi = sgi_hw_to_cdp[reg_value]; 255 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE); 256 rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0; 257 /* TODO: rs->beamformed should be set for SU beamforming also */ 258 } 259 260 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 261 /** 262 * hal_get_link_desc_size_6122(): API to get the link desc size 263 * 264 * Return: uint32_t 265 */ 266 static uint32_t hal_get_link_desc_size_6122(void) 267 { 268 return LINK_DESC_SIZE; 269 } 270 271 /** 272 * hal_rx_get_tlv_6122(): API to get the tlv 273 * 274 * @rx_tlv: TLV data extracted from the rx packet 275 * Return: uint8_t 276 */ 277 static uint8_t hal_rx_get_tlv_6122(void *rx_tlv) 278 { 279 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH); 280 } 281 282 /** 283 * hal_rx_mpdu_start_tlv_tag_valid_6122 () - API to check if RX_MPDU_START 284 * tlv tag is valid 285 * 286 *@rx_tlv_hdr: start address of rx_pkt_tlvs 287 * 288 * Return: true if RX_MPDU_START is valid, else false. 289 */ 290 uint8_t hal_rx_mpdu_start_tlv_tag_valid_6122(void *rx_tlv_hdr) 291 { 292 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 293 uint32_t tlv_tag; 294 295 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(&rx_desc->mpdu_start_tlv); 296 297 return tlv_tag == WIFIRX_MPDU_START_E ? true : false; 298 } 299 300 /** 301 * hal_rx_wbm_err_msdu_continuation_get_6122 () - API to check if WBM 302 * msdu continuation bit is set 303 * 304 *@wbm_desc: wbm release ring descriptor 305 * 306 * Return: true if msdu continuation bit is set. 307 */ 308 uint8_t hal_rx_wbm_err_msdu_continuation_get_6122(void *wbm_desc) 309 { 310 uint32_t comp_desc = 311 *(uint32_t *)(((uint8_t *)wbm_desc) + 312 WBM_RELEASE_RING_3_MSDU_CONTINUATION_OFFSET); 313 314 return (comp_desc & WBM_RELEASE_RING_3_MSDU_CONTINUATION_MASK) >> 315 WBM_RELEASE_RING_3_MSDU_CONTINUATION_LSB; 316 } 317 318 /** 319 * hal_rx_proc_phyrx_other_receive_info_tlv_6122(): API to get tlv info 320 * 321 * Return: uint32_t 322 */ 323 static inline 324 void hal_rx_proc_phyrx_other_receive_info_tlv_6122(void *rx_tlv_hdr, 325 void *ppdu_info_hdl) 326 { 327 } 328 329 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) 330 static inline 331 void hal_rx_get_bb_info_6122(void *rx_tlv, 332 void *ppdu_info_hdl) 333 { 334 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 335 336 ppdu_info->cfr_info.bb_captured_channel = 337 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_CHANNEL); 338 339 ppdu_info->cfr_info.bb_captured_timeout = 340 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_TIMEOUT); 341 342 ppdu_info->cfr_info.bb_captured_reason = 343 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_REASON); 344 } 345 346 static inline 347 void hal_rx_get_rtt_info_6122(void *rx_tlv, 348 void *ppdu_info_hdl) 349 { 350 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 351 352 ppdu_info->cfr_info.rx_location_info_valid = 353 HAL_RX_GET(rx_tlv, PHYRX_PKT_END_13_RX_PKT_END_DETAILS, 354 RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID); 355 356 ppdu_info->cfr_info.rtt_che_buffer_pointer_low32 = 357 HAL_RX_GET(rx_tlv, 358 PHYRX_PKT_END_12_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 359 RTT_CHE_BUFFER_POINTER_LOW32); 360 361 ppdu_info->cfr_info.rtt_che_buffer_pointer_high8 = 362 HAL_RX_GET(rx_tlv, 363 PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 364 RTT_CHE_BUFFER_POINTER_HIGH8); 365 366 ppdu_info->cfr_info.chan_capture_status = 367 HAL_RX_GET(rx_tlv, 368 PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 369 RESERVED_8); 370 } 371 #endif 372 373 /** 374 * hal_rx_dump_msdu_start_tlv_6122() : dump RX msdu_start TLV in structured 375 * human readable format. 376 * @ msdu_start: pointer the msdu_start TLV in pkt. 377 * @ dbg_level: log level. 378 * 379 * Return: void 380 */ 381 static void hal_rx_dump_msdu_start_tlv_6122(void *msdustart, 382 uint8_t dbg_level) 383 { 384 struct rx_msdu_start *msdu_start = (struct rx_msdu_start *)msdustart; 385 386 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 387 "rx_msdu_start tlv - " 388 "rxpcu_mpdu_filter_in_category: %d " 389 "sw_frame_group_id: %d " 390 "phy_ppdu_id: %d " 391 "msdu_length: %d " 392 "ipsec_esp: %d " 393 "l3_offset: %d " 394 "ipsec_ah: %d " 395 "l4_offset: %d " 396 "msdu_number: %d " 397 "decap_format: %d " 398 "ipv4_proto: %d " 399 "ipv6_proto: %d " 400 "tcp_proto: %d " 401 "udp_proto: %d " 402 "ip_frag: %d " 403 "tcp_only_ack: %d " 404 "da_is_bcast_mcast: %d " 405 "ip4_protocol_ip6_next_header: %d " 406 "toeplitz_hash_2_or_4: %d " 407 "flow_id_toeplitz: %d " 408 "user_rssi: %d " 409 "pkt_type: %d " 410 "stbc: %d " 411 "sgi: %d " 412 "rate_mcs: %d " 413 "receive_bandwidth: %d " 414 "reception_type: %d " 415 "ppdu_start_timestamp: %d " 416 "sw_phy_meta_data: %d ", 417 msdu_start->rxpcu_mpdu_filter_in_category, 418 msdu_start->sw_frame_group_id, 419 msdu_start->phy_ppdu_id, 420 msdu_start->msdu_length, 421 msdu_start->ipsec_esp, 422 msdu_start->l3_offset, 423 msdu_start->ipsec_ah, 424 msdu_start->l4_offset, 425 msdu_start->msdu_number, 426 msdu_start->decap_format, 427 msdu_start->ipv4_proto, 428 msdu_start->ipv6_proto, 429 msdu_start->tcp_proto, 430 msdu_start->udp_proto, 431 msdu_start->ip_frag, 432 msdu_start->tcp_only_ack, 433 msdu_start->da_is_bcast_mcast, 434 msdu_start->ip4_protocol_ip6_next_header, 435 msdu_start->toeplitz_hash_2_or_4, 436 msdu_start->flow_id_toeplitz, 437 msdu_start->user_rssi, 438 msdu_start->pkt_type, 439 msdu_start->stbc, 440 msdu_start->sgi, 441 msdu_start->rate_mcs, 442 msdu_start->receive_bandwidth, 443 msdu_start->reception_type, 444 msdu_start->ppdu_start_timestamp, 445 msdu_start->sw_phy_meta_data); 446 } 447 448 /** 449 * hal_rx_dump_msdu_end_tlv_6122: dump RX msdu_end TLV in structured 450 * human readable format. 451 * @ msdu_end: pointer the msdu_end TLV in pkt. 452 * @ dbg_level: log level. 453 * 454 * Return: void 455 */ 456 static void hal_rx_dump_msdu_end_tlv_6122(void *msduend, 457 uint8_t dbg_level) 458 { 459 struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend; 460 461 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 462 "rx_msdu_end tlv - " 463 "rxpcu_mpdu_filter_in_category: %d " 464 "sw_frame_group_id: %d " 465 "phy_ppdu_id: %d " 466 "ip_hdr_chksum: %d " 467 "reported_mpdu_length: %d " 468 "key_id_octet: %d " 469 "cce_super_rule: %d " 470 "cce_classify_not_done_truncat: %d " 471 "cce_classify_not_done_cce_dis: %d " 472 "rule_indication_31_0: %d " 473 "rule_indication_63_32: %d " 474 "da_offset: %d " 475 "sa_offset: %d " 476 "da_offset_valid: %d " 477 "sa_offset_valid: %d " 478 "ipv6_options_crc: %d " 479 "tcp_seq_number: %d " 480 "tcp_ack_number: %d " 481 "tcp_flag: %d " 482 "lro_eligible: %d " 483 "window_size: %d " 484 "tcp_udp_chksum: %d " 485 "sa_idx_timeout: %d " 486 "da_idx_timeout: %d " 487 "msdu_limit_error: %d " 488 "flow_idx_timeout: %d " 489 "flow_idx_invalid: %d " 490 "wifi_parser_error: %d " 491 "amsdu_parser_error: %d " 492 "sa_is_valid: %d " 493 "da_is_valid: %d " 494 "da_is_mcbc: %d " 495 "l3_header_padding: %d " 496 "first_msdu: %d " 497 "last_msdu: %d " 498 "sa_idx: %d " 499 "msdu_drop: %d " 500 "reo_destination_indication: %d " 501 "flow_idx: %d " 502 "fse_metadata: %d " 503 "cce_metadata: %d " 504 "sa_sw_peer_id: %d ", 505 msdu_end->rxpcu_mpdu_filter_in_category, 506 msdu_end->sw_frame_group_id, 507 msdu_end->phy_ppdu_id, 508 msdu_end->ip_hdr_chksum, 509 msdu_end->reported_mpdu_length, 510 msdu_end->key_id_octet, 511 msdu_end->cce_super_rule, 512 msdu_end->cce_classify_not_done_truncate, 513 msdu_end->cce_classify_not_done_cce_dis, 514 msdu_end->rule_indication_31_0, 515 msdu_end->rule_indication_63_32, 516 msdu_end->da_offset, 517 msdu_end->sa_offset, 518 msdu_end->da_offset_valid, 519 msdu_end->sa_offset_valid, 520 msdu_end->ipv6_options_crc, 521 msdu_end->tcp_seq_number, 522 msdu_end->tcp_ack_number, 523 msdu_end->tcp_flag, 524 msdu_end->lro_eligible, 525 msdu_end->window_size, 526 msdu_end->tcp_udp_chksum, 527 msdu_end->sa_idx_timeout, 528 msdu_end->da_idx_timeout, 529 msdu_end->msdu_limit_error, 530 msdu_end->flow_idx_timeout, 531 msdu_end->flow_idx_invalid, 532 msdu_end->wifi_parser_error, 533 msdu_end->amsdu_parser_error, 534 msdu_end->sa_is_valid, 535 msdu_end->da_is_valid, 536 msdu_end->da_is_mcbc, 537 msdu_end->l3_header_padding, 538 msdu_end->first_msdu, 539 msdu_end->last_msdu, 540 msdu_end->sa_idx, 541 msdu_end->msdu_drop, 542 msdu_end->reo_destination_indication, 543 msdu_end->flow_idx, 544 msdu_end->fse_metadata, 545 msdu_end->cce_metadata, 546 msdu_end->sa_sw_peer_id); 547 } 548 549 /** 550 * hal_rx_mpdu_start_tid_get_6122(): API to get tid 551 * from rx_msdu_start 552 * 553 * @buf: pointer to the start of RX PKT TLV header 554 * Return: uint32_t(tid value) 555 */ 556 static uint32_t hal_rx_mpdu_start_tid_get_6122(uint8_t *buf) 557 { 558 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 559 struct rx_mpdu_start *mpdu_start = 560 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 561 uint32_t tid; 562 563 tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details); 564 565 return tid; 566 } 567 568 /** 569 * hal_rx_msdu_start_reception_type_get(): API to get the reception type 570 * Interval from rx_msdu_start 571 * 572 * @buf: pointer to the start of RX PKT TLV header 573 * Return: uint32_t(reception_type) 574 */ 575 static uint32_t hal_rx_msdu_start_reception_type_get_6122(uint8_t *buf) 576 { 577 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 578 struct rx_msdu_start *msdu_start = 579 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 580 uint32_t reception_type; 581 582 reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start); 583 584 return reception_type; 585 } 586 587 /** 588 * hal_rx_msdu_end_da_idx_get_6122: API to get da_idx 589 * from rx_msdu_end TLV 590 * 591 * @ buf: pointer to the start of RX PKT TLV headers 592 * Return: da index 593 */ 594 static uint16_t hal_rx_msdu_end_da_idx_get_6122(uint8_t *buf) 595 { 596 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 597 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 598 uint16_t da_idx; 599 600 da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 601 602 return da_idx; 603 } 604 605 /** 606 * hal_rx_get_rx_fragment_number_6122(): Function to retrieve rx fragment number 607 * 608 * @nbuf: Network buffer 609 * Returns: rx fragment number 610 */ 611 static 612 uint8_t hal_rx_get_rx_fragment_number_6122(uint8_t *buf) 613 { 614 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 615 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 616 617 /* Return first 4 bits as fragment number */ 618 return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & 619 DOT11_SEQ_FRAG_MASK); 620 } 621 622 /** 623 * hal_rx_msdu_end_da_is_mcbc_get_6122(): API to check if pkt is MCBC 624 * from rx_msdu_end TLV 625 * 626 * @ buf: pointer to the start of RX PKT TLV headers 627 * Return: da_is_mcbc 628 */ 629 static uint8_t 630 hal_rx_msdu_end_da_is_mcbc_get_6122(uint8_t *buf) 631 { 632 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 633 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 634 635 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); 636 } 637 638 /** 639 * hal_rx_msdu_end_sa_is_valid_get_6122(): API to get_6122 the 640 * sa_is_valid bit from rx_msdu_end TLV 641 * 642 * @ buf: pointer to the start of RX PKT TLV headers 643 * Return: sa_is_valid bit 644 */ 645 static uint8_t 646 hal_rx_msdu_end_sa_is_valid_get_6122(uint8_t *buf) 647 { 648 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 649 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 650 uint8_t sa_is_valid; 651 652 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); 653 654 return sa_is_valid; 655 } 656 657 /** 658 * hal_rx_msdu_end_sa_idx_get_6122(): API to get_6122 the 659 * sa_idx from rx_msdu_end TLV 660 * 661 * @ buf: pointer to the start of RX PKT TLV headers 662 * Return: sa_idx (SA AST index) 663 */ 664 static uint16_t hal_rx_msdu_end_sa_idx_get_6122(uint8_t *buf) 665 { 666 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 667 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 668 uint16_t sa_idx; 669 670 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 671 672 return sa_idx; 673 } 674 675 /** 676 * hal_rx_desc_is_first_msdu_6122() - Check if first msdu 677 * 678 * @hal_soc_hdl: hal_soc handle 679 * @hw_desc_addr: hardware descriptor address 680 * 681 * Return: 0 - success/ non-zero failure 682 */ 683 static uint32_t hal_rx_desc_is_first_msdu_6122(void *hw_desc_addr) 684 { 685 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; 686 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; 687 688 return HAL_RX_GET(msdu_end, RX_MSDU_END_10, FIRST_MSDU); 689 } 690 691 /** 692 * hal_rx_msdu_end_l3_hdr_padding_get_6122(): API to get_6122 the 693 * l3_header padding from rx_msdu_end TLV 694 * 695 * @ buf: pointer to the start of RX PKT TLV headers 696 * Return: number of l3 header padding bytes 697 */ 698 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_6122(uint8_t *buf) 699 { 700 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 701 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 702 uint32_t l3_header_padding; 703 704 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 705 706 return l3_header_padding; 707 } 708 709 /** 710 * @ hal_rx_encryption_info_valid_6122: Returns encryption type. 711 * 712 * @ buf: rx_tlv_hdr of the received packet 713 * @ Return: encryption type 714 */ 715 inline uint32_t hal_rx_encryption_info_valid_6122(uint8_t *buf) 716 { 717 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 718 struct rx_mpdu_start *mpdu_start = 719 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 720 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 721 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); 722 723 return encryption_info; 724 } 725 726 /* 727 * @ hal_rx_print_pn_6122: Prints the PN of rx packet. 728 * 729 * @ buf: rx_tlv_hdr of the received packet 730 * @ Return: void 731 */ 732 static void hal_rx_print_pn_6122(uint8_t *buf) 733 { 734 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 735 struct rx_mpdu_start *mpdu_start = 736 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 737 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 738 739 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); 740 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); 741 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); 742 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); 743 744 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ", 745 pn_127_96, pn_95_64, pn_63_32, pn_31_0); 746 } 747 748 /** 749 * hal_rx_msdu_end_first_msdu_get_6122: API to get first msdu status 750 * from rx_msdu_end TLV 751 * 752 * @ buf: pointer to the start of RX PKT TLV headers 753 * Return: first_msdu 754 */ 755 static uint8_t hal_rx_msdu_end_first_msdu_get_6122(uint8_t *buf) 756 { 757 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 758 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 759 uint8_t first_msdu; 760 761 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); 762 763 return first_msdu; 764 } 765 766 /** 767 * hal_rx_msdu_end_da_is_valid_get_6122: API to check if da is valid 768 * from rx_msdu_end TLV 769 * 770 * @ buf: pointer to the start of RX PKT TLV headers 771 * Return: da_is_valid 772 */ 773 static uint8_t hal_rx_msdu_end_da_is_valid_get_6122(uint8_t *buf) 774 { 775 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 776 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 777 uint8_t da_is_valid; 778 779 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); 780 781 return da_is_valid; 782 } 783 784 /** 785 * hal_rx_msdu_end_last_msdu_get_6122: API to get last msdu status 786 * from rx_msdu_end TLV 787 * 788 * @ buf: pointer to the start of RX PKT TLV headers 789 * Return: last_msdu 790 */ 791 static uint8_t hal_rx_msdu_end_last_msdu_get_6122(uint8_t *buf) 792 { 793 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 794 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 795 uint8_t last_msdu; 796 797 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); 798 799 return last_msdu; 800 } 801 802 /* 803 * hal_rx_get_mpdu_mac_ad4_valid(): Retrieves if mpdu 4th addr is valid 804 * 805 * @nbuf: Network buffer 806 * Returns: value of mpdu 4th address valid field 807 */ 808 inline bool hal_rx_get_mpdu_mac_ad4_valid_6122(uint8_t *buf) 809 { 810 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 811 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 812 bool ad4_valid = 0; 813 814 ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(rx_mpdu_info); 815 816 return ad4_valid; 817 } 818 819 /** 820 * hal_rx_mpdu_start_sw_peer_id_get_6122: Retrieve sw peer_id 821 * @buf: network buffer 822 * 823 * Return: sw peer_id 824 */ 825 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_6122(uint8_t *buf) 826 { 827 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 828 struct rx_mpdu_start *mpdu_start = 829 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 830 831 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET( 832 &mpdu_start->rx_mpdu_info_details); 833 } 834 835 /* 836 * hal_rx_mpdu_get_to_ds_6122(): API to get the tods info 837 * from rx_mpdu_start 838 * 839 * @buf: pointer to the start of RX PKT TLV header 840 * Return: uint32_t(to_ds) 841 */ 842 static uint32_t hal_rx_mpdu_get_to_ds_6122(uint8_t *buf) 843 { 844 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 845 struct rx_mpdu_start *mpdu_start = 846 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 847 848 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 849 850 return HAL_RX_MPDU_GET_TODS(mpdu_info); 851 } 852 853 /* 854 * hal_rx_mpdu_get_fr_ds_6122(): API to get the from ds info 855 * from rx_mpdu_start 856 * 857 * @buf: pointer to the start of RX PKT TLV header 858 * Return: uint32_t(fr_ds) 859 */ 860 static uint32_t hal_rx_mpdu_get_fr_ds_6122(uint8_t *buf) 861 { 862 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 863 struct rx_mpdu_start *mpdu_start = 864 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 865 866 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 867 868 return HAL_RX_MPDU_GET_FROMDS(mpdu_info); 869 } 870 871 /* 872 * hal_rx_get_mpdu_frame_control_valid_6122(): Retrieves mpdu 873 * frame control valid 874 * 875 * @nbuf: Network buffer 876 * Returns: value of frame control valid field 877 */ 878 static uint8_t hal_rx_get_mpdu_frame_control_valid_6122(uint8_t *buf) 879 { 880 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 881 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 882 883 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); 884 } 885 886 /** 887 * hal_rx_get_mpdu_frame_control_field_6122(): Function to 888 * retrieve frame control field 889 * 890 * @nbuf: Network buffer 891 * Returns: value of frame control field 892 * 893 */ 894 static uint16_t hal_rx_get_mpdu_frame_control_field_6122(uint8_t *buf) 895 { 896 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 897 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 898 uint16_t frame_ctrl = 0; 899 900 frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info); 901 902 return frame_ctrl; 903 } 904 905 /* 906 * hal_rx_mpdu_get_addr1_6122(): API to check get address1 of the mpdu 907 * 908 * @buf: pointer to the start of RX PKT TLV headera 909 * @mac_addr: pointer to mac address 910 * Return: success/failure 911 */ 912 static QDF_STATUS hal_rx_mpdu_get_addr1_6122(uint8_t *buf, 913 uint8_t *mac_addr) 914 { 915 struct __attribute__((__packed__)) hal_addr1 { 916 uint32_t ad1_31_0; 917 uint16_t ad1_47_32; 918 }; 919 920 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 921 struct rx_mpdu_start *mpdu_start = 922 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 923 924 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 925 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; 926 uint32_t mac_addr_ad1_valid; 927 928 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); 929 930 if (mac_addr_ad1_valid) { 931 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); 932 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); 933 return QDF_STATUS_SUCCESS; 934 } 935 936 return QDF_STATUS_E_FAILURE; 937 } 938 939 /* 940 * hal_rx_mpdu_get_addr2_6122(): API to check get address2 of the mpdu 941 * in the packet 942 * 943 * @buf: pointer to the start of RX PKT TLV header 944 * @mac_addr: pointer to mac address 945 * Return: success/failure 946 */ 947 static QDF_STATUS hal_rx_mpdu_get_addr2_6122(uint8_t *buf, uint8_t *mac_addr) 948 { 949 struct __attribute__((__packed__)) hal_addr2 { 950 uint16_t ad2_15_0; 951 uint32_t ad2_47_16; 952 }; 953 954 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 955 struct rx_mpdu_start *mpdu_start = 956 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 957 958 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 959 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; 960 uint32_t mac_addr_ad2_valid; 961 962 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); 963 964 if (mac_addr_ad2_valid) { 965 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); 966 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); 967 return QDF_STATUS_SUCCESS; 968 } 969 970 return QDF_STATUS_E_FAILURE; 971 } 972 973 /* 974 * hal_rx_mpdu_get_addr3_6122(): API to get address3 of the mpdu 975 * in the packet 976 * 977 * @buf: pointer to the start of RX PKT TLV header 978 * @mac_addr: pointer to mac address 979 * Return: success/failure 980 */ 981 static QDF_STATUS hal_rx_mpdu_get_addr3_6122(uint8_t *buf, uint8_t *mac_addr) 982 { 983 struct __attribute__((__packed__)) hal_addr3 { 984 uint32_t ad3_31_0; 985 uint16_t ad3_47_32; 986 }; 987 988 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 989 struct rx_mpdu_start *mpdu_start = 990 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 991 992 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 993 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; 994 uint32_t mac_addr_ad3_valid; 995 996 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); 997 998 if (mac_addr_ad3_valid) { 999 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); 1000 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); 1001 return QDF_STATUS_SUCCESS; 1002 } 1003 1004 return QDF_STATUS_E_FAILURE; 1005 } 1006 1007 /* 1008 * hal_rx_mpdu_get_addr4_6122(): API to get address4 of the mpdu 1009 * in the packet 1010 * 1011 * @buf: pointer to the start of RX PKT TLV header 1012 * @mac_addr: pointer to mac address 1013 * Return: success/failure 1014 */ 1015 static QDF_STATUS hal_rx_mpdu_get_addr4_6122(uint8_t *buf, uint8_t *mac_addr) 1016 { 1017 struct __attribute__((__packed__)) hal_addr4 { 1018 uint32_t ad4_31_0; 1019 uint16_t ad4_47_32; 1020 }; 1021 1022 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1023 struct rx_mpdu_start *mpdu_start = 1024 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1025 1026 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 1027 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; 1028 uint32_t mac_addr_ad4_valid; 1029 1030 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); 1031 1032 if (mac_addr_ad4_valid) { 1033 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); 1034 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); 1035 return QDF_STATUS_SUCCESS; 1036 } 1037 1038 return QDF_STATUS_E_FAILURE; 1039 } 1040 1041 /* 1042 * hal_rx_get_mpdu_sequence_control_valid_6122(): Get mpdu 1043 * sequence control valid 1044 * 1045 * @nbuf: Network buffer 1046 * Returns: value of sequence control valid field 1047 */ 1048 static uint8_t hal_rx_get_mpdu_sequence_control_valid_6122(uint8_t *buf) 1049 { 1050 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 1051 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 1052 1053 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); 1054 } 1055 1056 /** 1057 * hal_rx_is_unicast_6122: check packet is unicast frame or not. 1058 * 1059 * @ buf: pointer to rx pkt TLV. 1060 * 1061 * Return: true on unicast. 1062 */ 1063 static bool hal_rx_is_unicast_6122(uint8_t *buf) 1064 { 1065 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1066 struct rx_mpdu_start *mpdu_start = 1067 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1068 uint32_t grp_id; 1069 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 1070 1071 grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 1072 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_OFFSET)), 1073 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_MASK, 1074 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_LSB)); 1075 1076 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false; 1077 } 1078 1079 /** 1080 * hal_rx_tid_get_6122: get tid based on qos control valid. 1081 * @hal_soc_hdl: hal soc handle 1082 * @buf: pointer to rx pkt TLV. 1083 * 1084 * Return: tid 1085 */ 1086 static uint32_t hal_rx_tid_get_6122(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1087 { 1088 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1089 struct rx_mpdu_start *mpdu_start = 1090 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1091 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 1092 uint8_t qos_control_valid = 1093 (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 1094 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_OFFSET)), 1095 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_MASK, 1096 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_LSB)); 1097 1098 if (qos_control_valid) 1099 return hal_rx_mpdu_start_tid_get_6122(buf); 1100 1101 return HAL_RX_NON_QOS_TID; 1102 } 1103 1104 /** 1105 * hal_rx_hw_desc_get_ppduid_get_6122(): retrieve ppdu id 1106 * @rx_tlv_hdr: rx tlv header 1107 * @rxdma_dst_ring_desc: rxdma HW descriptor 1108 * 1109 * Return: ppdu id 1110 */ 1111 static uint32_t hal_rx_hw_desc_get_ppduid_get_6122(void *rx_tlv_hdr, 1112 void *rxdma_dst_ring_desc) 1113 { 1114 struct reo_entrance_ring *reo_ent = rxdma_dst_ring_desc; 1115 1116 return reo_ent->phy_ppdu_id; 1117 } 1118 1119 /** 1120 * hal_reo_status_get_header_6122 - Process reo desc info 1121 * @ring_desc: REO status ring descriptor 1122 * @b - tlv type info 1123 * @h1 - Pointer to hal_reo_status_header where info to be stored 1124 * 1125 * Return - none. 1126 * 1127 */ 1128 static void hal_reo_status_get_header_6122(hal_ring_desc_t ring_desc, int b, 1129 void *h1) 1130 { 1131 uint32_t *d = (uint32_t *)ring_desc; 1132 uint32_t val1 = 0; 1133 struct hal_reo_status_header *h = 1134 (struct hal_reo_status_header *)h1; 1135 1136 /* Offsets of descriptor fields defined in HW headers start 1137 * from the field after TLV header 1138 */ 1139 d += HAL_GET_NUM_DWORDS(sizeof(struct tlv_32_hdr)); 1140 1141 switch (b) { 1142 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1143 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, 1144 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1145 break; 1146 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1147 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, 1148 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1149 break; 1150 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1151 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, 1152 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1153 break; 1154 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1155 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, 1156 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1157 break; 1158 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1159 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, 1160 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1161 break; 1162 case HAL_REO_DESC_THRES_STATUS_TLV: 1163 val1 = 1164 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, 1165 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1166 break; 1167 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1168 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, 1169 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1170 break; 1171 default: 1172 qdf_nofl_err("ERROR: Unknown tlv\n"); 1173 break; 1174 } 1175 h->cmd_num = 1176 HAL_GET_FIELD( 1177 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, 1178 val1); 1179 h->exec_time = 1180 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1181 CMD_EXECUTION_TIME, val1); 1182 h->status = 1183 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1184 REO_CMD_EXECUTION_STATUS, val1); 1185 switch (b) { 1186 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1187 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, 1188 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1189 break; 1190 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1191 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, 1192 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1193 break; 1194 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1195 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, 1196 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1197 break; 1198 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1199 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, 1200 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1201 break; 1202 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1203 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, 1204 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1205 break; 1206 case HAL_REO_DESC_THRES_STATUS_TLV: 1207 val1 = 1208 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, 1209 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1210 break; 1211 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1212 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, 1213 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1214 break; 1215 default: 1216 qdf_nofl_err("ERROR: Unknown tlv\n"); 1217 break; 1218 } 1219 h->tstamp = 1220 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); 1221 } 1222 1223 /** 1224 * hal_rx_mpdu_start_mpdu_qos_control_valid_get_6122(): 1225 * Retrieve qos control valid bit from the tlv. 1226 * @buf: pointer to rx pkt TLV. 1227 * 1228 * Return: qos control value. 1229 */ 1230 static inline uint32_t 1231 hal_rx_mpdu_start_mpdu_qos_control_valid_get_6122(uint8_t *buf) 1232 { 1233 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1234 struct rx_mpdu_start *mpdu_start = 1235 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1236 1237 return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET( 1238 &mpdu_start->rx_mpdu_info_details); 1239 } 1240 1241 /** 1242 * hal_rx_msdu_end_sa_sw_peer_id_get_6122(): API to get the 1243 * sa_sw_peer_id from rx_msdu_end TLV 1244 * @buf: pointer to the start of RX PKT TLV headers 1245 * 1246 * Return: sa_sw_peer_id index 1247 */ 1248 static inline uint32_t 1249 hal_rx_msdu_end_sa_sw_peer_id_get_6122(uint8_t *buf) 1250 { 1251 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1252 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1253 1254 return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 1255 } 1256 1257 /** 1258 * hal_tx_desc_set_mesh_en_6122 - Set mesh_enable flag in Tx descriptor 1259 * @desc: Handle to Tx Descriptor 1260 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 1261 * enabling the interpretation of the 'Mesh Control Present' bit 1262 * (bit 8) of QoS Control (otherwise this bit is ignored), 1263 * For native WiFi frames, this indicates that a 'Mesh Control' field 1264 * is present between the header and the LLC. 1265 * 1266 * Return: void 1267 */ 1268 static inline 1269 void hal_tx_desc_set_mesh_en_6122(void *desc, uint8_t en) 1270 { 1271 HAL_SET_FLD(desc, TCL_DATA_CMD_5, MESH_ENABLE) |= 1272 HAL_TX_SM(TCL_DATA_CMD_5, MESH_ENABLE, en); 1273 } 1274 1275 static 1276 void *hal_rx_msdu0_buffer_addr_lsb_6122(void *link_desc_va) 1277 { 1278 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 1279 } 1280 1281 static 1282 void *hal_rx_msdu_desc_info_ptr_get_6122(void *msdu0) 1283 { 1284 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 1285 } 1286 1287 static 1288 void *hal_ent_mpdu_desc_info_6122(void *ent_ring_desc) 1289 { 1290 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 1291 } 1292 1293 static 1294 void *hal_dst_mpdu_desc_info_6122(void *dst_ring_desc) 1295 { 1296 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 1297 } 1298 1299 static 1300 uint8_t hal_rx_get_fc_valid_6122(uint8_t *buf) 1301 { 1302 return HAL_RX_GET_FC_VALID(buf); 1303 } 1304 1305 static uint8_t hal_rx_get_to_ds_flag_6122(uint8_t *buf) 1306 { 1307 return HAL_RX_GET_TO_DS_FLAG(buf); 1308 } 1309 1310 static uint8_t hal_rx_get_mac_addr2_valid_6122(uint8_t *buf) 1311 { 1312 return HAL_RX_GET_MAC_ADDR2_VALID(buf); 1313 } 1314 1315 static uint8_t hal_rx_get_filter_category_6122(uint8_t *buf) 1316 { 1317 return HAL_RX_GET_FILTER_CATEGORY(buf); 1318 } 1319 1320 static uint32_t 1321 hal_rx_get_ppdu_id_6122(uint8_t *buf) 1322 { 1323 struct rx_mpdu_info *rx_mpdu_info; 1324 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)buf; 1325 1326 rx_mpdu_info = 1327 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 1328 1329 return HAL_RX_GET_PPDU_ID(rx_mpdu_info); 1330 } 1331 1332 /** 1333 * hal_reo_config_6122(): Set reo config parameters 1334 * @soc: hal soc handle 1335 * @reg_val: value to be set 1336 * @reo_params: reo parameters 1337 * 1338 * Return: void 1339 */ 1340 static void 1341 hal_reo_config_6122(struct hal_soc *soc, 1342 uint32_t reg_val, 1343 struct hal_reo_params *reo_params) 1344 { 1345 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 1346 } 1347 1348 /** 1349 * hal_rx_msdu_desc_info_get_ptr_6122() - Get msdu desc info ptr 1350 * @msdu_details_ptr - Pointer to msdu_details_ptr 1351 * 1352 * Return - Pointer to rx_msdu_desc_info structure. 1353 * 1354 */ 1355 static void *hal_rx_msdu_desc_info_get_ptr_6122(void *msdu_details_ptr) 1356 { 1357 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 1358 } 1359 1360 /** 1361 * hal_rx_link_desc_msdu0_ptr_6122 - Get pointer to rx_msdu details 1362 * @link_desc - Pointer to link desc 1363 * 1364 * Return - Pointer to rx_msdu_details structure 1365 * 1366 */ 1367 static void *hal_rx_link_desc_msdu0_ptr_6122(void *link_desc) 1368 { 1369 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 1370 } 1371 1372 /** 1373 * hal_rx_msdu_flow_idx_get_6122: API to get flow index 1374 * from rx_msdu_end TLV 1375 * @buf: pointer to the start of RX PKT TLV headers 1376 * 1377 * Return: flow index value from MSDU END TLV 1378 */ 1379 static inline uint32_t hal_rx_msdu_flow_idx_get_6122(uint8_t *buf) 1380 { 1381 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1382 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1383 1384 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 1385 } 1386 1387 /** 1388 * hal_rx_msdu_flow_idx_invalid_6122: API to get flow index invalid 1389 * from rx_msdu_end TLV 1390 * @buf: pointer to the start of RX PKT TLV headers 1391 * 1392 * Return: flow index invalid value from MSDU END TLV 1393 */ 1394 static bool hal_rx_msdu_flow_idx_invalid_6122(uint8_t *buf) 1395 { 1396 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1397 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1398 1399 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 1400 } 1401 1402 /** 1403 * hal_rx_msdu_flow_idx_timeout_6122: API to get flow index timeout 1404 * from rx_msdu_end TLV 1405 * @buf: pointer to the start of RX PKT TLV headers 1406 * 1407 * Return: flow index timeout value from MSDU END TLV 1408 */ 1409 static bool hal_rx_msdu_flow_idx_timeout_6122(uint8_t *buf) 1410 { 1411 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1412 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1413 1414 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 1415 } 1416 1417 /** 1418 * hal_rx_msdu_fse_metadata_get_6122: API to get FSE metadata 1419 * from rx_msdu_end TLV 1420 * @buf: pointer to the start of RX PKT TLV headers 1421 * 1422 * Return: fse metadata value from MSDU END TLV 1423 */ 1424 static uint32_t hal_rx_msdu_fse_metadata_get_6122(uint8_t *buf) 1425 { 1426 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1427 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1428 1429 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end); 1430 } 1431 1432 /** 1433 * hal_rx_msdu_cce_metadata_get_6122: API to get CCE metadata 1434 * from rx_msdu_end TLV 1435 * @buf: pointer to the start of RX PKT TLV headers 1436 * 1437 * Return: cce_metadata 1438 */ 1439 static uint16_t 1440 hal_rx_msdu_cce_metadata_get_6122(uint8_t *buf) 1441 { 1442 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1443 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1444 1445 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end); 1446 } 1447 1448 /** 1449 * hal_rx_msdu_get_flow_params_6122: API to get flow index, flow index invalid 1450 * and flow index timeout from rx_msdu_end TLV 1451 * @buf: pointer to the start of RX PKT TLV headers 1452 * @flow_invalid: pointer to return value of flow_idx_valid 1453 * @flow_timeout: pointer to return value of flow_idx_timeout 1454 * @flow_index: pointer to return value of flow_idx 1455 * 1456 * Return: none 1457 */ 1458 static inline void 1459 hal_rx_msdu_get_flow_params_6122(uint8_t *buf, 1460 bool *flow_invalid, 1461 bool *flow_timeout, 1462 uint32_t *flow_index) 1463 { 1464 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1465 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1466 1467 *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 1468 *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 1469 *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 1470 } 1471 1472 /** 1473 * hal_rx_tlv_get_tcp_chksum_6122() - API to get tcp checksum 1474 * @buf: rx_tlv_hdr 1475 * 1476 * Return: tcp checksum 1477 */ 1478 static uint16_t 1479 hal_rx_tlv_get_tcp_chksum_6122(uint8_t *buf) 1480 { 1481 return HAL_RX_TLV_GET_TCP_CHKSUM(buf); 1482 } 1483 1484 /** 1485 * hal_rx_get_rx_sequence_6122(): Function to retrieve rx sequence number 1486 * 1487 * @nbuf: Network buffer 1488 * Returns: rx sequence number 1489 */ 1490 static 1491 uint16_t hal_rx_get_rx_sequence_6122(uint8_t *buf) 1492 { 1493 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 1494 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 1495 1496 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info); 1497 } 1498 1499 /** 1500 * hal_get_window_address_6122(): Function to get hp/tp address 1501 * @hal_soc: Pointer to hal_soc 1502 * @addr: address offset of register 1503 * 1504 * Return: modified address offset of register 1505 */ 1506 #define SPRUCE_SEQ_WCSS_UMAC_OFFSET 0x00a00000 1507 #define SPRUCE_CE_WFSS_CE_REG_BASE 0x3B80000 1508 static inline qdf_iomem_t hal_get_window_address_6122(struct hal_soc *hal_soc, 1509 qdf_iomem_t addr) 1510 { 1511 uint32_t offset = addr - hal_soc->dev_base_addr; 1512 qdf_iomem_t new_offset; 1513 1514 /* 1515 * If offset lies within DP register range, use 3rd window to write 1516 * into DP region. 1517 */ 1518 if ((offset ^ SPRUCE_SEQ_WCSS_UMAC_OFFSET) < WINDOW_RANGE_MASK) { 1519 new_offset = (hal_soc->dev_base_addr + (3 * WINDOW_START) + 1520 (offset & WINDOW_RANGE_MASK)); 1521 /* 1522 * If offset lies within CE register range, use 2nd window to write 1523 * into CE region. 1524 */ 1525 } else if ((offset ^ SPRUCE_CE_WFSS_CE_REG_BASE) < WINDOW_RANGE_MASK) { 1526 new_offset = (hal_soc->dev_base_addr + (2 * WINDOW_START) + 1527 (offset & WINDOW_RANGE_MASK)); 1528 } else { 1529 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 1530 "%s: ERROR: Accessing Wrong register\n", __func__); 1531 qdf_assert_always(0); 1532 return 0; 1533 } 1534 return new_offset; 1535 } 1536 1537 static inline void hal_write_window_register(struct hal_soc *hal_soc) 1538 { 1539 /* Write value into window configuration register */ 1540 qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_REG_ADDRESS, 1541 WINDOW_CONFIGURATION_VALUE_6122); 1542 } 1543 1544 /** 1545 * hal_rx_msdu_packet_metadata_get_6122(): API to get the 1546 * msdu information from rx_msdu_end TLV 1547 * 1548 * @ buf: pointer to the start of RX PKT TLV headers 1549 * @ hal_rx_msdu_metadata: pointer to the msdu info structure 1550 */ 1551 static void 1552 hal_rx_msdu_packet_metadata_get_6122(uint8_t *buf, 1553 void *msdu_pkt_metadata) 1554 { 1555 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1556 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1557 struct hal_rx_msdu_metadata *msdu_metadata = 1558 (struct hal_rx_msdu_metadata *)msdu_pkt_metadata; 1559 1560 msdu_metadata->l3_hdr_pad = 1561 HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 1562 msdu_metadata->sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 1563 msdu_metadata->da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 1564 msdu_metadata->sa_sw_peer_id = 1565 HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 1566 } 1567 1568 /** 1569 * hal_rx_flow_setup_fse_6122() - Setup a flow search entry in HW FST 1570 * @fst: Pointer to the Rx Flow Search Table 1571 * @table_offset: offset into the table where the flow is to be setup 1572 * @flow: Flow Parameters 1573 * 1574 * Return: Success/Failure 1575 */ 1576 static void * 1577 hal_rx_flow_setup_fse_6122(uint8_t *rx_fst, uint32_t table_offset, 1578 uint8_t *rx_flow) 1579 { 1580 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 1581 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 1582 uint8_t *fse; 1583 bool fse_valid; 1584 1585 if (table_offset >= fst->max_entries) { 1586 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 1587 "HAL FSE table offset %u exceeds max entries %u", 1588 table_offset, fst->max_entries); 1589 return NULL; 1590 } 1591 1592 fse = (uint8_t *)fst->base_vaddr + 1593 (table_offset * HAL_RX_FST_ENTRY_SIZE); 1594 1595 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1596 1597 if (fse_valid) { 1598 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 1599 "HAL FSE %pK already valid", fse); 1600 return NULL; 1601 } 1602 1603 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96) = 1604 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96, 1605 qdf_htonl(flow->tuple_info.src_ip_127_96)); 1606 1607 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64) = 1608 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64, 1609 qdf_htonl(flow->tuple_info.src_ip_95_64)); 1610 1611 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32) = 1612 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32, 1613 qdf_htonl(flow->tuple_info.src_ip_63_32)); 1614 1615 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0) = 1616 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0, 1617 qdf_htonl(flow->tuple_info.src_ip_31_0)); 1618 1619 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96) = 1620 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96, 1621 qdf_htonl(flow->tuple_info.dest_ip_127_96)); 1622 1623 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64) = 1624 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64, 1625 qdf_htonl(flow->tuple_info.dest_ip_95_64)); 1626 1627 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32) = 1628 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32, 1629 qdf_htonl(flow->tuple_info.dest_ip_63_32)); 1630 1631 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0) = 1632 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0, 1633 qdf_htonl(flow->tuple_info.dest_ip_31_0)); 1634 1635 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT); 1636 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT) |= 1637 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, DEST_PORT, 1638 (flow->tuple_info.dest_port)); 1639 1640 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT); 1641 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT) |= 1642 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, SRC_PORT, 1643 (flow->tuple_info.src_port)); 1644 1645 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL); 1646 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL) |= 1647 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL, 1648 flow->tuple_info.l4_protocol); 1649 1650 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER); 1651 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER) |= 1652 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER, 1653 flow->reo_destination_handler); 1654 1655 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1656 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID) |= 1657 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, VALID, 1); 1658 1659 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA); 1660 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA) = 1661 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_10, METADATA, 1662 flow->fse_metadata); 1663 1664 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION); 1665 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION) |= 1666 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, 1667 REO_DESTINATION_INDICATION, 1668 flow->reo_destination_indication); 1669 1670 /* Reset all the other fields in FSE */ 1671 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, RESERVED_9); 1672 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, MSDU_DROP); 1673 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_COUNT); 1674 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_12, MSDU_BYTE_COUNT); 1675 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_13, TIMESTAMP); 1676 1677 return fse; 1678 } 1679 1680 void hal_compute_reo_remap_ix2_ix3_6122(uint32_t *ring, uint32_t num_rings, 1681 uint32_t *remap1, uint32_t *remap2) 1682 { 1683 switch (num_rings) { 1684 case 1: 1685 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1686 HAL_REO_REMAP_IX2(ring[0], 17) | 1687 HAL_REO_REMAP_IX2(ring[0], 18) | 1688 HAL_REO_REMAP_IX2(ring[0], 19) | 1689 HAL_REO_REMAP_IX2(ring[0], 20) | 1690 HAL_REO_REMAP_IX2(ring[0], 21) | 1691 HAL_REO_REMAP_IX2(ring[0], 22) | 1692 HAL_REO_REMAP_IX2(ring[0], 23); 1693 1694 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1695 HAL_REO_REMAP_IX3(ring[0], 25) | 1696 HAL_REO_REMAP_IX3(ring[0], 26) | 1697 HAL_REO_REMAP_IX3(ring[0], 27) | 1698 HAL_REO_REMAP_IX3(ring[0], 28) | 1699 HAL_REO_REMAP_IX3(ring[0], 29) | 1700 HAL_REO_REMAP_IX3(ring[0], 30) | 1701 HAL_REO_REMAP_IX3(ring[0], 31); 1702 break; 1703 case 2: 1704 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1705 HAL_REO_REMAP_IX2(ring[0], 17) | 1706 HAL_REO_REMAP_IX2(ring[1], 18) | 1707 HAL_REO_REMAP_IX2(ring[1], 19) | 1708 HAL_REO_REMAP_IX2(ring[0], 20) | 1709 HAL_REO_REMAP_IX2(ring[0], 21) | 1710 HAL_REO_REMAP_IX2(ring[1], 22) | 1711 HAL_REO_REMAP_IX2(ring[1], 23); 1712 1713 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1714 HAL_REO_REMAP_IX3(ring[0], 25) | 1715 HAL_REO_REMAP_IX3(ring[1], 26) | 1716 HAL_REO_REMAP_IX3(ring[1], 27) | 1717 HAL_REO_REMAP_IX3(ring[0], 28) | 1718 HAL_REO_REMAP_IX3(ring[0], 29) | 1719 HAL_REO_REMAP_IX3(ring[1], 30) | 1720 HAL_REO_REMAP_IX3(ring[1], 31); 1721 break; 1722 case 3: 1723 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1724 HAL_REO_REMAP_IX2(ring[1], 17) | 1725 HAL_REO_REMAP_IX2(ring[2], 18) | 1726 HAL_REO_REMAP_IX2(ring[0], 19) | 1727 HAL_REO_REMAP_IX2(ring[1], 20) | 1728 HAL_REO_REMAP_IX2(ring[2], 21) | 1729 HAL_REO_REMAP_IX2(ring[0], 22) | 1730 HAL_REO_REMAP_IX2(ring[1], 23); 1731 1732 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) | 1733 HAL_REO_REMAP_IX3(ring[0], 25) | 1734 HAL_REO_REMAP_IX3(ring[1], 26) | 1735 HAL_REO_REMAP_IX3(ring[2], 27) | 1736 HAL_REO_REMAP_IX3(ring[0], 28) | 1737 HAL_REO_REMAP_IX3(ring[1], 29) | 1738 HAL_REO_REMAP_IX3(ring[2], 30) | 1739 HAL_REO_REMAP_IX3(ring[0], 31); 1740 break; 1741 case 4: 1742 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1743 HAL_REO_REMAP_IX2(ring[1], 17) | 1744 HAL_REO_REMAP_IX2(ring[2], 18) | 1745 HAL_REO_REMAP_IX2(ring[3], 19) | 1746 HAL_REO_REMAP_IX2(ring[0], 20) | 1747 HAL_REO_REMAP_IX2(ring[1], 21) | 1748 HAL_REO_REMAP_IX2(ring[2], 22) | 1749 HAL_REO_REMAP_IX2(ring[3], 23); 1750 1751 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1752 HAL_REO_REMAP_IX3(ring[1], 25) | 1753 HAL_REO_REMAP_IX3(ring[2], 26) | 1754 HAL_REO_REMAP_IX3(ring[3], 27) | 1755 HAL_REO_REMAP_IX3(ring[0], 28) | 1756 HAL_REO_REMAP_IX3(ring[1], 29) | 1757 HAL_REO_REMAP_IX3(ring[2], 30) | 1758 HAL_REO_REMAP_IX3(ring[3], 31); 1759 break; 1760 } 1761 } 1762 1763 static void hal_hw_txrx_ops_attach_qcn6122(struct hal_soc *hal_soc) 1764 { 1765 1766 /* init and setup */ 1767 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic; 1768 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic; 1769 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic; 1770 hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_li; 1771 hal_soc->ops->hal_get_window_address = hal_get_window_address_6122; 1772 1773 /* tx */ 1774 hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id = 1775 hal_tx_desc_set_dscp_tid_table_id_6122; 1776 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_6122; 1777 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_6122; 1778 hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_6122; 1779 hal_soc->ops->hal_tx_desc_set_buf_addr = 1780 hal_tx_desc_set_buf_addr_generic_li; 1781 hal_soc->ops->hal_tx_desc_set_search_type = 1782 hal_tx_desc_set_search_type_generic_li; 1783 hal_soc->ops->hal_tx_desc_set_search_index = 1784 hal_tx_desc_set_search_index_generic_li; 1785 hal_soc->ops->hal_tx_desc_set_cache_set_num = 1786 hal_tx_desc_set_cache_set_num_generic_li; 1787 hal_soc->ops->hal_tx_comp_get_status = 1788 hal_tx_comp_get_status_generic_li; 1789 hal_soc->ops->hal_tx_comp_get_release_reason = 1790 hal_tx_comp_get_release_reason_generic_li; 1791 hal_soc->ops->hal_get_wbm_internal_error = 1792 hal_get_wbm_internal_error_generic_li; 1793 hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_6122; 1794 hal_soc->ops->hal_tx_init_cmd_credit_ring = 1795 hal_tx_init_cmd_credit_ring_6122; 1796 1797 /* rx */ 1798 hal_soc->ops->hal_rx_msdu_start_nss_get = 1799 hal_rx_msdu_start_nss_get_6122; 1800 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status = 1801 hal_rx_mon_hw_desc_get_mpdu_status_6122; 1802 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_6122; 1803 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv = 1804 hal_rx_proc_phyrx_other_receive_info_tlv_6122; 1805 hal_soc->ops->hal_rx_dump_msdu_start_tlv = 1806 hal_rx_dump_msdu_start_tlv_6122; 1807 hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_6122; 1808 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_6122; 1809 hal_soc->ops->hal_rx_mpdu_start_tid_get = 1810 hal_rx_mpdu_start_tid_get_6122; 1811 hal_soc->ops->hal_rx_msdu_start_reception_type_get = 1812 hal_rx_msdu_start_reception_type_get_6122; 1813 hal_soc->ops->hal_rx_msdu_end_da_idx_get = 1814 hal_rx_msdu_end_da_idx_get_6122; 1815 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = 1816 hal_rx_msdu_desc_info_get_ptr_6122; 1817 hal_soc->ops->hal_rx_link_desc_msdu0_ptr = 1818 hal_rx_link_desc_msdu0_ptr_6122; 1819 hal_soc->ops->hal_reo_status_get_header = 1820 hal_reo_status_get_header_6122; 1821 hal_soc->ops->hal_rx_status_get_tlv_info = 1822 hal_rx_status_get_tlv_info_generic_li; 1823 hal_soc->ops->hal_rx_wbm_err_info_get = 1824 hal_rx_wbm_err_info_get_generic_li; 1825 hal_soc->ops->hal_rx_dump_mpdu_start_tlv = 1826 hal_rx_dump_mpdu_start_tlv_generic_li; 1827 1828 hal_soc->ops->hal_tx_set_pcp_tid_map = 1829 hal_tx_set_pcp_tid_map_generic_li; 1830 hal_soc->ops->hal_tx_update_pcp_tid_map = 1831 hal_tx_update_pcp_tid_generic_li; 1832 hal_soc->ops->hal_tx_set_tidmap_prty = 1833 hal_tx_update_tidmap_prty_generic_li; 1834 hal_soc->ops->hal_rx_get_rx_fragment_number = 1835 hal_rx_get_rx_fragment_number_6122; 1836 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = 1837 hal_rx_msdu_end_da_is_mcbc_get_6122; 1838 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = 1839 hal_rx_msdu_end_sa_is_valid_get_6122; 1840 hal_soc->ops->hal_rx_msdu_end_sa_idx_get = 1841 hal_rx_msdu_end_sa_idx_get_6122; 1842 hal_soc->ops->hal_rx_desc_is_first_msdu = 1843 hal_rx_desc_is_first_msdu_6122; 1844 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get = 1845 hal_rx_msdu_end_l3_hdr_padding_get_6122; 1846 hal_soc->ops->hal_rx_encryption_info_valid = 1847 hal_rx_encryption_info_valid_6122; 1848 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_6122; 1849 hal_soc->ops->hal_rx_msdu_end_first_msdu_get = 1850 hal_rx_msdu_end_first_msdu_get_6122; 1851 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = 1852 hal_rx_msdu_end_da_is_valid_get_6122; 1853 hal_soc->ops->hal_rx_msdu_end_last_msdu_get = 1854 hal_rx_msdu_end_last_msdu_get_6122; 1855 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = 1856 hal_rx_get_mpdu_mac_ad4_valid_6122; 1857 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get = 1858 hal_rx_mpdu_start_sw_peer_id_get_6122; 1859 hal_soc->ops->hal_rx_tlv_peer_meta_data_get = 1860 hal_rx_mpdu_peer_meta_data_get_li; 1861 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_6122; 1862 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_6122; 1863 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid = 1864 hal_rx_get_mpdu_frame_control_valid_6122; 1865 hal_soc->ops->hal_rx_get_frame_ctrl_field = 1866 hal_rx_get_mpdu_frame_control_field_6122; 1867 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_6122; 1868 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_6122; 1869 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_6122; 1870 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_6122; 1871 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid = 1872 hal_rx_get_mpdu_sequence_control_valid_6122; 1873 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_6122; 1874 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_6122; 1875 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = 1876 hal_rx_hw_desc_get_ppduid_get_6122; 1877 hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get = 1878 hal_rx_mpdu_start_mpdu_qos_control_valid_get_6122; 1879 hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get = 1880 hal_rx_msdu_end_sa_sw_peer_id_get_6122; 1881 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = 1882 hal_rx_msdu0_buffer_addr_lsb_6122; 1883 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = 1884 hal_rx_msdu_desc_info_ptr_get_6122; 1885 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_6122; 1886 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_6122; 1887 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_6122; 1888 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_6122; 1889 hal_soc->ops->hal_rx_get_mac_addr2_valid = 1890 hal_rx_get_mac_addr2_valid_6122; 1891 hal_soc->ops->hal_rx_get_filter_category = 1892 hal_rx_get_filter_category_6122; 1893 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_6122; 1894 hal_soc->ops->hal_reo_config = hal_reo_config_6122; 1895 hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_6122; 1896 hal_soc->ops->hal_rx_msdu_flow_idx_invalid = 1897 hal_rx_msdu_flow_idx_invalid_6122; 1898 hal_soc->ops->hal_rx_msdu_flow_idx_timeout = 1899 hal_rx_msdu_flow_idx_timeout_6122; 1900 hal_soc->ops->hal_rx_msdu_fse_metadata_get = 1901 hal_rx_msdu_fse_metadata_get_6122; 1902 hal_soc->ops->hal_rx_msdu_cce_match_get = 1903 hal_rx_msdu_cce_match_get_li; 1904 hal_soc->ops->hal_rx_msdu_cce_metadata_get = 1905 hal_rx_msdu_cce_metadata_get_6122; 1906 hal_soc->ops->hal_rx_msdu_get_flow_params = 1907 hal_rx_msdu_get_flow_params_6122; 1908 hal_soc->ops->hal_rx_tlv_get_tcp_chksum = 1909 hal_rx_tlv_get_tcp_chksum_6122; 1910 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_6122; 1911 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) 1912 hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_6122; 1913 hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_6122; 1914 #endif 1915 /* rx - msdu fast path info fields */ 1916 hal_soc->ops->hal_rx_msdu_packet_metadata_get = 1917 hal_rx_msdu_packet_metadata_get_6122; 1918 hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid = 1919 hal_rx_mpdu_start_tlv_tag_valid_6122; 1920 hal_soc->ops->hal_rx_sw_mon_desc_info_get = 1921 hal_rx_sw_mon_desc_info_get_6122; 1922 hal_soc->ops->hal_rx_wbm_err_msdu_continuation_get = 1923 hal_rx_wbm_err_msdu_continuation_get_6122; 1924 1925 /* rx - TLV struct offsets */ 1926 hal_soc->ops->hal_rx_msdu_end_offset_get = 1927 hal_rx_msdu_end_offset_get_generic; 1928 hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic; 1929 hal_soc->ops->hal_rx_msdu_start_offset_get = 1930 hal_rx_msdu_start_offset_get_generic; 1931 hal_soc->ops->hal_rx_mpdu_start_offset_get = 1932 hal_rx_mpdu_start_offset_get_generic; 1933 hal_soc->ops->hal_rx_mpdu_end_offset_get = 1934 hal_rx_mpdu_end_offset_get_generic; 1935 #ifndef NO_RX_PKT_HDR_TLV 1936 hal_soc->ops->hal_rx_pkt_tlv_offset_get = 1937 hal_rx_pkt_tlv_offset_get_generic; 1938 #endif 1939 hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_6122; 1940 hal_soc->ops->hal_rx_flow_get_tuple_info = 1941 hal_rx_flow_get_tuple_info_li; 1942 hal_soc->ops->hal_rx_flow_delete_entry = 1943 hal_rx_flow_delete_entry_li; 1944 hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_li; 1945 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = 1946 hal_compute_reo_remap_ix2_ix3_6122; 1947 hal_soc->ops->hal_setup_link_idle_list = 1948 hal_setup_link_idle_list_generic_li; 1949 hal_soc->ops->hal_compute_reo_remap_ix0 = NULL; 1950 hal_soc->ops->hal_rx_tlv_msdu_len_get = 1951 hal_rx_msdu_start_get_len_6122; 1952 }; 1953 1954 struct hal_hw_srng_config hw_srng_table_6122[] = { 1955 /* TODO: max_rings can populated by querying HW capabilities */ 1956 { /* REO_DST */ 1957 .start_ring_id = HAL_SRNG_REO2SW1, 1958 .max_rings = 4, 1959 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1960 .lmac_ring = FALSE, 1961 .ring_dir = HAL_SRNG_DST_RING, 1962 .reg_start = { 1963 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 1964 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1965 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 1966 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1967 }, 1968 .reg_size = { 1969 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 1970 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 1971 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 1972 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 1973 }, 1974 .max_size = 1975 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 1976 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 1977 }, 1978 { /* REO_EXCEPTION */ 1979 /* Designating REO2TCL ring as exception ring. This ring is 1980 * similar to other REO2SW rings though it is named as REO2TCL. 1981 * Any of theREO2SW rings can be used as exception ring. 1982 */ 1983 .start_ring_id = HAL_SRNG_REO2TCL, 1984 .max_rings = 1, 1985 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1986 .lmac_ring = FALSE, 1987 .ring_dir = HAL_SRNG_DST_RING, 1988 .reg_start = { 1989 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 1990 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1991 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 1992 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1993 }, 1994 /* Single ring - provide ring size if multiple rings of this 1995 * type are supported 1996 */ 1997 .reg_size = {}, 1998 .max_size = 1999 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 2000 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 2001 }, 2002 { /* REO_REINJECT */ 2003 .start_ring_id = HAL_SRNG_SW2REO, 2004 .max_rings = 1, 2005 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2006 .lmac_ring = FALSE, 2007 .ring_dir = HAL_SRNG_SRC_RING, 2008 .reg_start = { 2009 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 2010 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2011 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 2012 SEQ_WCSS_UMAC_REO_REG_OFFSET) 2013 }, 2014 /* Single ring - provide ring size if multiple rings of this 2015 * type are supported 2016 */ 2017 .reg_size = {}, 2018 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 2019 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 2020 }, 2021 { /* REO_CMD */ 2022 .start_ring_id = HAL_SRNG_REO_CMD, 2023 .max_rings = 1, 2024 .entry_size = (sizeof(struct tlv_32_hdr) + 2025 sizeof(struct reo_get_queue_stats)) >> 2, 2026 .lmac_ring = FALSE, 2027 .ring_dir = HAL_SRNG_SRC_RING, 2028 .reg_start = { 2029 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 2030 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2031 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 2032 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2033 }, 2034 /* Single ring - provide ring size if multiple rings of this 2035 * type are supported 2036 */ 2037 .reg_size = {}, 2038 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 2039 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 2040 }, 2041 { /* REO_STATUS */ 2042 .start_ring_id = HAL_SRNG_REO_STATUS, 2043 .max_rings = 1, 2044 .entry_size = (sizeof(struct tlv_32_hdr) + 2045 sizeof(struct reo_get_queue_stats_status)) >> 2, 2046 .lmac_ring = FALSE, 2047 .ring_dir = HAL_SRNG_DST_RING, 2048 .reg_start = { 2049 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 2050 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2051 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 2052 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2053 }, 2054 /* Single ring - provide ring size if multiple rings of this 2055 * type are supported 2056 */ 2057 .reg_size = {}, 2058 .max_size = 2059 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 2060 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 2061 }, 2062 { /* TCL_DATA */ 2063 .start_ring_id = HAL_SRNG_SW2TCL1, 2064 .max_rings = 3, 2065 .entry_size = (sizeof(struct tlv_32_hdr) + 2066 sizeof(struct tcl_data_cmd)) >> 2, 2067 .lmac_ring = FALSE, 2068 .ring_dir = HAL_SRNG_SRC_RING, 2069 .reg_start = { 2070 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 2071 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2072 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 2073 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2074 }, 2075 .reg_size = { 2076 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 2077 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 2078 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 2079 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 2080 }, 2081 .max_size = 2082 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 2083 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 2084 }, 2085 { /* TCL_CMD/CREDIT */ 2086 /* qca8074v2 and qcn6122 uses this ring for data commands */ 2087 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 2088 .max_rings = 1, 2089 .entry_size = (sizeof(struct tlv_32_hdr) + 2090 sizeof(struct tcl_data_cmd)) >> 2, 2091 .lmac_ring = FALSE, 2092 .ring_dir = HAL_SRNG_SRC_RING, 2093 .reg_start = { 2094 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR( 2095 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2096 HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR( 2097 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2098 }, 2099 /* Single ring - provide ring size if multiple rings of this 2100 * type are supported 2101 */ 2102 .reg_size = {}, 2103 .max_size = 2104 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >> 2105 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT, 2106 }, 2107 { /* TCL_STATUS */ 2108 .start_ring_id = HAL_SRNG_TCL_STATUS, 2109 .max_rings = 1, 2110 .entry_size = (sizeof(struct tlv_32_hdr) + 2111 sizeof(struct tcl_status_ring)) >> 2, 2112 .lmac_ring = FALSE, 2113 .ring_dir = HAL_SRNG_DST_RING, 2114 .reg_start = { 2115 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 2116 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2117 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 2118 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2119 }, 2120 /* Single ring - provide ring size if multiple rings of this 2121 * type are supported 2122 */ 2123 .reg_size = {}, 2124 .max_size = 2125 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 2126 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 2127 }, 2128 { /* CE_SRC */ 2129 .start_ring_id = HAL_SRNG_CE_0_SRC, 2130 .max_rings = 12, 2131 .entry_size = sizeof(struct ce_src_desc) >> 2, 2132 .lmac_ring = FALSE, 2133 .ring_dir = HAL_SRNG_SRC_RING, 2134 .reg_start = { 2135 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 2136 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 2137 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 2138 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 2139 }, 2140 .reg_size = { 2141 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 2142 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 2143 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 2144 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 2145 }, 2146 .max_size = 2147 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 2148 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 2149 }, 2150 { /* CE_DST */ 2151 .start_ring_id = HAL_SRNG_CE_0_DST, 2152 .max_rings = 12, 2153 .entry_size = 8 >> 2, 2154 /*TODO: entry_size above should actually be 2155 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 2156 * of struct ce_dst_desc in HW header files 2157 */ 2158 .lmac_ring = FALSE, 2159 .ring_dir = HAL_SRNG_SRC_RING, 2160 .reg_start = { 2161 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 2162 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2163 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 2164 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2165 }, 2166 .reg_size = { 2167 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2168 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2169 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2170 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2171 }, 2172 .max_size = 2173 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 2174 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 2175 }, 2176 { /* CE_DST_STATUS */ 2177 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 2178 .max_rings = 12, 2179 .entry_size = sizeof(struct ce_stat_desc) >> 2, 2180 .lmac_ring = FALSE, 2181 .ring_dir = HAL_SRNG_DST_RING, 2182 .reg_start = { 2183 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 2184 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2185 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 2186 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2187 }, 2188 /* TODO: check destination status ring registers */ 2189 .reg_size = { 2190 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2191 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2192 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2193 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2194 }, 2195 .max_size = 2196 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 2197 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 2198 }, 2199 { /* WBM_IDLE_LINK */ 2200 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 2201 .max_rings = 1, 2202 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 2203 .lmac_ring = FALSE, 2204 .ring_dir = HAL_SRNG_SRC_RING, 2205 .reg_start = { 2206 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2207 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2208 }, 2209 /* Single ring - provide ring size if multiple rings of this 2210 * type are supported 2211 */ 2212 .reg_size = {}, 2213 .max_size = 2214 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 2215 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 2216 }, 2217 { /* SW2WBM_RELEASE */ 2218 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 2219 .max_rings = 1, 2220 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2221 .lmac_ring = FALSE, 2222 .ring_dir = HAL_SRNG_SRC_RING, 2223 .reg_start = { 2224 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2225 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2226 }, 2227 /* Single ring - provide ring size if multiple rings of this 2228 * type are supported 2229 */ 2230 .reg_size = {}, 2231 .max_size = 2232 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2233 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2234 }, 2235 { /* WBM2SW_RELEASE */ 2236 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 2237 .max_rings = 5, 2238 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2239 .lmac_ring = FALSE, 2240 .ring_dir = HAL_SRNG_DST_RING, 2241 .reg_start = { 2242 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2243 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2244 }, 2245 .reg_size = { 2246 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 2247 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2248 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 2249 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2250 }, 2251 .max_size = 2252 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2253 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2254 }, 2255 { /* RXDMA_BUF */ 2256 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 2257 #ifdef IPA_OFFLOAD 2258 .max_rings = 3, 2259 #else 2260 .max_rings = 2, 2261 #endif 2262 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2263 .lmac_ring = TRUE, 2264 .ring_dir = HAL_SRNG_SRC_RING, 2265 /* reg_start is not set because LMAC rings are not accessed 2266 * from host 2267 */ 2268 .reg_start = {}, 2269 .reg_size = {}, 2270 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2271 }, 2272 { /* RXDMA_DST */ 2273 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 2274 .max_rings = 1, 2275 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2276 .lmac_ring = TRUE, 2277 .ring_dir = HAL_SRNG_DST_RING, 2278 /* reg_start is not set because LMAC rings are not accessed 2279 * from host 2280 */ 2281 .reg_start = {}, 2282 .reg_size = {}, 2283 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2284 }, 2285 { /* RXDMA_MONITOR_BUF */ 2286 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 2287 .max_rings = 1, 2288 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2289 .lmac_ring = TRUE, 2290 .ring_dir = HAL_SRNG_SRC_RING, 2291 /* reg_start is not set because LMAC rings are not accessed 2292 * from host 2293 */ 2294 .reg_start = {}, 2295 .reg_size = {}, 2296 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2297 }, 2298 { /* RXDMA_MONITOR_STATUS */ 2299 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 2300 .max_rings = 1, 2301 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2302 .lmac_ring = TRUE, 2303 .ring_dir = HAL_SRNG_SRC_RING, 2304 /* reg_start is not set because LMAC rings are not accessed 2305 * from host 2306 */ 2307 .reg_start = {}, 2308 .reg_size = {}, 2309 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2310 }, 2311 { /* RXDMA_MONITOR_DST */ 2312 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 2313 .max_rings = 1, 2314 .entry_size = sizeof(struct sw_monitor_ring) >> 2, 2315 .lmac_ring = TRUE, 2316 .ring_dir = HAL_SRNG_DST_RING, 2317 /* reg_start is not set because LMAC rings are not accessed 2318 * from host 2319 */ 2320 .reg_start = {}, 2321 .reg_size = {}, 2322 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2323 }, 2324 { /* RXDMA_MONITOR_DESC */ 2325 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 2326 .max_rings = 1, 2327 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2328 .lmac_ring = TRUE, 2329 .ring_dir = HAL_SRNG_SRC_RING, 2330 /* reg_start is not set because LMAC rings are not accessed 2331 * from host 2332 */ 2333 .reg_start = {}, 2334 .reg_size = {}, 2335 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2336 }, 2337 { /* DIR_BUF_RX_DMA_SRC */ 2338 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 2339 /* one ring for spectral and one ring for cfr */ 2340 .max_rings = 2, 2341 .entry_size = 2, 2342 .lmac_ring = TRUE, 2343 .ring_dir = HAL_SRNG_SRC_RING, 2344 /* reg_start is not set because LMAC rings are not accessed 2345 * from host 2346 */ 2347 .reg_start = {}, 2348 .reg_size = {}, 2349 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2350 }, 2351 #ifdef WLAN_FEATURE_CIF_CFR 2352 { /* WIFI_POS_SRC */ 2353 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 2354 .max_rings = 1, 2355 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 2356 .lmac_ring = TRUE, 2357 .ring_dir = HAL_SRNG_SRC_RING, 2358 /* reg_start is not set because LMAC rings are not accessed 2359 * from host 2360 */ 2361 .reg_start = {}, 2362 .reg_size = {}, 2363 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2364 }, 2365 #endif 2366 { /* REO2PPE */ 0}, 2367 { /* PPE2TCL */ 0}, 2368 { /* PPE_RELEASE */ 0}, 2369 { /* TX_MONITOR_BUF */ 0}, 2370 { /* TX_MONITOR_DST */ 0}, 2371 { /* SW2RXDMA_NEW */ 0}, 2372 }; 2373 2374 /** 2375 * hal_qcn6122_attach()- Attach 6122 target specific hal_soc ops, 2376 * offset and srng table 2377 * Return: void 2378 */ 2379 void hal_qcn6122_attach(struct hal_soc *hal_soc) 2380 { 2381 hal_soc->hw_srng_table = hw_srng_table_6122; 2382 hal_srng_hw_reg_offset_init_generic(hal_soc); 2383 2384 hal_hw_txrx_default_ops_attach_li(hal_soc); 2385 hal_hw_txrx_ops_attach_qcn6122(hal_soc); 2386 if (hal_soc->static_window_map) 2387 hal_write_window_register(hal_soc); 2388 } 2389