1 /* 2 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #include "hal_li_hw_headers.h" 19 #include "hal_internal.h" 20 #include "hal_api.h" 21 #include "target_type.h" 22 #include "wcss_version.h" 23 #include "qdf_module.h" 24 #include "hal_qcn6122_rx.h" 25 #include "hal_api_mon.h" 26 #include "hal_flow.h" 27 #include "rx_flow_search_entry.h" 28 #include "hal_rx_flow_info.h" 29 30 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 31 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET 32 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 33 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK 34 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 35 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB 36 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 37 PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 38 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 39 PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 40 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 41 PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 42 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 43 PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 44 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 45 PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 46 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 47 PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 48 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 49 PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 50 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 51 PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 52 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 53 PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 54 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 55 PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 56 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 57 PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 58 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 59 RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 60 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 61 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 62 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 63 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 64 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 65 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 66 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 67 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 68 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER \ 69 STATUS_HEADER_REO_STATUS_NUMBER 70 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 71 STATUS_HEADER_TIMESTAMP 72 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 73 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 74 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 75 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 76 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 77 TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 78 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 79 TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 80 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 81 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 82 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 83 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 84 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 85 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 86 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 87 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 88 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 89 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 90 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 91 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 92 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 93 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 94 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 95 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 96 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 97 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 98 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 99 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 100 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 101 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 102 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 103 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 104 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 105 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 106 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 107 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 108 109 #define CE_WINDOW_ADDRESS_6122 \ 110 ((SOC_WFSS_CE_REG_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) 111 112 #define UMAC_WINDOW_ADDRESS_6122 \ 113 ((SEQ_WCSS_UMAC_OFFSET >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) 114 115 #define WINDOW_CONFIGURATION_VALUE_6122 \ 116 ((CE_WINDOW_ADDRESS_6122 << 6) |\ 117 (UMAC_WINDOW_ADDRESS_6122 << 12) | \ 118 WINDOW_ENABLE_BIT) 119 120 #include "hal_qcn6122_tx.h" 121 #include <hal_generic_api.h> 122 #include "hal_li_rx.h" 123 #include "hal_li_api.h" 124 #include "hal_li_generic_api.h" 125 126 /** 127 * hal_rx_sw_mon_desc_info_get_6122(): API to read the 128 * sw monitor ring descriptor 129 * 130 * @rxdma_dst_ring_desc: sw monitor ring descriptor 131 * @desc_info_buf: Descriptor info buffer to which 132 * sw monitor ring descriptor is populated to 133 * 134 * Return: void 135 */ 136 static void 137 hal_rx_sw_mon_desc_info_get_6122(hal_ring_desc_t rxdma_dst_ring_desc, 138 hal_rx_mon_desc_info_t desc_info_buf) 139 { 140 struct sw_monitor_ring *sw_mon_ring = 141 (struct sw_monitor_ring *)rxdma_dst_ring_desc; 142 struct buffer_addr_info *buf_addr_info; 143 uint32_t *mpdu_info; 144 uint32_t loop_cnt; 145 struct hal_rx_mon_desc_info *desc_info; 146 147 desc_info = (struct hal_rx_mon_desc_info *)desc_info_buf; 148 mpdu_info = (uint32_t *)&sw_mon_ring-> 149 reo_level_mpdu_frame_info.rx_mpdu_desc_info_details; 150 151 loop_cnt = HAL_RX_GET(sw_mon_ring, SW_MONITOR_RING_7, LOOPING_COUNT); 152 desc_info->msdu_count = HAL_RX_MPDU_MSDU_COUNT_GET(mpdu_info); 153 154 /* Get msdu link descriptor buf_addr_info */ 155 buf_addr_info = &sw_mon_ring-> 156 reo_level_mpdu_frame_info.msdu_link_desc_addr_info; 157 desc_info->link_desc.paddr = HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) 158 | ((uint64_t)(HAL_RX_BUFFER_ADDR_39_32_GET( 159 buf_addr_info)) << 32); 160 desc_info->link_desc.sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info); 161 buf_addr_info = &sw_mon_ring->status_buff_addr_info; 162 desc_info->status_buf.paddr = HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) 163 | ((uint64_t) 164 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32); 165 desc_info->status_buf.sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info); 166 desc_info->end_of_ppdu = HAL_RX_GET(sw_mon_ring, 167 SW_MONITOR_RING_6, 168 END_OF_PPDU); 169 desc_info->status_buf_count = HAL_RX_GET(sw_mon_ring, 170 SW_MONITOR_RING_6, 171 STATUS_BUF_COUNT); 172 desc_info->rxdma_push_reason = HAL_RX_GET(sw_mon_ring, 173 SW_MONITOR_RING_6, 174 RXDMA_PUSH_REASON); 175 desc_info->ppdu_id = HAL_RX_GET(sw_mon_ring, 176 SW_MONITOR_RING_7, 177 PHY_PPDU_ID); 178 } 179 180 /** 181 * hal_rx_msdu_start_nss_get_6122(): API to get the NSS 182 * Interval from rx_msdu_start 183 * 184 * @buf: pointer to the start of RX PKT TLV header 185 * Return: uint32_t(nss) 186 */ 187 static uint32_t hal_rx_msdu_start_nss_get_6122(uint8_t *buf) 188 { 189 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 190 struct rx_msdu_start *msdu_start = 191 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 192 uint8_t mimo_ss_bitmap; 193 194 mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start); 195 196 return qdf_get_hweight8(mimo_ss_bitmap); 197 } 198 199 /** 200 * hal_rx_msdu_start_get_len_6122(): API to get the MSDU length 201 * from rx_msdu_start TLV 202 * 203 * @ buf: pointer to the start of RX PKT TLV headers 204 * Return: (uint32_t)msdu length 205 */ 206 static uint32_t hal_rx_msdu_start_get_len_6122(uint8_t *buf) 207 { 208 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 209 struct rx_msdu_start *msdu_start = 210 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 211 uint32_t msdu_len; 212 213 msdu_len = HAL_RX_MSDU_START_MSDU_LEN_GET(msdu_start); 214 215 return msdu_len; 216 } 217 218 /** 219 * hal_rx_mon_hw_desc_get_mpdu_status_6122(): Retrieve MPDU status 220 * 221 * @ hw_desc_addr: Start address of Rx HW TLVs 222 * @ rs: Status for monitor mode 223 * 224 * Return: void 225 */ 226 static void hal_rx_mon_hw_desc_get_mpdu_status_6122(void *hw_desc_addr, 227 struct mon_rx_status *rs) 228 { 229 struct rx_msdu_start *rx_msdu_start; 230 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 231 uint32_t reg_value; 232 const uint32_t sgi_hw_to_cdp[] = { 233 CDP_SGI_0_8_US, 234 CDP_SGI_0_4_US, 235 CDP_SGI_1_6_US, 236 CDP_SGI_3_2_US, 237 }; 238 239 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 240 241 HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs); 242 243 rs->ant_signal_db = HAL_RX_GET(rx_msdu_start, 244 RX_MSDU_START_5, USER_RSSI); 245 rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC); 246 247 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI); 248 rs->sgi = sgi_hw_to_cdp[reg_value]; 249 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE); 250 rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0; 251 /* TODO: rs->beamformed should be set for SU beamforming also */ 252 } 253 254 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 255 /** 256 * hal_get_link_desc_size_6122(): API to get the link desc size 257 * 258 * Return: uint32_t 259 */ 260 static uint32_t hal_get_link_desc_size_6122(void) 261 { 262 return LINK_DESC_SIZE; 263 } 264 265 /** 266 * hal_rx_get_tlv_6122(): API to get the tlv 267 * 268 * @rx_tlv: TLV data extracted from the rx packet 269 * Return: uint8_t 270 */ 271 static uint8_t hal_rx_get_tlv_6122(void *rx_tlv) 272 { 273 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH); 274 } 275 276 /** 277 * hal_rx_mpdu_start_tlv_tag_valid_6122 () - API to check if RX_MPDU_START 278 * tlv tag is valid 279 * 280 *@rx_tlv_hdr: start address of rx_pkt_tlvs 281 * 282 * Return: true if RX_MPDU_START is valied, else false. 283 */ 284 uint8_t hal_rx_mpdu_start_tlv_tag_valid_6122(void *rx_tlv_hdr) 285 { 286 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 287 uint32_t tlv_tag; 288 289 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(&rx_desc->mpdu_start_tlv); 290 291 return tlv_tag == WIFIRX_MPDU_START_E ? true : false; 292 } 293 294 /** 295 * hal_rx_wbm_err_msdu_continuation_get_6122 () - API to check if WBM 296 * msdu continuation bit is set 297 * 298 *@wbm_desc: wbm release ring descriptor 299 * 300 * Return: true if msdu continuation bit is set. 301 */ 302 uint8_t hal_rx_wbm_err_msdu_continuation_get_6122(void *wbm_desc) 303 { 304 uint32_t comp_desc = 305 *(uint32_t *)(((uint8_t *)wbm_desc) + 306 WBM_RELEASE_RING_3_MSDU_CONTINUATION_OFFSET); 307 308 return (comp_desc & WBM_RELEASE_RING_3_MSDU_CONTINUATION_MASK) >> 309 WBM_RELEASE_RING_3_MSDU_CONTINUATION_LSB; 310 } 311 312 /** 313 * hal_rx_proc_phyrx_other_receive_info_tlv_6122(): API to get tlv info 314 * 315 * Return: uint32_t 316 */ 317 static inline 318 void hal_rx_proc_phyrx_other_receive_info_tlv_6122(void *rx_tlv_hdr, 319 void *ppdu_info_hdl) 320 { 321 } 322 323 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) 324 static inline 325 void hal_rx_get_bb_info_6122(void *rx_tlv, 326 void *ppdu_info_hdl) 327 { 328 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 329 330 ppdu_info->cfr_info.bb_captured_channel = 331 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_CHANNEL); 332 333 ppdu_info->cfr_info.bb_captured_timeout = 334 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_TIMEOUT); 335 336 ppdu_info->cfr_info.bb_captured_reason = 337 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_REASON); 338 } 339 340 static inline 341 void hal_rx_get_rtt_info_6122(void *rx_tlv, 342 void *ppdu_info_hdl) 343 { 344 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 345 346 ppdu_info->cfr_info.rx_location_info_valid = 347 HAL_RX_GET(rx_tlv, PHYRX_PKT_END_13_RX_PKT_END_DETAILS, 348 RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID); 349 350 ppdu_info->cfr_info.rtt_che_buffer_pointer_low32 = 351 HAL_RX_GET(rx_tlv, 352 PHYRX_PKT_END_12_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 353 RTT_CHE_BUFFER_POINTER_LOW32); 354 355 ppdu_info->cfr_info.rtt_che_buffer_pointer_high8 = 356 HAL_RX_GET(rx_tlv, 357 PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 358 RTT_CHE_BUFFER_POINTER_HIGH8); 359 360 ppdu_info->cfr_info.chan_capture_status = 361 HAL_RX_GET(rx_tlv, 362 PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 363 RESERVED_8); 364 } 365 #endif 366 367 /** 368 * hal_rx_dump_msdu_start_tlv_6122() : dump RX msdu_start TLV in structured 369 * human readable format. 370 * @ msdu_start: pointer the msdu_start TLV in pkt. 371 * @ dbg_level: log level. 372 * 373 * Return: void 374 */ 375 static void hal_rx_dump_msdu_start_tlv_6122(void *msdustart, 376 uint8_t dbg_level) 377 { 378 struct rx_msdu_start *msdu_start = (struct rx_msdu_start *)msdustart; 379 380 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 381 "rx_msdu_start tlv - " 382 "rxpcu_mpdu_filter_in_category: %d " 383 "sw_frame_group_id: %d " 384 "phy_ppdu_id: %d " 385 "msdu_length: %d " 386 "ipsec_esp: %d " 387 "l3_offset: %d " 388 "ipsec_ah: %d " 389 "l4_offset: %d " 390 "msdu_number: %d " 391 "decap_format: %d " 392 "ipv4_proto: %d " 393 "ipv6_proto: %d " 394 "tcp_proto: %d " 395 "udp_proto: %d " 396 "ip_frag: %d " 397 "tcp_only_ack: %d " 398 "da_is_bcast_mcast: %d " 399 "ip4_protocol_ip6_next_header: %d " 400 "toeplitz_hash_2_or_4: %d " 401 "flow_id_toeplitz: %d " 402 "user_rssi: %d " 403 "pkt_type: %d " 404 "stbc: %d " 405 "sgi: %d " 406 "rate_mcs: %d " 407 "receive_bandwidth: %d " 408 "reception_type: %d " 409 "ppdu_start_timestamp: %d " 410 "sw_phy_meta_data: %d ", 411 msdu_start->rxpcu_mpdu_filter_in_category, 412 msdu_start->sw_frame_group_id, 413 msdu_start->phy_ppdu_id, 414 msdu_start->msdu_length, 415 msdu_start->ipsec_esp, 416 msdu_start->l3_offset, 417 msdu_start->ipsec_ah, 418 msdu_start->l4_offset, 419 msdu_start->msdu_number, 420 msdu_start->decap_format, 421 msdu_start->ipv4_proto, 422 msdu_start->ipv6_proto, 423 msdu_start->tcp_proto, 424 msdu_start->udp_proto, 425 msdu_start->ip_frag, 426 msdu_start->tcp_only_ack, 427 msdu_start->da_is_bcast_mcast, 428 msdu_start->ip4_protocol_ip6_next_header, 429 msdu_start->toeplitz_hash_2_or_4, 430 msdu_start->flow_id_toeplitz, 431 msdu_start->user_rssi, 432 msdu_start->pkt_type, 433 msdu_start->stbc, 434 msdu_start->sgi, 435 msdu_start->rate_mcs, 436 msdu_start->receive_bandwidth, 437 msdu_start->reception_type, 438 msdu_start->ppdu_start_timestamp, 439 msdu_start->sw_phy_meta_data); 440 } 441 442 /** 443 * hal_rx_dump_msdu_end_tlv_6122: dump RX msdu_end TLV in structured 444 * human readable format. 445 * @ msdu_end: pointer the msdu_end TLV in pkt. 446 * @ dbg_level: log level. 447 * 448 * Return: void 449 */ 450 static void hal_rx_dump_msdu_end_tlv_6122(void *msduend, 451 uint8_t dbg_level) 452 { 453 struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend; 454 455 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 456 "rx_msdu_end tlv - " 457 "rxpcu_mpdu_filter_in_category: %d " 458 "sw_frame_group_id: %d " 459 "phy_ppdu_id: %d " 460 "ip_hdr_chksum: %d " 461 "reported_mpdu_length: %d " 462 "key_id_octet: %d " 463 "cce_super_rule: %d " 464 "cce_classify_not_done_truncat: %d " 465 "cce_classify_not_done_cce_dis: %d " 466 "rule_indication_31_0: %d " 467 "rule_indication_63_32: %d " 468 "da_offset: %d " 469 "sa_offset: %d " 470 "da_offset_valid: %d " 471 "sa_offset_valid: %d " 472 "ipv6_options_crc: %d " 473 "tcp_seq_number: %d " 474 "tcp_ack_number: %d " 475 "tcp_flag: %d " 476 "lro_eligible: %d " 477 "window_size: %d " 478 "tcp_udp_chksum: %d " 479 "sa_idx_timeout: %d " 480 "da_idx_timeout: %d " 481 "msdu_limit_error: %d " 482 "flow_idx_timeout: %d " 483 "flow_idx_invalid: %d " 484 "wifi_parser_error: %d " 485 "amsdu_parser_error: %d " 486 "sa_is_valid: %d " 487 "da_is_valid: %d " 488 "da_is_mcbc: %d " 489 "l3_header_padding: %d " 490 "first_msdu: %d " 491 "last_msdu: %d " 492 "sa_idx: %d " 493 "msdu_drop: %d " 494 "reo_destination_indication: %d " 495 "flow_idx: %d " 496 "fse_metadata: %d " 497 "cce_metadata: %d " 498 "sa_sw_peer_id: %d ", 499 msdu_end->rxpcu_mpdu_filter_in_category, 500 msdu_end->sw_frame_group_id, 501 msdu_end->phy_ppdu_id, 502 msdu_end->ip_hdr_chksum, 503 msdu_end->reported_mpdu_length, 504 msdu_end->key_id_octet, 505 msdu_end->cce_super_rule, 506 msdu_end->cce_classify_not_done_truncate, 507 msdu_end->cce_classify_not_done_cce_dis, 508 msdu_end->rule_indication_31_0, 509 msdu_end->rule_indication_63_32, 510 msdu_end->da_offset, 511 msdu_end->sa_offset, 512 msdu_end->da_offset_valid, 513 msdu_end->sa_offset_valid, 514 msdu_end->ipv6_options_crc, 515 msdu_end->tcp_seq_number, 516 msdu_end->tcp_ack_number, 517 msdu_end->tcp_flag, 518 msdu_end->lro_eligible, 519 msdu_end->window_size, 520 msdu_end->tcp_udp_chksum, 521 msdu_end->sa_idx_timeout, 522 msdu_end->da_idx_timeout, 523 msdu_end->msdu_limit_error, 524 msdu_end->flow_idx_timeout, 525 msdu_end->flow_idx_invalid, 526 msdu_end->wifi_parser_error, 527 msdu_end->amsdu_parser_error, 528 msdu_end->sa_is_valid, 529 msdu_end->da_is_valid, 530 msdu_end->da_is_mcbc, 531 msdu_end->l3_header_padding, 532 msdu_end->first_msdu, 533 msdu_end->last_msdu, 534 msdu_end->sa_idx, 535 msdu_end->msdu_drop, 536 msdu_end->reo_destination_indication, 537 msdu_end->flow_idx, 538 msdu_end->fse_metadata, 539 msdu_end->cce_metadata, 540 msdu_end->sa_sw_peer_id); 541 } 542 543 /** 544 * hal_rx_mpdu_start_tid_get_6122(): API to get tid 545 * from rx_msdu_start 546 * 547 * @buf: pointer to the start of RX PKT TLV header 548 * Return: uint32_t(tid value) 549 */ 550 static uint32_t hal_rx_mpdu_start_tid_get_6122(uint8_t *buf) 551 { 552 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 553 struct rx_mpdu_start *mpdu_start = 554 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 555 uint32_t tid; 556 557 tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details); 558 559 return tid; 560 } 561 562 /** 563 * hal_rx_msdu_start_reception_type_get(): API to get the reception type 564 * Interval from rx_msdu_start 565 * 566 * @buf: pointer to the start of RX PKT TLV header 567 * Return: uint32_t(reception_type) 568 */ 569 static uint32_t hal_rx_msdu_start_reception_type_get_6122(uint8_t *buf) 570 { 571 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 572 struct rx_msdu_start *msdu_start = 573 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 574 uint32_t reception_type; 575 576 reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start); 577 578 return reception_type; 579 } 580 581 /** 582 * hal_rx_msdu_end_da_idx_get_6122: API to get da_idx 583 * from rx_msdu_end TLV 584 * 585 * @ buf: pointer to the start of RX PKT TLV headers 586 * Return: da index 587 */ 588 static uint16_t hal_rx_msdu_end_da_idx_get_6122(uint8_t *buf) 589 { 590 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 591 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 592 uint16_t da_idx; 593 594 da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 595 596 return da_idx; 597 } 598 599 /** 600 * hal_rx_get_rx_fragment_number_6122(): Function to retrieve rx fragment number 601 * 602 * @nbuf: Network buffer 603 * Returns: rx fragment number 604 */ 605 static 606 uint8_t hal_rx_get_rx_fragment_number_6122(uint8_t *buf) 607 { 608 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 609 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 610 611 /* Return first 4 bits as fragment number */ 612 return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & 613 DOT11_SEQ_FRAG_MASK); 614 } 615 616 /** 617 * hal_rx_msdu_end_da_is_mcbc_get_6122(): API to check if pkt is MCBC 618 * from rx_msdu_end TLV 619 * 620 * @ buf: pointer to the start of RX PKT TLV headers 621 * Return: da_is_mcbc 622 */ 623 static uint8_t 624 hal_rx_msdu_end_da_is_mcbc_get_6122(uint8_t *buf) 625 { 626 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 627 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 628 629 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); 630 } 631 632 /** 633 * hal_rx_msdu_end_sa_is_valid_get_6122(): API to get_6122 the 634 * sa_is_valid bit from rx_msdu_end TLV 635 * 636 * @ buf: pointer to the start of RX PKT TLV headers 637 * Return: sa_is_valid bit 638 */ 639 static uint8_t 640 hal_rx_msdu_end_sa_is_valid_get_6122(uint8_t *buf) 641 { 642 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 643 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 644 uint8_t sa_is_valid; 645 646 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); 647 648 return sa_is_valid; 649 } 650 651 /** 652 * hal_rx_msdu_end_sa_idx_get_6122(): API to get_6122 the 653 * sa_idx from rx_msdu_end TLV 654 * 655 * @ buf: pointer to the start of RX PKT TLV headers 656 * Return: sa_idx (SA AST index) 657 */ 658 static uint16_t hal_rx_msdu_end_sa_idx_get_6122(uint8_t *buf) 659 { 660 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 661 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 662 uint16_t sa_idx; 663 664 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 665 666 return sa_idx; 667 } 668 669 /** 670 * hal_rx_desc_is_first_msdu_6122() - Check if first msdu 671 * 672 * @hal_soc_hdl: hal_soc handle 673 * @hw_desc_addr: hardware descriptor address 674 * 675 * Return: 0 - success/ non-zero failure 676 */ 677 static uint32_t hal_rx_desc_is_first_msdu_6122(void *hw_desc_addr) 678 { 679 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; 680 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; 681 682 return HAL_RX_GET(msdu_end, RX_MSDU_END_10, FIRST_MSDU); 683 } 684 685 /** 686 * hal_rx_msdu_end_l3_hdr_padding_get_6122(): API to get_6122 the 687 * l3_header padding from rx_msdu_end TLV 688 * 689 * @ buf: pointer to the start of RX PKT TLV headers 690 * Return: number of l3 header padding bytes 691 */ 692 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_6122(uint8_t *buf) 693 { 694 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 695 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 696 uint32_t l3_header_padding; 697 698 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 699 700 return l3_header_padding; 701 } 702 703 /** 704 * @ hal_rx_encryption_info_valid_6122: Returns encryption type. 705 * 706 * @ buf: rx_tlv_hdr of the received packet 707 * @ Return: encryption type 708 */ 709 inline uint32_t hal_rx_encryption_info_valid_6122(uint8_t *buf) 710 { 711 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 712 struct rx_mpdu_start *mpdu_start = 713 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 714 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 715 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); 716 717 return encryption_info; 718 } 719 720 /* 721 * @ hal_rx_print_pn_6122: Prints the PN of rx packet. 722 * 723 * @ buf: rx_tlv_hdr of the received packet 724 * @ Return: void 725 */ 726 static void hal_rx_print_pn_6122(uint8_t *buf) 727 { 728 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 729 struct rx_mpdu_start *mpdu_start = 730 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 731 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 732 733 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); 734 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); 735 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); 736 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); 737 738 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ", 739 pn_127_96, pn_95_64, pn_63_32, pn_31_0); 740 } 741 742 /** 743 * hal_rx_msdu_end_first_msdu_get_6122: API to get first msdu status 744 * from rx_msdu_end TLV 745 * 746 * @ buf: pointer to the start of RX PKT TLV headers 747 * Return: first_msdu 748 */ 749 static uint8_t hal_rx_msdu_end_first_msdu_get_6122(uint8_t *buf) 750 { 751 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 752 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 753 uint8_t first_msdu; 754 755 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); 756 757 return first_msdu; 758 } 759 760 /** 761 * hal_rx_msdu_end_da_is_valid_get_6122: API to check if da is valid 762 * from rx_msdu_end TLV 763 * 764 * @ buf: pointer to the start of RX PKT TLV headers 765 * Return: da_is_valid 766 */ 767 static uint8_t hal_rx_msdu_end_da_is_valid_get_6122(uint8_t *buf) 768 { 769 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 770 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 771 uint8_t da_is_valid; 772 773 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); 774 775 return da_is_valid; 776 } 777 778 /** 779 * hal_rx_msdu_end_last_msdu_get_6122: API to get last msdu status 780 * from rx_msdu_end TLV 781 * 782 * @ buf: pointer to the start of RX PKT TLV headers 783 * Return: last_msdu 784 */ 785 static uint8_t hal_rx_msdu_end_last_msdu_get_6122(uint8_t *buf) 786 { 787 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 788 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 789 uint8_t last_msdu; 790 791 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); 792 793 return last_msdu; 794 } 795 796 /* 797 * hal_rx_get_mpdu_mac_ad4_valid(): Retrieves if mpdu 4th addr is valid 798 * 799 * @nbuf: Network buffer 800 * Returns: value of mpdu 4th address valid field 801 */ 802 inline bool hal_rx_get_mpdu_mac_ad4_valid_6122(uint8_t *buf) 803 { 804 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 805 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 806 bool ad4_valid = 0; 807 808 ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(rx_mpdu_info); 809 810 return ad4_valid; 811 } 812 813 /** 814 * hal_rx_mpdu_start_sw_peer_id_get_6122: Retrieve sw peer_id 815 * @buf: network buffer 816 * 817 * Return: sw peer_id 818 */ 819 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_6122(uint8_t *buf) 820 { 821 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 822 struct rx_mpdu_start *mpdu_start = 823 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 824 825 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET( 826 &mpdu_start->rx_mpdu_info_details); 827 } 828 829 /* 830 * hal_rx_mpdu_get_to_ds_6122(): API to get the tods info 831 * from rx_mpdu_start 832 * 833 * @buf: pointer to the start of RX PKT TLV header 834 * Return: uint32_t(to_ds) 835 */ 836 static uint32_t hal_rx_mpdu_get_to_ds_6122(uint8_t *buf) 837 { 838 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 839 struct rx_mpdu_start *mpdu_start = 840 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 841 842 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 843 844 return HAL_RX_MPDU_GET_TODS(mpdu_info); 845 } 846 847 /* 848 * hal_rx_mpdu_get_fr_ds_6122(): API to get the from ds info 849 * from rx_mpdu_start 850 * 851 * @buf: pointer to the start of RX PKT TLV header 852 * Return: uint32_t(fr_ds) 853 */ 854 static uint32_t hal_rx_mpdu_get_fr_ds_6122(uint8_t *buf) 855 { 856 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 857 struct rx_mpdu_start *mpdu_start = 858 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 859 860 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 861 862 return HAL_RX_MPDU_GET_FROMDS(mpdu_info); 863 } 864 865 /* 866 * hal_rx_get_mpdu_frame_control_valid_6122(): Retrieves mpdu 867 * frame control valid 868 * 869 * @nbuf: Network buffer 870 * Returns: value of frame control valid field 871 */ 872 static uint8_t hal_rx_get_mpdu_frame_control_valid_6122(uint8_t *buf) 873 { 874 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 875 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 876 877 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); 878 } 879 880 /** 881 * hal_rx_get_mpdu_frame_control_field_6122(): Function to 882 * retrieve frame control field 883 * 884 * @nbuf: Network buffer 885 * Returns: value of frame control field 886 * 887 */ 888 static uint16_t hal_rx_get_mpdu_frame_control_field_6122(uint8_t *buf) 889 { 890 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 891 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 892 uint16_t frame_ctrl = 0; 893 894 frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info); 895 896 return frame_ctrl; 897 } 898 899 /* 900 * hal_rx_mpdu_get_addr1_6122(): API to check get address1 of the mpdu 901 * 902 * @buf: pointer to the start of RX PKT TLV headera 903 * @mac_addr: pointer to mac address 904 * Return: success/failure 905 */ 906 static QDF_STATUS hal_rx_mpdu_get_addr1_6122(uint8_t *buf, 907 uint8_t *mac_addr) 908 { 909 struct __attribute__((__packed__)) hal_addr1 { 910 uint32_t ad1_31_0; 911 uint16_t ad1_47_32; 912 }; 913 914 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 915 struct rx_mpdu_start *mpdu_start = 916 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 917 918 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 919 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; 920 uint32_t mac_addr_ad1_valid; 921 922 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); 923 924 if (mac_addr_ad1_valid) { 925 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); 926 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); 927 return QDF_STATUS_SUCCESS; 928 } 929 930 return QDF_STATUS_E_FAILURE; 931 } 932 933 /* 934 * hal_rx_mpdu_get_addr2_6122(): API to check get address2 of the mpdu 935 * in the packet 936 * 937 * @buf: pointer to the start of RX PKT TLV header 938 * @mac_addr: pointer to mac address 939 * Return: success/failure 940 */ 941 static QDF_STATUS hal_rx_mpdu_get_addr2_6122(uint8_t *buf, uint8_t *mac_addr) 942 { 943 struct __attribute__((__packed__)) hal_addr2 { 944 uint16_t ad2_15_0; 945 uint32_t ad2_47_16; 946 }; 947 948 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 949 struct rx_mpdu_start *mpdu_start = 950 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 951 952 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 953 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; 954 uint32_t mac_addr_ad2_valid; 955 956 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); 957 958 if (mac_addr_ad2_valid) { 959 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); 960 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); 961 return QDF_STATUS_SUCCESS; 962 } 963 964 return QDF_STATUS_E_FAILURE; 965 } 966 967 /* 968 * hal_rx_mpdu_get_addr3_6122(): API to get address3 of the mpdu 969 * in the packet 970 * 971 * @buf: pointer to the start of RX PKT TLV header 972 * @mac_addr: pointer to mac address 973 * Return: success/failure 974 */ 975 static QDF_STATUS hal_rx_mpdu_get_addr3_6122(uint8_t *buf, uint8_t *mac_addr) 976 { 977 struct __attribute__((__packed__)) hal_addr3 { 978 uint32_t ad3_31_0; 979 uint16_t ad3_47_32; 980 }; 981 982 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 983 struct rx_mpdu_start *mpdu_start = 984 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 985 986 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 987 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; 988 uint32_t mac_addr_ad3_valid; 989 990 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); 991 992 if (mac_addr_ad3_valid) { 993 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); 994 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); 995 return QDF_STATUS_SUCCESS; 996 } 997 998 return QDF_STATUS_E_FAILURE; 999 } 1000 1001 /* 1002 * hal_rx_mpdu_get_addr4_6122(): API to get address4 of the mpdu 1003 * in the packet 1004 * 1005 * @buf: pointer to the start of RX PKT TLV header 1006 * @mac_addr: pointer to mac address 1007 * Return: success/failure 1008 */ 1009 static QDF_STATUS hal_rx_mpdu_get_addr4_6122(uint8_t *buf, uint8_t *mac_addr) 1010 { 1011 struct __attribute__((__packed__)) hal_addr4 { 1012 uint32_t ad4_31_0; 1013 uint16_t ad4_47_32; 1014 }; 1015 1016 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1017 struct rx_mpdu_start *mpdu_start = 1018 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1019 1020 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 1021 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; 1022 uint32_t mac_addr_ad4_valid; 1023 1024 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); 1025 1026 if (mac_addr_ad4_valid) { 1027 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); 1028 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); 1029 return QDF_STATUS_SUCCESS; 1030 } 1031 1032 return QDF_STATUS_E_FAILURE; 1033 } 1034 1035 /* 1036 * hal_rx_get_mpdu_sequence_control_valid_6122(): Get mpdu 1037 * sequence control valid 1038 * 1039 * @nbuf: Network buffer 1040 * Returns: value of sequence control valid field 1041 */ 1042 static uint8_t hal_rx_get_mpdu_sequence_control_valid_6122(uint8_t *buf) 1043 { 1044 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 1045 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 1046 1047 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); 1048 } 1049 1050 /** 1051 * hal_rx_is_unicast_6122: check packet is unicast frame or not. 1052 * 1053 * @ buf: pointer to rx pkt TLV. 1054 * 1055 * Return: true on unicast. 1056 */ 1057 static bool hal_rx_is_unicast_6122(uint8_t *buf) 1058 { 1059 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1060 struct rx_mpdu_start *mpdu_start = 1061 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1062 uint32_t grp_id; 1063 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 1064 1065 grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 1066 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_OFFSET)), 1067 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_MASK, 1068 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_LSB)); 1069 1070 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false; 1071 } 1072 1073 /** 1074 * hal_rx_tid_get_6122: get tid based on qos control valid. 1075 * @hal_soc_hdl: hal soc handle 1076 * @buf: pointer to rx pkt TLV. 1077 * 1078 * Return: tid 1079 */ 1080 static uint32_t hal_rx_tid_get_6122(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1081 { 1082 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1083 struct rx_mpdu_start *mpdu_start = 1084 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1085 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 1086 uint8_t qos_control_valid = 1087 (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 1088 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_OFFSET)), 1089 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_MASK, 1090 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_LSB)); 1091 1092 if (qos_control_valid) 1093 return hal_rx_mpdu_start_tid_get_6122(buf); 1094 1095 return HAL_RX_NON_QOS_TID; 1096 } 1097 1098 /** 1099 * hal_rx_hw_desc_get_ppduid_get_6122(): retrieve ppdu id 1100 * @rx_tlv_hdr: rx tlv header 1101 * @rxdma_dst_ring_desc: rxdma HW descriptor 1102 * 1103 * Return: ppdu id 1104 */ 1105 static uint32_t hal_rx_hw_desc_get_ppduid_get_6122(void *rx_tlv_hdr, 1106 void *rxdma_dst_ring_desc) 1107 { 1108 struct reo_entrance_ring *reo_ent = rxdma_dst_ring_desc; 1109 1110 return reo_ent->phy_ppdu_id; 1111 } 1112 1113 /** 1114 * hal_reo_status_get_header_6122 - Process reo desc info 1115 * @ring_desc: REO status ring descriptor 1116 * @b - tlv type info 1117 * @h1 - Pointer to hal_reo_status_header where info to be stored 1118 * 1119 * Return - none. 1120 * 1121 */ 1122 static void hal_reo_status_get_header_6122(hal_ring_desc_t ring_desc, int b, 1123 void *h1) 1124 { 1125 uint32_t *d = (uint32_t *)ring_desc; 1126 uint32_t val1 = 0; 1127 struct hal_reo_status_header *h = 1128 (struct hal_reo_status_header *)h1; 1129 1130 /* Offsets of descriptor fields defined in HW headers start 1131 * from the field after TLV header 1132 */ 1133 d += HAL_GET_NUM_DWORDS(sizeof(struct tlv_32_hdr)); 1134 1135 switch (b) { 1136 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1137 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, 1138 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1139 break; 1140 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1141 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, 1142 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1143 break; 1144 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1145 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, 1146 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1147 break; 1148 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1149 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, 1150 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1151 break; 1152 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1153 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, 1154 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1155 break; 1156 case HAL_REO_DESC_THRES_STATUS_TLV: 1157 val1 = 1158 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, 1159 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1160 break; 1161 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1162 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, 1163 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1164 break; 1165 default: 1166 qdf_nofl_err("ERROR: Unknown tlv\n"); 1167 break; 1168 } 1169 h->cmd_num = 1170 HAL_GET_FIELD( 1171 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, 1172 val1); 1173 h->exec_time = 1174 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1175 CMD_EXECUTION_TIME, val1); 1176 h->status = 1177 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1178 REO_CMD_EXECUTION_STATUS, val1); 1179 switch (b) { 1180 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1181 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, 1182 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1183 break; 1184 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1185 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, 1186 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1187 break; 1188 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1189 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, 1190 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1191 break; 1192 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1193 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, 1194 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1195 break; 1196 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1197 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, 1198 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1199 break; 1200 case HAL_REO_DESC_THRES_STATUS_TLV: 1201 val1 = 1202 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, 1203 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1204 break; 1205 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1206 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, 1207 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1208 break; 1209 default: 1210 qdf_nofl_err("ERROR: Unknown tlv\n"); 1211 break; 1212 } 1213 h->tstamp = 1214 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); 1215 } 1216 1217 /** 1218 * hal_rx_mpdu_start_mpdu_qos_control_valid_get_6122(): 1219 * Retrieve qos control valid bit from the tlv. 1220 * @buf: pointer to rx pkt TLV. 1221 * 1222 * Return: qos control value. 1223 */ 1224 static inline uint32_t 1225 hal_rx_mpdu_start_mpdu_qos_control_valid_get_6122(uint8_t *buf) 1226 { 1227 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1228 struct rx_mpdu_start *mpdu_start = 1229 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1230 1231 return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET( 1232 &mpdu_start->rx_mpdu_info_details); 1233 } 1234 1235 /** 1236 * hal_rx_msdu_end_sa_sw_peer_id_get_6122(): API to get the 1237 * sa_sw_peer_id from rx_msdu_end TLV 1238 * @buf: pointer to the start of RX PKT TLV headers 1239 * 1240 * Return: sa_sw_peer_id index 1241 */ 1242 static inline uint32_t 1243 hal_rx_msdu_end_sa_sw_peer_id_get_6122(uint8_t *buf) 1244 { 1245 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1246 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1247 1248 return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 1249 } 1250 1251 /** 1252 * hal_tx_desc_set_mesh_en_6122 - Set mesh_enable flag in Tx descriptor 1253 * @desc: Handle to Tx Descriptor 1254 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 1255 * enabling the interpretation of the 'Mesh Control Present' bit 1256 * (bit 8) of QoS Control (otherwise this bit is ignored), 1257 * For native WiFi frames, this indicates that a 'Mesh Control' field 1258 * is present between the header and the LLC. 1259 * 1260 * Return: void 1261 */ 1262 static inline 1263 void hal_tx_desc_set_mesh_en_6122(void *desc, uint8_t en) 1264 { 1265 HAL_SET_FLD(desc, TCL_DATA_CMD_5, MESH_ENABLE) |= 1266 HAL_TX_SM(TCL_DATA_CMD_5, MESH_ENABLE, en); 1267 } 1268 1269 static 1270 void *hal_rx_msdu0_buffer_addr_lsb_6122(void *link_desc_va) 1271 { 1272 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 1273 } 1274 1275 static 1276 void *hal_rx_msdu_desc_info_ptr_get_6122(void *msdu0) 1277 { 1278 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 1279 } 1280 1281 static 1282 void *hal_ent_mpdu_desc_info_6122(void *ent_ring_desc) 1283 { 1284 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 1285 } 1286 1287 static 1288 void *hal_dst_mpdu_desc_info_6122(void *dst_ring_desc) 1289 { 1290 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 1291 } 1292 1293 static 1294 uint8_t hal_rx_get_fc_valid_6122(uint8_t *buf) 1295 { 1296 return HAL_RX_GET_FC_VALID(buf); 1297 } 1298 1299 static uint8_t hal_rx_get_to_ds_flag_6122(uint8_t *buf) 1300 { 1301 return HAL_RX_GET_TO_DS_FLAG(buf); 1302 } 1303 1304 static uint8_t hal_rx_get_mac_addr2_valid_6122(uint8_t *buf) 1305 { 1306 return HAL_RX_GET_MAC_ADDR2_VALID(buf); 1307 } 1308 1309 static uint8_t hal_rx_get_filter_category_6122(uint8_t *buf) 1310 { 1311 return HAL_RX_GET_FILTER_CATEGORY(buf); 1312 } 1313 1314 static uint32_t 1315 hal_rx_get_ppdu_id_6122(uint8_t *buf) 1316 { 1317 struct rx_mpdu_info *rx_mpdu_info; 1318 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)buf; 1319 1320 rx_mpdu_info = 1321 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 1322 1323 return HAL_RX_GET_PPDU_ID(rx_mpdu_info); 1324 } 1325 1326 /** 1327 * hal_reo_config_6122(): Set reo config parameters 1328 * @soc: hal soc handle 1329 * @reg_val: value to be set 1330 * @reo_params: reo parameters 1331 * 1332 * Return: void 1333 */ 1334 static void 1335 hal_reo_config_6122(struct hal_soc *soc, 1336 uint32_t reg_val, 1337 struct hal_reo_params *reo_params) 1338 { 1339 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 1340 } 1341 1342 /** 1343 * hal_rx_msdu_desc_info_get_ptr_6122() - Get msdu desc info ptr 1344 * @msdu_details_ptr - Pointer to msdu_details_ptr 1345 * 1346 * Return - Pointer to rx_msdu_desc_info structure. 1347 * 1348 */ 1349 static void *hal_rx_msdu_desc_info_get_ptr_6122(void *msdu_details_ptr) 1350 { 1351 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 1352 } 1353 1354 /** 1355 * hal_rx_link_desc_msdu0_ptr_6122 - Get pointer to rx_msdu details 1356 * @link_desc - Pointer to link desc 1357 * 1358 * Return - Pointer to rx_msdu_details structure 1359 * 1360 */ 1361 static void *hal_rx_link_desc_msdu0_ptr_6122(void *link_desc) 1362 { 1363 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 1364 } 1365 1366 /** 1367 * hal_rx_msdu_flow_idx_get_6122: API to get flow index 1368 * from rx_msdu_end TLV 1369 * @buf: pointer to the start of RX PKT TLV headers 1370 * 1371 * Return: flow index value from MSDU END TLV 1372 */ 1373 static inline uint32_t hal_rx_msdu_flow_idx_get_6122(uint8_t *buf) 1374 { 1375 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1376 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1377 1378 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 1379 } 1380 1381 /** 1382 * hal_rx_msdu_flow_idx_invalid_6122: API to get flow index invalid 1383 * from rx_msdu_end TLV 1384 * @buf: pointer to the start of RX PKT TLV headers 1385 * 1386 * Return: flow index invalid value from MSDU END TLV 1387 */ 1388 static bool hal_rx_msdu_flow_idx_invalid_6122(uint8_t *buf) 1389 { 1390 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1391 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1392 1393 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 1394 } 1395 1396 /** 1397 * hal_rx_msdu_flow_idx_timeout_6122: API to get flow index timeout 1398 * from rx_msdu_end TLV 1399 * @buf: pointer to the start of RX PKT TLV headers 1400 * 1401 * Return: flow index timeout value from MSDU END TLV 1402 */ 1403 static bool hal_rx_msdu_flow_idx_timeout_6122(uint8_t *buf) 1404 { 1405 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1406 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1407 1408 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 1409 } 1410 1411 /** 1412 * hal_rx_msdu_fse_metadata_get_6122: API to get FSE metadata 1413 * from rx_msdu_end TLV 1414 * @buf: pointer to the start of RX PKT TLV headers 1415 * 1416 * Return: fse metadata value from MSDU END TLV 1417 */ 1418 static uint32_t hal_rx_msdu_fse_metadata_get_6122(uint8_t *buf) 1419 { 1420 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1421 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1422 1423 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end); 1424 } 1425 1426 /** 1427 * hal_rx_msdu_cce_metadata_get_6122: API to get CCE metadata 1428 * from rx_msdu_end TLV 1429 * @buf: pointer to the start of RX PKT TLV headers 1430 * 1431 * Return: cce_metadata 1432 */ 1433 static uint16_t 1434 hal_rx_msdu_cce_metadata_get_6122(uint8_t *buf) 1435 { 1436 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1437 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1438 1439 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end); 1440 } 1441 1442 /** 1443 * hal_rx_msdu_get_flow_params_6122: API to get flow index, flow index invalid 1444 * and flow index timeout from rx_msdu_end TLV 1445 * @buf: pointer to the start of RX PKT TLV headers 1446 * @flow_invalid: pointer to return value of flow_idx_valid 1447 * @flow_timeout: pointer to return value of flow_idx_timeout 1448 * @flow_index: pointer to return value of flow_idx 1449 * 1450 * Return: none 1451 */ 1452 static inline void 1453 hal_rx_msdu_get_flow_params_6122(uint8_t *buf, 1454 bool *flow_invalid, 1455 bool *flow_timeout, 1456 uint32_t *flow_index) 1457 { 1458 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1459 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1460 1461 *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 1462 *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 1463 *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 1464 } 1465 1466 /** 1467 * hal_rx_tlv_get_tcp_chksum_6122() - API to get tcp checksum 1468 * @buf: rx_tlv_hdr 1469 * 1470 * Return: tcp checksum 1471 */ 1472 static uint16_t 1473 hal_rx_tlv_get_tcp_chksum_6122(uint8_t *buf) 1474 { 1475 return HAL_RX_TLV_GET_TCP_CHKSUM(buf); 1476 } 1477 1478 /** 1479 * hal_rx_get_rx_sequence_6122(): Function to retrieve rx sequence number 1480 * 1481 * @nbuf: Network buffer 1482 * Returns: rx sequence number 1483 */ 1484 static 1485 uint16_t hal_rx_get_rx_sequence_6122(uint8_t *buf) 1486 { 1487 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 1488 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 1489 1490 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info); 1491 } 1492 1493 /** 1494 * hal_get_window_address_6122(): Function to get hp/tp address 1495 * @hal_soc: Pointer to hal_soc 1496 * @addr: address offset of register 1497 * 1498 * Return: modified address offset of register 1499 */ 1500 #define SPRUCE_SEQ_WCSS_UMAC_OFFSET 0x00a00000 1501 #define SPRUCE_CE_WFSS_CE_REG_BASE 0x3B80000 1502 static inline qdf_iomem_t hal_get_window_address_6122(struct hal_soc *hal_soc, 1503 qdf_iomem_t addr) 1504 { 1505 uint32_t offset = addr - hal_soc->dev_base_addr; 1506 qdf_iomem_t new_offset; 1507 1508 /* 1509 * If offset lies within DP register range, use 3rd window to write 1510 * into DP region. 1511 */ 1512 if ((offset ^ SPRUCE_SEQ_WCSS_UMAC_OFFSET) < WINDOW_RANGE_MASK) { 1513 new_offset = (hal_soc->dev_base_addr + (3 * WINDOW_START) + 1514 (offset & WINDOW_RANGE_MASK)); 1515 /* 1516 * If offset lies within CE register range, use 2nd window to write 1517 * into CE region. 1518 */ 1519 } else if ((offset ^ SPRUCE_CE_WFSS_CE_REG_BASE) < WINDOW_RANGE_MASK) { 1520 new_offset = (hal_soc->dev_base_addr + (2 * WINDOW_START) + 1521 (offset & WINDOW_RANGE_MASK)); 1522 } else { 1523 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 1524 "%s: ERROR: Accessing Wrong register\n", __func__); 1525 qdf_assert_always(0); 1526 return 0; 1527 } 1528 return new_offset; 1529 } 1530 1531 static inline void hal_write_window_register(struct hal_soc *hal_soc) 1532 { 1533 /* Write value into window configuration register */ 1534 qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_REG_ADDRESS, 1535 WINDOW_CONFIGURATION_VALUE_6122); 1536 } 1537 1538 /** 1539 * hal_rx_msdu_packet_metadata_get_6122(): API to get the 1540 * msdu information from rx_msdu_end TLV 1541 * 1542 * @ buf: pointer to the start of RX PKT TLV headers 1543 * @ hal_rx_msdu_metadata: pointer to the msdu info structure 1544 */ 1545 static void 1546 hal_rx_msdu_packet_metadata_get_6122(uint8_t *buf, 1547 void *msdu_pkt_metadata) 1548 { 1549 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1550 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1551 struct hal_rx_msdu_metadata *msdu_metadata = 1552 (struct hal_rx_msdu_metadata *)msdu_pkt_metadata; 1553 1554 msdu_metadata->l3_hdr_pad = 1555 HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 1556 msdu_metadata->sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 1557 msdu_metadata->da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 1558 msdu_metadata->sa_sw_peer_id = 1559 HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 1560 } 1561 1562 /** 1563 * hal_rx_flow_setup_fse_6122() - Setup a flow search entry in HW FST 1564 * @fst: Pointer to the Rx Flow Search Table 1565 * @table_offset: offset into the table where the flow is to be setup 1566 * @flow: Flow Parameters 1567 * 1568 * Return: Success/Failure 1569 */ 1570 static void * 1571 hal_rx_flow_setup_fse_6122(uint8_t *rx_fst, uint32_t table_offset, 1572 uint8_t *rx_flow) 1573 { 1574 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 1575 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 1576 uint8_t *fse; 1577 bool fse_valid; 1578 1579 if (table_offset >= fst->max_entries) { 1580 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 1581 "HAL FSE table offset %u exceeds max entries %u", 1582 table_offset, fst->max_entries); 1583 return NULL; 1584 } 1585 1586 fse = (uint8_t *)fst->base_vaddr + 1587 (table_offset * HAL_RX_FST_ENTRY_SIZE); 1588 1589 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1590 1591 if (fse_valid) { 1592 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 1593 "HAL FSE %pK already valid", fse); 1594 return NULL; 1595 } 1596 1597 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96) = 1598 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96, 1599 qdf_htonl(flow->tuple_info.src_ip_127_96)); 1600 1601 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64) = 1602 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64, 1603 qdf_htonl(flow->tuple_info.src_ip_95_64)); 1604 1605 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32) = 1606 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32, 1607 qdf_htonl(flow->tuple_info.src_ip_63_32)); 1608 1609 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0) = 1610 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0, 1611 qdf_htonl(flow->tuple_info.src_ip_31_0)); 1612 1613 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96) = 1614 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96, 1615 qdf_htonl(flow->tuple_info.dest_ip_127_96)); 1616 1617 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64) = 1618 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64, 1619 qdf_htonl(flow->tuple_info.dest_ip_95_64)); 1620 1621 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32) = 1622 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32, 1623 qdf_htonl(flow->tuple_info.dest_ip_63_32)); 1624 1625 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0) = 1626 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0, 1627 qdf_htonl(flow->tuple_info.dest_ip_31_0)); 1628 1629 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT); 1630 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT) |= 1631 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, DEST_PORT, 1632 (flow->tuple_info.dest_port)); 1633 1634 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT); 1635 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT) |= 1636 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, SRC_PORT, 1637 (flow->tuple_info.src_port)); 1638 1639 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL); 1640 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL) |= 1641 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL, 1642 flow->tuple_info.l4_protocol); 1643 1644 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER); 1645 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER) |= 1646 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER, 1647 flow->reo_destination_handler); 1648 1649 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1650 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID) |= 1651 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, VALID, 1); 1652 1653 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA); 1654 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA) = 1655 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_10, METADATA, 1656 flow->fse_metadata); 1657 1658 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION); 1659 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION) |= 1660 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, 1661 REO_DESTINATION_INDICATION, 1662 flow->reo_destination_indication); 1663 1664 /* Reset all the other fields in FSE */ 1665 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, RESERVED_9); 1666 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, MSDU_DROP); 1667 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_COUNT); 1668 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_12, MSDU_BYTE_COUNT); 1669 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_13, TIMESTAMP); 1670 1671 return fse; 1672 } 1673 1674 void hal_compute_reo_remap_ix2_ix3_6122(uint32_t *ring, uint32_t num_rings, 1675 uint32_t *remap1, uint32_t *remap2) 1676 { 1677 switch (num_rings) { 1678 case 1: 1679 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1680 HAL_REO_REMAP_IX2(ring[0], 17) | 1681 HAL_REO_REMAP_IX2(ring[0], 18) | 1682 HAL_REO_REMAP_IX2(ring[0], 19) | 1683 HAL_REO_REMAP_IX2(ring[0], 20) | 1684 HAL_REO_REMAP_IX2(ring[0], 21) | 1685 HAL_REO_REMAP_IX2(ring[0], 22) | 1686 HAL_REO_REMAP_IX2(ring[0], 23); 1687 1688 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1689 HAL_REO_REMAP_IX3(ring[0], 25) | 1690 HAL_REO_REMAP_IX3(ring[0], 26) | 1691 HAL_REO_REMAP_IX3(ring[0], 27) | 1692 HAL_REO_REMAP_IX3(ring[0], 28) | 1693 HAL_REO_REMAP_IX3(ring[0], 29) | 1694 HAL_REO_REMAP_IX3(ring[0], 30) | 1695 HAL_REO_REMAP_IX3(ring[0], 31); 1696 break; 1697 case 2: 1698 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1699 HAL_REO_REMAP_IX2(ring[0], 17) | 1700 HAL_REO_REMAP_IX2(ring[1], 18) | 1701 HAL_REO_REMAP_IX2(ring[1], 19) | 1702 HAL_REO_REMAP_IX2(ring[0], 20) | 1703 HAL_REO_REMAP_IX2(ring[0], 21) | 1704 HAL_REO_REMAP_IX2(ring[1], 22) | 1705 HAL_REO_REMAP_IX2(ring[1], 23); 1706 1707 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1708 HAL_REO_REMAP_IX3(ring[0], 25) | 1709 HAL_REO_REMAP_IX3(ring[1], 26) | 1710 HAL_REO_REMAP_IX3(ring[1], 27) | 1711 HAL_REO_REMAP_IX3(ring[0], 28) | 1712 HAL_REO_REMAP_IX3(ring[0], 29) | 1713 HAL_REO_REMAP_IX3(ring[1], 30) | 1714 HAL_REO_REMAP_IX3(ring[1], 31); 1715 break; 1716 case 3: 1717 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1718 HAL_REO_REMAP_IX2(ring[1], 17) | 1719 HAL_REO_REMAP_IX2(ring[2], 18) | 1720 HAL_REO_REMAP_IX2(ring[0], 19) | 1721 HAL_REO_REMAP_IX2(ring[1], 20) | 1722 HAL_REO_REMAP_IX2(ring[2], 21) | 1723 HAL_REO_REMAP_IX2(ring[0], 22) | 1724 HAL_REO_REMAP_IX2(ring[1], 23); 1725 1726 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) | 1727 HAL_REO_REMAP_IX3(ring[0], 25) | 1728 HAL_REO_REMAP_IX3(ring[1], 26) | 1729 HAL_REO_REMAP_IX3(ring[2], 27) | 1730 HAL_REO_REMAP_IX3(ring[0], 28) | 1731 HAL_REO_REMAP_IX3(ring[1], 29) | 1732 HAL_REO_REMAP_IX3(ring[2], 30) | 1733 HAL_REO_REMAP_IX3(ring[0], 31); 1734 break; 1735 case 4: 1736 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1737 HAL_REO_REMAP_IX2(ring[1], 17) | 1738 HAL_REO_REMAP_IX2(ring[2], 18) | 1739 HAL_REO_REMAP_IX2(ring[3], 19) | 1740 HAL_REO_REMAP_IX2(ring[0], 20) | 1741 HAL_REO_REMAP_IX2(ring[1], 21) | 1742 HAL_REO_REMAP_IX2(ring[2], 22) | 1743 HAL_REO_REMAP_IX2(ring[3], 23); 1744 1745 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1746 HAL_REO_REMAP_IX3(ring[1], 25) | 1747 HAL_REO_REMAP_IX3(ring[2], 26) | 1748 HAL_REO_REMAP_IX3(ring[3], 27) | 1749 HAL_REO_REMAP_IX3(ring[0], 28) | 1750 HAL_REO_REMAP_IX3(ring[1], 29) | 1751 HAL_REO_REMAP_IX3(ring[2], 30) | 1752 HAL_REO_REMAP_IX3(ring[3], 31); 1753 break; 1754 } 1755 } 1756 1757 static void hal_hw_txrx_ops_attach_qcn6122(struct hal_soc *hal_soc) 1758 { 1759 1760 /* init and setup */ 1761 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic; 1762 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic; 1763 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic; 1764 hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_li; 1765 hal_soc->ops->hal_get_window_address = hal_get_window_address_6122; 1766 1767 /* tx */ 1768 hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id = 1769 hal_tx_desc_set_dscp_tid_table_id_6122; 1770 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_6122; 1771 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_6122; 1772 hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_6122; 1773 hal_soc->ops->hal_tx_desc_set_buf_addr = 1774 hal_tx_desc_set_buf_addr_generic_li; 1775 hal_soc->ops->hal_tx_desc_set_search_type = 1776 hal_tx_desc_set_search_type_generic_li; 1777 hal_soc->ops->hal_tx_desc_set_search_index = 1778 hal_tx_desc_set_search_index_generic_li; 1779 hal_soc->ops->hal_tx_desc_set_cache_set_num = 1780 hal_tx_desc_set_cache_set_num_generic_li; 1781 hal_soc->ops->hal_tx_comp_get_status = 1782 hal_tx_comp_get_status_generic_li; 1783 hal_soc->ops->hal_tx_comp_get_release_reason = 1784 hal_tx_comp_get_release_reason_generic_li; 1785 hal_soc->ops->hal_get_wbm_internal_error = 1786 hal_get_wbm_internal_error_generic_li; 1787 hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_6122; 1788 hal_soc->ops->hal_tx_init_cmd_credit_ring = 1789 hal_tx_init_cmd_credit_ring_6122; 1790 1791 /* rx */ 1792 hal_soc->ops->hal_rx_msdu_start_nss_get = 1793 hal_rx_msdu_start_nss_get_6122; 1794 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status = 1795 hal_rx_mon_hw_desc_get_mpdu_status_6122; 1796 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_6122; 1797 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv = 1798 hal_rx_proc_phyrx_other_receive_info_tlv_6122; 1799 hal_soc->ops->hal_rx_dump_msdu_start_tlv = 1800 hal_rx_dump_msdu_start_tlv_6122; 1801 hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_6122; 1802 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_6122; 1803 hal_soc->ops->hal_rx_mpdu_start_tid_get = 1804 hal_rx_mpdu_start_tid_get_6122; 1805 hal_soc->ops->hal_rx_msdu_start_reception_type_get = 1806 hal_rx_msdu_start_reception_type_get_6122; 1807 hal_soc->ops->hal_rx_msdu_end_da_idx_get = 1808 hal_rx_msdu_end_da_idx_get_6122; 1809 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = 1810 hal_rx_msdu_desc_info_get_ptr_6122; 1811 hal_soc->ops->hal_rx_link_desc_msdu0_ptr = 1812 hal_rx_link_desc_msdu0_ptr_6122; 1813 hal_soc->ops->hal_reo_status_get_header = 1814 hal_reo_status_get_header_6122; 1815 hal_soc->ops->hal_rx_status_get_tlv_info = 1816 hal_rx_status_get_tlv_info_generic_li; 1817 hal_soc->ops->hal_rx_wbm_err_info_get = 1818 hal_rx_wbm_err_info_get_generic_li; 1819 hal_soc->ops->hal_rx_dump_mpdu_start_tlv = 1820 hal_rx_dump_mpdu_start_tlv_generic_li; 1821 1822 hal_soc->ops->hal_tx_set_pcp_tid_map = 1823 hal_tx_set_pcp_tid_map_generic_li; 1824 hal_soc->ops->hal_tx_update_pcp_tid_map = 1825 hal_tx_update_pcp_tid_generic_li; 1826 hal_soc->ops->hal_tx_set_tidmap_prty = 1827 hal_tx_update_tidmap_prty_generic_li; 1828 hal_soc->ops->hal_rx_get_rx_fragment_number = 1829 hal_rx_get_rx_fragment_number_6122; 1830 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = 1831 hal_rx_msdu_end_da_is_mcbc_get_6122; 1832 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = 1833 hal_rx_msdu_end_sa_is_valid_get_6122; 1834 hal_soc->ops->hal_rx_msdu_end_sa_idx_get = 1835 hal_rx_msdu_end_sa_idx_get_6122; 1836 hal_soc->ops->hal_rx_desc_is_first_msdu = 1837 hal_rx_desc_is_first_msdu_6122; 1838 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get = 1839 hal_rx_msdu_end_l3_hdr_padding_get_6122; 1840 hal_soc->ops->hal_rx_encryption_info_valid = 1841 hal_rx_encryption_info_valid_6122; 1842 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_6122; 1843 hal_soc->ops->hal_rx_msdu_end_first_msdu_get = 1844 hal_rx_msdu_end_first_msdu_get_6122; 1845 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = 1846 hal_rx_msdu_end_da_is_valid_get_6122; 1847 hal_soc->ops->hal_rx_msdu_end_last_msdu_get = 1848 hal_rx_msdu_end_last_msdu_get_6122; 1849 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = 1850 hal_rx_get_mpdu_mac_ad4_valid_6122; 1851 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get = 1852 hal_rx_mpdu_start_sw_peer_id_get_6122; 1853 hal_soc->ops->hal_rx_tlv_peer_meta_data_get = 1854 hal_rx_mpdu_peer_meta_data_get_li; 1855 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_6122; 1856 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_6122; 1857 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid = 1858 hal_rx_get_mpdu_frame_control_valid_6122; 1859 hal_soc->ops->hal_rx_get_frame_ctrl_field = 1860 hal_rx_get_mpdu_frame_control_field_6122; 1861 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_6122; 1862 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_6122; 1863 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_6122; 1864 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_6122; 1865 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid = 1866 hal_rx_get_mpdu_sequence_control_valid_6122; 1867 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_6122; 1868 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_6122; 1869 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = 1870 hal_rx_hw_desc_get_ppduid_get_6122; 1871 hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get = 1872 hal_rx_mpdu_start_mpdu_qos_control_valid_get_6122; 1873 hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get = 1874 hal_rx_msdu_end_sa_sw_peer_id_get_6122; 1875 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = 1876 hal_rx_msdu0_buffer_addr_lsb_6122; 1877 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = 1878 hal_rx_msdu_desc_info_ptr_get_6122; 1879 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_6122; 1880 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_6122; 1881 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_6122; 1882 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_6122; 1883 hal_soc->ops->hal_rx_get_mac_addr2_valid = 1884 hal_rx_get_mac_addr2_valid_6122; 1885 hal_soc->ops->hal_rx_get_filter_category = 1886 hal_rx_get_filter_category_6122; 1887 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_6122; 1888 hal_soc->ops->hal_reo_config = hal_reo_config_6122; 1889 hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_6122; 1890 hal_soc->ops->hal_rx_msdu_flow_idx_invalid = 1891 hal_rx_msdu_flow_idx_invalid_6122; 1892 hal_soc->ops->hal_rx_msdu_flow_idx_timeout = 1893 hal_rx_msdu_flow_idx_timeout_6122; 1894 hal_soc->ops->hal_rx_msdu_fse_metadata_get = 1895 hal_rx_msdu_fse_metadata_get_6122; 1896 hal_soc->ops->hal_rx_msdu_cce_match_get = 1897 hal_rx_msdu_cce_match_get_li; 1898 hal_soc->ops->hal_rx_msdu_cce_metadata_get = 1899 hal_rx_msdu_cce_metadata_get_6122; 1900 hal_soc->ops->hal_rx_msdu_get_flow_params = 1901 hal_rx_msdu_get_flow_params_6122; 1902 hal_soc->ops->hal_rx_tlv_get_tcp_chksum = 1903 hal_rx_tlv_get_tcp_chksum_6122; 1904 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_6122; 1905 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) 1906 hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_6122; 1907 hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_6122; 1908 #endif 1909 /* rx - msdu fast path info fields */ 1910 hal_soc->ops->hal_rx_msdu_packet_metadata_get = 1911 hal_rx_msdu_packet_metadata_get_6122; 1912 hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid = 1913 hal_rx_mpdu_start_tlv_tag_valid_6122; 1914 hal_soc->ops->hal_rx_sw_mon_desc_info_get = 1915 hal_rx_sw_mon_desc_info_get_6122; 1916 hal_soc->ops->hal_rx_wbm_err_msdu_continuation_get = 1917 hal_rx_wbm_err_msdu_continuation_get_6122; 1918 1919 /* rx - TLV struct offsets */ 1920 hal_soc->ops->hal_rx_msdu_end_offset_get = 1921 hal_rx_msdu_end_offset_get_generic; 1922 hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic; 1923 hal_soc->ops->hal_rx_msdu_start_offset_get = 1924 hal_rx_msdu_start_offset_get_generic; 1925 hal_soc->ops->hal_rx_mpdu_start_offset_get = 1926 hal_rx_mpdu_start_offset_get_generic; 1927 hal_soc->ops->hal_rx_mpdu_end_offset_get = 1928 hal_rx_mpdu_end_offset_get_generic; 1929 #ifndef NO_RX_PKT_HDR_TLV 1930 hal_soc->ops->hal_rx_pkt_tlv_offset_get = 1931 hal_rx_pkt_tlv_offset_get_generic; 1932 #endif 1933 hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_6122; 1934 hal_soc->ops->hal_rx_flow_get_tuple_info = 1935 hal_rx_flow_get_tuple_info_li; 1936 hal_soc->ops->hal_rx_flow_delete_entry = 1937 hal_rx_flow_delete_entry_li; 1938 hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_li; 1939 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = 1940 hal_compute_reo_remap_ix2_ix3_6122; 1941 hal_soc->ops->hal_setup_link_idle_list = 1942 hal_setup_link_idle_list_generic_li; 1943 hal_soc->ops->hal_compute_reo_remap_ix0 = NULL; 1944 hal_soc->ops->hal_rx_tlv_msdu_len_get = 1945 hal_rx_msdu_start_get_len_6122; 1946 }; 1947 1948 struct hal_hw_srng_config hw_srng_table_6122[] = { 1949 /* TODO: max_rings can populated by querying HW capabilities */ 1950 { /* REO_DST */ 1951 .start_ring_id = HAL_SRNG_REO2SW1, 1952 .max_rings = 4, 1953 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1954 .lmac_ring = FALSE, 1955 .ring_dir = HAL_SRNG_DST_RING, 1956 .reg_start = { 1957 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 1958 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1959 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 1960 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1961 }, 1962 .reg_size = { 1963 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 1964 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 1965 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 1966 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 1967 }, 1968 .max_size = 1969 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 1970 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 1971 }, 1972 { /* REO_EXCEPTION */ 1973 /* Designating REO2TCL ring as exception ring. This ring is 1974 * similar to other REO2SW rings though it is named as REO2TCL. 1975 * Any of theREO2SW rings can be used as exception ring. 1976 */ 1977 .start_ring_id = HAL_SRNG_REO2TCL, 1978 .max_rings = 1, 1979 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1980 .lmac_ring = FALSE, 1981 .ring_dir = HAL_SRNG_DST_RING, 1982 .reg_start = { 1983 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 1984 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1985 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 1986 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1987 }, 1988 /* Single ring - provide ring size if multiple rings of this 1989 * type are supported 1990 */ 1991 .reg_size = {}, 1992 .max_size = 1993 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 1994 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 1995 }, 1996 { /* REO_REINJECT */ 1997 .start_ring_id = HAL_SRNG_SW2REO, 1998 .max_rings = 1, 1999 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2000 .lmac_ring = FALSE, 2001 .ring_dir = HAL_SRNG_SRC_RING, 2002 .reg_start = { 2003 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 2004 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2005 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 2006 SEQ_WCSS_UMAC_REO_REG_OFFSET) 2007 }, 2008 /* Single ring - provide ring size if multiple rings of this 2009 * type are supported 2010 */ 2011 .reg_size = {}, 2012 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 2013 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 2014 }, 2015 { /* REO_CMD */ 2016 .start_ring_id = HAL_SRNG_REO_CMD, 2017 .max_rings = 1, 2018 .entry_size = (sizeof(struct tlv_32_hdr) + 2019 sizeof(struct reo_get_queue_stats)) >> 2, 2020 .lmac_ring = FALSE, 2021 .ring_dir = HAL_SRNG_SRC_RING, 2022 .reg_start = { 2023 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 2024 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2025 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 2026 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2027 }, 2028 /* Single ring - provide ring size if multiple rings of this 2029 * type are supported 2030 */ 2031 .reg_size = {}, 2032 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 2033 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 2034 }, 2035 { /* REO_STATUS */ 2036 .start_ring_id = HAL_SRNG_REO_STATUS, 2037 .max_rings = 1, 2038 .entry_size = (sizeof(struct tlv_32_hdr) + 2039 sizeof(struct reo_get_queue_stats_status)) >> 2, 2040 .lmac_ring = FALSE, 2041 .ring_dir = HAL_SRNG_DST_RING, 2042 .reg_start = { 2043 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 2044 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2045 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 2046 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2047 }, 2048 /* Single ring - provide ring size if multiple rings of this 2049 * type are supported 2050 */ 2051 .reg_size = {}, 2052 .max_size = 2053 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 2054 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 2055 }, 2056 { /* TCL_DATA */ 2057 .start_ring_id = HAL_SRNG_SW2TCL1, 2058 .max_rings = 3, 2059 .entry_size = (sizeof(struct tlv_32_hdr) + 2060 sizeof(struct tcl_data_cmd)) >> 2, 2061 .lmac_ring = FALSE, 2062 .ring_dir = HAL_SRNG_SRC_RING, 2063 .reg_start = { 2064 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 2065 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2066 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 2067 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2068 }, 2069 .reg_size = { 2070 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 2071 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 2072 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 2073 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 2074 }, 2075 .max_size = 2076 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 2077 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 2078 }, 2079 { /* TCL_CMD/CREDIT */ 2080 /* qca8074v2 and qcn6122 uses this ring for data commands */ 2081 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 2082 .max_rings = 1, 2083 .entry_size = (sizeof(struct tlv_32_hdr) + 2084 sizeof(struct tcl_data_cmd)) >> 2, 2085 .lmac_ring = FALSE, 2086 .ring_dir = HAL_SRNG_SRC_RING, 2087 .reg_start = { 2088 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR( 2089 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2090 HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR( 2091 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2092 }, 2093 /* Single ring - provide ring size if multiple rings of this 2094 * type are supported 2095 */ 2096 .reg_size = {}, 2097 .max_size = 2098 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >> 2099 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT, 2100 }, 2101 { /* TCL_STATUS */ 2102 .start_ring_id = HAL_SRNG_TCL_STATUS, 2103 .max_rings = 1, 2104 .entry_size = (sizeof(struct tlv_32_hdr) + 2105 sizeof(struct tcl_status_ring)) >> 2, 2106 .lmac_ring = FALSE, 2107 .ring_dir = HAL_SRNG_DST_RING, 2108 .reg_start = { 2109 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 2110 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2111 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 2112 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2113 }, 2114 /* Single ring - provide ring size if multiple rings of this 2115 * type are supported 2116 */ 2117 .reg_size = {}, 2118 .max_size = 2119 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 2120 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 2121 }, 2122 { /* CE_SRC */ 2123 .start_ring_id = HAL_SRNG_CE_0_SRC, 2124 .max_rings = 12, 2125 .entry_size = sizeof(struct ce_src_desc) >> 2, 2126 .lmac_ring = FALSE, 2127 .ring_dir = HAL_SRNG_SRC_RING, 2128 .reg_start = { 2129 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 2130 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 2131 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 2132 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 2133 }, 2134 .reg_size = { 2135 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 2136 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 2137 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 2138 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 2139 }, 2140 .max_size = 2141 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 2142 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 2143 }, 2144 { /* CE_DST */ 2145 .start_ring_id = HAL_SRNG_CE_0_DST, 2146 .max_rings = 12, 2147 .entry_size = 8 >> 2, 2148 /*TODO: entry_size above should actually be 2149 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 2150 * of struct ce_dst_desc in HW header files 2151 */ 2152 .lmac_ring = FALSE, 2153 .ring_dir = HAL_SRNG_SRC_RING, 2154 .reg_start = { 2155 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 2156 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2157 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 2158 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2159 }, 2160 .reg_size = { 2161 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2162 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2163 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2164 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2165 }, 2166 .max_size = 2167 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 2168 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 2169 }, 2170 { /* CE_DST_STATUS */ 2171 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 2172 .max_rings = 12, 2173 .entry_size = sizeof(struct ce_stat_desc) >> 2, 2174 .lmac_ring = FALSE, 2175 .ring_dir = HAL_SRNG_DST_RING, 2176 .reg_start = { 2177 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 2178 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2179 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 2180 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2181 }, 2182 /* TODO: check destination status ring registers */ 2183 .reg_size = { 2184 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2185 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2186 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2187 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2188 }, 2189 .max_size = 2190 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 2191 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 2192 }, 2193 { /* WBM_IDLE_LINK */ 2194 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 2195 .max_rings = 1, 2196 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 2197 .lmac_ring = FALSE, 2198 .ring_dir = HAL_SRNG_SRC_RING, 2199 .reg_start = { 2200 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2201 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2202 }, 2203 /* Single ring - provide ring size if multiple rings of this 2204 * type are supported 2205 */ 2206 .reg_size = {}, 2207 .max_size = 2208 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 2209 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 2210 }, 2211 { /* SW2WBM_RELEASE */ 2212 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 2213 .max_rings = 1, 2214 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2215 .lmac_ring = FALSE, 2216 .ring_dir = HAL_SRNG_SRC_RING, 2217 .reg_start = { 2218 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2219 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2220 }, 2221 /* Single ring - provide ring size if multiple rings of this 2222 * type are supported 2223 */ 2224 .reg_size = {}, 2225 .max_size = 2226 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2227 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2228 }, 2229 { /* WBM2SW_RELEASE */ 2230 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 2231 .max_rings = 5, 2232 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2233 .lmac_ring = FALSE, 2234 .ring_dir = HAL_SRNG_DST_RING, 2235 .reg_start = { 2236 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2237 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2238 }, 2239 .reg_size = { 2240 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 2241 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2242 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 2243 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2244 }, 2245 .max_size = 2246 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2247 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2248 }, 2249 { /* RXDMA_BUF */ 2250 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 2251 #ifdef IPA_OFFLOAD 2252 .max_rings = 3, 2253 #else 2254 .max_rings = 2, 2255 #endif 2256 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2257 .lmac_ring = TRUE, 2258 .ring_dir = HAL_SRNG_SRC_RING, 2259 /* reg_start is not set because LMAC rings are not accessed 2260 * from host 2261 */ 2262 .reg_start = {}, 2263 .reg_size = {}, 2264 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2265 }, 2266 { /* RXDMA_DST */ 2267 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 2268 .max_rings = 1, 2269 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2270 .lmac_ring = TRUE, 2271 .ring_dir = HAL_SRNG_DST_RING, 2272 /* reg_start is not set because LMAC rings are not accessed 2273 * from host 2274 */ 2275 .reg_start = {}, 2276 .reg_size = {}, 2277 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2278 }, 2279 { /* RXDMA_MONITOR_BUF */ 2280 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 2281 .max_rings = 1, 2282 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2283 .lmac_ring = TRUE, 2284 .ring_dir = HAL_SRNG_SRC_RING, 2285 /* reg_start is not set because LMAC rings are not accessed 2286 * from host 2287 */ 2288 .reg_start = {}, 2289 .reg_size = {}, 2290 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2291 }, 2292 { /* RXDMA_MONITOR_STATUS */ 2293 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 2294 .max_rings = 1, 2295 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2296 .lmac_ring = TRUE, 2297 .ring_dir = HAL_SRNG_SRC_RING, 2298 /* reg_start is not set because LMAC rings are not accessed 2299 * from host 2300 */ 2301 .reg_start = {}, 2302 .reg_size = {}, 2303 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2304 }, 2305 { /* RXDMA_MONITOR_DST */ 2306 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 2307 .max_rings = 1, 2308 .entry_size = sizeof(struct sw_monitor_ring) >> 2, 2309 .lmac_ring = TRUE, 2310 .ring_dir = HAL_SRNG_DST_RING, 2311 /* reg_start is not set because LMAC rings are not accessed 2312 * from host 2313 */ 2314 .reg_start = {}, 2315 .reg_size = {}, 2316 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2317 }, 2318 { /* RXDMA_MONITOR_DESC */ 2319 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 2320 .max_rings = 1, 2321 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2322 .lmac_ring = TRUE, 2323 .ring_dir = HAL_SRNG_SRC_RING, 2324 /* reg_start is not set because LMAC rings are not accessed 2325 * from host 2326 */ 2327 .reg_start = {}, 2328 .reg_size = {}, 2329 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2330 }, 2331 { /* DIR_BUF_RX_DMA_SRC */ 2332 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 2333 /* one ring for spectral and one ring for cfr */ 2334 .max_rings = 2, 2335 .entry_size = 2, 2336 .lmac_ring = TRUE, 2337 .ring_dir = HAL_SRNG_SRC_RING, 2338 /* reg_start is not set because LMAC rings are not accessed 2339 * from host 2340 */ 2341 .reg_start = {}, 2342 .reg_size = {}, 2343 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2344 }, 2345 #ifdef WLAN_FEATURE_CIF_CFR 2346 { /* WIFI_POS_SRC */ 2347 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 2348 .max_rings = 1, 2349 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 2350 .lmac_ring = TRUE, 2351 .ring_dir = HAL_SRNG_SRC_RING, 2352 /* reg_start is not set because LMAC rings are not accessed 2353 * from host 2354 */ 2355 .reg_start = {}, 2356 .reg_size = {}, 2357 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2358 }, 2359 #endif 2360 { /* REO2PPE */ 0}, 2361 { /* PPE2TCL */ 0}, 2362 { /* PPE_RELEASE */ 0}, 2363 { /* TX_MONITOR_BUF */ 0}, 2364 { /* TX_MONITOR_DST */ 0}, 2365 { /* SW2RXDMA_NEW */ 0}, 2366 }; 2367 2368 /** 2369 * hal_qcn6122_attach()- Attach 6122 target specific hal_soc ops, 2370 * offset and srng table 2371 * Return: void 2372 */ 2373 void hal_qcn6122_attach(struct hal_soc *hal_soc) 2374 { 2375 hal_soc->hw_srng_table = hw_srng_table_6122; 2376 hal_srng_hw_reg_offset_init_generic(hal_soc); 2377 2378 hal_hw_txrx_default_ops_attach_li(hal_soc); 2379 hal_hw_txrx_ops_attach_qcn6122(hal_soc); 2380 if (hal_soc->static_window_map) 2381 hal_write_window_register(hal_soc); 2382 } 2383