1 /* 2 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #include "hal_li_hw_headers.h" 19 #include "hal_internal.h" 20 #include "hal_api.h" 21 #include "target_type.h" 22 #include "wcss_version.h" 23 #include "qdf_module.h" 24 #include "hal_qcn6122_rx.h" 25 #include "hal_api_mon.h" 26 #include "hal_flow.h" 27 #include "rx_flow_search_entry.h" 28 #include "hal_rx_flow_info.h" 29 30 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 31 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET 32 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 33 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK 34 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 35 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB 36 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 37 PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 38 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 39 PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 40 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 41 PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 42 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 43 PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 44 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 45 PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 46 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 47 PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 48 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 49 PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 50 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 51 PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 52 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 53 PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 54 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 55 PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 56 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 57 PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 58 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 59 RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 60 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 61 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 62 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 63 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 64 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 65 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 66 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 67 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 68 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER \ 69 STATUS_HEADER_REO_STATUS_NUMBER 70 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 71 STATUS_HEADER_TIMESTAMP 72 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 73 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 74 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 75 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 76 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 77 TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 78 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 79 TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 80 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 81 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 82 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 83 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 84 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 85 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 86 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 87 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 88 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 89 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 90 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 91 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 92 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 93 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 94 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 95 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 96 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 97 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 98 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 99 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 100 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 101 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 102 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 103 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 104 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 105 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 106 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 107 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 108 109 #define CE_WINDOW_ADDRESS_6122 \ 110 ((SOC_WFSS_CE_REG_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) 111 112 #define UMAC_WINDOW_ADDRESS_6122 \ 113 ((SEQ_WCSS_UMAC_OFFSET >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) 114 115 #define WINDOW_CONFIGURATION_VALUE_6122 \ 116 ((CE_WINDOW_ADDRESS_6122 << 6) |\ 117 (UMAC_WINDOW_ADDRESS_6122 << 12) | \ 118 WINDOW_ENABLE_BIT) 119 120 #include "hal_qcn6122_tx.h" 121 #include <hal_generic_api.h> 122 #include "hal_li_rx.h" 123 #include "hal_li_api.h" 124 #include "hal_li_generic_api.h" 125 126 /** 127 * hal_rx_sw_mon_desc_info_get_6122(): API to read the 128 * sw monitor ring descriptor 129 * 130 * @rxdma_dst_ring_desc: sw monitor ring descriptor 131 * @desc_info_buf: Descriptor info buffer to which 132 * sw monitor ring descriptor is populated to 133 * 134 * Return: void 135 */ 136 static void 137 hal_rx_sw_mon_desc_info_get_6122(hal_ring_desc_t rxdma_dst_ring_desc, 138 hal_rx_mon_desc_info_t desc_info_buf) 139 { 140 struct sw_monitor_ring *sw_mon_ring = 141 (struct sw_monitor_ring *)rxdma_dst_ring_desc; 142 struct buffer_addr_info *buf_addr_info; 143 uint32_t *mpdu_info; 144 uint32_t loop_cnt; 145 struct hal_rx_mon_desc_info *desc_info; 146 147 desc_info = (struct hal_rx_mon_desc_info *)desc_info_buf; 148 mpdu_info = (uint32_t *)&sw_mon_ring-> 149 reo_level_mpdu_frame_info.rx_mpdu_desc_info_details; 150 151 loop_cnt = HAL_RX_GET(sw_mon_ring, SW_MONITOR_RING_7, LOOPING_COUNT); 152 desc_info->msdu_count = HAL_RX_MPDU_MSDU_COUNT_GET(mpdu_info); 153 154 /* Get msdu link descriptor buf_addr_info */ 155 buf_addr_info = &sw_mon_ring-> 156 reo_level_mpdu_frame_info.msdu_link_desc_addr_info; 157 desc_info->link_desc.paddr = HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) 158 | ((uint64_t)(HAL_RX_BUFFER_ADDR_39_32_GET( 159 buf_addr_info)) << 32); 160 desc_info->link_desc.sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info); 161 buf_addr_info = &sw_mon_ring->status_buff_addr_info; 162 desc_info->status_buf.paddr = HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) 163 | ((uint64_t) 164 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32); 165 desc_info->status_buf.sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info); 166 desc_info->end_of_ppdu = HAL_RX_GET(sw_mon_ring, 167 SW_MONITOR_RING_6, 168 END_OF_PPDU); 169 desc_info->status_buf_count = HAL_RX_GET(sw_mon_ring, 170 SW_MONITOR_RING_6, 171 STATUS_BUF_COUNT); 172 desc_info->rxdma_push_reason = HAL_RX_GET(sw_mon_ring, 173 SW_MONITOR_RING_6, 174 RXDMA_PUSH_REASON); 175 desc_info->ppdu_id = HAL_RX_GET(sw_mon_ring, 176 SW_MONITOR_RING_7, 177 PHY_PPDU_ID); 178 } 179 180 /** 181 * hal_rx_msdu_start_nss_get_6122(): API to get the NSS 182 * Interval from rx_msdu_start 183 * 184 * @buf: pointer to the start of RX PKT TLV header 185 * Return: uint32_t(nss) 186 */ 187 static uint32_t hal_rx_msdu_start_nss_get_6122(uint8_t *buf) 188 { 189 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 190 struct rx_msdu_start *msdu_start = 191 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 192 uint8_t mimo_ss_bitmap; 193 194 mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start); 195 196 return qdf_get_hweight8(mimo_ss_bitmap); 197 } 198 199 /** 200 * hal_rx_msdu_start_get_len_6122(): API to get the MSDU length 201 * from rx_msdu_start TLV 202 * 203 * @ buf: pointer to the start of RX PKT TLV headers 204 * Return: (uint32_t)msdu length 205 */ 206 static uint32_t hal_rx_msdu_start_get_len_6122(uint8_t *buf) 207 { 208 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 209 struct rx_msdu_start *msdu_start = 210 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 211 uint32_t msdu_len; 212 213 msdu_len = HAL_RX_MSDU_START_MSDU_LEN_GET(msdu_start); 214 215 return msdu_len; 216 } 217 218 /** 219 * hal_rx_mon_hw_desc_get_mpdu_status_6122(): Retrieve MPDU status 220 * 221 * @ hw_desc_addr: Start address of Rx HW TLVs 222 * @ rs: Status for monitor mode 223 * 224 * Return: void 225 */ 226 static void hal_rx_mon_hw_desc_get_mpdu_status_6122(void *hw_desc_addr, 227 struct mon_rx_status *rs) 228 { 229 struct rx_msdu_start *rx_msdu_start; 230 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 231 uint32_t reg_value; 232 const uint32_t sgi_hw_to_cdp[] = { 233 CDP_SGI_0_8_US, 234 CDP_SGI_0_4_US, 235 CDP_SGI_1_6_US, 236 CDP_SGI_3_2_US, 237 }; 238 239 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 240 241 HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs); 242 243 rs->ant_signal_db = HAL_RX_GET(rx_msdu_start, 244 RX_MSDU_START_5, USER_RSSI); 245 rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC); 246 247 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI); 248 rs->sgi = sgi_hw_to_cdp[reg_value]; 249 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE); 250 rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0; 251 /* TODO: rs->beamformed should be set for SU beamforming also */ 252 } 253 254 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 255 /** 256 * hal_get_link_desc_size_6122(): API to get the link desc size 257 * 258 * Return: uint32_t 259 */ 260 static uint32_t hal_get_link_desc_size_6122(void) 261 { 262 return LINK_DESC_SIZE; 263 } 264 265 /** 266 * hal_rx_get_tlv_6122(): API to get the tlv 267 * 268 * @rx_tlv: TLV data extracted from the rx packet 269 * Return: uint8_t 270 */ 271 static uint8_t hal_rx_get_tlv_6122(void *rx_tlv) 272 { 273 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH); 274 } 275 276 /** 277 * hal_rx_mpdu_start_tlv_tag_valid_6122 () - API to check if RX_MPDU_START 278 * tlv tag is valid 279 * 280 *@rx_tlv_hdr: start address of rx_pkt_tlvs 281 * 282 * Return: true if RX_MPDU_START is valied, else false. 283 */ 284 uint8_t hal_rx_mpdu_start_tlv_tag_valid_6122(void *rx_tlv_hdr) 285 { 286 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 287 uint32_t tlv_tag; 288 289 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(&rx_desc->mpdu_start_tlv); 290 291 return tlv_tag == WIFIRX_MPDU_START_E ? true : false; 292 } 293 294 /** 295 * hal_rx_wbm_err_msdu_continuation_get_6122 () - API to check if WBM 296 * msdu continuation bit is set 297 * 298 *@wbm_desc: wbm release ring descriptor 299 * 300 * Return: true if msdu continuation bit is set. 301 */ 302 uint8_t hal_rx_wbm_err_msdu_continuation_get_6122(void *wbm_desc) 303 { 304 uint32_t comp_desc = 305 *(uint32_t *)(((uint8_t *)wbm_desc) + 306 WBM_RELEASE_RING_3_MSDU_CONTINUATION_OFFSET); 307 308 return (comp_desc & WBM_RELEASE_RING_3_MSDU_CONTINUATION_MASK) >> 309 WBM_RELEASE_RING_3_MSDU_CONTINUATION_LSB; 310 } 311 312 /** 313 * hal_rx_proc_phyrx_other_receive_info_tlv_6122(): API to get tlv info 314 * 315 * Return: uint32_t 316 */ 317 static inline 318 void hal_rx_proc_phyrx_other_receive_info_tlv_6122(void *rx_tlv_hdr, 319 void *ppdu_info_hdl) 320 { 321 } 322 323 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) 324 static inline 325 void hal_rx_get_bb_info_6122(void *rx_tlv, 326 void *ppdu_info_hdl) 327 { 328 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 329 330 ppdu_info->cfr_info.bb_captured_channel = 331 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_CHANNEL); 332 333 ppdu_info->cfr_info.bb_captured_timeout = 334 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_TIMEOUT); 335 336 ppdu_info->cfr_info.bb_captured_reason = 337 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_REASON); 338 } 339 340 static inline 341 void hal_rx_get_rtt_info_6122(void *rx_tlv, 342 void *ppdu_info_hdl) 343 { 344 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 345 346 ppdu_info->cfr_info.rx_location_info_valid = 347 HAL_RX_GET(rx_tlv, PHYRX_PKT_END_13_RX_PKT_END_DETAILS, 348 RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID); 349 350 ppdu_info->cfr_info.rtt_che_buffer_pointer_low32 = 351 HAL_RX_GET(rx_tlv, 352 PHYRX_PKT_END_12_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 353 RTT_CHE_BUFFER_POINTER_LOW32); 354 355 ppdu_info->cfr_info.rtt_che_buffer_pointer_high8 = 356 HAL_RX_GET(rx_tlv, 357 PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 358 RTT_CHE_BUFFER_POINTER_HIGH8); 359 360 ppdu_info->cfr_info.chan_capture_status = 361 HAL_RX_GET(rx_tlv, 362 PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 363 RESERVED_8); 364 } 365 #endif 366 367 /** 368 * hal_rx_dump_msdu_start_tlv_6122() : dump RX msdu_start TLV in structured 369 * human readable format. 370 * @ msdu_start: pointer the msdu_start TLV in pkt. 371 * @ dbg_level: log level. 372 * 373 * Return: void 374 */ 375 static void hal_rx_dump_msdu_start_tlv_6122(void *msdustart, 376 uint8_t dbg_level) 377 { 378 struct rx_msdu_start *msdu_start = (struct rx_msdu_start *)msdustart; 379 380 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 381 "rx_msdu_start tlv - " 382 "rxpcu_mpdu_filter_in_category: %d " 383 "sw_frame_group_id: %d " 384 "phy_ppdu_id: %d " 385 "msdu_length: %d " 386 "ipsec_esp: %d " 387 "l3_offset: %d " 388 "ipsec_ah: %d " 389 "l4_offset: %d " 390 "msdu_number: %d " 391 "decap_format: %d " 392 "ipv4_proto: %d " 393 "ipv6_proto: %d " 394 "tcp_proto: %d " 395 "udp_proto: %d " 396 "ip_frag: %d " 397 "tcp_only_ack: %d " 398 "da_is_bcast_mcast: %d " 399 "ip4_protocol_ip6_next_header: %d " 400 "toeplitz_hash_2_or_4: %d " 401 "flow_id_toeplitz: %d " 402 "user_rssi: %d " 403 "pkt_type: %d " 404 "stbc: %d " 405 "sgi: %d " 406 "rate_mcs: %d " 407 "receive_bandwidth: %d " 408 "reception_type: %d " 409 "ppdu_start_timestamp: %d " 410 "sw_phy_meta_data: %d ", 411 msdu_start->rxpcu_mpdu_filter_in_category, 412 msdu_start->sw_frame_group_id, 413 msdu_start->phy_ppdu_id, 414 msdu_start->msdu_length, 415 msdu_start->ipsec_esp, 416 msdu_start->l3_offset, 417 msdu_start->ipsec_ah, 418 msdu_start->l4_offset, 419 msdu_start->msdu_number, 420 msdu_start->decap_format, 421 msdu_start->ipv4_proto, 422 msdu_start->ipv6_proto, 423 msdu_start->tcp_proto, 424 msdu_start->udp_proto, 425 msdu_start->ip_frag, 426 msdu_start->tcp_only_ack, 427 msdu_start->da_is_bcast_mcast, 428 msdu_start->ip4_protocol_ip6_next_header, 429 msdu_start->toeplitz_hash_2_or_4, 430 msdu_start->flow_id_toeplitz, 431 msdu_start->user_rssi, 432 msdu_start->pkt_type, 433 msdu_start->stbc, 434 msdu_start->sgi, 435 msdu_start->rate_mcs, 436 msdu_start->receive_bandwidth, 437 msdu_start->reception_type, 438 msdu_start->ppdu_start_timestamp, 439 msdu_start->sw_phy_meta_data); 440 } 441 442 /** 443 * hal_rx_dump_msdu_end_tlv_6122: dump RX msdu_end TLV in structured 444 * human readable format. 445 * @ msdu_end: pointer the msdu_end TLV in pkt. 446 * @ dbg_level: log level. 447 * 448 * Return: void 449 */ 450 static void hal_rx_dump_msdu_end_tlv_6122(void *msduend, 451 uint8_t dbg_level) 452 { 453 struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend; 454 455 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 456 "rx_msdu_end tlv - " 457 "rxpcu_mpdu_filter_in_category: %d " 458 "sw_frame_group_id: %d " 459 "phy_ppdu_id: %d " 460 "ip_hdr_chksum: %d " 461 "reported_mpdu_length: %d " 462 "key_id_octet: %d " 463 "cce_super_rule: %d " 464 "cce_classify_not_done_truncat: %d " 465 "cce_classify_not_done_cce_dis: %d " 466 "rule_indication_31_0: %d " 467 "rule_indication_63_32: %d " 468 "da_offset: %d " 469 "sa_offset: %d " 470 "da_offset_valid: %d " 471 "sa_offset_valid: %d " 472 "ipv6_options_crc: %d " 473 "tcp_seq_number: %d " 474 "tcp_ack_number: %d " 475 "tcp_flag: %d " 476 "lro_eligible: %d " 477 "window_size: %d " 478 "tcp_udp_chksum: %d " 479 "sa_idx_timeout: %d " 480 "da_idx_timeout: %d " 481 "msdu_limit_error: %d " 482 "flow_idx_timeout: %d " 483 "flow_idx_invalid: %d " 484 "wifi_parser_error: %d " 485 "amsdu_parser_error: %d " 486 "sa_is_valid: %d " 487 "da_is_valid: %d " 488 "da_is_mcbc: %d " 489 "l3_header_padding: %d " 490 "first_msdu: %d " 491 "last_msdu: %d " 492 "sa_idx: %d " 493 "msdu_drop: %d " 494 "reo_destination_indication: %d " 495 "flow_idx: %d " 496 "fse_metadata: %d " 497 "cce_metadata: %d " 498 "sa_sw_peer_id: %d ", 499 msdu_end->rxpcu_mpdu_filter_in_category, 500 msdu_end->sw_frame_group_id, 501 msdu_end->phy_ppdu_id, 502 msdu_end->ip_hdr_chksum, 503 msdu_end->reported_mpdu_length, 504 msdu_end->key_id_octet, 505 msdu_end->cce_super_rule, 506 msdu_end->cce_classify_not_done_truncate, 507 msdu_end->cce_classify_not_done_cce_dis, 508 msdu_end->rule_indication_31_0, 509 msdu_end->rule_indication_63_32, 510 msdu_end->da_offset, 511 msdu_end->sa_offset, 512 msdu_end->da_offset_valid, 513 msdu_end->sa_offset_valid, 514 msdu_end->ipv6_options_crc, 515 msdu_end->tcp_seq_number, 516 msdu_end->tcp_ack_number, 517 msdu_end->tcp_flag, 518 msdu_end->lro_eligible, 519 msdu_end->window_size, 520 msdu_end->tcp_udp_chksum, 521 msdu_end->sa_idx_timeout, 522 msdu_end->da_idx_timeout, 523 msdu_end->msdu_limit_error, 524 msdu_end->flow_idx_timeout, 525 msdu_end->flow_idx_invalid, 526 msdu_end->wifi_parser_error, 527 msdu_end->amsdu_parser_error, 528 msdu_end->sa_is_valid, 529 msdu_end->da_is_valid, 530 msdu_end->da_is_mcbc, 531 msdu_end->l3_header_padding, 532 msdu_end->first_msdu, 533 msdu_end->last_msdu, 534 msdu_end->sa_idx, 535 msdu_end->msdu_drop, 536 msdu_end->reo_destination_indication, 537 msdu_end->flow_idx, 538 msdu_end->fse_metadata, 539 msdu_end->cce_metadata, 540 msdu_end->sa_sw_peer_id); 541 } 542 543 /** 544 * hal_rx_mpdu_start_tid_get_6122(): API to get tid 545 * from rx_msdu_start 546 * 547 * @buf: pointer to the start of RX PKT TLV header 548 * Return: uint32_t(tid value) 549 */ 550 static uint32_t hal_rx_mpdu_start_tid_get_6122(uint8_t *buf) 551 { 552 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 553 struct rx_mpdu_start *mpdu_start = 554 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 555 uint32_t tid; 556 557 tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details); 558 559 return tid; 560 } 561 562 /** 563 * hal_rx_msdu_start_reception_type_get(): API to get the reception type 564 * Interval from rx_msdu_start 565 * 566 * @buf: pointer to the start of RX PKT TLV header 567 * Return: uint32_t(reception_type) 568 */ 569 static uint32_t hal_rx_msdu_start_reception_type_get_6122(uint8_t *buf) 570 { 571 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 572 struct rx_msdu_start *msdu_start = 573 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 574 uint32_t reception_type; 575 576 reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start); 577 578 return reception_type; 579 } 580 581 /** 582 * hal_rx_msdu_end_da_idx_get_6122: API to get da_idx 583 * from rx_msdu_end TLV 584 * 585 * @ buf: pointer to the start of RX PKT TLV headers 586 * Return: da index 587 */ 588 static uint16_t hal_rx_msdu_end_da_idx_get_6122(uint8_t *buf) 589 { 590 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 591 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 592 uint16_t da_idx; 593 594 da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 595 596 return da_idx; 597 } 598 599 /** 600 * hal_rx_get_rx_fragment_number_6122(): Function to retrieve rx fragment number 601 * 602 * @nbuf: Network buffer 603 * Returns: rx fragment number 604 */ 605 static 606 uint8_t hal_rx_get_rx_fragment_number_6122(uint8_t *buf) 607 { 608 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 609 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 610 611 /* Return first 4 bits as fragment number */ 612 return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & 613 DOT11_SEQ_FRAG_MASK); 614 } 615 616 /** 617 * hal_rx_msdu_end_da_is_mcbc_get_6122(): API to check if pkt is MCBC 618 * from rx_msdu_end TLV 619 * 620 * @ buf: pointer to the start of RX PKT TLV headers 621 * Return: da_is_mcbc 622 */ 623 static uint8_t 624 hal_rx_msdu_end_da_is_mcbc_get_6122(uint8_t *buf) 625 { 626 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 627 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 628 629 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); 630 } 631 632 /** 633 * hal_rx_msdu_end_sa_is_valid_get_6122(): API to get_6122 the 634 * sa_is_valid bit from rx_msdu_end TLV 635 * 636 * @ buf: pointer to the start of RX PKT TLV headers 637 * Return: sa_is_valid bit 638 */ 639 static uint8_t 640 hal_rx_msdu_end_sa_is_valid_get_6122(uint8_t *buf) 641 { 642 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 643 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 644 uint8_t sa_is_valid; 645 646 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); 647 648 return sa_is_valid; 649 } 650 651 /** 652 * hal_rx_msdu_end_sa_idx_get_6122(): API to get_6122 the 653 * sa_idx from rx_msdu_end TLV 654 * 655 * @ buf: pointer to the start of RX PKT TLV headers 656 * Return: sa_idx (SA AST index) 657 */ 658 static uint16_t hal_rx_msdu_end_sa_idx_get_6122(uint8_t *buf) 659 { 660 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 661 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 662 uint16_t sa_idx; 663 664 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 665 666 return sa_idx; 667 } 668 669 /** 670 * hal_rx_desc_is_first_msdu_6122() - Check if first msdu 671 * 672 * @hal_soc_hdl: hal_soc handle 673 * @hw_desc_addr: hardware descriptor address 674 * 675 * Return: 0 - success/ non-zero failure 676 */ 677 static uint32_t hal_rx_desc_is_first_msdu_6122(void *hw_desc_addr) 678 { 679 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; 680 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; 681 682 return HAL_RX_GET(msdu_end, RX_MSDU_END_10, FIRST_MSDU); 683 } 684 685 /** 686 * hal_rx_msdu_end_l3_hdr_padding_get_6122(): API to get_6122 the 687 * l3_header padding from rx_msdu_end TLV 688 * 689 * @ buf: pointer to the start of RX PKT TLV headers 690 * Return: number of l3 header padding bytes 691 */ 692 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_6122(uint8_t *buf) 693 { 694 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 695 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 696 uint32_t l3_header_padding; 697 698 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 699 700 return l3_header_padding; 701 } 702 703 /** 704 * @ hal_rx_encryption_info_valid_6122: Returns encryption type. 705 * 706 * @ buf: rx_tlv_hdr of the received packet 707 * @ Return: encryption type 708 */ 709 inline uint32_t hal_rx_encryption_info_valid_6122(uint8_t *buf) 710 { 711 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 712 struct rx_mpdu_start *mpdu_start = 713 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 714 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 715 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); 716 717 return encryption_info; 718 } 719 720 /* 721 * @ hal_rx_print_pn_6122: Prints the PN of rx packet. 722 * 723 * @ buf: rx_tlv_hdr of the received packet 724 * @ Return: void 725 */ 726 static void hal_rx_print_pn_6122(uint8_t *buf) 727 { 728 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 729 struct rx_mpdu_start *mpdu_start = 730 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 731 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 732 733 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); 734 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); 735 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); 736 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); 737 738 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ", 739 pn_127_96, pn_95_64, pn_63_32, pn_31_0); 740 } 741 742 /** 743 * hal_rx_msdu_end_first_msdu_get_6122: API to get first msdu status 744 * from rx_msdu_end TLV 745 * 746 * @ buf: pointer to the start of RX PKT TLV headers 747 * Return: first_msdu 748 */ 749 static uint8_t hal_rx_msdu_end_first_msdu_get_6122(uint8_t *buf) 750 { 751 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 752 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 753 uint8_t first_msdu; 754 755 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); 756 757 return first_msdu; 758 } 759 760 /** 761 * hal_rx_msdu_end_da_is_valid_get_6122: API to check if da is valid 762 * from rx_msdu_end TLV 763 * 764 * @ buf: pointer to the start of RX PKT TLV headers 765 * Return: da_is_valid 766 */ 767 static uint8_t hal_rx_msdu_end_da_is_valid_get_6122(uint8_t *buf) 768 { 769 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 770 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 771 uint8_t da_is_valid; 772 773 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); 774 775 return da_is_valid; 776 } 777 778 /** 779 * hal_rx_msdu_end_last_msdu_get_6122: API to get last msdu status 780 * from rx_msdu_end TLV 781 * 782 * @ buf: pointer to the start of RX PKT TLV headers 783 * Return: last_msdu 784 */ 785 static uint8_t hal_rx_msdu_end_last_msdu_get_6122(uint8_t *buf) 786 { 787 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 788 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 789 uint8_t last_msdu; 790 791 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); 792 793 return last_msdu; 794 } 795 796 /* 797 * hal_rx_get_mpdu_mac_ad4_valid(): Retrieves if mpdu 4th addr is valid 798 * 799 * @nbuf: Network buffer 800 * Returns: value of mpdu 4th address valid field 801 */ 802 inline bool hal_rx_get_mpdu_mac_ad4_valid_6122(uint8_t *buf) 803 { 804 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 805 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 806 bool ad4_valid = 0; 807 808 ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(rx_mpdu_info); 809 810 return ad4_valid; 811 } 812 813 /** 814 * hal_rx_mpdu_start_sw_peer_id_get_6122: Retrieve sw peer_id 815 * @buf: network buffer 816 * 817 * Return: sw peer_id 818 */ 819 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_6122(uint8_t *buf) 820 { 821 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 822 struct rx_mpdu_start *mpdu_start = 823 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 824 825 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET( 826 &mpdu_start->rx_mpdu_info_details); 827 } 828 829 /* 830 * hal_rx_mpdu_get_to_ds_6122(): API to get the tods info 831 * from rx_mpdu_start 832 * 833 * @buf: pointer to the start of RX PKT TLV header 834 * Return: uint32_t(to_ds) 835 */ 836 static uint32_t hal_rx_mpdu_get_to_ds_6122(uint8_t *buf) 837 { 838 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 839 struct rx_mpdu_start *mpdu_start = 840 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 841 842 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 843 844 return HAL_RX_MPDU_GET_TODS(mpdu_info); 845 } 846 847 /* 848 * hal_rx_mpdu_get_fr_ds_6122(): API to get the from ds info 849 * from rx_mpdu_start 850 * 851 * @buf: pointer to the start of RX PKT TLV header 852 * Return: uint32_t(fr_ds) 853 */ 854 static uint32_t hal_rx_mpdu_get_fr_ds_6122(uint8_t *buf) 855 { 856 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 857 struct rx_mpdu_start *mpdu_start = 858 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 859 860 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 861 862 return HAL_RX_MPDU_GET_FROMDS(mpdu_info); 863 } 864 865 /* 866 * hal_rx_get_mpdu_frame_control_valid_6122(): Retrieves mpdu 867 * frame control valid 868 * 869 * @nbuf: Network buffer 870 * Returns: value of frame control valid field 871 */ 872 static uint8_t hal_rx_get_mpdu_frame_control_valid_6122(uint8_t *buf) 873 { 874 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 875 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 876 877 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); 878 } 879 880 /* 881 * hal_rx_mpdu_get_addr1_6122(): API to check get address1 of the mpdu 882 * 883 * @buf: pointer to the start of RX PKT TLV headera 884 * @mac_addr: pointer to mac address 885 * Return: success/failure 886 */ 887 static QDF_STATUS hal_rx_mpdu_get_addr1_6122(uint8_t *buf, 888 uint8_t *mac_addr) 889 { 890 struct __attribute__((__packed__)) hal_addr1 { 891 uint32_t ad1_31_0; 892 uint16_t ad1_47_32; 893 }; 894 895 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 896 struct rx_mpdu_start *mpdu_start = 897 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 898 899 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 900 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; 901 uint32_t mac_addr_ad1_valid; 902 903 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); 904 905 if (mac_addr_ad1_valid) { 906 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); 907 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); 908 return QDF_STATUS_SUCCESS; 909 } 910 911 return QDF_STATUS_E_FAILURE; 912 } 913 914 /* 915 * hal_rx_mpdu_get_addr2_6122(): API to check get address2 of the mpdu 916 * in the packet 917 * 918 * @buf: pointer to the start of RX PKT TLV header 919 * @mac_addr: pointer to mac address 920 * Return: success/failure 921 */ 922 static QDF_STATUS hal_rx_mpdu_get_addr2_6122(uint8_t *buf, uint8_t *mac_addr) 923 { 924 struct __attribute__((__packed__)) hal_addr2 { 925 uint16_t ad2_15_0; 926 uint32_t ad2_47_16; 927 }; 928 929 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 930 struct rx_mpdu_start *mpdu_start = 931 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 932 933 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 934 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; 935 uint32_t mac_addr_ad2_valid; 936 937 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); 938 939 if (mac_addr_ad2_valid) { 940 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); 941 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); 942 return QDF_STATUS_SUCCESS; 943 } 944 945 return QDF_STATUS_E_FAILURE; 946 } 947 948 /* 949 * hal_rx_mpdu_get_addr3_6122(): API to get address3 of the mpdu 950 * in the packet 951 * 952 * @buf: pointer to the start of RX PKT TLV header 953 * @mac_addr: pointer to mac address 954 * Return: success/failure 955 */ 956 static QDF_STATUS hal_rx_mpdu_get_addr3_6122(uint8_t *buf, uint8_t *mac_addr) 957 { 958 struct __attribute__((__packed__)) hal_addr3 { 959 uint32_t ad3_31_0; 960 uint16_t ad3_47_32; 961 }; 962 963 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 964 struct rx_mpdu_start *mpdu_start = 965 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 966 967 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 968 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; 969 uint32_t mac_addr_ad3_valid; 970 971 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); 972 973 if (mac_addr_ad3_valid) { 974 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); 975 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); 976 return QDF_STATUS_SUCCESS; 977 } 978 979 return QDF_STATUS_E_FAILURE; 980 } 981 982 /* 983 * hal_rx_mpdu_get_addr4_6122(): API to get address4 of the mpdu 984 * in the packet 985 * 986 * @buf: pointer to the start of RX PKT TLV header 987 * @mac_addr: pointer to mac address 988 * Return: success/failure 989 */ 990 static QDF_STATUS hal_rx_mpdu_get_addr4_6122(uint8_t *buf, uint8_t *mac_addr) 991 { 992 struct __attribute__((__packed__)) hal_addr4 { 993 uint32_t ad4_31_0; 994 uint16_t ad4_47_32; 995 }; 996 997 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 998 struct rx_mpdu_start *mpdu_start = 999 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1000 1001 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 1002 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; 1003 uint32_t mac_addr_ad4_valid; 1004 1005 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); 1006 1007 if (mac_addr_ad4_valid) { 1008 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); 1009 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); 1010 return QDF_STATUS_SUCCESS; 1011 } 1012 1013 return QDF_STATUS_E_FAILURE; 1014 } 1015 1016 /* 1017 * hal_rx_get_mpdu_sequence_control_valid_6122(): Get mpdu 1018 * sequence control valid 1019 * 1020 * @nbuf: Network buffer 1021 * Returns: value of sequence control valid field 1022 */ 1023 static uint8_t hal_rx_get_mpdu_sequence_control_valid_6122(uint8_t *buf) 1024 { 1025 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 1026 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 1027 1028 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); 1029 } 1030 1031 /** 1032 * hal_rx_is_unicast_6122: check packet is unicast frame or not. 1033 * 1034 * @ buf: pointer to rx pkt TLV. 1035 * 1036 * Return: true on unicast. 1037 */ 1038 static bool hal_rx_is_unicast_6122(uint8_t *buf) 1039 { 1040 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1041 struct rx_mpdu_start *mpdu_start = 1042 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1043 uint32_t grp_id; 1044 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 1045 1046 grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 1047 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_OFFSET)), 1048 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_MASK, 1049 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_LSB)); 1050 1051 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false; 1052 } 1053 1054 /** 1055 * hal_rx_tid_get_6122: get tid based on qos control valid. 1056 * @hal_soc_hdl: hal soc handle 1057 * @buf: pointer to rx pkt TLV. 1058 * 1059 * Return: tid 1060 */ 1061 static uint32_t hal_rx_tid_get_6122(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1062 { 1063 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1064 struct rx_mpdu_start *mpdu_start = 1065 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1066 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 1067 uint8_t qos_control_valid = 1068 (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 1069 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_OFFSET)), 1070 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_MASK, 1071 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_LSB)); 1072 1073 if (qos_control_valid) 1074 return hal_rx_mpdu_start_tid_get_6122(buf); 1075 1076 return HAL_RX_NON_QOS_TID; 1077 } 1078 1079 /** 1080 * hal_rx_hw_desc_get_ppduid_get_6122(): retrieve ppdu id 1081 * @rx_tlv_hdr: rx tlv header 1082 * @rxdma_dst_ring_desc: rxdma HW descriptor 1083 * 1084 * Return: ppdu id 1085 */ 1086 static uint32_t hal_rx_hw_desc_get_ppduid_get_6122(void *rx_tlv_hdr, 1087 void *rxdma_dst_ring_desc) 1088 { 1089 struct reo_entrance_ring *reo_ent = rxdma_dst_ring_desc; 1090 1091 return reo_ent->phy_ppdu_id; 1092 } 1093 1094 /** 1095 * hal_reo_status_get_header_6122 - Process reo desc info 1096 * @ring_desc: REO status ring descriptor 1097 * @b - tlv type info 1098 * @h1 - Pointer to hal_reo_status_header where info to be stored 1099 * 1100 * Return - none. 1101 * 1102 */ 1103 static void hal_reo_status_get_header_6122(hal_ring_desc_t ring_desc, int b, 1104 void *h1) 1105 { 1106 uint32_t *d = (uint32_t *)ring_desc; 1107 uint32_t val1 = 0; 1108 struct hal_reo_status_header *h = 1109 (struct hal_reo_status_header *)h1; 1110 1111 /* Offsets of descriptor fields defined in HW headers start 1112 * from the field after TLV header 1113 */ 1114 d += HAL_GET_NUM_DWORDS(sizeof(struct tlv_32_hdr)); 1115 1116 switch (b) { 1117 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1118 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, 1119 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1120 break; 1121 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1122 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, 1123 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1124 break; 1125 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1126 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, 1127 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1128 break; 1129 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1130 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, 1131 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1132 break; 1133 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1134 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, 1135 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1136 break; 1137 case HAL_REO_DESC_THRES_STATUS_TLV: 1138 val1 = 1139 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, 1140 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1141 break; 1142 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1143 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, 1144 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1145 break; 1146 default: 1147 qdf_nofl_err("ERROR: Unknown tlv\n"); 1148 break; 1149 } 1150 h->cmd_num = 1151 HAL_GET_FIELD( 1152 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, 1153 val1); 1154 h->exec_time = 1155 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1156 CMD_EXECUTION_TIME, val1); 1157 h->status = 1158 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1159 REO_CMD_EXECUTION_STATUS, val1); 1160 switch (b) { 1161 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1162 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, 1163 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1164 break; 1165 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1166 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, 1167 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1168 break; 1169 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1170 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, 1171 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1172 break; 1173 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1174 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, 1175 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1176 break; 1177 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1178 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, 1179 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1180 break; 1181 case HAL_REO_DESC_THRES_STATUS_TLV: 1182 val1 = 1183 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, 1184 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1185 break; 1186 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1187 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, 1188 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1189 break; 1190 default: 1191 qdf_nofl_err("ERROR: Unknown tlv\n"); 1192 break; 1193 } 1194 h->tstamp = 1195 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); 1196 } 1197 1198 /** 1199 * hal_rx_mpdu_start_mpdu_qos_control_valid_get_6122(): 1200 * Retrieve qos control valid bit from the tlv. 1201 * @buf: pointer to rx pkt TLV. 1202 * 1203 * Return: qos control value. 1204 */ 1205 static inline uint32_t 1206 hal_rx_mpdu_start_mpdu_qos_control_valid_get_6122(uint8_t *buf) 1207 { 1208 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1209 struct rx_mpdu_start *mpdu_start = 1210 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1211 1212 return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET( 1213 &mpdu_start->rx_mpdu_info_details); 1214 } 1215 1216 /** 1217 * hal_rx_msdu_end_sa_sw_peer_id_get_6122(): API to get the 1218 * sa_sw_peer_id from rx_msdu_end TLV 1219 * @buf: pointer to the start of RX PKT TLV headers 1220 * 1221 * Return: sa_sw_peer_id index 1222 */ 1223 static inline uint32_t 1224 hal_rx_msdu_end_sa_sw_peer_id_get_6122(uint8_t *buf) 1225 { 1226 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1227 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1228 1229 return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 1230 } 1231 1232 /** 1233 * hal_tx_desc_set_mesh_en_6122 - Set mesh_enable flag in Tx descriptor 1234 * @desc: Handle to Tx Descriptor 1235 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 1236 * enabling the interpretation of the 'Mesh Control Present' bit 1237 * (bit 8) of QoS Control (otherwise this bit is ignored), 1238 * For native WiFi frames, this indicates that a 'Mesh Control' field 1239 * is present between the header and the LLC. 1240 * 1241 * Return: void 1242 */ 1243 static inline 1244 void hal_tx_desc_set_mesh_en_6122(void *desc, uint8_t en) 1245 { 1246 HAL_SET_FLD(desc, TCL_DATA_CMD_5, MESH_ENABLE) |= 1247 HAL_TX_SM(TCL_DATA_CMD_5, MESH_ENABLE, en); 1248 } 1249 1250 static 1251 void *hal_rx_msdu0_buffer_addr_lsb_6122(void *link_desc_va) 1252 { 1253 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 1254 } 1255 1256 static 1257 void *hal_rx_msdu_desc_info_ptr_get_6122(void *msdu0) 1258 { 1259 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 1260 } 1261 1262 static 1263 void *hal_ent_mpdu_desc_info_6122(void *ent_ring_desc) 1264 { 1265 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 1266 } 1267 1268 static 1269 void *hal_dst_mpdu_desc_info_6122(void *dst_ring_desc) 1270 { 1271 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 1272 } 1273 1274 static 1275 uint8_t hal_rx_get_fc_valid_6122(uint8_t *buf) 1276 { 1277 return HAL_RX_GET_FC_VALID(buf); 1278 } 1279 1280 static uint8_t hal_rx_get_to_ds_flag_6122(uint8_t *buf) 1281 { 1282 return HAL_RX_GET_TO_DS_FLAG(buf); 1283 } 1284 1285 static uint8_t hal_rx_get_mac_addr2_valid_6122(uint8_t *buf) 1286 { 1287 return HAL_RX_GET_MAC_ADDR2_VALID(buf); 1288 } 1289 1290 static uint8_t hal_rx_get_filter_category_6122(uint8_t *buf) 1291 { 1292 return HAL_RX_GET_FILTER_CATEGORY(buf); 1293 } 1294 1295 static uint32_t 1296 hal_rx_get_ppdu_id_6122(uint8_t *buf) 1297 { 1298 struct rx_mpdu_info *rx_mpdu_info; 1299 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)buf; 1300 1301 rx_mpdu_info = 1302 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 1303 1304 return HAL_RX_GET_PPDU_ID(rx_mpdu_info); 1305 } 1306 1307 /** 1308 * hal_reo_config_6122(): Set reo config parameters 1309 * @soc: hal soc handle 1310 * @reg_val: value to be set 1311 * @reo_params: reo parameters 1312 * 1313 * Return: void 1314 */ 1315 static void 1316 hal_reo_config_6122(struct hal_soc *soc, 1317 uint32_t reg_val, 1318 struct hal_reo_params *reo_params) 1319 { 1320 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 1321 } 1322 1323 /** 1324 * hal_rx_msdu_desc_info_get_ptr_6122() - Get msdu desc info ptr 1325 * @msdu_details_ptr - Pointer to msdu_details_ptr 1326 * 1327 * Return - Pointer to rx_msdu_desc_info structure. 1328 * 1329 */ 1330 static void *hal_rx_msdu_desc_info_get_ptr_6122(void *msdu_details_ptr) 1331 { 1332 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 1333 } 1334 1335 /** 1336 * hal_rx_link_desc_msdu0_ptr_6122 - Get pointer to rx_msdu details 1337 * @link_desc - Pointer to link desc 1338 * 1339 * Return - Pointer to rx_msdu_details structure 1340 * 1341 */ 1342 static void *hal_rx_link_desc_msdu0_ptr_6122(void *link_desc) 1343 { 1344 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 1345 } 1346 1347 /** 1348 * hal_rx_msdu_flow_idx_get_6122: API to get flow index 1349 * from rx_msdu_end TLV 1350 * @buf: pointer to the start of RX PKT TLV headers 1351 * 1352 * Return: flow index value from MSDU END TLV 1353 */ 1354 static inline uint32_t hal_rx_msdu_flow_idx_get_6122(uint8_t *buf) 1355 { 1356 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1357 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1358 1359 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 1360 } 1361 1362 /** 1363 * hal_rx_msdu_flow_idx_invalid_6122: API to get flow index invalid 1364 * from rx_msdu_end TLV 1365 * @buf: pointer to the start of RX PKT TLV headers 1366 * 1367 * Return: flow index invalid value from MSDU END TLV 1368 */ 1369 static bool hal_rx_msdu_flow_idx_invalid_6122(uint8_t *buf) 1370 { 1371 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1372 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1373 1374 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 1375 } 1376 1377 /** 1378 * hal_rx_msdu_flow_idx_timeout_6122: API to get flow index timeout 1379 * from rx_msdu_end TLV 1380 * @buf: pointer to the start of RX PKT TLV headers 1381 * 1382 * Return: flow index timeout value from MSDU END TLV 1383 */ 1384 static bool hal_rx_msdu_flow_idx_timeout_6122(uint8_t *buf) 1385 { 1386 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1387 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1388 1389 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 1390 } 1391 1392 /** 1393 * hal_rx_msdu_fse_metadata_get_6122: API to get FSE metadata 1394 * from rx_msdu_end TLV 1395 * @buf: pointer to the start of RX PKT TLV headers 1396 * 1397 * Return: fse metadata value from MSDU END TLV 1398 */ 1399 static uint32_t hal_rx_msdu_fse_metadata_get_6122(uint8_t *buf) 1400 { 1401 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1402 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1403 1404 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end); 1405 } 1406 1407 /** 1408 * hal_rx_msdu_cce_metadata_get_6122: API to get CCE metadata 1409 * from rx_msdu_end TLV 1410 * @buf: pointer to the start of RX PKT TLV headers 1411 * 1412 * Return: cce_metadata 1413 */ 1414 static uint16_t 1415 hal_rx_msdu_cce_metadata_get_6122(uint8_t *buf) 1416 { 1417 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1418 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1419 1420 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end); 1421 } 1422 1423 /** 1424 * hal_rx_msdu_get_flow_params_6122: API to get flow index, flow index invalid 1425 * and flow index timeout from rx_msdu_end TLV 1426 * @buf: pointer to the start of RX PKT TLV headers 1427 * @flow_invalid: pointer to return value of flow_idx_valid 1428 * @flow_timeout: pointer to return value of flow_idx_timeout 1429 * @flow_index: pointer to return value of flow_idx 1430 * 1431 * Return: none 1432 */ 1433 static inline void 1434 hal_rx_msdu_get_flow_params_6122(uint8_t *buf, 1435 bool *flow_invalid, 1436 bool *flow_timeout, 1437 uint32_t *flow_index) 1438 { 1439 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1440 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1441 1442 *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 1443 *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 1444 *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 1445 } 1446 1447 /** 1448 * hal_rx_tlv_get_tcp_chksum_6122() - API to get tcp checksum 1449 * @buf: rx_tlv_hdr 1450 * 1451 * Return: tcp checksum 1452 */ 1453 static uint16_t 1454 hal_rx_tlv_get_tcp_chksum_6122(uint8_t *buf) 1455 { 1456 return HAL_RX_TLV_GET_TCP_CHKSUM(buf); 1457 } 1458 1459 /** 1460 * hal_rx_get_rx_sequence_6122(): Function to retrieve rx sequence number 1461 * 1462 * @nbuf: Network buffer 1463 * Returns: rx sequence number 1464 */ 1465 static 1466 uint16_t hal_rx_get_rx_sequence_6122(uint8_t *buf) 1467 { 1468 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 1469 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 1470 1471 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info); 1472 } 1473 1474 /** 1475 * hal_get_window_address_6122(): Function to get hp/tp address 1476 * @hal_soc: Pointer to hal_soc 1477 * @addr: address offset of register 1478 * 1479 * Return: modified address offset of register 1480 */ 1481 #define SPRUCE_SEQ_WCSS_UMAC_OFFSET 0x00a00000 1482 #define SPRUCE_CE_WFSS_CE_REG_BASE 0x3B80000 1483 static inline qdf_iomem_t hal_get_window_address_6122(struct hal_soc *hal_soc, 1484 qdf_iomem_t addr) 1485 { 1486 uint32_t offset = addr - hal_soc->dev_base_addr; 1487 qdf_iomem_t new_offset; 1488 1489 /* 1490 * If offset lies within DP register range, use 3rd window to write 1491 * into DP region. 1492 */ 1493 if ((offset ^ SPRUCE_SEQ_WCSS_UMAC_OFFSET) < WINDOW_RANGE_MASK) { 1494 new_offset = (hal_soc->dev_base_addr + (3 * WINDOW_START) + 1495 (offset & WINDOW_RANGE_MASK)); 1496 /* 1497 * If offset lies within CE register range, use 2nd window to write 1498 * into CE region. 1499 */ 1500 } else if ((offset ^ SPRUCE_CE_WFSS_CE_REG_BASE) < WINDOW_RANGE_MASK) { 1501 new_offset = (hal_soc->dev_base_addr + (2 * WINDOW_START) + 1502 (offset & WINDOW_RANGE_MASK)); 1503 } else { 1504 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 1505 "%s: ERROR: Accessing Wrong register\n", __func__); 1506 qdf_assert_always(0); 1507 return 0; 1508 } 1509 return new_offset; 1510 } 1511 1512 static inline void hal_write_window_register(struct hal_soc *hal_soc) 1513 { 1514 /* Write value into window configuration register */ 1515 qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_REG_ADDRESS, 1516 WINDOW_CONFIGURATION_VALUE_6122); 1517 } 1518 1519 /** 1520 * hal_rx_msdu_packet_metadata_get_6122(): API to get the 1521 * msdu information from rx_msdu_end TLV 1522 * 1523 * @ buf: pointer to the start of RX PKT TLV headers 1524 * @ hal_rx_msdu_metadata: pointer to the msdu info structure 1525 */ 1526 static void 1527 hal_rx_msdu_packet_metadata_get_6122(uint8_t *buf, 1528 void *msdu_pkt_metadata) 1529 { 1530 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1531 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1532 struct hal_rx_msdu_metadata *msdu_metadata = 1533 (struct hal_rx_msdu_metadata *)msdu_pkt_metadata; 1534 1535 msdu_metadata->l3_hdr_pad = 1536 HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 1537 msdu_metadata->sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 1538 msdu_metadata->da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 1539 msdu_metadata->sa_sw_peer_id = 1540 HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 1541 } 1542 1543 /** 1544 * hal_rx_flow_setup_fse_6122() - Setup a flow search entry in HW FST 1545 * @fst: Pointer to the Rx Flow Search Table 1546 * @table_offset: offset into the table where the flow is to be setup 1547 * @flow: Flow Parameters 1548 * 1549 * Return: Success/Failure 1550 */ 1551 static void * 1552 hal_rx_flow_setup_fse_6122(uint8_t *rx_fst, uint32_t table_offset, 1553 uint8_t *rx_flow) 1554 { 1555 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 1556 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 1557 uint8_t *fse; 1558 bool fse_valid; 1559 1560 if (table_offset >= fst->max_entries) { 1561 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 1562 "HAL FSE table offset %u exceeds max entries %u", 1563 table_offset, fst->max_entries); 1564 return NULL; 1565 } 1566 1567 fse = (uint8_t *)fst->base_vaddr + 1568 (table_offset * HAL_RX_FST_ENTRY_SIZE); 1569 1570 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1571 1572 if (fse_valid) { 1573 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 1574 "HAL FSE %pK already valid", fse); 1575 return NULL; 1576 } 1577 1578 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96) = 1579 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96, 1580 qdf_htonl(flow->tuple_info.src_ip_127_96)); 1581 1582 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64) = 1583 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64, 1584 qdf_htonl(flow->tuple_info.src_ip_95_64)); 1585 1586 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32) = 1587 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32, 1588 qdf_htonl(flow->tuple_info.src_ip_63_32)); 1589 1590 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0) = 1591 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0, 1592 qdf_htonl(flow->tuple_info.src_ip_31_0)); 1593 1594 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96) = 1595 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96, 1596 qdf_htonl(flow->tuple_info.dest_ip_127_96)); 1597 1598 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64) = 1599 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64, 1600 qdf_htonl(flow->tuple_info.dest_ip_95_64)); 1601 1602 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32) = 1603 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32, 1604 qdf_htonl(flow->tuple_info.dest_ip_63_32)); 1605 1606 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0) = 1607 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0, 1608 qdf_htonl(flow->tuple_info.dest_ip_31_0)); 1609 1610 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT); 1611 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT) |= 1612 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, DEST_PORT, 1613 (flow->tuple_info.dest_port)); 1614 1615 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT); 1616 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT) |= 1617 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, SRC_PORT, 1618 (flow->tuple_info.src_port)); 1619 1620 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL); 1621 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL) |= 1622 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL, 1623 flow->tuple_info.l4_protocol); 1624 1625 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER); 1626 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER) |= 1627 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER, 1628 flow->reo_destination_handler); 1629 1630 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1631 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID) |= 1632 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, VALID, 1); 1633 1634 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA); 1635 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA) = 1636 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_10, METADATA, 1637 flow->fse_metadata); 1638 1639 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION); 1640 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION) |= 1641 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, 1642 REO_DESTINATION_INDICATION, 1643 flow->reo_destination_indication); 1644 1645 /* Reset all the other fields in FSE */ 1646 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, RESERVED_9); 1647 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, MSDU_DROP); 1648 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_COUNT); 1649 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_12, MSDU_BYTE_COUNT); 1650 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_13, TIMESTAMP); 1651 1652 return fse; 1653 } 1654 1655 void hal_compute_reo_remap_ix2_ix3_6122(uint32_t *ring, uint32_t num_rings, 1656 uint32_t *remap1, uint32_t *remap2) 1657 { 1658 switch (num_rings) { 1659 case 1: 1660 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1661 HAL_REO_REMAP_IX2(ring[0], 17) | 1662 HAL_REO_REMAP_IX2(ring[0], 18) | 1663 HAL_REO_REMAP_IX2(ring[0], 19) | 1664 HAL_REO_REMAP_IX2(ring[0], 20) | 1665 HAL_REO_REMAP_IX2(ring[0], 21) | 1666 HAL_REO_REMAP_IX2(ring[0], 22) | 1667 HAL_REO_REMAP_IX2(ring[0], 23); 1668 1669 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1670 HAL_REO_REMAP_IX3(ring[0], 25) | 1671 HAL_REO_REMAP_IX3(ring[0], 26) | 1672 HAL_REO_REMAP_IX3(ring[0], 27) | 1673 HAL_REO_REMAP_IX3(ring[0], 28) | 1674 HAL_REO_REMAP_IX3(ring[0], 29) | 1675 HAL_REO_REMAP_IX3(ring[0], 30) | 1676 HAL_REO_REMAP_IX3(ring[0], 31); 1677 break; 1678 case 2: 1679 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1680 HAL_REO_REMAP_IX2(ring[0], 17) | 1681 HAL_REO_REMAP_IX2(ring[1], 18) | 1682 HAL_REO_REMAP_IX2(ring[1], 19) | 1683 HAL_REO_REMAP_IX2(ring[0], 20) | 1684 HAL_REO_REMAP_IX2(ring[0], 21) | 1685 HAL_REO_REMAP_IX2(ring[1], 22) | 1686 HAL_REO_REMAP_IX2(ring[1], 23); 1687 1688 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1689 HAL_REO_REMAP_IX3(ring[0], 25) | 1690 HAL_REO_REMAP_IX3(ring[1], 26) | 1691 HAL_REO_REMAP_IX3(ring[1], 27) | 1692 HAL_REO_REMAP_IX3(ring[0], 28) | 1693 HAL_REO_REMAP_IX3(ring[0], 29) | 1694 HAL_REO_REMAP_IX3(ring[1], 30) | 1695 HAL_REO_REMAP_IX3(ring[1], 31); 1696 break; 1697 case 3: 1698 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1699 HAL_REO_REMAP_IX2(ring[1], 17) | 1700 HAL_REO_REMAP_IX2(ring[2], 18) | 1701 HAL_REO_REMAP_IX2(ring[0], 19) | 1702 HAL_REO_REMAP_IX2(ring[1], 20) | 1703 HAL_REO_REMAP_IX2(ring[2], 21) | 1704 HAL_REO_REMAP_IX2(ring[0], 22) | 1705 HAL_REO_REMAP_IX2(ring[1], 23); 1706 1707 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) | 1708 HAL_REO_REMAP_IX3(ring[0], 25) | 1709 HAL_REO_REMAP_IX3(ring[1], 26) | 1710 HAL_REO_REMAP_IX3(ring[2], 27) | 1711 HAL_REO_REMAP_IX3(ring[0], 28) | 1712 HAL_REO_REMAP_IX3(ring[1], 29) | 1713 HAL_REO_REMAP_IX3(ring[2], 30) | 1714 HAL_REO_REMAP_IX3(ring[0], 31); 1715 break; 1716 case 4: 1717 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1718 HAL_REO_REMAP_IX2(ring[1], 17) | 1719 HAL_REO_REMAP_IX2(ring[2], 18) | 1720 HAL_REO_REMAP_IX2(ring[3], 19) | 1721 HAL_REO_REMAP_IX2(ring[0], 20) | 1722 HAL_REO_REMAP_IX2(ring[1], 21) | 1723 HAL_REO_REMAP_IX2(ring[2], 22) | 1724 HAL_REO_REMAP_IX2(ring[3], 23); 1725 1726 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1727 HAL_REO_REMAP_IX3(ring[1], 25) | 1728 HAL_REO_REMAP_IX3(ring[2], 26) | 1729 HAL_REO_REMAP_IX3(ring[3], 27) | 1730 HAL_REO_REMAP_IX3(ring[0], 28) | 1731 HAL_REO_REMAP_IX3(ring[1], 29) | 1732 HAL_REO_REMAP_IX3(ring[2], 30) | 1733 HAL_REO_REMAP_IX3(ring[3], 31); 1734 break; 1735 } 1736 } 1737 1738 static void hal_hw_txrx_ops_attach_qcn6122(struct hal_soc *hal_soc) 1739 { 1740 1741 /* init and setup */ 1742 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic; 1743 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic; 1744 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic; 1745 hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_li; 1746 hal_soc->ops->hal_get_window_address = hal_get_window_address_6122; 1747 1748 /* tx */ 1749 hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id = 1750 hal_tx_desc_set_dscp_tid_table_id_6122; 1751 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_6122; 1752 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_6122; 1753 hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_6122; 1754 hal_soc->ops->hal_tx_desc_set_buf_addr = 1755 hal_tx_desc_set_buf_addr_generic_li; 1756 hal_soc->ops->hal_tx_desc_set_search_type = 1757 hal_tx_desc_set_search_type_generic_li; 1758 hal_soc->ops->hal_tx_desc_set_search_index = 1759 hal_tx_desc_set_search_index_generic_li; 1760 hal_soc->ops->hal_tx_desc_set_cache_set_num = 1761 hal_tx_desc_set_cache_set_num_generic_li; 1762 hal_soc->ops->hal_tx_comp_get_status = 1763 hal_tx_comp_get_status_generic_li; 1764 hal_soc->ops->hal_tx_comp_get_release_reason = 1765 hal_tx_comp_get_release_reason_generic_li; 1766 hal_soc->ops->hal_get_wbm_internal_error = 1767 hal_get_wbm_internal_error_generic_li; 1768 hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_6122; 1769 hal_soc->ops->hal_tx_init_cmd_credit_ring = 1770 hal_tx_init_cmd_credit_ring_6122; 1771 1772 /* rx */ 1773 hal_soc->ops->hal_rx_msdu_start_nss_get = 1774 hal_rx_msdu_start_nss_get_6122; 1775 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status = 1776 hal_rx_mon_hw_desc_get_mpdu_status_6122; 1777 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_6122; 1778 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv = 1779 hal_rx_proc_phyrx_other_receive_info_tlv_6122; 1780 hal_soc->ops->hal_rx_dump_msdu_start_tlv = 1781 hal_rx_dump_msdu_start_tlv_6122; 1782 hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_6122; 1783 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_6122; 1784 hal_soc->ops->hal_rx_mpdu_start_tid_get = 1785 hal_rx_mpdu_start_tid_get_6122; 1786 hal_soc->ops->hal_rx_msdu_start_reception_type_get = 1787 hal_rx_msdu_start_reception_type_get_6122; 1788 hal_soc->ops->hal_rx_msdu_end_da_idx_get = 1789 hal_rx_msdu_end_da_idx_get_6122; 1790 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = 1791 hal_rx_msdu_desc_info_get_ptr_6122; 1792 hal_soc->ops->hal_rx_link_desc_msdu0_ptr = 1793 hal_rx_link_desc_msdu0_ptr_6122; 1794 hal_soc->ops->hal_reo_status_get_header = 1795 hal_reo_status_get_header_6122; 1796 hal_soc->ops->hal_rx_status_get_tlv_info = 1797 hal_rx_status_get_tlv_info_generic_li; 1798 hal_soc->ops->hal_rx_wbm_err_info_get = 1799 hal_rx_wbm_err_info_get_generic_li; 1800 hal_soc->ops->hal_rx_dump_mpdu_start_tlv = 1801 hal_rx_dump_mpdu_start_tlv_generic_li; 1802 1803 hal_soc->ops->hal_tx_set_pcp_tid_map = 1804 hal_tx_set_pcp_tid_map_generic_li; 1805 hal_soc->ops->hal_tx_update_pcp_tid_map = 1806 hal_tx_update_pcp_tid_generic_li; 1807 hal_soc->ops->hal_tx_set_tidmap_prty = 1808 hal_tx_update_tidmap_prty_generic_li; 1809 hal_soc->ops->hal_rx_get_rx_fragment_number = 1810 hal_rx_get_rx_fragment_number_6122; 1811 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = 1812 hal_rx_msdu_end_da_is_mcbc_get_6122; 1813 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = 1814 hal_rx_msdu_end_sa_is_valid_get_6122; 1815 hal_soc->ops->hal_rx_msdu_end_sa_idx_get = 1816 hal_rx_msdu_end_sa_idx_get_6122; 1817 hal_soc->ops->hal_rx_desc_is_first_msdu = 1818 hal_rx_desc_is_first_msdu_6122; 1819 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get = 1820 hal_rx_msdu_end_l3_hdr_padding_get_6122; 1821 hal_soc->ops->hal_rx_encryption_info_valid = 1822 hal_rx_encryption_info_valid_6122; 1823 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_6122; 1824 hal_soc->ops->hal_rx_msdu_end_first_msdu_get = 1825 hal_rx_msdu_end_first_msdu_get_6122; 1826 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = 1827 hal_rx_msdu_end_da_is_valid_get_6122; 1828 hal_soc->ops->hal_rx_msdu_end_last_msdu_get = 1829 hal_rx_msdu_end_last_msdu_get_6122; 1830 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = 1831 hal_rx_get_mpdu_mac_ad4_valid_6122; 1832 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get = 1833 hal_rx_mpdu_start_sw_peer_id_get_6122; 1834 hal_soc->ops->hal_rx_tlv_peer_meta_data_get = 1835 hal_rx_mpdu_peer_meta_data_get_li; 1836 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_6122; 1837 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_6122; 1838 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid = 1839 hal_rx_get_mpdu_frame_control_valid_6122; 1840 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_6122; 1841 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_6122; 1842 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_6122; 1843 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_6122; 1844 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid = 1845 hal_rx_get_mpdu_sequence_control_valid_6122; 1846 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_6122; 1847 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_6122; 1848 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = 1849 hal_rx_hw_desc_get_ppduid_get_6122; 1850 hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get = 1851 hal_rx_mpdu_start_mpdu_qos_control_valid_get_6122; 1852 hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get = 1853 hal_rx_msdu_end_sa_sw_peer_id_get_6122; 1854 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = 1855 hal_rx_msdu0_buffer_addr_lsb_6122; 1856 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = 1857 hal_rx_msdu_desc_info_ptr_get_6122; 1858 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_6122; 1859 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_6122; 1860 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_6122; 1861 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_6122; 1862 hal_soc->ops->hal_rx_get_mac_addr2_valid = 1863 hal_rx_get_mac_addr2_valid_6122; 1864 hal_soc->ops->hal_rx_get_filter_category = 1865 hal_rx_get_filter_category_6122; 1866 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_6122; 1867 hal_soc->ops->hal_reo_config = hal_reo_config_6122; 1868 hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_6122; 1869 hal_soc->ops->hal_rx_msdu_flow_idx_invalid = 1870 hal_rx_msdu_flow_idx_invalid_6122; 1871 hal_soc->ops->hal_rx_msdu_flow_idx_timeout = 1872 hal_rx_msdu_flow_idx_timeout_6122; 1873 hal_soc->ops->hal_rx_msdu_fse_metadata_get = 1874 hal_rx_msdu_fse_metadata_get_6122; 1875 hal_soc->ops->hal_rx_msdu_cce_match_get = 1876 hal_rx_msdu_cce_match_get_li; 1877 hal_soc->ops->hal_rx_msdu_cce_metadata_get = 1878 hal_rx_msdu_cce_metadata_get_6122; 1879 hal_soc->ops->hal_rx_msdu_get_flow_params = 1880 hal_rx_msdu_get_flow_params_6122; 1881 hal_soc->ops->hal_rx_tlv_get_tcp_chksum = 1882 hal_rx_tlv_get_tcp_chksum_6122; 1883 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_6122; 1884 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) 1885 hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_6122; 1886 hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_6122; 1887 #endif 1888 /* rx - msdu fast path info fields */ 1889 hal_soc->ops->hal_rx_msdu_packet_metadata_get = 1890 hal_rx_msdu_packet_metadata_get_6122; 1891 hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid = 1892 hal_rx_mpdu_start_tlv_tag_valid_6122; 1893 hal_soc->ops->hal_rx_sw_mon_desc_info_get = 1894 hal_rx_sw_mon_desc_info_get_6122; 1895 hal_soc->ops->hal_rx_wbm_err_msdu_continuation_get = 1896 hal_rx_wbm_err_msdu_continuation_get_6122; 1897 1898 /* rx - TLV struct offsets */ 1899 hal_soc->ops->hal_rx_msdu_end_offset_get = 1900 hal_rx_msdu_end_offset_get_generic; 1901 hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic; 1902 hal_soc->ops->hal_rx_msdu_start_offset_get = 1903 hal_rx_msdu_start_offset_get_generic; 1904 hal_soc->ops->hal_rx_mpdu_start_offset_get = 1905 hal_rx_mpdu_start_offset_get_generic; 1906 hal_soc->ops->hal_rx_mpdu_end_offset_get = 1907 hal_rx_mpdu_end_offset_get_generic; 1908 #ifndef NO_RX_PKT_HDR_TLV 1909 hal_soc->ops->hal_rx_pkt_tlv_offset_get = 1910 hal_rx_pkt_tlv_offset_get_generic; 1911 #endif 1912 hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_6122; 1913 hal_soc->ops->hal_rx_flow_get_tuple_info = 1914 hal_rx_flow_get_tuple_info_li; 1915 hal_soc->ops->hal_rx_flow_delete_entry = 1916 hal_rx_flow_delete_entry_li; 1917 hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_li; 1918 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = 1919 hal_compute_reo_remap_ix2_ix3_6122; 1920 hal_soc->ops->hal_setup_link_idle_list = 1921 hal_setup_link_idle_list_generic_li; 1922 hal_soc->ops->hal_compute_reo_remap_ix0 = NULL; 1923 hal_soc->ops->hal_rx_tlv_msdu_len_get = 1924 hal_rx_msdu_start_get_len_6122; 1925 }; 1926 1927 struct hal_hw_srng_config hw_srng_table_6122[] = { 1928 /* TODO: max_rings can populated by querying HW capabilities */ 1929 { /* REO_DST */ 1930 .start_ring_id = HAL_SRNG_REO2SW1, 1931 .max_rings = 4, 1932 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1933 .lmac_ring = FALSE, 1934 .ring_dir = HAL_SRNG_DST_RING, 1935 .reg_start = { 1936 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 1937 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1938 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 1939 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1940 }, 1941 .reg_size = { 1942 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 1943 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 1944 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 1945 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 1946 }, 1947 .max_size = 1948 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 1949 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 1950 }, 1951 { /* REO_EXCEPTION */ 1952 /* Designating REO2TCL ring as exception ring. This ring is 1953 * similar to other REO2SW rings though it is named as REO2TCL. 1954 * Any of theREO2SW rings can be used as exception ring. 1955 */ 1956 .start_ring_id = HAL_SRNG_REO2TCL, 1957 .max_rings = 1, 1958 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1959 .lmac_ring = FALSE, 1960 .ring_dir = HAL_SRNG_DST_RING, 1961 .reg_start = { 1962 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 1963 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1964 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 1965 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1966 }, 1967 /* Single ring - provide ring size if multiple rings of this 1968 * type are supported 1969 */ 1970 .reg_size = {}, 1971 .max_size = 1972 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 1973 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 1974 }, 1975 { /* REO_REINJECT */ 1976 .start_ring_id = HAL_SRNG_SW2REO, 1977 .max_rings = 1, 1978 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1979 .lmac_ring = FALSE, 1980 .ring_dir = HAL_SRNG_SRC_RING, 1981 .reg_start = { 1982 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 1983 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1984 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 1985 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1986 }, 1987 /* Single ring - provide ring size if multiple rings of this 1988 * type are supported 1989 */ 1990 .reg_size = {}, 1991 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 1992 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 1993 }, 1994 { /* REO_CMD */ 1995 .start_ring_id = HAL_SRNG_REO_CMD, 1996 .max_rings = 1, 1997 .entry_size = (sizeof(struct tlv_32_hdr) + 1998 sizeof(struct reo_get_queue_stats)) >> 2, 1999 .lmac_ring = FALSE, 2000 .ring_dir = HAL_SRNG_SRC_RING, 2001 .reg_start = { 2002 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 2003 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2004 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 2005 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2006 }, 2007 /* Single ring - provide ring size if multiple rings of this 2008 * type are supported 2009 */ 2010 .reg_size = {}, 2011 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 2012 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 2013 }, 2014 { /* REO_STATUS */ 2015 .start_ring_id = HAL_SRNG_REO_STATUS, 2016 .max_rings = 1, 2017 .entry_size = (sizeof(struct tlv_32_hdr) + 2018 sizeof(struct reo_get_queue_stats_status)) >> 2, 2019 .lmac_ring = FALSE, 2020 .ring_dir = HAL_SRNG_DST_RING, 2021 .reg_start = { 2022 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 2023 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2024 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 2025 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2026 }, 2027 /* Single ring - provide ring size if multiple rings of this 2028 * type are supported 2029 */ 2030 .reg_size = {}, 2031 .max_size = 2032 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 2033 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 2034 }, 2035 { /* TCL_DATA */ 2036 .start_ring_id = HAL_SRNG_SW2TCL1, 2037 .max_rings = 3, 2038 .entry_size = (sizeof(struct tlv_32_hdr) + 2039 sizeof(struct tcl_data_cmd)) >> 2, 2040 .lmac_ring = FALSE, 2041 .ring_dir = HAL_SRNG_SRC_RING, 2042 .reg_start = { 2043 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 2044 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2045 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 2046 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2047 }, 2048 .reg_size = { 2049 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 2050 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 2051 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 2052 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 2053 }, 2054 .max_size = 2055 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 2056 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 2057 }, 2058 { /* TCL_CMD/CREDIT */ 2059 /* qca8074v2 and qcn6122 uses this ring for data commands */ 2060 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 2061 .max_rings = 1, 2062 .entry_size = (sizeof(struct tlv_32_hdr) + 2063 sizeof(struct tcl_data_cmd)) >> 2, 2064 .lmac_ring = FALSE, 2065 .ring_dir = HAL_SRNG_SRC_RING, 2066 .reg_start = { 2067 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR( 2068 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2069 HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR( 2070 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2071 }, 2072 /* Single ring - provide ring size if multiple rings of this 2073 * type are supported 2074 */ 2075 .reg_size = {}, 2076 .max_size = 2077 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >> 2078 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT, 2079 }, 2080 { /* TCL_STATUS */ 2081 .start_ring_id = HAL_SRNG_TCL_STATUS, 2082 .max_rings = 1, 2083 .entry_size = (sizeof(struct tlv_32_hdr) + 2084 sizeof(struct tcl_status_ring)) >> 2, 2085 .lmac_ring = FALSE, 2086 .ring_dir = HAL_SRNG_DST_RING, 2087 .reg_start = { 2088 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 2089 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2090 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 2091 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2092 }, 2093 /* Single ring - provide ring size if multiple rings of this 2094 * type are supported 2095 */ 2096 .reg_size = {}, 2097 .max_size = 2098 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 2099 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 2100 }, 2101 { /* CE_SRC */ 2102 .start_ring_id = HAL_SRNG_CE_0_SRC, 2103 .max_rings = 12, 2104 .entry_size = sizeof(struct ce_src_desc) >> 2, 2105 .lmac_ring = FALSE, 2106 .ring_dir = HAL_SRNG_SRC_RING, 2107 .reg_start = { 2108 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 2109 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 2110 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 2111 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 2112 }, 2113 .reg_size = { 2114 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 2115 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 2116 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 2117 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 2118 }, 2119 .max_size = 2120 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 2121 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 2122 }, 2123 { /* CE_DST */ 2124 .start_ring_id = HAL_SRNG_CE_0_DST, 2125 .max_rings = 12, 2126 .entry_size = 8 >> 2, 2127 /*TODO: entry_size above should actually be 2128 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 2129 * of struct ce_dst_desc in HW header files 2130 */ 2131 .lmac_ring = FALSE, 2132 .ring_dir = HAL_SRNG_SRC_RING, 2133 .reg_start = { 2134 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 2135 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2136 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 2137 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2138 }, 2139 .reg_size = { 2140 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2141 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2142 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2143 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2144 }, 2145 .max_size = 2146 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 2147 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 2148 }, 2149 { /* CE_DST_STATUS */ 2150 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 2151 .max_rings = 12, 2152 .entry_size = sizeof(struct ce_stat_desc) >> 2, 2153 .lmac_ring = FALSE, 2154 .ring_dir = HAL_SRNG_DST_RING, 2155 .reg_start = { 2156 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 2157 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2158 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 2159 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2160 }, 2161 /* TODO: check destination status ring registers */ 2162 .reg_size = { 2163 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2164 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2165 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2166 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2167 }, 2168 .max_size = 2169 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 2170 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 2171 }, 2172 { /* WBM_IDLE_LINK */ 2173 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 2174 .max_rings = 1, 2175 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 2176 .lmac_ring = FALSE, 2177 .ring_dir = HAL_SRNG_SRC_RING, 2178 .reg_start = { 2179 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2180 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2181 }, 2182 /* Single ring - provide ring size if multiple rings of this 2183 * type are supported 2184 */ 2185 .reg_size = {}, 2186 .max_size = 2187 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 2188 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 2189 }, 2190 { /* SW2WBM_RELEASE */ 2191 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 2192 .max_rings = 1, 2193 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2194 .lmac_ring = FALSE, 2195 .ring_dir = HAL_SRNG_SRC_RING, 2196 .reg_start = { 2197 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2198 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2199 }, 2200 /* Single ring - provide ring size if multiple rings of this 2201 * type are supported 2202 */ 2203 .reg_size = {}, 2204 .max_size = 2205 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2206 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2207 }, 2208 { /* WBM2SW_RELEASE */ 2209 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 2210 .max_rings = 5, 2211 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2212 .lmac_ring = FALSE, 2213 .ring_dir = HAL_SRNG_DST_RING, 2214 .reg_start = { 2215 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2216 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2217 }, 2218 .reg_size = { 2219 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 2220 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2221 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 2222 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2223 }, 2224 .max_size = 2225 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2226 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2227 }, 2228 { /* RXDMA_BUF */ 2229 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 2230 #ifdef IPA_OFFLOAD 2231 .max_rings = 3, 2232 #else 2233 .max_rings = 2, 2234 #endif 2235 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2236 .lmac_ring = TRUE, 2237 .ring_dir = HAL_SRNG_SRC_RING, 2238 /* reg_start is not set because LMAC rings are not accessed 2239 * from host 2240 */ 2241 .reg_start = {}, 2242 .reg_size = {}, 2243 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2244 }, 2245 { /* RXDMA_DST */ 2246 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 2247 .max_rings = 1, 2248 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2249 .lmac_ring = TRUE, 2250 .ring_dir = HAL_SRNG_DST_RING, 2251 /* reg_start is not set because LMAC rings are not accessed 2252 * from host 2253 */ 2254 .reg_start = {}, 2255 .reg_size = {}, 2256 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2257 }, 2258 { /* RXDMA_MONITOR_BUF */ 2259 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 2260 .max_rings = 1, 2261 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2262 .lmac_ring = TRUE, 2263 .ring_dir = HAL_SRNG_SRC_RING, 2264 /* reg_start is not set because LMAC rings are not accessed 2265 * from host 2266 */ 2267 .reg_start = {}, 2268 .reg_size = {}, 2269 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2270 }, 2271 { /* RXDMA_MONITOR_STATUS */ 2272 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 2273 .max_rings = 1, 2274 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2275 .lmac_ring = TRUE, 2276 .ring_dir = HAL_SRNG_SRC_RING, 2277 /* reg_start is not set because LMAC rings are not accessed 2278 * from host 2279 */ 2280 .reg_start = {}, 2281 .reg_size = {}, 2282 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2283 }, 2284 { /* RXDMA_MONITOR_DST */ 2285 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 2286 .max_rings = 1, 2287 .entry_size = sizeof(struct sw_monitor_ring) >> 2, 2288 .lmac_ring = TRUE, 2289 .ring_dir = HAL_SRNG_DST_RING, 2290 /* reg_start is not set because LMAC rings are not accessed 2291 * from host 2292 */ 2293 .reg_start = {}, 2294 .reg_size = {}, 2295 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2296 }, 2297 { /* RXDMA_MONITOR_DESC */ 2298 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 2299 .max_rings = 1, 2300 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2301 .lmac_ring = TRUE, 2302 .ring_dir = HAL_SRNG_SRC_RING, 2303 /* reg_start is not set because LMAC rings are not accessed 2304 * from host 2305 */ 2306 .reg_start = {}, 2307 .reg_size = {}, 2308 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2309 }, 2310 { /* DIR_BUF_RX_DMA_SRC */ 2311 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 2312 /* one ring for spectral and one ring for cfr */ 2313 .max_rings = 2, 2314 .entry_size = 2, 2315 .lmac_ring = TRUE, 2316 .ring_dir = HAL_SRNG_SRC_RING, 2317 /* reg_start is not set because LMAC rings are not accessed 2318 * from host 2319 */ 2320 .reg_start = {}, 2321 .reg_size = {}, 2322 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2323 }, 2324 #ifdef WLAN_FEATURE_CIF_CFR 2325 { /* WIFI_POS_SRC */ 2326 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 2327 .max_rings = 1, 2328 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 2329 .lmac_ring = TRUE, 2330 .ring_dir = HAL_SRNG_SRC_RING, 2331 /* reg_start is not set because LMAC rings are not accessed 2332 * from host 2333 */ 2334 .reg_start = {}, 2335 .reg_size = {}, 2336 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2337 }, 2338 #endif 2339 { /* REO2PPE */ 0}, 2340 { /* PPE2TCL */ 0}, 2341 { /* PPE_RELEASE */ 0}, 2342 { /* TX_MONITOR_BUF */ 0}, 2343 { /* TX_MONITOR_DST */ 0}, 2344 { /* SW2RXDMA_NEW */ 0}, 2345 }; 2346 2347 /** 2348 * hal_qcn6122_attach()- Attach 6122 target specific hal_soc ops, 2349 * offset and srng table 2350 * Return: void 2351 */ 2352 void hal_qcn6122_attach(struct hal_soc *hal_soc) 2353 { 2354 hal_soc->hw_srng_table = hw_srng_table_6122; 2355 hal_srng_hw_reg_offset_init_generic(hal_soc); 2356 2357 hal_hw_txrx_default_ops_attach_li(hal_soc); 2358 hal_hw_txrx_ops_attach_qcn6122(hal_soc); 2359 if (hal_soc->static_window_map) 2360 hal_write_window_register(hal_soc); 2361 } 2362