1 /* 2 * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 #include "hal_hw_headers.h" 20 #include "hal_internal.h" 21 #include "cdp_txrx_mon_struct.h" 22 #include "qdf_trace.h" 23 #include "hal_rx.h" 24 #include "hal_tx.h" 25 #include "dp_types.h" 26 #include "hal_api_mon.h" 27 28 /** 29 * hal_tx_desc_set_dscp_tid_table_id_8074v2() - Sets DSCP to TID conversion 30 * table ID 31 * @desc: Handle to Tx Descriptor 32 * @id: DSCP to tid conversion table to be used for this frame 33 * 34 * Return: void 35 */ 36 37 static void hal_tx_desc_set_dscp_tid_table_id_8074v2(void *desc, uint8_t id) 38 { 39 HAL_SET_FLD(desc, TCL_DATA_CMD_5, 40 DSCP_TID_TABLE_NUM) |= 41 HAL_TX_SM(TCL_DATA_CMD_5, 42 DSCP_TID_TABLE_NUM, id); 43 } 44 45 46 #define DSCP_TID_TABLE_SIZE 24 47 #define NUM_WORDS_PER_DSCP_TID_TABLE (DSCP_TID_TABLE_SIZE / 4) 48 #define HAL_TX_NUM_DSCP_REGISTER_SIZE 32 49 /** 50 * hal_tx_set_dscp_tid_map_8074v2() - Configure default DSCP to TID map table 51 * @soc: HAL SoC context 52 * @map: DSCP-TID mapping table 53 * @id: mapping table ID - 0,1 54 * 55 * DSCP are mapped to 8 TID values using TID values programmed 56 * in two set of mapping registers DSCP_TID1_MAP_<0 to 6> (id = 0) 57 * and DSCP_TID2_MAP_<0 to 6> (id = 1) 58 * Each mapping register has TID mapping for 10 DSCP values 59 * 60 * Return: none 61 */ 62 63 static void hal_tx_set_dscp_tid_map_8074v2(struct hal_soc *soc, 64 uint8_t *map, 65 uint8_t id) 66 { 67 int i; 68 uint32_t addr, cmn_reg_addr; 69 uint32_t value = 0, regval; 70 uint8_t val[DSCP_TID_TABLE_SIZE], cnt = 0; 71 72 if (id >= HAL_MAX_HW_DSCP_TID_V2_MAPS) 73 return; 74 75 cmn_reg_addr = HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR( 76 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET); 77 78 addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR( 79 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET, 80 id * NUM_WORDS_PER_DSCP_TID_TABLE); 81 82 /* Enable read/write access */ 83 regval = HAL_REG_READ(soc, cmn_reg_addr); 84 regval |= 85 (1 << HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT); 86 87 HAL_REG_WRITE(soc, cmn_reg_addr, regval); 88 89 /* Write 8 (24 bits) DSCP-TID mappings in each iteration */ 90 for (i = 0; i < 64; i += 8) { 91 value = (map[i] | 92 (map[i + 1] << 0x3) | 93 (map[i + 2] << 0x6) | 94 (map[i + 3] << 0x9) | 95 (map[i + 4] << 0xc) | 96 (map[i + 5] << 0xf) | 97 (map[i + 6] << 0x12) | 98 (map[i + 7] << 0x15)); 99 100 qdf_mem_copy(&val[cnt], &value, 3); 101 cnt += 3; 102 } 103 104 for (i = 0; i < DSCP_TID_TABLE_SIZE; i += 4) { 105 regval = *(uint32_t *)(val + i); 106 HAL_REG_WRITE(soc, addr, 107 (regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK)); 108 addr += 4; 109 } 110 111 /* Diasble read/write access */ 112 regval = HAL_REG_READ(soc, cmn_reg_addr); 113 regval &= 114 ~(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK); 115 116 HAL_REG_WRITE(soc, cmn_reg_addr, regval); 117 } 118 119 /** 120 * hal_tx_update_dscp_tid_8074v2() - Update the dscp tid map table as 121 updated by user 122 * @soc: HAL SoC context 123 * @map: DSCP-TID mapping table 124 * @id : MAP ID 125 * @dscp: DSCP_TID map index 126 * 127 * Return: void 128 */ 129 static void hal_tx_update_dscp_tid_8074v2(struct hal_soc *soc, uint8_t tid, 130 uint8_t id, uint8_t dscp) 131 { 132 uint32_t addr, addr1, cmn_reg_addr, regmask = 0xFFFFFFFF; 133 uint32_t start_value = 0, end_value = 0; 134 uint32_t regval; 135 uint8_t end_bits = 0; 136 uint8_t start_bits = 0; 137 uint32_t start_index, end_index; 138 cmn_reg_addr = HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR( 139 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET); 140 141 addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR( 142 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET, 143 id * NUM_WORDS_PER_DSCP_TID_TABLE); 144 145 start_index = dscp * HAL_TX_BITS_PER_TID; 146 end_index = (start_index + (HAL_TX_BITS_PER_TID - 1)) 147 % HAL_TX_NUM_DSCP_REGISTER_SIZE; 148 start_index = start_index % HAL_TX_NUM_DSCP_REGISTER_SIZE; 149 addr += (4 * ((dscp * HAL_TX_BITS_PER_TID) / 150 HAL_TX_NUM_DSCP_REGISTER_SIZE)); 151 152 if (end_index < start_index) { 153 end_bits = end_index + 1; 154 start_bits = HAL_TX_BITS_PER_TID - end_bits; 155 start_value = tid << start_index; 156 end_value = tid >> start_bits; 157 addr1 = addr + 4; 158 } else { 159 start_bits = HAL_TX_BITS_PER_TID - end_bits; 160 start_value = tid << start_index; 161 addr1 = 0; 162 } 163 164 /* Enable read/write access */ 165 regval = HAL_REG_READ(soc, cmn_reg_addr); 166 regval |= 167 (1 << HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT); 168 169 HAL_REG_WRITE(soc, cmn_reg_addr, regval); 170 171 regval = HAL_REG_READ(soc, addr); 172 173 if (end_index < start_index) 174 regval &= (regmask >> start_bits); 175 else 176 regval &= ~(7 << start_index); 177 178 regval |= start_value; 179 180 HAL_REG_WRITE(soc, addr, (regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK)); 181 182 if (addr1) { 183 regval = HAL_REG_READ(soc, addr1); 184 regval &= (~0) << end_bits; 185 regval |= end_value; 186 187 HAL_REG_WRITE(soc, addr1, (regval & 188 HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK)); 189 } 190 191 /* Diasble read/write access */ 192 regval = HAL_REG_READ(soc, cmn_reg_addr); 193 regval &= 194 ~(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK); 195 HAL_REG_WRITE(soc, cmn_reg_addr, regval); 196 } 197 198 /** 199 * hal_tx_desc_set_lmac_id - Set the lmac_id value 200 * @desc: Handle to Tx Descriptor 201 * @lmac_id: mac Id to ast matching 202 * b00 – mac 0 203 * b01 – mac 1 204 * b10 – mac 2 205 * b11 – all macs (legacy HK way) 206 * 207 * Return: void 208 */ 209 static void hal_tx_desc_set_lmac_id_8074v2(void *desc, uint8_t lmac_id) 210 { 211 HAL_SET_FLD(desc, TCL_DATA_CMD_4, LMAC_ID) |= 212 HAL_TX_SM(TCL_DATA_CMD_4, LMAC_ID, lmac_id); 213 } 214 215 /** 216 * hal_tx_init_cmd_credit_ring_8074v2() - Initialize command/credit SRNG 217 * @hal_soc_hdl: Handle to HAL SoC structure 218 * @hal_srng: Handle to HAL SRNG structure 219 * 220 * Return: none 221 */ 222 static inline void hal_tx_init_cmd_credit_ring_8074v2(hal_soc_handle_t hal_soc_hdl, 223 hal_ring_handle_t hal_ring_hdl) 224 { 225 uint8_t *desc_addr; 226 struct hal_srng_params srng_params; 227 uint32_t desc_size; 228 uint32_t num_desc; 229 230 hal_get_srng_params(hal_soc_hdl, hal_ring_hdl, &srng_params); 231 232 desc_addr = (uint8_t *)srng_params.ring_base_vaddr; 233 desc_size = sizeof(struct tcl_data_cmd); 234 num_desc = srng_params.num_entries; 235 236 while (num_desc) { 237 /* using CMD/CREDIT Ring to send DATA CMD tag */ 238 HAL_TX_DESC_SET_TLV_HDR(desc_addr, WIFITCL_DATA_CMD_E, 239 desc_size); 240 desc_addr += (desc_size + sizeof(struct tlv_32_hdr)); 241 num_desc--; 242 } 243 } 244