1 /* 2 * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #include "hal_hw_headers.h" 19 #include "hal_internal.h" 20 #include "cdp_txrx_mon_struct.h" 21 #include "qdf_trace.h" 22 #include "hal_rx.h" 23 #include "hal_tx.h" 24 #include "dp_types.h" 25 #include "hal_api_mon.h" 26 27 /** 28 * hal_tx_desc_set_dscp_tid_table_id_8074v2() - Sets DSCP to TID conversion 29 * table ID 30 * @desc: Handle to Tx Descriptor 31 * @id: DSCP to tid conversion table to be used for this frame 32 * 33 * Return: void 34 */ 35 36 static void hal_tx_desc_set_dscp_tid_table_id_8074v2(void *desc, uint8_t id) 37 { 38 HAL_SET_FLD(desc, TCL_DATA_CMD_5, 39 DSCP_TID_TABLE_NUM) |= 40 HAL_TX_SM(TCL_DATA_CMD_5, 41 DSCP_TID_TABLE_NUM, id); 42 } 43 44 45 #define DSCP_TID_TABLE_SIZE 24 46 #define NUM_WORDS_PER_DSCP_TID_TABLE (DSCP_TID_TABLE_SIZE / 4) 47 #define HAL_TX_NUM_DSCP_REGISTER_SIZE 32 48 /** 49 * hal_tx_set_dscp_tid_map_8074v2() - Configure default DSCP to TID map table 50 * @soc: HAL SoC context 51 * @map: DSCP-TID mapping table 52 * @id: mapping table ID - 0,1 53 * 54 * DSCP are mapped to 8 TID values using TID values programmed 55 * in two set of mapping registers DSCP_TID1_MAP_<0 to 6> (id = 0) 56 * and DSCP_TID2_MAP_<0 to 6> (id = 1) 57 * Each mapping register has TID mapping for 10 DSCP values 58 * 59 * Return: none 60 */ 61 62 static void hal_tx_set_dscp_tid_map_8074v2(void *hal_soc, uint8_t *map, 63 uint8_t id) 64 { 65 int i; 66 uint32_t addr, cmn_reg_addr; 67 uint32_t value = 0, regval; 68 uint8_t val[DSCP_TID_TABLE_SIZE], cnt = 0; 69 70 struct hal_soc *soc = (struct hal_soc *)hal_soc; 71 72 if (id >= HAL_MAX_HW_DSCP_TID_V2_MAPS) 73 return; 74 75 cmn_reg_addr = HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR( 76 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET); 77 78 addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR( 79 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET, 80 id * NUM_WORDS_PER_DSCP_TID_TABLE); 81 82 /* Enable read/write access */ 83 regval = HAL_REG_READ(soc, cmn_reg_addr); 84 regval |= 85 (1 << HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT); 86 87 HAL_REG_WRITE(soc, cmn_reg_addr, regval); 88 89 /* Write 8 (24 bits) DSCP-TID mappings in each interation */ 90 for (i = 0; i < 64; i += 8) { 91 value = (map[i] | 92 (map[i + 1] << 0x3) | 93 (map[i + 2] << 0x6) | 94 (map[i + 3] << 0x9) | 95 (map[i + 4] << 0xc) | 96 (map[i + 5] << 0xf) | 97 (map[i + 6] << 0x12) | 98 (map[i + 7] << 0x15)); 99 100 qdf_mem_copy(&val[cnt], (void *)&value, 3); 101 cnt += 3; 102 } 103 104 for (i = 0; i < DSCP_TID_TABLE_SIZE; i += 4) { 105 regval = *(uint32_t *)(val + i); 106 HAL_REG_WRITE(soc, addr, 107 (regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK)); 108 addr += 4; 109 } 110 111 /* Diasble read/write access */ 112 regval = HAL_REG_READ(soc, cmn_reg_addr); 113 regval &= 114 ~(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK); 115 116 HAL_REG_WRITE(soc, cmn_reg_addr, regval); 117 } 118 119 /** 120 * hal_tx_update_dscp_tid_8074v2() - Update the dscp tid map table as 121 updated by user 122 * @soc: HAL SoC context 123 * @map: DSCP-TID mapping table 124 * @id : MAP ID 125 * @dscp: DSCP_TID map index 126 * 127 * Return: void 128 */ 129 static void hal_tx_update_dscp_tid_8074v2(void *hal_soc, uint8_t tid, 130 uint8_t id, uint8_t dscp) 131 { 132 uint32_t addr, addr1, cmn_reg_addr; 133 uint32_t start_value = 0, end_value = 0; 134 uint32_t regval; 135 struct hal_soc *soc = (struct hal_soc *)hal_soc; 136 uint8_t end_bits = 0; 137 uint8_t start_bits = 0; 138 uint32_t start_index, end_index; 139 140 cmn_reg_addr = HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR( 141 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET); 142 143 addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR( 144 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET, 145 id * NUM_WORDS_PER_DSCP_TID_TABLE); 146 147 start_index = dscp * HAL_TX_BITS_PER_TID; 148 end_index = (start_index + (HAL_TX_BITS_PER_TID - 1)) 149 % HAL_TX_NUM_DSCP_REGISTER_SIZE; 150 start_index = start_index % HAL_TX_NUM_DSCP_REGISTER_SIZE; 151 addr += (4 * ((dscp * HAL_TX_BITS_PER_TID) / 152 HAL_TX_NUM_DSCP_REGISTER_SIZE)); 153 154 if (end_index < start_index) { 155 end_bits = end_index + 1; 156 start_bits = HAL_TX_BITS_PER_TID - end_bits; 157 start_value = tid << start_index; 158 end_value = tid >> start_bits; 159 addr1 = addr + 4; 160 } else { 161 start_bits = HAL_TX_BITS_PER_TID - end_bits; 162 start_value = tid << start_index; 163 addr1 = 0; 164 } 165 166 /* Enable read/write access */ 167 regval = HAL_REG_READ(soc, cmn_reg_addr); 168 regval |= 169 (1 << HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT); 170 171 HAL_REG_WRITE(soc, cmn_reg_addr, regval); 172 173 regval = HAL_REG_READ(soc, addr); 174 175 if (end_index < start_index) 176 regval &= (~0) >> start_bits; 177 else 178 regval &= ~(7 << start_index); 179 180 regval |= start_value; 181 182 HAL_REG_WRITE(soc, addr, (regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK)); 183 184 if (addr1) { 185 regval = HAL_REG_READ(soc, addr1); 186 regval &= (~0) << end_bits; 187 regval |= end_value; 188 189 HAL_REG_WRITE(soc, addr1, (regval & 190 HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK)); 191 } 192 193 /* Diasble read/write access */ 194 regval = HAL_REG_READ(soc, cmn_reg_addr); 195 regval &= 196 ~(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK); 197 HAL_REG_WRITE(soc, cmn_reg_addr, regval); 198 } 199 200 /** 201 * hal_tx_desc_set_lmac_id - Set the lmac_id value 202 * @desc: Handle to Tx Descriptor 203 * @lmac_id: mac Id to ast matching 204 * b00 – mac 0 205 * b01 – mac 1 206 * b10 – mac 2 207 * b11 – all macs (legacy HK way) 208 * 209 * Return: void 210 */ 211 static void hal_tx_desc_set_lmac_id_8074v2(void *desc, uint8_t lmac_id) 212 { 213 HAL_SET_FLD(desc, TCL_DATA_CMD_4, LMAC_ID) |= 214 HAL_TX_SM(TCL_DATA_CMD_4, LMAC_ID, lmac_id); 215 } 216 217