1 /* 2 * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #include "hal_hw_headers.h" 19 #include "hal_internal.h" 20 #include "cdp_txrx_mon_struct.h" 21 #include "qdf_trace.h" 22 #include "hal_rx.h" 23 #include "hal_tx.h" 24 #include "dp_types.h" 25 #include "hal_api_mon.h" 26 #ifndef QCA_WIFI_QCA6018 27 #include "phyrx_other_receive_info_su_evm_details.h" 28 #endif 29 30 #define HAL_RX_MPDU_GET_SEQUENCE_NUMBER(_rx_mpdu_info) \ 31 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 32 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_OFFSET)), \ 33 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_MASK, \ 34 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_LSB)) 35 36 #define HAL_RX_MSDU_END_DA_IS_MCBC_GET(_rx_msdu_end) \ 37 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 38 RX_MSDU_END_5_DA_IS_MCBC_OFFSET)), \ 39 RX_MSDU_END_5_DA_IS_MCBC_MASK, \ 40 RX_MSDU_END_5_DA_IS_MCBC_LSB)) 41 42 #define HAL_RX_MSDU_END_SA_IS_VALID_GET(_rx_msdu_end) \ 43 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 44 RX_MSDU_END_5_SA_IS_VALID_OFFSET)), \ 45 RX_MSDU_END_5_SA_IS_VALID_MASK, \ 46 RX_MSDU_END_5_SA_IS_VALID_LSB)) 47 48 #define HAL_RX_MSDU_END_SA_IDX_GET(_rx_msdu_end) \ 49 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 50 RX_MSDU_END_13_SA_IDX_OFFSET)), \ 51 RX_MSDU_END_13_SA_IDX_MASK, \ 52 RX_MSDU_END_13_SA_IDX_LSB)) 53 54 #define HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(_rx_msdu_end) \ 55 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 56 RX_MSDU_END_5_L3_HEADER_PADDING_OFFSET)), \ 57 RX_MSDU_END_5_L3_HEADER_PADDING_MASK, \ 58 RX_MSDU_END_5_L3_HEADER_PADDING_LSB)) 59 60 #define HAL_RX_MPDU_ENCRYPTION_INFO_VALID(_rx_mpdu_info) \ 61 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 62 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_OFFSET)), \ 63 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_MASK, \ 64 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_LSB)) 65 66 #define HAL_RX_MPDU_PN_31_0_GET(_rx_mpdu_info) \ 67 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 68 RX_MPDU_INFO_4_PN_31_0_OFFSET)), \ 69 RX_MPDU_INFO_4_PN_31_0_MASK, \ 70 RX_MPDU_INFO_4_PN_31_0_LSB)) 71 72 #define HAL_RX_MPDU_PN_63_32_GET(_rx_mpdu_info) \ 73 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 74 RX_MPDU_INFO_5_PN_63_32_OFFSET)), \ 75 RX_MPDU_INFO_5_PN_63_32_MASK, \ 76 RX_MPDU_INFO_5_PN_63_32_LSB)) 77 78 #define HAL_RX_MPDU_PN_95_64_GET(_rx_mpdu_info) \ 79 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 80 RX_MPDU_INFO_6_PN_95_64_OFFSET)), \ 81 RX_MPDU_INFO_6_PN_95_64_MASK, \ 82 RX_MPDU_INFO_6_PN_95_64_LSB)) 83 84 #define HAL_RX_MPDU_PN_127_96_GET(_rx_mpdu_info) \ 85 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 86 RX_MPDU_INFO_7_PN_127_96_OFFSET)), \ 87 RX_MPDU_INFO_7_PN_127_96_MASK, \ 88 RX_MPDU_INFO_7_PN_127_96_LSB)) 89 90 #define HAL_RX_MSDU_END_FIRST_MSDU_GET(_rx_msdu_end) \ 91 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 92 RX_MSDU_END_5_FIRST_MSDU_OFFSET)), \ 93 RX_MSDU_END_5_FIRST_MSDU_MASK, \ 94 RX_MSDU_END_5_FIRST_MSDU_LSB)) 95 96 #define HAL_RX_MSDU_START_MIMO_SS_BITMAP(_rx_msdu_start)\ 97 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ 98 RX_MSDU_START_5_MIMO_SS_BITMAP_OFFSET)), \ 99 RX_MSDU_START_5_MIMO_SS_BITMAP_MASK, \ 100 RX_MSDU_START_5_MIMO_SS_BITMAP_LSB)) 101 102 #define HAL_RX_MSDU_END_DA_IS_VALID_GET(_rx_msdu_end) \ 103 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 104 RX_MSDU_END_5_DA_IS_VALID_OFFSET)), \ 105 RX_MSDU_END_5_DA_IS_VALID_MASK, \ 106 RX_MSDU_END_5_DA_IS_VALID_LSB)) 107 108 #define HAL_RX_MSDU_END_LAST_MSDU_GET(_rx_msdu_end) \ 109 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 110 RX_MSDU_END_5_LAST_MSDU_OFFSET)), \ 111 RX_MSDU_END_5_LAST_MSDU_MASK, \ 112 RX_MSDU_END_5_LAST_MSDU_LSB)) 113 114 #define HAL_RX_MPDU_GET_MAC_AD4_VALID(_rx_mpdu_info) \ 115 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 116 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_OFFSET)), \ 117 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_MASK, \ 118 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_LSB)) 119 120 #define HAL_RX_MPDU_INFO_SW_PEER_ID_GET(_rx_mpdu_info) \ 121 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 122 RX_MPDU_INFO_1_SW_PEER_ID_OFFSET)), \ 123 RX_MPDU_INFO_1_SW_PEER_ID_MASK, \ 124 RX_MPDU_INFO_1_SW_PEER_ID_LSB)) 125 126 #define HAL_RX_MPDU_GET_TODS(_rx_mpdu_info) \ 127 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 128 RX_MPDU_INFO_2_TO_DS_OFFSET)), \ 129 RX_MPDU_INFO_2_TO_DS_MASK, \ 130 RX_MPDU_INFO_2_TO_DS_LSB)) 131 132 #define HAL_RX_MPDU_GET_FROMDS(_rx_mpdu_info) \ 133 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 134 RX_MPDU_INFO_2_FR_DS_OFFSET)), \ 135 RX_MPDU_INFO_2_FR_DS_MASK, \ 136 RX_MPDU_INFO_2_FR_DS_LSB)) 137 138 #define HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(_rx_mpdu_info) \ 139 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 140 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_OFFSET)), \ 141 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_MASK, \ 142 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_LSB)) 143 144 #define HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(_rx_mpdu_info) \ 145 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 146 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_OFFSET)), \ 147 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_MASK, \ 148 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_LSB)) 149 150 #define HAL_RX_MPDU_AD1_31_0_GET(_rx_mpdu_info) \ 151 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 152 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET)), \ 153 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK, \ 154 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB)) 155 156 #define HAL_RX_MPDU_AD1_47_32_GET(_rx_mpdu_info) \ 157 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 158 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET)), \ 159 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK, \ 160 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB)) 161 162 #define HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(_rx_mpdu_info) \ 163 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 164 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_OFFSET)), \ 165 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_MASK, \ 166 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_LSB)) 167 168 #define HAL_RX_MPDU_AD2_15_0_GET(_rx_mpdu_info) \ 169 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 170 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET)), \ 171 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK, \ 172 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB)) 173 174 #define HAL_RX_MPDU_AD2_47_16_GET(_rx_mpdu_info) \ 175 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 176 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET)), \ 177 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK, \ 178 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB)) 179 180 #define HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(_rx_mpdu_info) \ 181 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 182 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_OFFSET)), \ 183 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_MASK, \ 184 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_LSB)) 185 186 #define HAL_RX_MPDU_AD3_31_0_GET(_rx_mpdu_info) \ 187 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 188 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_OFFSET)), \ 189 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_MASK, \ 190 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_LSB)) 191 192 #define HAL_RX_MPDU_AD3_47_32_GET(_rx_mpdu_info) \ 193 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 194 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_OFFSET)), \ 195 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_MASK, \ 196 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_LSB)) 197 198 #define HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(_rx_mpdu_info) \ 199 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 200 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_OFFSET)), \ 201 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_MASK, \ 202 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_LSB)) 203 204 #define HAL_RX_MPDU_AD4_31_0_GET(_rx_mpdu_info) \ 205 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 206 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET)), \ 207 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK, \ 208 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB)) 209 210 #define HAL_RX_MPDU_AD4_47_32_GET(_rx_mpdu_info) \ 211 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 212 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET)), \ 213 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK, \ 214 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB)) 215 216 #define HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(_rx_mpdu_info) \ 217 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 218 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_OFFSET)), \ 219 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_MASK, \ 220 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_LSB)) 221 222 #define HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(_rx_mpdu_info) \ 223 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 224 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)), \ 225 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK, \ 226 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB)) 227 228 #define HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(_rx_msdu_end) \ 229 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 230 RX_MSDU_END_16_SA_SW_PEER_ID_OFFSET)), \ 231 RX_MSDU_END_16_SA_SW_PEER_ID_MASK, \ 232 RX_MSDU_END_16_SA_SW_PEER_ID_LSB)) 233 234 #define HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va) \ 235 (uint8_t *)(link_desc_va) + \ 236 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 237 238 #define HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0) \ 239 (uint8_t *)(msdu0) + \ 240 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 241 242 #define HAL_ENT_MPDU_DESC_INFO(ent_ring_desc) \ 243 (uint8_t *)(ent_ring_desc) + \ 244 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 245 246 #define HAL_DST_MPDU_DESC_INFO(dst_ring_desc) \ 247 (uint8_t *)(dst_ring_desc) + \ 248 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 249 250 #define HAL_RX_GET_FC_VALID(rx_mpdu_start) \ 251 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, MPDU_FRAME_CONTROL_VALID) 252 253 #define HAL_RX_GET_TO_DS_FLAG(rx_mpdu_start) \ 254 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, TO_DS) 255 256 #define HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start) \ 257 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, MAC_ADDR_AD1_VALID) 258 259 #define HAL_RX_GET_MAC_ADDR2_VALID(rx_mpdu_start) \ 260 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, MAC_ADDR_AD2_VALID) 261 262 #define HAL_RX_GET_FILTER_CATEGORY(rx_mpdu_start) \ 263 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, RXPCU_MPDU_FILTER_IN_CATEGORY) 264 265 #define HAL_RX_GET_PPDU_ID(rx_mpdu_start) \ 266 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, PHY_PPDU_ID) 267 268 #define HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start) \ 269 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, SW_FRAME_GROUP_ID) 270 271 #define HAL_REO_R0_CONFIG(soc, reg_val, reo_params) \ 272 do { \ 273 reg_val &= \ 274 ~(HWIO_REO_R0_GENERAL_ENABLE_FRAGMENT_DEST_RING_BMSK |\ 275 HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK | \ 276 HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK); \ 277 reg_val |= \ 278 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 279 FRAGMENT_DEST_RING, \ 280 (reo_params)->frag_dst_ring) | \ 281 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 282 AGING_LIST_ENABLE, 1) |\ 283 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 284 AGING_FLUSH_ENABLE, 1);\ 285 HAL_REG_WRITE((soc), \ 286 HWIO_REO_R0_GENERAL_ENABLE_ADDR( \ 287 SEQ_WCSS_UMAC_REO_REG_OFFSET), \ 288 (reg_val)); \ 289 } while (0) 290 291 #define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \ 292 ((struct rx_msdu_desc_info *) \ 293 _OFFSET_TO_BYTE_PTR((msdu_details_ptr), \ 294 UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET)) 295 296 #define HAL_RX_LINK_DESC_MSDU0_PTR(link_desc) \ 297 ((struct rx_msdu_details *) \ 298 _OFFSET_TO_BYTE_PTR((link_desc),\ 299 UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET)) 300 301 #define HAL_RX_MSDU_END_FLOW_IDX_GET(_rx_msdu_end) \ 302 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 303 RX_MSDU_END_14_FLOW_IDX_OFFSET)), \ 304 RX_MSDU_END_14_FLOW_IDX_MASK, \ 305 RX_MSDU_END_14_FLOW_IDX_LSB)) 306 307 #define HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(_rx_msdu_end) \ 308 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 309 RX_MSDU_END_5_FLOW_IDX_INVALID_OFFSET)), \ 310 RX_MSDU_END_5_FLOW_IDX_INVALID_MASK, \ 311 RX_MSDU_END_5_FLOW_IDX_INVALID_LSB)) 312 313 #define HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(_rx_msdu_end) \ 314 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 315 RX_MSDU_END_5_FLOW_IDX_TIMEOUT_OFFSET)), \ 316 RX_MSDU_END_5_FLOW_IDX_TIMEOUT_MASK, \ 317 RX_MSDU_END_5_FLOW_IDX_TIMEOUT_LSB)) 318 319 #define HAL_RX_MSDU_END_FSE_METADATA_GET(_rx_msdu_end) \ 320 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 321 RX_MSDU_END_15_FSE_METADATA_OFFSET)), \ 322 RX_MSDU_END_15_FSE_METADATA_MASK, \ 323 RX_MSDU_END_15_FSE_METADATA_LSB)) 324 325 #define HAL_RX_MSDU_END_CCE_METADATA_GET(_rx_msdu_end) \ 326 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 327 RX_MSDU_END_16_CCE_METADATA_OFFSET)), \ 328 RX_MSDU_END_16_CCE_METADATA_MASK, \ 329 RX_MSDU_END_16_CCE_METADATA_LSB)) 330 331 #define HAL_RX_TLV_GET_TCP_CHKSUM(buf) \ 332 (_HAL_MS( \ 333 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 334 msdu_end_tlv.rx_msdu_end), \ 335 RX_MSDU_END_1_TCP_UDP_CHKSUM_OFFSET)), \ 336 RX_MSDU_END_1_TCP_UDP_CHKSUM_MASK, \ 337 RX_MSDU_END_1_TCP_UDP_CHKSUM_LSB)) 338 339 /* 340 * hal_rx_msdu_start_nss_get_8074v2(): API to get the NSS 341 * Interval from rx_msdu_start 342 * 343 * @buf: pointer to the start of RX PKT TLV header 344 * Return: uint32_t(nss) 345 */ 346 static uint32_t hal_rx_msdu_start_nss_get_8074v2(uint8_t *buf) 347 { 348 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 349 struct rx_msdu_start *msdu_start = 350 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 351 uint8_t mimo_ss_bitmap; 352 353 mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start); 354 355 return qdf_get_hweight8(mimo_ss_bitmap); 356 } 357 358 /** 359 * hal_rx_mon_hw_desc_get_mpdu_status_8074v2(): Retrieve MPDU status 360 * 361 * @ hw_desc_addr: Start address of Rx HW TLVs 362 * @ rs: Status for monitor mode 363 * 364 * Return: void 365 */ 366 static void hal_rx_mon_hw_desc_get_mpdu_status_8074v2(void *hw_desc_addr, 367 struct mon_rx_status *rs) 368 { 369 struct rx_msdu_start *rx_msdu_start; 370 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 371 uint32_t reg_value; 372 const uint32_t sgi_hw_to_cdp[] = { 373 CDP_SGI_0_8_US, 374 CDP_SGI_0_4_US, 375 CDP_SGI_1_6_US, 376 CDP_SGI_3_2_US, 377 }; 378 379 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 380 381 HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs); 382 383 rs->ant_signal_db = HAL_RX_GET(rx_msdu_start, 384 RX_MSDU_START_5, USER_RSSI); 385 rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC); 386 387 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI); 388 rs->sgi = sgi_hw_to_cdp[reg_value]; 389 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE); 390 rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0; 391 /* TODO: rs->beamformed should be set for SU beamforming also */ 392 } 393 394 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 395 static uint32_t hal_get_link_desc_size_8074v2(void) 396 { 397 return LINK_DESC_SIZE; 398 } 399 400 /* 401 * hal_rx_get_tlv_8074v2(): API to get the tlv 402 * 403 * @rx_tlv: TLV data extracted from the rx packet 404 * Return: uint8_t 405 */ 406 static uint8_t hal_rx_get_tlv_8074v2(void *rx_tlv) 407 { 408 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH); 409 } 410 411 #ifndef QCA_WIFI_QCA6018 412 #define HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, evm, pilot) \ 413 (ppdu_info)->evm_info.pilot_evm[pilot] = HAL_RX_GET(rx_tlv, \ 414 PHYRX_OTHER_RECEIVE_INFO, \ 415 SU_EVM_DETAILS_##evm##_PILOT_##pilot##_EVM) 416 417 static inline void 418 hal_rx_update_su_evm_info(void *rx_tlv, 419 void *ppdu_info_hdl) 420 { 421 struct hal_rx_ppdu_info *ppdu_info = 422 (struct hal_rx_ppdu_info *)ppdu_info_hdl; 423 424 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 1, 0); 425 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 2, 1); 426 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 3, 2); 427 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 4, 3); 428 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 5, 4); 429 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 6, 5); 430 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 7, 6); 431 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 8, 7); 432 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 9, 8); 433 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 10, 9); 434 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 11, 10); 435 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 12, 11); 436 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 13, 12); 437 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 14, 13); 438 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 15, 14); 439 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 16, 15); 440 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 17, 16); 441 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 18, 17); 442 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 19, 18); 443 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 20, 19); 444 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 21, 20); 445 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 22, 21); 446 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 23, 22); 447 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 24, 23); 448 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 25, 24); 449 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 26, 25); 450 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 27, 26); 451 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 28, 27); 452 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 29, 28); 453 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 30, 29); 454 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 31, 30); 455 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 32, 31); 456 } 457 /** 458 * hal_rx_proc_phyrx_other_receive_info_tlv_8074v2() 459 * -process other receive info TLV 460 * @rx_tlv_hdr: pointer to TLV header 461 * @ppdu_info: pointer to ppdu_info 462 * 463 * Return: None 464 */ 465 static 466 void hal_rx_proc_phyrx_other_receive_info_tlv_8074v2(void *rx_tlv_hdr, 467 void *ppdu_info_hdl) 468 { 469 uint16_t tlv_tag; 470 void *rx_tlv; 471 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 472 473 /* Skip TLV_HDR for OTHER_RECEIVE_INFO and follows the 474 * embedded TLVs inside 475 */ 476 rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 477 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv); 478 479 switch (tlv_tag) { 480 case WIFIPHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_E: 481 482 /* Skip TLV length to get TLV content */ 483 rx_tlv = (uint8_t *)rx_tlv + HAL_RX_TLV32_HDR_SIZE; 484 485 ppdu_info->evm_info.number_of_symbols = HAL_RX_GET(rx_tlv, 486 PHYRX_OTHER_RECEIVE_INFO, 487 SU_EVM_DETAILS_0_NUMBER_OF_SYMBOLS); 488 ppdu_info->evm_info.pilot_count = HAL_RX_GET(rx_tlv, 489 PHYRX_OTHER_RECEIVE_INFO, 490 SU_EVM_DETAILS_0_PILOT_COUNT); 491 ppdu_info->evm_info.nss_count = HAL_RX_GET(rx_tlv, 492 PHYRX_OTHER_RECEIVE_INFO, 493 SU_EVM_DETAILS_0_NSS_COUNT); 494 hal_rx_update_su_evm_info(rx_tlv, ppdu_info_hdl); 495 break; 496 } 497 } 498 #else 499 static inline 500 void hal_rx_proc_phyrx_other_receive_info_tlv_8074v2(void *rx_tlv_hdr, 501 void *ppdu_info_hdl) 502 { 503 } 504 #endif 505 506 #if defined(QCA_WIFI_QCA6018) && defined(WLAN_CFR_ENABLE) && \ 507 defined(WLAN_ENH_CFR_ENABLE) 508 static inline 509 void hal_rx_get_bb_info_8074v2(void *rx_tlv, 510 void *ppdu_info_hdl) 511 { 512 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 513 514 ppdu_info->cfr_info.bb_captured_channel = 515 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_CHANNEL); 516 517 ppdu_info->cfr_info.bb_captured_timeout = 518 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_TIMEOUT); 519 520 ppdu_info->cfr_info.bb_captured_reason = 521 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_REASON); 522 } 523 524 static inline 525 void hal_rx_get_rtt_info_8074v2(void *rx_tlv, 526 void *ppdu_info_hdl) 527 { 528 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 529 530 ppdu_info->cfr_info.rx_location_info_valid = 531 HAL_RX_GET(rx_tlv, PHYRX_PKT_END_13_RX_PKT_END_DETAILS, 532 RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID); 533 534 ppdu_info->cfr_info.rtt_che_buffer_pointer_low32 = 535 HAL_RX_GET(rx_tlv, 536 PHYRX_PKT_END_12_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 537 RTT_CHE_BUFFER_POINTER_LOW32); 538 539 ppdu_info->cfr_info.rtt_che_buffer_pointer_high8 = 540 HAL_RX_GET(rx_tlv, 541 PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 542 RTT_CHE_BUFFER_POINTER_HIGH8); 543 544 ppdu_info->cfr_info.chan_capture_status = 545 HAL_RX_GET(rx_tlv, 546 PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 547 RESERVED_8); 548 } 549 #endif 550 551 /** 552 * hal_rx_dump_msdu_start_tlv_8074v2() : dump RX msdu_start TLV in structured 553 * human readable format. 554 * @ msdu_start: pointer the msdu_start TLV in pkt. 555 * @ dbg_level: log level. 556 * 557 * Return: void 558 */ 559 static void hal_rx_dump_msdu_start_tlv_8074v2(void *msdustart, 560 uint8_t dbg_level) 561 { 562 struct rx_msdu_start *msdu_start = (struct rx_msdu_start *)msdustart; 563 564 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 565 "rx_msdu_start tlv - " 566 "rxpcu_mpdu_filter_in_category: %d " 567 "sw_frame_group_id: %d " 568 "phy_ppdu_id: %d " 569 "msdu_length: %d " 570 "ipsec_esp: %d " 571 "l3_offset: %d " 572 "ipsec_ah: %d " 573 "l4_offset: %d " 574 "msdu_number: %d " 575 "decap_format: %d " 576 "ipv4_proto: %d " 577 "ipv6_proto: %d " 578 "tcp_proto: %d " 579 "udp_proto: %d " 580 "ip_frag: %d " 581 "tcp_only_ack: %d " 582 "da_is_bcast_mcast: %d " 583 "ip4_protocol_ip6_next_header: %d " 584 "toeplitz_hash_2_or_4: %d " 585 "flow_id_toeplitz: %d " 586 "user_rssi: %d " 587 "pkt_type: %d " 588 "stbc: %d " 589 "sgi: %d " 590 "rate_mcs: %d " 591 "receive_bandwidth: %d " 592 "reception_type: %d " 593 "ppdu_start_timestamp: %d " 594 "sw_phy_meta_data: %d ", 595 msdu_start->rxpcu_mpdu_filter_in_category, 596 msdu_start->sw_frame_group_id, 597 msdu_start->phy_ppdu_id, 598 msdu_start->msdu_length, 599 msdu_start->ipsec_esp, 600 msdu_start->l3_offset, 601 msdu_start->ipsec_ah, 602 msdu_start->l4_offset, 603 msdu_start->msdu_number, 604 msdu_start->decap_format, 605 msdu_start->ipv4_proto, 606 msdu_start->ipv6_proto, 607 msdu_start->tcp_proto, 608 msdu_start->udp_proto, 609 msdu_start->ip_frag, 610 msdu_start->tcp_only_ack, 611 msdu_start->da_is_bcast_mcast, 612 msdu_start->ip4_protocol_ip6_next_header, 613 msdu_start->toeplitz_hash_2_or_4, 614 msdu_start->flow_id_toeplitz, 615 msdu_start->user_rssi, 616 msdu_start->pkt_type, 617 msdu_start->stbc, 618 msdu_start->sgi, 619 msdu_start->rate_mcs, 620 msdu_start->receive_bandwidth, 621 msdu_start->reception_type, 622 msdu_start->ppdu_start_timestamp, 623 msdu_start->sw_phy_meta_data); 624 } 625 626 /** 627 * hal_rx_dump_msdu_end_tlv_8074v2: dump RX msdu_end TLV in structured 628 * human readable format. 629 * @ msdu_end: pointer the msdu_end TLV in pkt. 630 * @ dbg_level: log level. 631 * 632 * Return: void 633 */ 634 static void hal_rx_dump_msdu_end_tlv_8074v2(void *msduend, 635 uint8_t dbg_level) 636 { 637 struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend; 638 639 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 640 "rx_msdu_end tlv - " 641 "rxpcu_mpdu_filter_in_category: %d " 642 "sw_frame_group_id: %d " 643 "phy_ppdu_id: %d " 644 "ip_hdr_chksum: %d " 645 "tcp_udp_chksum: %d " 646 "key_id_octet: %d " 647 "cce_super_rule: %d " 648 "cce_classify_not_done_truncat: %d " 649 "cce_classify_not_done_cce_dis: %d " 650 "ext_wapi_pn_63_48: %d " 651 "ext_wapi_pn_95_64: %d " 652 "ext_wapi_pn_127_96: %d " 653 "reported_mpdu_length: %d " 654 "first_msdu: %d " 655 "last_msdu: %d " 656 "sa_idx_timeout: %d " 657 "da_idx_timeout: %d " 658 "msdu_limit_error: %d " 659 "flow_idx_timeout: %d " 660 "flow_idx_invalid: %d " 661 "wifi_parser_error: %d " 662 "amsdu_parser_error: %d " 663 "sa_is_valid: %d " 664 "da_is_valid: %d " 665 "da_is_mcbc: %d " 666 "l3_header_padding: %d " 667 "ipv6_options_crc: %d " 668 "tcp_seq_number: %d " 669 "tcp_ack_number: %d " 670 "tcp_flag: %d " 671 "lro_eligible: %d " 672 "window_size: %d " 673 "da_offset: %d " 674 "sa_offset: %d " 675 "da_offset_valid: %d " 676 "sa_offset_valid: %d " 677 "rule_indication_31_0: %d " 678 "rule_indication_63_32: %d " 679 "sa_idx: %d " 680 "msdu_drop: %d " 681 "reo_destination_indication: %d " 682 "flow_idx: %d " 683 "fse_metadata: %d " 684 "cce_metadata: %d " 685 "sa_sw_peer_id: %d ", 686 msdu_end->rxpcu_mpdu_filter_in_category, 687 msdu_end->sw_frame_group_id, 688 msdu_end->phy_ppdu_id, 689 msdu_end->ip_hdr_chksum, 690 msdu_end->tcp_udp_chksum, 691 msdu_end->key_id_octet, 692 msdu_end->cce_super_rule, 693 msdu_end->cce_classify_not_done_truncate, 694 msdu_end->cce_classify_not_done_cce_dis, 695 msdu_end->ext_wapi_pn_63_48, 696 msdu_end->ext_wapi_pn_95_64, 697 msdu_end->ext_wapi_pn_127_96, 698 msdu_end->reported_mpdu_length, 699 msdu_end->first_msdu, 700 msdu_end->last_msdu, 701 msdu_end->sa_idx_timeout, 702 msdu_end->da_idx_timeout, 703 msdu_end->msdu_limit_error, 704 msdu_end->flow_idx_timeout, 705 msdu_end->flow_idx_invalid, 706 msdu_end->wifi_parser_error, 707 msdu_end->amsdu_parser_error, 708 msdu_end->sa_is_valid, 709 msdu_end->da_is_valid, 710 msdu_end->da_is_mcbc, 711 msdu_end->l3_header_padding, 712 msdu_end->ipv6_options_crc, 713 msdu_end->tcp_seq_number, 714 msdu_end->tcp_ack_number, 715 msdu_end->tcp_flag, 716 msdu_end->lro_eligible, 717 msdu_end->window_size, 718 msdu_end->da_offset, 719 msdu_end->sa_offset, 720 msdu_end->da_offset_valid, 721 msdu_end->sa_offset_valid, 722 msdu_end->rule_indication_31_0, 723 msdu_end->rule_indication_63_32, 724 msdu_end->sa_idx, 725 msdu_end->msdu_drop, 726 msdu_end->reo_destination_indication, 727 msdu_end->flow_idx, 728 msdu_end->fse_metadata, 729 msdu_end->cce_metadata, 730 msdu_end->sa_sw_peer_id); 731 } 732 733 734 /* 735 * Get tid from RX_MPDU_START 736 */ 737 #define HAL_RX_MPDU_INFO_TID_GET(_rx_mpdu_info) \ 738 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 739 RX_MPDU_INFO_3_TID_OFFSET)), \ 740 RX_MPDU_INFO_3_TID_MASK, \ 741 RX_MPDU_INFO_3_TID_LSB)) 742 743 static uint32_t hal_rx_mpdu_start_tid_get_8074v2(uint8_t *buf) 744 { 745 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 746 struct rx_mpdu_start *mpdu_start = 747 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 748 uint32_t tid; 749 750 tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details); 751 752 return tid; 753 } 754 755 #define HAL_RX_MSDU_START_RECEPTION_TYPE_GET(_rx_msdu_start) \ 756 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \ 757 RX_MSDU_START_5_RECEPTION_TYPE_OFFSET)), \ 758 RX_MSDU_START_5_RECEPTION_TYPE_MASK, \ 759 RX_MSDU_START_5_RECEPTION_TYPE_LSB)) 760 761 /* 762 * hal_rx_msdu_start_reception_type_get(): API to get the reception type 763 * Interval from rx_msdu_start 764 * 765 * @buf: pointer to the start of RX PKT TLV header 766 * Return: uint32_t(reception_type) 767 */ 768 static uint32_t hal_rx_msdu_start_reception_type_get_8074v2(uint8_t *buf) 769 { 770 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 771 struct rx_msdu_start *msdu_start = 772 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 773 uint32_t reception_type; 774 775 reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start); 776 777 return reception_type; 778 } 779 780 /* RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_OFFSET */ 781 #define HAL_RX_MSDU_END_DA_IDX_GET(_rx_msdu_end) \ 782 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 783 RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_OFFSET)), \ 784 RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_MASK, \ 785 RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_LSB)) 786 /** 787 * hal_rx_msdu_end_da_idx_get_8074v2: API to get da_idx 788 * from rx_msdu_end TLV 789 * 790 * @ buf: pointer to the start of RX PKT TLV headers 791 * Return: da index 792 */ 793 static uint16_t hal_rx_msdu_end_da_idx_get_8074v2(uint8_t *buf) 794 { 795 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 796 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 797 uint16_t da_idx; 798 799 da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 800 801 return da_idx; 802 } 803