1 /* 2 * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #include "hal_hw_headers.h" 19 #include "hal_internal.h" 20 #include "cdp_txrx_mon_struct.h" 21 #include "qdf_trace.h" 22 #include "hal_rx.h" 23 #include "hal_tx.h" 24 #include "dp_types.h" 25 #include "hal_api_mon.h" 26 #ifndef QCA_WIFI_QCA6018 27 #include "phyrx_other_receive_info_su_evm_details.h" 28 #endif 29 30 #define HAL_RX_MPDU_GET_SEQUENCE_NUMBER(_rx_mpdu_info) \ 31 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 32 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_OFFSET)), \ 33 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_MASK, \ 34 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_LSB)) 35 36 #define HAL_RX_MSDU_END_DA_IS_MCBC_GET(_rx_msdu_end) \ 37 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 38 RX_MSDU_END_5_DA_IS_MCBC_OFFSET)), \ 39 RX_MSDU_END_5_DA_IS_MCBC_MASK, \ 40 RX_MSDU_END_5_DA_IS_MCBC_LSB)) 41 42 #define HAL_RX_MSDU_END_SA_IS_VALID_GET(_rx_msdu_end) \ 43 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 44 RX_MSDU_END_5_SA_IS_VALID_OFFSET)), \ 45 RX_MSDU_END_5_SA_IS_VALID_MASK, \ 46 RX_MSDU_END_5_SA_IS_VALID_LSB)) 47 48 #define HAL_RX_MSDU_END_SA_IDX_GET(_rx_msdu_end) \ 49 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 50 RX_MSDU_END_13_SA_IDX_OFFSET)), \ 51 RX_MSDU_END_13_SA_IDX_MASK, \ 52 RX_MSDU_END_13_SA_IDX_LSB)) 53 54 #define HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(_rx_msdu_end) \ 55 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 56 RX_MSDU_END_5_L3_HEADER_PADDING_OFFSET)), \ 57 RX_MSDU_END_5_L3_HEADER_PADDING_MASK, \ 58 RX_MSDU_END_5_L3_HEADER_PADDING_LSB)) 59 60 #define HAL_RX_MPDU_ENCRYPTION_INFO_VALID(_rx_mpdu_info) \ 61 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 62 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_OFFSET)), \ 63 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_MASK, \ 64 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_LSB)) 65 66 #define HAL_RX_MPDU_PN_31_0_GET(_rx_mpdu_info) \ 67 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 68 RX_MPDU_INFO_4_PN_31_0_OFFSET)), \ 69 RX_MPDU_INFO_4_PN_31_0_MASK, \ 70 RX_MPDU_INFO_4_PN_31_0_LSB)) 71 72 #define HAL_RX_MPDU_PN_63_32_GET(_rx_mpdu_info) \ 73 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 74 RX_MPDU_INFO_5_PN_63_32_OFFSET)), \ 75 RX_MPDU_INFO_5_PN_63_32_MASK, \ 76 RX_MPDU_INFO_5_PN_63_32_LSB)) 77 78 #define HAL_RX_MPDU_PN_95_64_GET(_rx_mpdu_info) \ 79 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 80 RX_MPDU_INFO_6_PN_95_64_OFFSET)), \ 81 RX_MPDU_INFO_6_PN_95_64_MASK, \ 82 RX_MPDU_INFO_6_PN_95_64_LSB)) 83 84 #define HAL_RX_MPDU_PN_127_96_GET(_rx_mpdu_info) \ 85 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 86 RX_MPDU_INFO_7_PN_127_96_OFFSET)), \ 87 RX_MPDU_INFO_7_PN_127_96_MASK, \ 88 RX_MPDU_INFO_7_PN_127_96_LSB)) 89 90 #define HAL_RX_MSDU_END_FIRST_MSDU_GET(_rx_msdu_end) \ 91 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 92 RX_MSDU_END_5_FIRST_MSDU_OFFSET)), \ 93 RX_MSDU_END_5_FIRST_MSDU_MASK, \ 94 RX_MSDU_END_5_FIRST_MSDU_LSB)) 95 96 #define HAL_RX_MSDU_START_MIMO_SS_BITMAP(_rx_msdu_start)\ 97 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ 98 RX_MSDU_START_5_MIMO_SS_BITMAP_OFFSET)), \ 99 RX_MSDU_START_5_MIMO_SS_BITMAP_MASK, \ 100 RX_MSDU_START_5_MIMO_SS_BITMAP_LSB)) 101 102 #define HAL_RX_MSDU_END_DA_IS_VALID_GET(_rx_msdu_end) \ 103 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 104 RX_MSDU_END_5_DA_IS_VALID_OFFSET)), \ 105 RX_MSDU_END_5_DA_IS_VALID_MASK, \ 106 RX_MSDU_END_5_DA_IS_VALID_LSB)) 107 108 #define HAL_RX_MSDU_END_LAST_MSDU_GET(_rx_msdu_end) \ 109 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 110 RX_MSDU_END_5_LAST_MSDU_OFFSET)), \ 111 RX_MSDU_END_5_LAST_MSDU_MASK, \ 112 RX_MSDU_END_5_LAST_MSDU_LSB)) 113 114 #define HAL_RX_MPDU_GET_MAC_AD4_VALID(_rx_mpdu_info) \ 115 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 116 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_OFFSET)), \ 117 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_MASK, \ 118 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_LSB)) 119 120 #define HAL_RX_MPDU_INFO_SW_PEER_ID_GET(_rx_mpdu_info) \ 121 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 122 RX_MPDU_INFO_1_SW_PEER_ID_OFFSET)), \ 123 RX_MPDU_INFO_1_SW_PEER_ID_MASK, \ 124 RX_MPDU_INFO_1_SW_PEER_ID_LSB)) 125 126 #define HAL_RX_MPDU_GET_TODS(_rx_mpdu_info) \ 127 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 128 RX_MPDU_INFO_2_TO_DS_OFFSET)), \ 129 RX_MPDU_INFO_2_TO_DS_MASK, \ 130 RX_MPDU_INFO_2_TO_DS_LSB)) 131 132 #define HAL_RX_MPDU_GET_FROMDS(_rx_mpdu_info) \ 133 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 134 RX_MPDU_INFO_2_FR_DS_OFFSET)), \ 135 RX_MPDU_INFO_2_FR_DS_MASK, \ 136 RX_MPDU_INFO_2_FR_DS_LSB)) 137 138 #define HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(_rx_mpdu_info) \ 139 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 140 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_OFFSET)), \ 141 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_MASK, \ 142 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_LSB)) 143 144 #define HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(_rx_mpdu_info) \ 145 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 146 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_OFFSET)), \ 147 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_MASK, \ 148 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_LSB)) 149 150 #define HAL_RX_MPDU_AD1_31_0_GET(_rx_mpdu_info) \ 151 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 152 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET)), \ 153 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK, \ 154 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB)) 155 156 #define HAL_RX_MPDU_AD1_47_32_GET(_rx_mpdu_info) \ 157 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 158 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET)), \ 159 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK, \ 160 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB)) 161 162 #define HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(_rx_mpdu_info) \ 163 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 164 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_OFFSET)), \ 165 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_MASK, \ 166 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_LSB)) 167 168 #define HAL_RX_MPDU_AD2_15_0_GET(_rx_mpdu_info) \ 169 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 170 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET)), \ 171 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK, \ 172 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB)) 173 174 #define HAL_RX_MPDU_AD2_47_16_GET(_rx_mpdu_info) \ 175 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 176 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET)), \ 177 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK, \ 178 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB)) 179 180 #define HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(_rx_mpdu_info) \ 181 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 182 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_OFFSET)), \ 183 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_MASK, \ 184 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_LSB)) 185 186 #define HAL_RX_MPDU_AD3_31_0_GET(_rx_mpdu_info) \ 187 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 188 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_OFFSET)), \ 189 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_MASK, \ 190 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_LSB)) 191 192 #define HAL_RX_MPDU_AD3_47_32_GET(_rx_mpdu_info) \ 193 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 194 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_OFFSET)), \ 195 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_MASK, \ 196 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_LSB)) 197 198 #define HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(_rx_mpdu_info) \ 199 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 200 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_OFFSET)), \ 201 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_MASK, \ 202 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_LSB)) 203 204 #define HAL_RX_MPDU_AD4_31_0_GET(_rx_mpdu_info) \ 205 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 206 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET)), \ 207 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK, \ 208 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB)) 209 210 #define HAL_RX_MPDU_AD4_47_32_GET(_rx_mpdu_info) \ 211 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 212 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET)), \ 213 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK, \ 214 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB)) 215 216 #define HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(_rx_mpdu_info) \ 217 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 218 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_OFFSET)), \ 219 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_MASK, \ 220 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_LSB)) 221 222 #define HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(_rx_mpdu_info) \ 223 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 224 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)), \ 225 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK, \ 226 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB)) 227 228 #define HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(_rx_msdu_end) \ 229 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 230 RX_MSDU_END_16_SA_SW_PEER_ID_OFFSET)), \ 231 RX_MSDU_END_16_SA_SW_PEER_ID_MASK, \ 232 RX_MSDU_END_16_SA_SW_PEER_ID_LSB)) 233 234 #define HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va) \ 235 (uint8_t *)(link_desc_va) + \ 236 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 237 238 #define HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0) \ 239 (uint8_t *)(msdu0) + \ 240 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 241 242 #define HAL_ENT_MPDU_DESC_INFO(ent_ring_desc) \ 243 (uint8_t *)(ent_ring_desc) + \ 244 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 245 246 #define HAL_DST_MPDU_DESC_INFO(dst_ring_desc) \ 247 (uint8_t *)(dst_ring_desc) + \ 248 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 249 250 #define HAL_RX_GET_FC_VALID(rx_mpdu_start) \ 251 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, MPDU_FRAME_CONTROL_VALID) 252 253 #define HAL_RX_GET_TO_DS_FLAG(rx_mpdu_start) \ 254 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, TO_DS) 255 256 #define HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start) \ 257 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, MAC_ADDR_AD1_VALID) 258 259 #define HAL_RX_GET_MAC_ADDR2_VALID(rx_mpdu_start) \ 260 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, MAC_ADDR_AD2_VALID) 261 262 #define HAL_RX_GET_FILTER_CATEGORY(rx_mpdu_start) \ 263 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, RXPCU_MPDU_FILTER_IN_CATEGORY) 264 265 #define HAL_RX_GET_PPDU_ID(rx_mpdu_start) \ 266 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, PHY_PPDU_ID) 267 268 #define HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start) \ 269 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, SW_FRAME_GROUP_ID) 270 271 #define HAL_REO_R0_CONFIG(soc, reg_val, reo_params) \ 272 do { \ 273 reg_val &= \ 274 ~(HWIO_REO_R0_GENERAL_ENABLE_FRAGMENT_DEST_RING_BMSK |\ 275 HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK | \ 276 HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK); \ 277 reg_val |= \ 278 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 279 FRAGMENT_DEST_RING, \ 280 (reo_params)->frag_dst_ring) | \ 281 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 282 AGING_LIST_ENABLE, 1) |\ 283 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 284 AGING_FLUSH_ENABLE, 1);\ 285 HAL_REG_WRITE((soc), \ 286 HWIO_REO_R0_GENERAL_ENABLE_ADDR( \ 287 SEQ_WCSS_UMAC_REO_REG_OFFSET), \ 288 (reg_val)); \ 289 (reg_val) = \ 290 HAL_REG_READ((soc), \ 291 HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR( \ 292 SEQ_WCSS_UMAC_REO_REG_OFFSET)); \ 293 (reg_val) &= \ 294 ~(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_0_BMSK); \ 295 (reg_val) |= \ 296 HAL_SM(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0, \ 297 DEST_RING_ALT_MAPPING_0, \ 298 (reo_params)->alt_dst_ind_0); \ 299 HAL_REG_WRITE((soc), \ 300 HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR( \ 301 SEQ_WCSS_UMAC_REO_REG_OFFSET), \ 302 (reg_val)); \ 303 } while (0) 304 305 #define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \ 306 ((struct rx_msdu_desc_info *) \ 307 _OFFSET_TO_BYTE_PTR((msdu_details_ptr), \ 308 UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET)) 309 310 #define HAL_RX_LINK_DESC_MSDU0_PTR(link_desc) \ 311 ((struct rx_msdu_details *) \ 312 _OFFSET_TO_BYTE_PTR((link_desc),\ 313 UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET)) 314 315 #define HAL_RX_MSDU_END_FLOW_IDX_GET(_rx_msdu_end) \ 316 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 317 RX_MSDU_END_14_FLOW_IDX_OFFSET)), \ 318 RX_MSDU_END_14_FLOW_IDX_MASK, \ 319 RX_MSDU_END_14_FLOW_IDX_LSB)) 320 321 #define HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(_rx_msdu_end) \ 322 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 323 RX_MSDU_END_5_FLOW_IDX_INVALID_OFFSET)), \ 324 RX_MSDU_END_5_FLOW_IDX_INVALID_MASK, \ 325 RX_MSDU_END_5_FLOW_IDX_INVALID_LSB)) 326 327 #define HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(_rx_msdu_end) \ 328 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 329 RX_MSDU_END_5_FLOW_IDX_TIMEOUT_OFFSET)), \ 330 RX_MSDU_END_5_FLOW_IDX_TIMEOUT_MASK, \ 331 RX_MSDU_END_5_FLOW_IDX_TIMEOUT_LSB)) 332 333 #define HAL_RX_MSDU_END_FSE_METADATA_GET(_rx_msdu_end) \ 334 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 335 RX_MSDU_END_15_FSE_METADATA_OFFSET)), \ 336 RX_MSDU_END_15_FSE_METADATA_MASK, \ 337 RX_MSDU_END_15_FSE_METADATA_LSB)) 338 339 #define HAL_RX_MSDU_END_CCE_METADATA_GET(_rx_msdu_end) \ 340 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 341 RX_MSDU_END_16_CCE_METADATA_OFFSET)), \ 342 RX_MSDU_END_16_CCE_METADATA_MASK, \ 343 RX_MSDU_END_16_CCE_METADATA_LSB)) 344 345 #define HAL_RX_TLV_GET_TCP_CHKSUM(buf) \ 346 (_HAL_MS( \ 347 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 348 msdu_end_tlv.rx_msdu_end), \ 349 RX_MSDU_END_1_TCP_UDP_CHKSUM_OFFSET)), \ 350 RX_MSDU_END_1_TCP_UDP_CHKSUM_MASK, \ 351 RX_MSDU_END_1_TCP_UDP_CHKSUM_LSB)) 352 353 /* 354 * hal_rx_msdu_start_nss_get_8074v2(): API to get the NSS 355 * Interval from rx_msdu_start 356 * 357 * @buf: pointer to the start of RX PKT TLV header 358 * Return: uint32_t(nss) 359 */ 360 static uint32_t hal_rx_msdu_start_nss_get_8074v2(uint8_t *buf) 361 { 362 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 363 struct rx_msdu_start *msdu_start = 364 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 365 uint8_t mimo_ss_bitmap; 366 367 mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start); 368 369 return qdf_get_hweight8(mimo_ss_bitmap); 370 } 371 372 /** 373 * hal_rx_mon_hw_desc_get_mpdu_status_8074v2(): Retrieve MPDU status 374 * 375 * @ hw_desc_addr: Start address of Rx HW TLVs 376 * @ rs: Status for monitor mode 377 * 378 * Return: void 379 */ 380 static void hal_rx_mon_hw_desc_get_mpdu_status_8074v2(void *hw_desc_addr, 381 struct mon_rx_status *rs) 382 { 383 struct rx_msdu_start *rx_msdu_start; 384 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 385 uint32_t reg_value; 386 const uint32_t sgi_hw_to_cdp[] = { 387 CDP_SGI_0_8_US, 388 CDP_SGI_0_4_US, 389 CDP_SGI_1_6_US, 390 CDP_SGI_3_2_US, 391 }; 392 393 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 394 395 HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs); 396 397 rs->ant_signal_db = HAL_RX_GET(rx_msdu_start, 398 RX_MSDU_START_5, USER_RSSI); 399 rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC); 400 401 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI); 402 rs->sgi = sgi_hw_to_cdp[reg_value]; 403 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE); 404 rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0; 405 /* TODO: rs->beamformed should be set for SU beamforming also */ 406 } 407 408 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 409 static uint32_t hal_get_link_desc_size_8074v2(void) 410 { 411 return LINK_DESC_SIZE; 412 } 413 414 /* 415 * hal_rx_get_tlv_8074v2(): API to get the tlv 416 * 417 * @rx_tlv: TLV data extracted from the rx packet 418 * Return: uint8_t 419 */ 420 static uint8_t hal_rx_get_tlv_8074v2(void *rx_tlv) 421 { 422 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH); 423 } 424 425 #ifndef QCA_WIFI_QCA6018 426 #define HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, evm, pilot) \ 427 (ppdu_info)->evm_info.pilot_evm[pilot] = HAL_RX_GET(rx_tlv, \ 428 PHYRX_OTHER_RECEIVE_INFO, \ 429 SU_EVM_DETAILS_##evm##_PILOT_##pilot##_EVM) 430 431 static inline void 432 hal_rx_update_su_evm_info(void *rx_tlv, 433 void *ppdu_info_hdl) 434 { 435 struct hal_rx_ppdu_info *ppdu_info = 436 (struct hal_rx_ppdu_info *)ppdu_info_hdl; 437 438 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 1, 0); 439 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 2, 1); 440 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 3, 2); 441 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 4, 3); 442 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 5, 4); 443 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 6, 5); 444 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 7, 6); 445 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 8, 7); 446 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 9, 8); 447 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 10, 9); 448 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 11, 10); 449 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 12, 11); 450 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 13, 12); 451 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 14, 13); 452 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 15, 14); 453 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 16, 15); 454 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 17, 16); 455 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 18, 17); 456 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 19, 18); 457 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 20, 19); 458 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 21, 20); 459 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 22, 21); 460 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 23, 22); 461 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 24, 23); 462 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 25, 24); 463 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 26, 25); 464 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 27, 26); 465 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 28, 27); 466 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 29, 28); 467 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 30, 29); 468 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 31, 30); 469 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 32, 31); 470 } 471 /** 472 * hal_rx_proc_phyrx_other_receive_info_tlv_8074v2() 473 * -process other receive info TLV 474 * @rx_tlv_hdr: pointer to TLV header 475 * @ppdu_info: pointer to ppdu_info 476 * 477 * Return: None 478 */ 479 static 480 void hal_rx_proc_phyrx_other_receive_info_tlv_8074v2(void *rx_tlv_hdr, 481 void *ppdu_info_hdl) 482 { 483 uint16_t tlv_tag; 484 void *rx_tlv; 485 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 486 487 /* Skip TLV_HDR for OTHER_RECEIVE_INFO and follows the 488 * embedded TLVs inside 489 */ 490 rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 491 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv); 492 493 switch (tlv_tag) { 494 case WIFIPHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_E: 495 496 /* Skip TLV length to get TLV content */ 497 rx_tlv = (uint8_t *)rx_tlv + HAL_RX_TLV32_HDR_SIZE; 498 499 ppdu_info->evm_info.number_of_symbols = HAL_RX_GET(rx_tlv, 500 PHYRX_OTHER_RECEIVE_INFO, 501 SU_EVM_DETAILS_0_NUMBER_OF_SYMBOLS); 502 ppdu_info->evm_info.pilot_count = HAL_RX_GET(rx_tlv, 503 PHYRX_OTHER_RECEIVE_INFO, 504 SU_EVM_DETAILS_0_PILOT_COUNT); 505 ppdu_info->evm_info.nss_count = HAL_RX_GET(rx_tlv, 506 PHYRX_OTHER_RECEIVE_INFO, 507 SU_EVM_DETAILS_0_NSS_COUNT); 508 hal_rx_update_su_evm_info(rx_tlv, ppdu_info_hdl); 509 break; 510 } 511 } 512 #else 513 static inline 514 void hal_rx_proc_phyrx_other_receive_info_tlv_8074v2(void *rx_tlv_hdr, 515 void *ppdu_info_hdl) 516 { 517 } 518 #endif 519 520 #if defined(QCA_WIFI_QCA6018) && defined(WLAN_CFR_ENABLE) && \ 521 defined(WLAN_ENH_CFR_ENABLE) 522 static inline 523 void hal_rx_get_bb_info_8074v2(void *rx_tlv, 524 void *ppdu_info_hdl) 525 { 526 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 527 528 ppdu_info->cfr_info.bb_captured_channel = 529 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_CHANNEL); 530 531 ppdu_info->cfr_info.bb_captured_timeout = 532 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_TIMEOUT); 533 534 ppdu_info->cfr_info.bb_captured_reason = 535 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_REASON); 536 } 537 538 static inline 539 void hal_rx_get_rtt_info_8074v2(void *rx_tlv, 540 void *ppdu_info_hdl) 541 { 542 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 543 544 ppdu_info->cfr_info.rx_location_info_valid = 545 HAL_RX_GET(rx_tlv, PHYRX_PKT_END_13_RX_PKT_END_DETAILS, 546 RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID); 547 548 ppdu_info->cfr_info.rtt_che_buffer_pointer_low32 = 549 HAL_RX_GET(rx_tlv, 550 PHYRX_PKT_END_12_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 551 RTT_CHE_BUFFER_POINTER_LOW32); 552 553 ppdu_info->cfr_info.rtt_che_buffer_pointer_high8 = 554 HAL_RX_GET(rx_tlv, 555 PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 556 RTT_CHE_BUFFER_POINTER_HIGH8); 557 558 ppdu_info->cfr_info.chan_capture_status = 559 HAL_RX_GET(rx_tlv, 560 PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 561 RESERVED_8); 562 } 563 #endif 564 565 /** 566 * hal_rx_dump_msdu_start_tlv_8074v2() : dump RX msdu_start TLV in structured 567 * human readable format. 568 * @ msdu_start: pointer the msdu_start TLV in pkt. 569 * @ dbg_level: log level. 570 * 571 * Return: void 572 */ 573 static void hal_rx_dump_msdu_start_tlv_8074v2(void *msdustart, 574 uint8_t dbg_level) 575 { 576 struct rx_msdu_start *msdu_start = (struct rx_msdu_start *)msdustart; 577 578 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 579 "rx_msdu_start tlv - " 580 "rxpcu_mpdu_filter_in_category: %d " 581 "sw_frame_group_id: %d " 582 "phy_ppdu_id: %d " 583 "msdu_length: %d " 584 "ipsec_esp: %d " 585 "l3_offset: %d " 586 "ipsec_ah: %d " 587 "l4_offset: %d " 588 "msdu_number: %d " 589 "decap_format: %d " 590 "ipv4_proto: %d " 591 "ipv6_proto: %d " 592 "tcp_proto: %d " 593 "udp_proto: %d " 594 "ip_frag: %d " 595 "tcp_only_ack: %d " 596 "da_is_bcast_mcast: %d " 597 "ip4_protocol_ip6_next_header: %d " 598 "toeplitz_hash_2_or_4: %d " 599 "flow_id_toeplitz: %d " 600 "user_rssi: %d " 601 "pkt_type: %d " 602 "stbc: %d " 603 "sgi: %d " 604 "rate_mcs: %d " 605 "receive_bandwidth: %d " 606 "reception_type: %d " 607 "ppdu_start_timestamp: %d " 608 "sw_phy_meta_data: %d ", 609 msdu_start->rxpcu_mpdu_filter_in_category, 610 msdu_start->sw_frame_group_id, 611 msdu_start->phy_ppdu_id, 612 msdu_start->msdu_length, 613 msdu_start->ipsec_esp, 614 msdu_start->l3_offset, 615 msdu_start->ipsec_ah, 616 msdu_start->l4_offset, 617 msdu_start->msdu_number, 618 msdu_start->decap_format, 619 msdu_start->ipv4_proto, 620 msdu_start->ipv6_proto, 621 msdu_start->tcp_proto, 622 msdu_start->udp_proto, 623 msdu_start->ip_frag, 624 msdu_start->tcp_only_ack, 625 msdu_start->da_is_bcast_mcast, 626 msdu_start->ip4_protocol_ip6_next_header, 627 msdu_start->toeplitz_hash_2_or_4, 628 msdu_start->flow_id_toeplitz, 629 msdu_start->user_rssi, 630 msdu_start->pkt_type, 631 msdu_start->stbc, 632 msdu_start->sgi, 633 msdu_start->rate_mcs, 634 msdu_start->receive_bandwidth, 635 msdu_start->reception_type, 636 msdu_start->ppdu_start_timestamp, 637 msdu_start->sw_phy_meta_data); 638 } 639 640 /** 641 * hal_rx_dump_msdu_end_tlv_8074v2: dump RX msdu_end TLV in structured 642 * human readable format. 643 * @ msdu_end: pointer the msdu_end TLV in pkt. 644 * @ dbg_level: log level. 645 * 646 * Return: void 647 */ 648 static void hal_rx_dump_msdu_end_tlv_8074v2(void *msduend, 649 uint8_t dbg_level) 650 { 651 struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend; 652 653 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 654 "rx_msdu_end tlv - " 655 "rxpcu_mpdu_filter_in_category: %d " 656 "sw_frame_group_id: %d " 657 "phy_ppdu_id: %d " 658 "ip_hdr_chksum: %d " 659 "tcp_udp_chksum: %d " 660 "key_id_octet: %d " 661 "cce_super_rule: %d " 662 "cce_classify_not_done_truncat: %d " 663 "cce_classify_not_done_cce_dis: %d " 664 "ext_wapi_pn_63_48: %d " 665 "ext_wapi_pn_95_64: %d " 666 "ext_wapi_pn_127_96: %d " 667 "reported_mpdu_length: %d " 668 "first_msdu: %d " 669 "last_msdu: %d " 670 "sa_idx_timeout: %d " 671 "da_idx_timeout: %d " 672 "msdu_limit_error: %d " 673 "flow_idx_timeout: %d " 674 "flow_idx_invalid: %d " 675 "wifi_parser_error: %d " 676 "amsdu_parser_error: %d " 677 "sa_is_valid: %d " 678 "da_is_valid: %d " 679 "da_is_mcbc: %d " 680 "l3_header_padding: %d " 681 "ipv6_options_crc: %d " 682 "tcp_seq_number: %d " 683 "tcp_ack_number: %d " 684 "tcp_flag: %d " 685 "lro_eligible: %d " 686 "window_size: %d " 687 "da_offset: %d " 688 "sa_offset: %d " 689 "da_offset_valid: %d " 690 "sa_offset_valid: %d " 691 "rule_indication_31_0: %d " 692 "rule_indication_63_32: %d " 693 "sa_idx: %d " 694 "msdu_drop: %d " 695 "reo_destination_indication: %d " 696 "flow_idx: %d " 697 "fse_metadata: %d " 698 "cce_metadata: %d " 699 "sa_sw_peer_id: %d ", 700 msdu_end->rxpcu_mpdu_filter_in_category, 701 msdu_end->sw_frame_group_id, 702 msdu_end->phy_ppdu_id, 703 msdu_end->ip_hdr_chksum, 704 msdu_end->tcp_udp_chksum, 705 msdu_end->key_id_octet, 706 msdu_end->cce_super_rule, 707 msdu_end->cce_classify_not_done_truncate, 708 msdu_end->cce_classify_not_done_cce_dis, 709 msdu_end->ext_wapi_pn_63_48, 710 msdu_end->ext_wapi_pn_95_64, 711 msdu_end->ext_wapi_pn_127_96, 712 msdu_end->reported_mpdu_length, 713 msdu_end->first_msdu, 714 msdu_end->last_msdu, 715 msdu_end->sa_idx_timeout, 716 msdu_end->da_idx_timeout, 717 msdu_end->msdu_limit_error, 718 msdu_end->flow_idx_timeout, 719 msdu_end->flow_idx_invalid, 720 msdu_end->wifi_parser_error, 721 msdu_end->amsdu_parser_error, 722 msdu_end->sa_is_valid, 723 msdu_end->da_is_valid, 724 msdu_end->da_is_mcbc, 725 msdu_end->l3_header_padding, 726 msdu_end->ipv6_options_crc, 727 msdu_end->tcp_seq_number, 728 msdu_end->tcp_ack_number, 729 msdu_end->tcp_flag, 730 msdu_end->lro_eligible, 731 msdu_end->window_size, 732 msdu_end->da_offset, 733 msdu_end->sa_offset, 734 msdu_end->da_offset_valid, 735 msdu_end->sa_offset_valid, 736 msdu_end->rule_indication_31_0, 737 msdu_end->rule_indication_63_32, 738 msdu_end->sa_idx, 739 msdu_end->msdu_drop, 740 msdu_end->reo_destination_indication, 741 msdu_end->flow_idx, 742 msdu_end->fse_metadata, 743 msdu_end->cce_metadata, 744 msdu_end->sa_sw_peer_id); 745 } 746 747 748 /* 749 * Get tid from RX_MPDU_START 750 */ 751 #define HAL_RX_MPDU_INFO_TID_GET(_rx_mpdu_info) \ 752 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 753 RX_MPDU_INFO_3_TID_OFFSET)), \ 754 RX_MPDU_INFO_3_TID_MASK, \ 755 RX_MPDU_INFO_3_TID_LSB)) 756 757 static uint32_t hal_rx_mpdu_start_tid_get_8074v2(uint8_t *buf) 758 { 759 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 760 struct rx_mpdu_start *mpdu_start = 761 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 762 uint32_t tid; 763 764 tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details); 765 766 return tid; 767 } 768 769 #define HAL_RX_MSDU_START_RECEPTION_TYPE_GET(_rx_msdu_start) \ 770 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \ 771 RX_MSDU_START_5_RECEPTION_TYPE_OFFSET)), \ 772 RX_MSDU_START_5_RECEPTION_TYPE_MASK, \ 773 RX_MSDU_START_5_RECEPTION_TYPE_LSB)) 774 775 /* 776 * hal_rx_msdu_start_reception_type_get(): API to get the reception type 777 * Interval from rx_msdu_start 778 * 779 * @buf: pointer to the start of RX PKT TLV header 780 * Return: uint32_t(reception_type) 781 */ 782 static uint32_t hal_rx_msdu_start_reception_type_get_8074v2(uint8_t *buf) 783 { 784 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 785 struct rx_msdu_start *msdu_start = 786 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 787 uint32_t reception_type; 788 789 reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start); 790 791 return reception_type; 792 } 793 794 /* RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_OFFSET */ 795 #define HAL_RX_MSDU_END_DA_IDX_GET(_rx_msdu_end) \ 796 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 797 RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_OFFSET)), \ 798 RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_MASK, \ 799 RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_LSB)) 800 /** 801 * hal_rx_msdu_end_da_idx_get_8074v2: API to get da_idx 802 * from rx_msdu_end TLV 803 * 804 * @ buf: pointer to the start of RX PKT TLV headers 805 * Return: da index 806 */ 807 static uint16_t hal_rx_msdu_end_da_idx_get_8074v2(uint8_t *buf) 808 { 809 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 810 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 811 uint16_t da_idx; 812 813 da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 814 815 return da_idx; 816 } 817