1 /* 2 * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #include "hal_hw_headers.h" 19 #include "hal_internal.h" 20 #include "cdp_txrx_mon_struct.h" 21 #include "qdf_trace.h" 22 #include "hal_rx.h" 23 #include "hal_tx.h" 24 #include "dp_types.h" 25 #include "hal_api_mon.h" 26 #ifndef QCA_WIFI_QCA6018 27 #include "phyrx_other_receive_info_su_evm_details.h" 28 #endif 29 30 #define HAL_RX_MPDU_GET_SEQUENCE_NUMBER(_rx_mpdu_info) \ 31 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 32 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_OFFSET)), \ 33 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_MASK, \ 34 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_LSB)) 35 36 #define HAL_RX_MSDU_END_DA_IS_MCBC_GET(_rx_msdu_end) \ 37 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 38 RX_MSDU_END_5_DA_IS_MCBC_OFFSET)), \ 39 RX_MSDU_END_5_DA_IS_MCBC_MASK, \ 40 RX_MSDU_END_5_DA_IS_MCBC_LSB)) 41 42 #define HAL_RX_MSDU_END_SA_IS_VALID_GET(_rx_msdu_end) \ 43 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 44 RX_MSDU_END_5_SA_IS_VALID_OFFSET)), \ 45 RX_MSDU_END_5_SA_IS_VALID_MASK, \ 46 RX_MSDU_END_5_SA_IS_VALID_LSB)) 47 48 #define HAL_RX_MSDU_END_SA_IDX_GET(_rx_msdu_end) \ 49 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 50 RX_MSDU_END_13_SA_IDX_OFFSET)), \ 51 RX_MSDU_END_13_SA_IDX_MASK, \ 52 RX_MSDU_END_13_SA_IDX_LSB)) 53 54 #define HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(_rx_msdu_end) \ 55 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 56 RX_MSDU_END_5_L3_HEADER_PADDING_OFFSET)), \ 57 RX_MSDU_END_5_L3_HEADER_PADDING_MASK, \ 58 RX_MSDU_END_5_L3_HEADER_PADDING_LSB)) 59 60 #define HAL_RX_MPDU_ENCRYPTION_INFO_VALID(_rx_mpdu_info) \ 61 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 62 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_OFFSET)), \ 63 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_MASK, \ 64 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_LSB)) 65 66 #define HAL_RX_MPDU_PN_31_0_GET(_rx_mpdu_info) \ 67 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 68 RX_MPDU_INFO_4_PN_31_0_OFFSET)), \ 69 RX_MPDU_INFO_4_PN_31_0_MASK, \ 70 RX_MPDU_INFO_4_PN_31_0_LSB)) 71 72 #define HAL_RX_MPDU_PN_63_32_GET(_rx_mpdu_info) \ 73 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 74 RX_MPDU_INFO_5_PN_63_32_OFFSET)), \ 75 RX_MPDU_INFO_5_PN_63_32_MASK, \ 76 RX_MPDU_INFO_5_PN_63_32_LSB)) 77 78 #define HAL_RX_MPDU_PN_95_64_GET(_rx_mpdu_info) \ 79 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 80 RX_MPDU_INFO_6_PN_95_64_OFFSET)), \ 81 RX_MPDU_INFO_6_PN_95_64_MASK, \ 82 RX_MPDU_INFO_6_PN_95_64_LSB)) 83 84 #define HAL_RX_MPDU_PN_127_96_GET(_rx_mpdu_info) \ 85 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 86 RX_MPDU_INFO_7_PN_127_96_OFFSET)), \ 87 RX_MPDU_INFO_7_PN_127_96_MASK, \ 88 RX_MPDU_INFO_7_PN_127_96_LSB)) 89 90 #define HAL_RX_MSDU_END_FIRST_MSDU_GET(_rx_msdu_end) \ 91 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 92 RX_MSDU_END_5_FIRST_MSDU_OFFSET)), \ 93 RX_MSDU_END_5_FIRST_MSDU_MASK, \ 94 RX_MSDU_END_5_FIRST_MSDU_LSB)) 95 96 #define HAL_RX_MSDU_START_MIMO_SS_BITMAP(_rx_msdu_start)\ 97 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ 98 RX_MSDU_START_5_MIMO_SS_BITMAP_OFFSET)), \ 99 RX_MSDU_START_5_MIMO_SS_BITMAP_MASK, \ 100 RX_MSDU_START_5_MIMO_SS_BITMAP_LSB)) 101 102 #define HAL_RX_MSDU_END_DA_IS_VALID_GET(_rx_msdu_end) \ 103 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 104 RX_MSDU_END_5_DA_IS_VALID_OFFSET)), \ 105 RX_MSDU_END_5_DA_IS_VALID_MASK, \ 106 RX_MSDU_END_5_DA_IS_VALID_LSB)) 107 108 #define HAL_RX_MSDU_END_LAST_MSDU_GET(_rx_msdu_end) \ 109 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 110 RX_MSDU_END_5_LAST_MSDU_OFFSET)), \ 111 RX_MSDU_END_5_LAST_MSDU_MASK, \ 112 RX_MSDU_END_5_LAST_MSDU_LSB)) 113 114 #define HAL_RX_MPDU_GET_MAC_AD4_VALID(_rx_mpdu_info) \ 115 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 116 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_OFFSET)), \ 117 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_MASK, \ 118 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_LSB)) 119 120 #define HAL_RX_MPDU_INFO_SW_PEER_ID_GET(_rx_mpdu_info) \ 121 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 122 RX_MPDU_INFO_1_SW_PEER_ID_OFFSET)), \ 123 RX_MPDU_INFO_1_SW_PEER_ID_MASK, \ 124 RX_MPDU_INFO_1_SW_PEER_ID_LSB)) 125 126 #define HAL_RX_MPDU_GET_TODS(_rx_mpdu_info) \ 127 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 128 RX_MPDU_INFO_2_TO_DS_OFFSET)), \ 129 RX_MPDU_INFO_2_TO_DS_MASK, \ 130 RX_MPDU_INFO_2_TO_DS_LSB)) 131 132 #define HAL_RX_MPDU_GET_FROMDS(_rx_mpdu_info) \ 133 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 134 RX_MPDU_INFO_2_FR_DS_OFFSET)), \ 135 RX_MPDU_INFO_2_FR_DS_MASK, \ 136 RX_MPDU_INFO_2_FR_DS_LSB)) 137 138 #define HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(_rx_mpdu_info) \ 139 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 140 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_OFFSET)), \ 141 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_MASK, \ 142 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_LSB)) 143 144 #define HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(_rx_mpdu_info) \ 145 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 146 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_OFFSET)), \ 147 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_MASK, \ 148 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_LSB)) 149 150 #define HAL_RX_MPDU_AD1_31_0_GET(_rx_mpdu_info) \ 151 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 152 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET)), \ 153 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK, \ 154 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB)) 155 156 #define HAL_RX_MPDU_AD1_47_32_GET(_rx_mpdu_info) \ 157 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 158 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET)), \ 159 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK, \ 160 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB)) 161 162 #define HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(_rx_mpdu_info) \ 163 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 164 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_OFFSET)), \ 165 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_MASK, \ 166 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_LSB)) 167 168 #define HAL_RX_MPDU_AD2_15_0_GET(_rx_mpdu_info) \ 169 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 170 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET)), \ 171 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK, \ 172 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB)) 173 174 #define HAL_RX_MPDU_AD2_47_16_GET(_rx_mpdu_info) \ 175 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 176 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET)), \ 177 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK, \ 178 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB)) 179 180 #define HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(_rx_mpdu_info) \ 181 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 182 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_OFFSET)), \ 183 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_MASK, \ 184 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_LSB)) 185 186 #define HAL_RX_MPDU_AD3_31_0_GET(_rx_mpdu_info) \ 187 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 188 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_OFFSET)), \ 189 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_MASK, \ 190 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_LSB)) 191 192 #define HAL_RX_MPDU_AD3_47_32_GET(_rx_mpdu_info) \ 193 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 194 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_OFFSET)), \ 195 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_MASK, \ 196 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_LSB)) 197 198 #define HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(_rx_mpdu_info) \ 199 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 200 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_OFFSET)), \ 201 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_MASK, \ 202 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_LSB)) 203 204 #define HAL_RX_MPDU_AD4_31_0_GET(_rx_mpdu_info) \ 205 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 206 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET)), \ 207 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK, \ 208 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB)) 209 210 #define HAL_RX_MPDU_AD4_47_32_GET(_rx_mpdu_info) \ 211 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 212 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET)), \ 213 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK, \ 214 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB)) 215 216 #define HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(_rx_mpdu_info) \ 217 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 218 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_OFFSET)), \ 219 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_MASK, \ 220 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_LSB)) 221 222 #define HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(_rx_mpdu_info) \ 223 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 224 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)), \ 225 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK, \ 226 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB)) 227 228 #define HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(_rx_msdu_end) \ 229 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 230 RX_MSDU_END_16_SA_SW_PEER_ID_OFFSET)), \ 231 RX_MSDU_END_16_SA_SW_PEER_ID_MASK, \ 232 RX_MSDU_END_16_SA_SW_PEER_ID_LSB)) 233 234 #define HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va) \ 235 (uint8_t *)(link_desc_va) + \ 236 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 237 238 #define HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0) \ 239 (uint8_t *)(msdu0) + \ 240 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 241 242 #define HAL_ENT_MPDU_DESC_INFO(ent_ring_desc) \ 243 (uint8_t *)(ent_ring_desc) + \ 244 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 245 246 #define HAL_DST_MPDU_DESC_INFO(dst_ring_desc) \ 247 (uint8_t *)(dst_ring_desc) + \ 248 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 249 250 #define HAL_RX_GET_FC_VALID(rx_mpdu_start) \ 251 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, MPDU_FRAME_CONTROL_VALID) 252 253 #define HAL_RX_GET_TO_DS_FLAG(rx_mpdu_start) \ 254 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, TO_DS) 255 256 #define HAL_RX_GET_MAC_ADDR2_VALID(rx_mpdu_start) \ 257 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, MAC_ADDR_AD2_VALID) 258 259 #define HAL_RX_GET_FILTER_CATEGORY(rx_mpdu_start) \ 260 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, RXPCU_MPDU_FILTER_IN_CATEGORY) 261 262 #define HAL_RX_GET_PPDU_ID(rx_mpdu_start) \ 263 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, PHY_PPDU_ID) 264 265 #define HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start) \ 266 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, SW_FRAME_GROUP_ID) 267 268 #define HAL_REO_R0_CONFIG(soc, reg_val, reo_params) \ 269 do { \ 270 reg_val &= \ 271 ~(HWIO_REO_R0_GENERAL_ENABLE_FRAGMENT_DEST_RING_BMSK |\ 272 HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK | \ 273 HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK); \ 274 reg_val |= \ 275 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 276 FRAGMENT_DEST_RING, \ 277 (reo_params)->frag_dst_ring) | \ 278 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 279 AGING_LIST_ENABLE, 1) |\ 280 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 281 AGING_FLUSH_ENABLE, 1);\ 282 HAL_REG_WRITE((soc), \ 283 HWIO_REO_R0_GENERAL_ENABLE_ADDR( \ 284 SEQ_WCSS_UMAC_REO_REG_OFFSET), \ 285 (reg_val)); \ 286 } while (0) 287 288 #define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \ 289 ((struct rx_msdu_desc_info *) \ 290 _OFFSET_TO_BYTE_PTR((msdu_details_ptr), \ 291 UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET)) 292 293 #define HAL_RX_LINK_DESC_MSDU0_PTR(link_desc) \ 294 ((struct rx_msdu_details *) \ 295 _OFFSET_TO_BYTE_PTR((link_desc),\ 296 UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET)) 297 298 #define HAL_RX_MSDU_END_FLOW_IDX_GET(_rx_msdu_end) \ 299 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 300 RX_MSDU_END_14_FLOW_IDX_OFFSET)), \ 301 RX_MSDU_END_14_FLOW_IDX_MASK, \ 302 RX_MSDU_END_14_FLOW_IDX_LSB)) 303 304 #define HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(_rx_msdu_end) \ 305 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 306 RX_MSDU_END_5_FLOW_IDX_INVALID_OFFSET)), \ 307 RX_MSDU_END_5_FLOW_IDX_INVALID_MASK, \ 308 RX_MSDU_END_5_FLOW_IDX_INVALID_LSB)) 309 310 #define HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(_rx_msdu_end) \ 311 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 312 RX_MSDU_END_5_FLOW_IDX_TIMEOUT_OFFSET)), \ 313 RX_MSDU_END_5_FLOW_IDX_TIMEOUT_MASK, \ 314 RX_MSDU_END_5_FLOW_IDX_TIMEOUT_LSB)) 315 316 #define HAL_RX_MSDU_END_FSE_METADATA_GET(_rx_msdu_end) \ 317 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 318 RX_MSDU_END_15_FSE_METADATA_OFFSET)), \ 319 RX_MSDU_END_15_FSE_METADATA_MASK, \ 320 RX_MSDU_END_15_FSE_METADATA_LSB)) 321 322 #define HAL_RX_MSDU_END_CCE_METADATA_GET(_rx_msdu_end) \ 323 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 324 RX_MSDU_END_16_CCE_METADATA_OFFSET)), \ 325 RX_MSDU_END_16_CCE_METADATA_MASK, \ 326 RX_MSDU_END_16_CCE_METADATA_LSB)) 327 328 #define HAL_RX_TLV_GET_TCP_CHKSUM(buf) \ 329 (_HAL_MS( \ 330 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 331 msdu_end_tlv.rx_msdu_end), \ 332 RX_MSDU_END_1_TCP_UDP_CHKSUM_OFFSET)), \ 333 RX_MSDU_END_1_TCP_UDP_CHKSUM_MASK, \ 334 RX_MSDU_END_1_TCP_UDP_CHKSUM_LSB)) 335 336 /* 337 * hal_rx_msdu_start_nss_get_8074v2(): API to get the NSS 338 * Interval from rx_msdu_start 339 * 340 * @buf: pointer to the start of RX PKT TLV header 341 * Return: uint32_t(nss) 342 */ 343 static uint32_t hal_rx_msdu_start_nss_get_8074v2(uint8_t *buf) 344 { 345 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 346 struct rx_msdu_start *msdu_start = 347 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 348 uint8_t mimo_ss_bitmap; 349 350 mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start); 351 352 return qdf_get_hweight8(mimo_ss_bitmap); 353 } 354 355 /** 356 * hal_rx_mon_hw_desc_get_mpdu_status_8074v2(): Retrieve MPDU status 357 * 358 * @ hw_desc_addr: Start address of Rx HW TLVs 359 * @ rs: Status for monitor mode 360 * 361 * Return: void 362 */ 363 static void hal_rx_mon_hw_desc_get_mpdu_status_8074v2(void *hw_desc_addr, 364 struct mon_rx_status *rs) 365 { 366 struct rx_msdu_start *rx_msdu_start; 367 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 368 uint32_t reg_value; 369 const uint32_t sgi_hw_to_cdp[] = { 370 CDP_SGI_0_8_US, 371 CDP_SGI_0_4_US, 372 CDP_SGI_1_6_US, 373 CDP_SGI_3_2_US, 374 }; 375 376 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 377 378 HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs); 379 380 rs->ant_signal_db = HAL_RX_GET(rx_msdu_start, 381 RX_MSDU_START_5, USER_RSSI); 382 rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC); 383 384 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI); 385 rs->sgi = sgi_hw_to_cdp[reg_value]; 386 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE); 387 rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0; 388 /* TODO: rs->beamformed should be set for SU beamforming also */ 389 } 390 391 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 392 static uint32_t hal_get_link_desc_size_8074v2(void) 393 { 394 return LINK_DESC_SIZE; 395 } 396 397 /* 398 * hal_rx_get_tlv_8074v2(): API to get the tlv 399 * 400 * @rx_tlv: TLV data extracted from the rx packet 401 * Return: uint8_t 402 */ 403 static uint8_t hal_rx_get_tlv_8074v2(void *rx_tlv) 404 { 405 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH); 406 } 407 408 #ifndef QCA_WIFI_QCA6018 409 #define HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, evm, pilot) \ 410 (ppdu_info)->evm_info.pilot_evm[pilot] = HAL_RX_GET(rx_tlv, \ 411 PHYRX_OTHER_RECEIVE_INFO, \ 412 SU_EVM_DETAILS_##evm##_PILOT_##pilot##_EVM) 413 414 static inline void 415 hal_rx_update_su_evm_info(void *rx_tlv, 416 void *ppdu_info_hdl) 417 { 418 struct hal_rx_ppdu_info *ppdu_info = 419 (struct hal_rx_ppdu_info *)ppdu_info_hdl; 420 421 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 1, 0); 422 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 2, 1); 423 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 3, 2); 424 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 4, 3); 425 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 5, 4); 426 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 6, 5); 427 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 7, 6); 428 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 8, 7); 429 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 9, 8); 430 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 10, 9); 431 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 11, 10); 432 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 12, 11); 433 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 13, 12); 434 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 14, 13); 435 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 15, 14); 436 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 16, 15); 437 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 17, 16); 438 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 18, 17); 439 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 19, 18); 440 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 20, 19); 441 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 21, 20); 442 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 22, 21); 443 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 23, 22); 444 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 24, 23); 445 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 25, 24); 446 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 26, 25); 447 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 27, 26); 448 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 28, 27); 449 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 29, 28); 450 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 30, 29); 451 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 31, 30); 452 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 32, 31); 453 } 454 /** 455 * hal_rx_proc_phyrx_other_receive_info_tlv_8074v2() 456 * -process other receive info TLV 457 * @rx_tlv_hdr: pointer to TLV header 458 * @ppdu_info: pointer to ppdu_info 459 * 460 * Return: None 461 */ 462 static 463 void hal_rx_proc_phyrx_other_receive_info_tlv_8074v2(void *rx_tlv_hdr, 464 void *ppdu_info_hdl) 465 { 466 uint16_t tlv_tag; 467 void *rx_tlv; 468 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 469 470 /* Skip TLV_HDR for OTHER_RECEIVE_INFO and follows the 471 * embedded TLVs inside 472 */ 473 rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 474 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv); 475 476 switch (tlv_tag) { 477 case WIFIPHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_E: 478 479 /* Skip TLV length to get TLV content */ 480 rx_tlv = (uint8_t *)rx_tlv + HAL_RX_TLV32_HDR_SIZE; 481 482 ppdu_info->evm_info.number_of_symbols = HAL_RX_GET(rx_tlv, 483 PHYRX_OTHER_RECEIVE_INFO, 484 SU_EVM_DETAILS_0_NUMBER_OF_SYMBOLS); 485 ppdu_info->evm_info.pilot_count = HAL_RX_GET(rx_tlv, 486 PHYRX_OTHER_RECEIVE_INFO, 487 SU_EVM_DETAILS_0_PILOT_COUNT); 488 ppdu_info->evm_info.nss_count = HAL_RX_GET(rx_tlv, 489 PHYRX_OTHER_RECEIVE_INFO, 490 SU_EVM_DETAILS_0_NSS_COUNT); 491 hal_rx_update_su_evm_info(rx_tlv, ppdu_info_hdl); 492 break; 493 } 494 } 495 #else 496 static inline 497 void hal_rx_proc_phyrx_other_receive_info_tlv_8074v2(void *rx_tlv_hdr, 498 void *ppdu_info_hdl) 499 { 500 } 501 #endif 502 503 #if defined(QCA_WIFI_QCA6018) && defined(WLAN_CFR_ENABLE) && \ 504 defined(WLAN_ENH_CFR_ENABLE) 505 static inline 506 void hal_rx_get_bb_info_8074v2(void *rx_tlv, 507 void *ppdu_info_hdl) 508 { 509 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 510 511 ppdu_info->cfr_info.bb_captured_channel = 512 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_CHANNEL); 513 514 ppdu_info->cfr_info.bb_captured_timeout = 515 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_TIMEOUT); 516 517 ppdu_info->cfr_info.bb_captured_reason = 518 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_REASON); 519 } 520 521 static inline 522 void hal_rx_get_rtt_info_8074v2(void *rx_tlv, 523 void *ppdu_info_hdl) 524 { 525 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 526 527 ppdu_info->cfr_info.rx_location_info_valid = 528 HAL_RX_GET(rx_tlv, PHYRX_PKT_END_13_RX_PKT_END_DETAILS, 529 RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID); 530 531 ppdu_info->cfr_info.rtt_che_buffer_pointer_low32 = 532 HAL_RX_GET(rx_tlv, 533 PHYRX_PKT_END_12_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 534 RTT_CHE_BUFFER_POINTER_LOW32); 535 536 ppdu_info->cfr_info.rtt_che_buffer_pointer_high8 = 537 HAL_RX_GET(rx_tlv, 538 PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 539 RTT_CHE_BUFFER_POINTER_HIGH8); 540 541 ppdu_info->cfr_info.chan_capture_status = 542 HAL_RX_GET(rx_tlv, 543 PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 544 RESERVED_8); 545 } 546 #endif 547 548 /** 549 * hal_rx_dump_msdu_start_tlv_8074v2() : dump RX msdu_start TLV in structured 550 * human readable format. 551 * @ msdu_start: pointer the msdu_start TLV in pkt. 552 * @ dbg_level: log level. 553 * 554 * Return: void 555 */ 556 static void hal_rx_dump_msdu_start_tlv_8074v2(void *msdustart, 557 uint8_t dbg_level) 558 { 559 struct rx_msdu_start *msdu_start = (struct rx_msdu_start *)msdustart; 560 561 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 562 "rx_msdu_start tlv - " 563 "rxpcu_mpdu_filter_in_category: %d " 564 "sw_frame_group_id: %d " 565 "phy_ppdu_id: %d " 566 "msdu_length: %d " 567 "ipsec_esp: %d " 568 "l3_offset: %d " 569 "ipsec_ah: %d " 570 "l4_offset: %d " 571 "msdu_number: %d " 572 "decap_format: %d " 573 "ipv4_proto: %d " 574 "ipv6_proto: %d " 575 "tcp_proto: %d " 576 "udp_proto: %d " 577 "ip_frag: %d " 578 "tcp_only_ack: %d " 579 "da_is_bcast_mcast: %d " 580 "ip4_protocol_ip6_next_header: %d " 581 "toeplitz_hash_2_or_4: %d " 582 "flow_id_toeplitz: %d " 583 "user_rssi: %d " 584 "pkt_type: %d " 585 "stbc: %d " 586 "sgi: %d " 587 "rate_mcs: %d " 588 "receive_bandwidth: %d " 589 "reception_type: %d " 590 "ppdu_start_timestamp: %d " 591 "sw_phy_meta_data: %d ", 592 msdu_start->rxpcu_mpdu_filter_in_category, 593 msdu_start->sw_frame_group_id, 594 msdu_start->phy_ppdu_id, 595 msdu_start->msdu_length, 596 msdu_start->ipsec_esp, 597 msdu_start->l3_offset, 598 msdu_start->ipsec_ah, 599 msdu_start->l4_offset, 600 msdu_start->msdu_number, 601 msdu_start->decap_format, 602 msdu_start->ipv4_proto, 603 msdu_start->ipv6_proto, 604 msdu_start->tcp_proto, 605 msdu_start->udp_proto, 606 msdu_start->ip_frag, 607 msdu_start->tcp_only_ack, 608 msdu_start->da_is_bcast_mcast, 609 msdu_start->ip4_protocol_ip6_next_header, 610 msdu_start->toeplitz_hash_2_or_4, 611 msdu_start->flow_id_toeplitz, 612 msdu_start->user_rssi, 613 msdu_start->pkt_type, 614 msdu_start->stbc, 615 msdu_start->sgi, 616 msdu_start->rate_mcs, 617 msdu_start->receive_bandwidth, 618 msdu_start->reception_type, 619 msdu_start->ppdu_start_timestamp, 620 msdu_start->sw_phy_meta_data); 621 } 622 623 /** 624 * hal_rx_dump_msdu_end_tlv_8074v2: dump RX msdu_end TLV in structured 625 * human readable format. 626 * @ msdu_end: pointer the msdu_end TLV in pkt. 627 * @ dbg_level: log level. 628 * 629 * Return: void 630 */ 631 static void hal_rx_dump_msdu_end_tlv_8074v2(void *msduend, 632 uint8_t dbg_level) 633 { 634 struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend; 635 636 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 637 "rx_msdu_end tlv - " 638 "rxpcu_mpdu_filter_in_category: %d " 639 "sw_frame_group_id: %d " 640 "phy_ppdu_id: %d " 641 "ip_hdr_chksum: %d " 642 "tcp_udp_chksum: %d " 643 "key_id_octet: %d " 644 "cce_super_rule: %d " 645 "cce_classify_not_done_truncat: %d " 646 "cce_classify_not_done_cce_dis: %d " 647 "ext_wapi_pn_63_48: %d " 648 "ext_wapi_pn_95_64: %d " 649 "ext_wapi_pn_127_96: %d " 650 "reported_mpdu_length: %d " 651 "first_msdu: %d " 652 "last_msdu: %d " 653 "sa_idx_timeout: %d " 654 "da_idx_timeout: %d " 655 "msdu_limit_error: %d " 656 "flow_idx_timeout: %d " 657 "flow_idx_invalid: %d " 658 "wifi_parser_error: %d " 659 "amsdu_parser_error: %d " 660 "sa_is_valid: %d " 661 "da_is_valid: %d " 662 "da_is_mcbc: %d " 663 "l3_header_padding: %d " 664 "ipv6_options_crc: %d " 665 "tcp_seq_number: %d " 666 "tcp_ack_number: %d " 667 "tcp_flag: %d " 668 "lro_eligible: %d " 669 "window_size: %d " 670 "da_offset: %d " 671 "sa_offset: %d " 672 "da_offset_valid: %d " 673 "sa_offset_valid: %d " 674 "rule_indication_31_0: %d " 675 "rule_indication_63_32: %d " 676 "sa_idx: %d " 677 "msdu_drop: %d " 678 "reo_destination_indication: %d " 679 "flow_idx: %d " 680 "fse_metadata: %d " 681 "cce_metadata: %d " 682 "sa_sw_peer_id: %d ", 683 msdu_end->rxpcu_mpdu_filter_in_category, 684 msdu_end->sw_frame_group_id, 685 msdu_end->phy_ppdu_id, 686 msdu_end->ip_hdr_chksum, 687 msdu_end->tcp_udp_chksum, 688 msdu_end->key_id_octet, 689 msdu_end->cce_super_rule, 690 msdu_end->cce_classify_not_done_truncate, 691 msdu_end->cce_classify_not_done_cce_dis, 692 msdu_end->ext_wapi_pn_63_48, 693 msdu_end->ext_wapi_pn_95_64, 694 msdu_end->ext_wapi_pn_127_96, 695 msdu_end->reported_mpdu_length, 696 msdu_end->first_msdu, 697 msdu_end->last_msdu, 698 msdu_end->sa_idx_timeout, 699 msdu_end->da_idx_timeout, 700 msdu_end->msdu_limit_error, 701 msdu_end->flow_idx_timeout, 702 msdu_end->flow_idx_invalid, 703 msdu_end->wifi_parser_error, 704 msdu_end->amsdu_parser_error, 705 msdu_end->sa_is_valid, 706 msdu_end->da_is_valid, 707 msdu_end->da_is_mcbc, 708 msdu_end->l3_header_padding, 709 msdu_end->ipv6_options_crc, 710 msdu_end->tcp_seq_number, 711 msdu_end->tcp_ack_number, 712 msdu_end->tcp_flag, 713 msdu_end->lro_eligible, 714 msdu_end->window_size, 715 msdu_end->da_offset, 716 msdu_end->sa_offset, 717 msdu_end->da_offset_valid, 718 msdu_end->sa_offset_valid, 719 msdu_end->rule_indication_31_0, 720 msdu_end->rule_indication_63_32, 721 msdu_end->sa_idx, 722 msdu_end->msdu_drop, 723 msdu_end->reo_destination_indication, 724 msdu_end->flow_idx, 725 msdu_end->fse_metadata, 726 msdu_end->cce_metadata, 727 msdu_end->sa_sw_peer_id); 728 } 729 730 731 /* 732 * Get tid from RX_MPDU_START 733 */ 734 #define HAL_RX_MPDU_INFO_TID_GET(_rx_mpdu_info) \ 735 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 736 RX_MPDU_INFO_3_TID_OFFSET)), \ 737 RX_MPDU_INFO_3_TID_MASK, \ 738 RX_MPDU_INFO_3_TID_LSB)) 739 740 static uint32_t hal_rx_mpdu_start_tid_get_8074v2(uint8_t *buf) 741 { 742 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 743 struct rx_mpdu_start *mpdu_start = 744 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 745 uint32_t tid; 746 747 tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details); 748 749 return tid; 750 } 751 752 #define HAL_RX_MSDU_START_RECEPTION_TYPE_GET(_rx_msdu_start) \ 753 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \ 754 RX_MSDU_START_5_RECEPTION_TYPE_OFFSET)), \ 755 RX_MSDU_START_5_RECEPTION_TYPE_MASK, \ 756 RX_MSDU_START_5_RECEPTION_TYPE_LSB)) 757 758 /* 759 * hal_rx_msdu_start_reception_type_get(): API to get the reception type 760 * Interval from rx_msdu_start 761 * 762 * @buf: pointer to the start of RX PKT TLV header 763 * Return: uint32_t(reception_type) 764 */ 765 static uint32_t hal_rx_msdu_start_reception_type_get_8074v2(uint8_t *buf) 766 { 767 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 768 struct rx_msdu_start *msdu_start = 769 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 770 uint32_t reception_type; 771 772 reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start); 773 774 return reception_type; 775 } 776 777 /* RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_OFFSET */ 778 #define HAL_RX_MSDU_END_DA_IDX_GET(_rx_msdu_end) \ 779 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 780 RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_OFFSET)), \ 781 RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_MASK, \ 782 RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_LSB)) 783 /** 784 * hal_rx_msdu_end_da_idx_get_8074v2: API to get da_idx 785 * from rx_msdu_end TLV 786 * 787 * @ buf: pointer to the start of RX PKT TLV headers 788 * Return: da index 789 */ 790 static uint16_t hal_rx_msdu_end_da_idx_get_8074v2(uint8_t *buf) 791 { 792 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 793 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 794 uint16_t da_idx; 795 796 da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 797 798 return da_idx; 799 } 800