1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #include "hal_hw_headers.h" 19 #include "hal_internal.h" 20 #include "cdp_txrx_mon_struct.h" 21 #include "qdf_trace.h" 22 #include "hal_li_rx.h" 23 #include "hal_tx.h" 24 #include "dp_types.h" 25 #include "hal_api_mon.h" 26 #if (!defined(QCA_WIFI_QCA6018)) && (!defined(QCA_WIFI_QCA9574)) 27 #include "phyrx_other_receive_info_su_evm_details.h" 28 #endif 29 30 #define HAL_RX_MPDU_GET_SEQUENCE_NUMBER(_rx_mpdu_info) \ 31 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 32 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_OFFSET)), \ 33 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_MASK, \ 34 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_LSB)) 35 36 #define HAL_RX_MSDU_END_DA_IS_MCBC_GET(_rx_msdu_end) \ 37 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 38 RX_MSDU_END_5_DA_IS_MCBC_OFFSET)), \ 39 RX_MSDU_END_5_DA_IS_MCBC_MASK, \ 40 RX_MSDU_END_5_DA_IS_MCBC_LSB)) 41 42 #define HAL_RX_MSDU_END_SA_IS_VALID_GET(_rx_msdu_end) \ 43 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 44 RX_MSDU_END_5_SA_IS_VALID_OFFSET)), \ 45 RX_MSDU_END_5_SA_IS_VALID_MASK, \ 46 RX_MSDU_END_5_SA_IS_VALID_LSB)) 47 48 #define HAL_RX_MSDU_END_SA_IDX_GET(_rx_msdu_end) \ 49 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 50 RX_MSDU_END_13_SA_IDX_OFFSET)), \ 51 RX_MSDU_END_13_SA_IDX_MASK, \ 52 RX_MSDU_END_13_SA_IDX_LSB)) 53 54 #define HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(_rx_msdu_end) \ 55 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 56 RX_MSDU_END_5_L3_HEADER_PADDING_OFFSET)), \ 57 RX_MSDU_END_5_L3_HEADER_PADDING_MASK, \ 58 RX_MSDU_END_5_L3_HEADER_PADDING_LSB)) 59 60 #define HAL_RX_MPDU_ENCRYPTION_INFO_VALID(_rx_mpdu_info) \ 61 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 62 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_OFFSET)), \ 63 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_MASK, \ 64 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_LSB)) 65 66 #define HAL_RX_MPDU_PN_31_0_GET(_rx_mpdu_info) \ 67 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 68 RX_MPDU_INFO_4_PN_31_0_OFFSET)), \ 69 RX_MPDU_INFO_4_PN_31_0_MASK, \ 70 RX_MPDU_INFO_4_PN_31_0_LSB)) 71 72 #define HAL_RX_MPDU_PN_63_32_GET(_rx_mpdu_info) \ 73 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 74 RX_MPDU_INFO_5_PN_63_32_OFFSET)), \ 75 RX_MPDU_INFO_5_PN_63_32_MASK, \ 76 RX_MPDU_INFO_5_PN_63_32_LSB)) 77 78 #define HAL_RX_MPDU_PN_95_64_GET(_rx_mpdu_info) \ 79 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 80 RX_MPDU_INFO_6_PN_95_64_OFFSET)), \ 81 RX_MPDU_INFO_6_PN_95_64_MASK, \ 82 RX_MPDU_INFO_6_PN_95_64_LSB)) 83 84 #define HAL_RX_MPDU_PN_127_96_GET(_rx_mpdu_info) \ 85 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 86 RX_MPDU_INFO_7_PN_127_96_OFFSET)), \ 87 RX_MPDU_INFO_7_PN_127_96_MASK, \ 88 RX_MPDU_INFO_7_PN_127_96_LSB)) 89 90 #define HAL_RX_MSDU_END_FIRST_MSDU_GET(_rx_msdu_end) \ 91 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 92 RX_MSDU_END_5_FIRST_MSDU_OFFSET)), \ 93 RX_MSDU_END_5_FIRST_MSDU_MASK, \ 94 RX_MSDU_END_5_FIRST_MSDU_LSB)) 95 96 #define HAL_RX_MSDU_START_MIMO_SS_BITMAP(_rx_msdu_start)\ 97 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ 98 RX_MSDU_START_5_MIMO_SS_BITMAP_OFFSET)), \ 99 RX_MSDU_START_5_MIMO_SS_BITMAP_MASK, \ 100 RX_MSDU_START_5_MIMO_SS_BITMAP_LSB)) 101 102 #define HAL_RX_MSDU_END_DA_IS_VALID_GET(_rx_msdu_end) \ 103 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 104 RX_MSDU_END_5_DA_IS_VALID_OFFSET)), \ 105 RX_MSDU_END_5_DA_IS_VALID_MASK, \ 106 RX_MSDU_END_5_DA_IS_VALID_LSB)) 107 108 #define HAL_RX_MSDU_END_LAST_MSDU_GET(_rx_msdu_end) \ 109 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 110 RX_MSDU_END_5_LAST_MSDU_OFFSET)), \ 111 RX_MSDU_END_5_LAST_MSDU_MASK, \ 112 RX_MSDU_END_5_LAST_MSDU_LSB)) 113 114 #define HAL_RX_MPDU_GET_MAC_AD4_VALID(_rx_mpdu_info) \ 115 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 116 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_OFFSET)), \ 117 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_MASK, \ 118 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_LSB)) 119 120 #define HAL_RX_MPDU_INFO_SW_PEER_ID_GET(_rx_mpdu_info) \ 121 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 122 RX_MPDU_INFO_1_SW_PEER_ID_OFFSET)), \ 123 RX_MPDU_INFO_1_SW_PEER_ID_MASK, \ 124 RX_MPDU_INFO_1_SW_PEER_ID_LSB)) 125 126 #define HAL_RX_MPDU_GET_TODS(_rx_mpdu_info) \ 127 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 128 RX_MPDU_INFO_2_TO_DS_OFFSET)), \ 129 RX_MPDU_INFO_2_TO_DS_MASK, \ 130 RX_MPDU_INFO_2_TO_DS_LSB)) 131 132 #define HAL_RX_MPDU_GET_FROMDS(_rx_mpdu_info) \ 133 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 134 RX_MPDU_INFO_2_FR_DS_OFFSET)), \ 135 RX_MPDU_INFO_2_FR_DS_MASK, \ 136 RX_MPDU_INFO_2_FR_DS_LSB)) 137 138 #define HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(_rx_mpdu_info) \ 139 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 140 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_OFFSET)), \ 141 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_MASK, \ 142 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_LSB)) 143 144 #define HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(_rx_mpdu_info) \ 145 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 146 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_OFFSET)), \ 147 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_MASK, \ 148 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_LSB)) 149 150 #define HAL_RX_MPDU_AD1_31_0_GET(_rx_mpdu_info) \ 151 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 152 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET)), \ 153 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK, \ 154 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB)) 155 156 #define HAL_RX_MPDU_AD1_47_32_GET(_rx_mpdu_info) \ 157 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 158 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET)), \ 159 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK, \ 160 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB)) 161 162 #define HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(_rx_mpdu_info) \ 163 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 164 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_OFFSET)), \ 165 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_MASK, \ 166 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_LSB)) 167 168 #define HAL_RX_MPDU_AD2_15_0_GET(_rx_mpdu_info) \ 169 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 170 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET)), \ 171 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK, \ 172 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB)) 173 174 #define HAL_RX_MPDU_AD2_47_16_GET(_rx_mpdu_info) \ 175 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 176 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET)), \ 177 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK, \ 178 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB)) 179 180 #define HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(_rx_mpdu_info) \ 181 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 182 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_OFFSET)), \ 183 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_MASK, \ 184 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_LSB)) 185 186 #define HAL_RX_MPDU_AD3_31_0_GET(_rx_mpdu_info) \ 187 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 188 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_OFFSET)), \ 189 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_MASK, \ 190 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_LSB)) 191 192 #define HAL_RX_MPDU_AD3_47_32_GET(_rx_mpdu_info) \ 193 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 194 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_OFFSET)), \ 195 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_MASK, \ 196 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_LSB)) 197 198 #define HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(_rx_mpdu_info) \ 199 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 200 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_OFFSET)), \ 201 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_MASK, \ 202 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_LSB)) 203 204 #define HAL_RX_MPDU_AD4_31_0_GET(_rx_mpdu_info) \ 205 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 206 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET)), \ 207 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK, \ 208 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB)) 209 210 #define HAL_RX_MPDU_AD4_47_32_GET(_rx_mpdu_info) \ 211 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 212 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET)), \ 213 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK, \ 214 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB)) 215 216 #define HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(_rx_mpdu_info) \ 217 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 218 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_OFFSET)), \ 219 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_MASK, \ 220 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_LSB)) 221 222 #define HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(_rx_mpdu_info) \ 223 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 224 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)), \ 225 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK, \ 226 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB)) 227 228 #define HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(_rx_msdu_end) \ 229 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 230 RX_MSDU_END_16_SA_SW_PEER_ID_OFFSET)), \ 231 RX_MSDU_END_16_SA_SW_PEER_ID_MASK, \ 232 RX_MSDU_END_16_SA_SW_PEER_ID_LSB)) 233 234 #define HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va) \ 235 (uint8_t *)(link_desc_va) + \ 236 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 237 238 #define HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0) \ 239 (uint8_t *)(msdu0) + \ 240 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 241 242 #define HAL_ENT_MPDU_DESC_INFO(ent_ring_desc) \ 243 (uint8_t *)(ent_ring_desc) + \ 244 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 245 246 #define HAL_DST_MPDU_DESC_INFO(dst_ring_desc) \ 247 (uint8_t *)(dst_ring_desc) + \ 248 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 249 250 #define HAL_RX_GET_FC_VALID(rx_mpdu_start) \ 251 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, MPDU_FRAME_CONTROL_VALID) 252 253 #define HAL_RX_GET_TO_DS_FLAG(rx_mpdu_start) \ 254 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, TO_DS) 255 256 #define HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start) \ 257 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, MAC_ADDR_AD1_VALID) 258 259 #define HAL_RX_GET_MAC_ADDR2_VALID(rx_mpdu_start) \ 260 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, MAC_ADDR_AD2_VALID) 261 262 #define HAL_RX_GET_FILTER_CATEGORY(rx_mpdu_start) \ 263 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, RXPCU_MPDU_FILTER_IN_CATEGORY) 264 265 #define HAL_RX_GET_PPDU_ID(rx_mpdu_start) \ 266 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, PHY_PPDU_ID) 267 268 #define HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start) \ 269 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, SW_FRAME_GROUP_ID) 270 271 #define HAL_RX_GET_SW_PEER_ID(rx_mpdu_start) \ 272 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_1, SW_PEER_ID) 273 274 #define HAL_REO_R0_CONFIG(soc, reg_val, reo_params) \ 275 do { \ 276 reg_val &= \ 277 ~(HWIO_REO_R0_GENERAL_ENABLE_FRAGMENT_DEST_RING_BMSK |\ 278 HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK | \ 279 HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK); \ 280 reg_val |= \ 281 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 282 FRAGMENT_DEST_RING, \ 283 (reo_params)->frag_dst_ring) | \ 284 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 285 AGING_LIST_ENABLE, 1) |\ 286 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 287 AGING_FLUSH_ENABLE, 1);\ 288 HAL_REG_WRITE((soc), \ 289 HWIO_REO_R0_GENERAL_ENABLE_ADDR( \ 290 SEQ_WCSS_UMAC_REO_REG_OFFSET), \ 291 (reg_val)); \ 292 (reg_val) = \ 293 HAL_REG_READ((soc), \ 294 HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR( \ 295 SEQ_WCSS_UMAC_REO_REG_OFFSET)); \ 296 (reg_val) &= \ 297 ~(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_0_BMSK); \ 298 (reg_val) |= \ 299 HAL_SM(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0, \ 300 DEST_RING_ALT_MAPPING_0, \ 301 (reo_params)->alt_dst_ind_0); \ 302 HAL_REG_WRITE((soc), \ 303 HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR( \ 304 SEQ_WCSS_UMAC_REO_REG_OFFSET), \ 305 (reg_val)); \ 306 } while (0) 307 308 #define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \ 309 ((struct rx_msdu_desc_info *) \ 310 _OFFSET_TO_BYTE_PTR((msdu_details_ptr), \ 311 UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET)) 312 313 #define HAL_RX_LINK_DESC_MSDU0_PTR(link_desc) \ 314 ((struct rx_msdu_details *) \ 315 _OFFSET_TO_BYTE_PTR((link_desc),\ 316 UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET)) 317 318 #define HAL_RX_MSDU_END_FLOW_IDX_GET(_rx_msdu_end) \ 319 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 320 RX_MSDU_END_14_FLOW_IDX_OFFSET)), \ 321 RX_MSDU_END_14_FLOW_IDX_MASK, \ 322 RX_MSDU_END_14_FLOW_IDX_LSB)) 323 324 #define HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(_rx_msdu_end) \ 325 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 326 RX_MSDU_END_5_FLOW_IDX_INVALID_OFFSET)), \ 327 RX_MSDU_END_5_FLOW_IDX_INVALID_MASK, \ 328 RX_MSDU_END_5_FLOW_IDX_INVALID_LSB)) 329 330 #define HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(_rx_msdu_end) \ 331 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 332 RX_MSDU_END_5_FLOW_IDX_TIMEOUT_OFFSET)), \ 333 RX_MSDU_END_5_FLOW_IDX_TIMEOUT_MASK, \ 334 RX_MSDU_END_5_FLOW_IDX_TIMEOUT_LSB)) 335 336 #define HAL_RX_MSDU_END_FSE_METADATA_GET(_rx_msdu_end) \ 337 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 338 RX_MSDU_END_15_FSE_METADATA_OFFSET)), \ 339 RX_MSDU_END_15_FSE_METADATA_MASK, \ 340 RX_MSDU_END_15_FSE_METADATA_LSB)) 341 342 #define HAL_RX_MSDU_END_CCE_METADATA_GET(_rx_msdu_end) \ 343 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 344 RX_MSDU_END_16_CCE_METADATA_OFFSET)), \ 345 RX_MSDU_END_16_CCE_METADATA_MASK, \ 346 RX_MSDU_END_16_CCE_METADATA_LSB)) 347 348 #define HAL_RX_TLV_GET_TCP_CHKSUM(buf) \ 349 (_HAL_MS( \ 350 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 351 msdu_end_tlv.rx_msdu_end), \ 352 RX_MSDU_END_1_TCP_UDP_CHKSUM_OFFSET)), \ 353 RX_MSDU_END_1_TCP_UDP_CHKSUM_MASK, \ 354 RX_MSDU_END_1_TCP_UDP_CHKSUM_LSB)) 355 356 /* 357 * hal_rx_msdu_start_nss_get_8074v2(): API to get the NSS 358 * Interval from rx_msdu_start 359 * 360 * @buf: pointer to the start of RX PKT TLV header 361 * Return: uint32_t(nss) 362 */ 363 static uint32_t hal_rx_msdu_start_nss_get_8074v2(uint8_t *buf) 364 { 365 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 366 struct rx_msdu_start *msdu_start = 367 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 368 uint8_t mimo_ss_bitmap; 369 370 mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start); 371 372 return qdf_get_hweight8(mimo_ss_bitmap); 373 } 374 375 /** 376 * hal_rx_mon_hw_desc_get_mpdu_status_8074v2(): Retrieve MPDU status 377 * 378 * @ hw_desc_addr: Start address of Rx HW TLVs 379 * @ rs: Status for monitor mode 380 * 381 * Return: void 382 */ 383 static void hal_rx_mon_hw_desc_get_mpdu_status_8074v2(void *hw_desc_addr, 384 struct mon_rx_status *rs) 385 { 386 struct rx_msdu_start *rx_msdu_start; 387 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 388 uint32_t reg_value; 389 const uint32_t sgi_hw_to_cdp[] = { 390 CDP_SGI_0_8_US, 391 CDP_SGI_0_4_US, 392 CDP_SGI_1_6_US, 393 CDP_SGI_3_2_US, 394 }; 395 396 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 397 398 HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs); 399 400 rs->ant_signal_db = HAL_RX_GET(rx_msdu_start, 401 RX_MSDU_START_5, USER_RSSI); 402 rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC); 403 404 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI); 405 rs->sgi = sgi_hw_to_cdp[reg_value]; 406 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE); 407 rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0; 408 /* TODO: rs->beamformed should be set for SU beamforming also */ 409 } 410 411 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 412 static uint32_t hal_get_link_desc_size_8074v2(void) 413 { 414 return LINK_DESC_SIZE; 415 } 416 417 /* 418 * hal_rx_get_tlv_8074v2(): API to get the tlv 419 * 420 * @rx_tlv: TLV data extracted from the rx packet 421 * Return: uint8_t 422 */ 423 static uint8_t hal_rx_get_tlv_8074v2(void *rx_tlv) 424 { 425 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH); 426 } 427 428 #if (!defined(QCA_WIFI_QCA6018)) && (!defined(QCA_WIFI_QCA9574)) 429 #define HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, evm, pilot) \ 430 (ppdu_info)->evm_info.pilot_evm[pilot] = HAL_RX_GET(rx_tlv, \ 431 PHYRX_OTHER_RECEIVE_INFO, \ 432 SU_EVM_DETAILS_##evm##_PILOT_##pilot##_EVM) 433 434 static inline void 435 hal_rx_update_su_evm_info(void *rx_tlv, 436 void *ppdu_info_hdl) 437 { 438 struct hal_rx_ppdu_info *ppdu_info = 439 (struct hal_rx_ppdu_info *)ppdu_info_hdl; 440 441 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 1, 0); 442 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 2, 1); 443 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 3, 2); 444 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 4, 3); 445 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 5, 4); 446 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 6, 5); 447 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 7, 6); 448 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 8, 7); 449 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 9, 8); 450 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 10, 9); 451 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 11, 10); 452 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 12, 11); 453 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 13, 12); 454 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 14, 13); 455 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 15, 14); 456 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 16, 15); 457 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 17, 16); 458 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 18, 17); 459 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 19, 18); 460 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 20, 19); 461 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 21, 20); 462 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 22, 21); 463 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 23, 22); 464 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 24, 23); 465 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 25, 24); 466 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 26, 25); 467 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 27, 26); 468 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 28, 27); 469 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 29, 28); 470 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 30, 29); 471 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 31, 30); 472 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 32, 31); 473 } 474 /** 475 * hal_rx_proc_phyrx_other_receive_info_tlv_8074v2() 476 * -process other receive info TLV 477 * @rx_tlv_hdr: pointer to TLV header 478 * @ppdu_info: pointer to ppdu_info 479 * 480 * Return: None 481 */ 482 static 483 void hal_rx_proc_phyrx_other_receive_info_tlv_8074v2(void *rx_tlv_hdr, 484 void *ppdu_info_hdl) 485 { 486 uint16_t tlv_tag; 487 void *rx_tlv; 488 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 489 490 /* Skip TLV_HDR for OTHER_RECEIVE_INFO and follows the 491 * embedded TLVs inside 492 */ 493 rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 494 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv); 495 496 switch (tlv_tag) { 497 case WIFIPHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_E: 498 499 /* Skip TLV length to get TLV content */ 500 rx_tlv = (uint8_t *)rx_tlv + HAL_RX_TLV32_HDR_SIZE; 501 502 ppdu_info->evm_info.number_of_symbols = HAL_RX_GET(rx_tlv, 503 PHYRX_OTHER_RECEIVE_INFO, 504 SU_EVM_DETAILS_0_NUMBER_OF_SYMBOLS); 505 ppdu_info->evm_info.pilot_count = HAL_RX_GET(rx_tlv, 506 PHYRX_OTHER_RECEIVE_INFO, 507 SU_EVM_DETAILS_0_PILOT_COUNT); 508 ppdu_info->evm_info.nss_count = HAL_RX_GET(rx_tlv, 509 PHYRX_OTHER_RECEIVE_INFO, 510 SU_EVM_DETAILS_0_NSS_COUNT); 511 hal_rx_update_su_evm_info(rx_tlv, ppdu_info_hdl); 512 break; 513 } 514 } 515 #else 516 static inline 517 void hal_rx_proc_phyrx_other_receive_info_tlv_8074v2(void *rx_tlv_hdr, 518 void *ppdu_info_hdl) 519 { 520 } 521 #endif 522 523 #if defined(QCA_WIFI_QCA6018) && defined(WLAN_CFR_ENABLE) && \ 524 defined(WLAN_ENH_CFR_ENABLE) 525 static inline 526 void hal_rx_get_bb_info_8074v2(void *rx_tlv, 527 void *ppdu_info_hdl) 528 { 529 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 530 531 ppdu_info->cfr_info.bb_captured_channel = 532 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_CHANNEL); 533 534 ppdu_info->cfr_info.bb_captured_timeout = 535 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_TIMEOUT); 536 537 ppdu_info->cfr_info.bb_captured_reason = 538 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_REASON); 539 } 540 541 static inline 542 void hal_rx_get_rtt_info_8074v2(void *rx_tlv, 543 void *ppdu_info_hdl) 544 { 545 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 546 547 ppdu_info->cfr_info.rx_location_info_valid = 548 HAL_RX_GET(rx_tlv, PHYRX_PKT_END_13_RX_PKT_END_DETAILS, 549 RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID); 550 551 ppdu_info->cfr_info.rtt_che_buffer_pointer_low32 = 552 HAL_RX_GET(rx_tlv, 553 PHYRX_PKT_END_12_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 554 RTT_CHE_BUFFER_POINTER_LOW32); 555 556 ppdu_info->cfr_info.rtt_che_buffer_pointer_high8 = 557 HAL_RX_GET(rx_tlv, 558 PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 559 RTT_CHE_BUFFER_POINTER_HIGH8); 560 561 ppdu_info->cfr_info.chan_capture_status = 562 HAL_RX_GET(rx_tlv, 563 PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 564 RESERVED_8); 565 566 ppdu_info->cfr_info.rx_start_ts = 567 HAL_RX_GET(rx_tlv, 568 PHYRX_PKT_END_9_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 569 RX_START_TS); 570 571 ppdu_info->cfr_info.rtt_cfo_measurement = (int16_t) 572 HAL_RX_GET(rx_tlv, 573 PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 574 RTT_CFO_MEASUREMENT); 575 576 ppdu_info->cfr_info.agc_gain_info0 = 577 HAL_RX_GET(rx_tlv, 578 PHYRX_PKT_END_1_RX_PKT_END_DETAILS, 579 PHY_TIMESTAMP_1_LOWER_32); 580 581 ppdu_info->cfr_info.agc_gain_info1 = 582 HAL_RX_GET(rx_tlv, 583 PHYRX_PKT_END_2_RX_PKT_END_DETAILS, 584 PHY_TIMESTAMP_1_UPPER_32); 585 586 ppdu_info->cfr_info.agc_gain_info2 = 587 HAL_RX_GET(rx_tlv, 588 PHYRX_PKT_END_3_RX_PKT_END_DETAILS, 589 PHY_TIMESTAMP_2_LOWER_32); 590 591 ppdu_info->cfr_info.agc_gain_info3 = 592 HAL_RX_GET(rx_tlv, 593 PHYRX_PKT_END_4_RX_PKT_END_DETAILS, 594 PHY_TIMESTAMP_2_UPPER_32); 595 596 ppdu_info->cfr_info.mcs_rate = 597 HAL_RX_GET(rx_tlv, 598 PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 599 RTT_MCS_RATE); 600 601 ppdu_info->cfr_info.gi_type = 602 HAL_RX_GET(rx_tlv, 603 PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 604 RTT_GI_TYPE); 605 } 606 #endif 607 608 /** 609 * hal_rx_dump_msdu_start_tlv_8074v2() : dump RX msdu_start TLV in structured 610 * human readable format. 611 * @ msdu_start: pointer the msdu_start TLV in pkt. 612 * @ dbg_level: log level. 613 * 614 * Return: void 615 */ 616 static void hal_rx_dump_msdu_start_tlv_8074v2(void *msdustart, 617 uint8_t dbg_level) 618 { 619 struct rx_msdu_start *msdu_start = (struct rx_msdu_start *)msdustart; 620 621 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 622 "rx_msdu_start tlv - " 623 "rxpcu_mpdu_filter_in_category: %d " 624 "sw_frame_group_id: %d " 625 "phy_ppdu_id: %d " 626 "msdu_length: %d " 627 "ipsec_esp: %d " 628 "l3_offset: %d " 629 "ipsec_ah: %d " 630 "l4_offset: %d " 631 "msdu_number: %d " 632 "decap_format: %d " 633 "ipv4_proto: %d " 634 "ipv6_proto: %d " 635 "tcp_proto: %d " 636 "udp_proto: %d " 637 "ip_frag: %d " 638 "tcp_only_ack: %d " 639 "da_is_bcast_mcast: %d " 640 "ip4_protocol_ip6_next_header: %d " 641 "toeplitz_hash_2_or_4: %d " 642 "flow_id_toeplitz: %d " 643 "user_rssi: %d " 644 "pkt_type: %d " 645 "stbc: %d " 646 "sgi: %d " 647 "rate_mcs: %d " 648 "receive_bandwidth: %d " 649 "reception_type: %d " 650 "ppdu_start_timestamp: %d " 651 "sw_phy_meta_data: %d ", 652 msdu_start->rxpcu_mpdu_filter_in_category, 653 msdu_start->sw_frame_group_id, 654 msdu_start->phy_ppdu_id, 655 msdu_start->msdu_length, 656 msdu_start->ipsec_esp, 657 msdu_start->l3_offset, 658 msdu_start->ipsec_ah, 659 msdu_start->l4_offset, 660 msdu_start->msdu_number, 661 msdu_start->decap_format, 662 msdu_start->ipv4_proto, 663 msdu_start->ipv6_proto, 664 msdu_start->tcp_proto, 665 msdu_start->udp_proto, 666 msdu_start->ip_frag, 667 msdu_start->tcp_only_ack, 668 msdu_start->da_is_bcast_mcast, 669 msdu_start->ip4_protocol_ip6_next_header, 670 msdu_start->toeplitz_hash_2_or_4, 671 msdu_start->flow_id_toeplitz, 672 msdu_start->user_rssi, 673 msdu_start->pkt_type, 674 msdu_start->stbc, 675 msdu_start->sgi, 676 msdu_start->rate_mcs, 677 msdu_start->receive_bandwidth, 678 msdu_start->reception_type, 679 msdu_start->ppdu_start_timestamp, 680 msdu_start->sw_phy_meta_data); 681 } 682 683 /** 684 * hal_rx_dump_msdu_end_tlv_8074v2: dump RX msdu_end TLV in structured 685 * human readable format. 686 * @ msdu_end: pointer the msdu_end TLV in pkt. 687 * @ dbg_level: log level. 688 * 689 * Return: void 690 */ 691 static void hal_rx_dump_msdu_end_tlv_8074v2(void *msduend, 692 uint8_t dbg_level) 693 { 694 struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend; 695 696 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 697 "rx_msdu_end tlv - " 698 "rxpcu_mpdu_filter_in_category: %d " 699 "sw_frame_group_id: %d " 700 "phy_ppdu_id: %d " 701 "ip_hdr_chksum: %d " 702 "tcp_udp_chksum: %d " 703 "key_id_octet: %d " 704 "cce_super_rule: %d " 705 "cce_classify_not_done_truncat: %d " 706 "cce_classify_not_done_cce_dis: %d " 707 "ext_wapi_pn_63_48: %d " 708 "ext_wapi_pn_95_64: %d " 709 "ext_wapi_pn_127_96: %d " 710 "reported_mpdu_length: %d " 711 "first_msdu: %d " 712 "last_msdu: %d " 713 "sa_idx_timeout: %d " 714 "da_idx_timeout: %d " 715 "msdu_limit_error: %d " 716 "flow_idx_timeout: %d " 717 "flow_idx_invalid: %d " 718 "wifi_parser_error: %d " 719 "amsdu_parser_error: %d " 720 "sa_is_valid: %d " 721 "da_is_valid: %d " 722 "da_is_mcbc: %d " 723 "l3_header_padding: %d " 724 "ipv6_options_crc: %d " 725 "tcp_seq_number: %d " 726 "tcp_ack_number: %d " 727 "tcp_flag: %d " 728 "lro_eligible: %d " 729 "window_size: %d " 730 "da_offset: %d " 731 "sa_offset: %d " 732 "da_offset_valid: %d " 733 "sa_offset_valid: %d " 734 "rule_indication_31_0: %d " 735 "rule_indication_63_32: %d " 736 "sa_idx: %d " 737 "msdu_drop: %d " 738 "reo_destination_indication: %d " 739 "flow_idx: %d " 740 "fse_metadata: %d " 741 "cce_metadata: %d " 742 "sa_sw_peer_id: %d ", 743 msdu_end->rxpcu_mpdu_filter_in_category, 744 msdu_end->sw_frame_group_id, 745 msdu_end->phy_ppdu_id, 746 msdu_end->ip_hdr_chksum, 747 msdu_end->tcp_udp_chksum, 748 msdu_end->key_id_octet, 749 msdu_end->cce_super_rule, 750 msdu_end->cce_classify_not_done_truncate, 751 msdu_end->cce_classify_not_done_cce_dis, 752 msdu_end->ext_wapi_pn_63_48, 753 msdu_end->ext_wapi_pn_95_64, 754 msdu_end->ext_wapi_pn_127_96, 755 msdu_end->reported_mpdu_length, 756 msdu_end->first_msdu, 757 msdu_end->last_msdu, 758 msdu_end->sa_idx_timeout, 759 msdu_end->da_idx_timeout, 760 msdu_end->msdu_limit_error, 761 msdu_end->flow_idx_timeout, 762 msdu_end->flow_idx_invalid, 763 msdu_end->wifi_parser_error, 764 msdu_end->amsdu_parser_error, 765 msdu_end->sa_is_valid, 766 msdu_end->da_is_valid, 767 msdu_end->da_is_mcbc, 768 msdu_end->l3_header_padding, 769 msdu_end->ipv6_options_crc, 770 msdu_end->tcp_seq_number, 771 msdu_end->tcp_ack_number, 772 msdu_end->tcp_flag, 773 msdu_end->lro_eligible, 774 msdu_end->window_size, 775 msdu_end->da_offset, 776 msdu_end->sa_offset, 777 msdu_end->da_offset_valid, 778 msdu_end->sa_offset_valid, 779 msdu_end->rule_indication_31_0, 780 msdu_end->rule_indication_63_32, 781 msdu_end->sa_idx, 782 msdu_end->msdu_drop, 783 msdu_end->reo_destination_indication, 784 msdu_end->flow_idx, 785 msdu_end->fse_metadata, 786 msdu_end->cce_metadata, 787 msdu_end->sa_sw_peer_id); 788 } 789 790 791 /* 792 * Get tid from RX_MPDU_START 793 */ 794 #define HAL_RX_MPDU_INFO_TID_GET(_rx_mpdu_info) \ 795 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 796 RX_MPDU_INFO_3_TID_OFFSET)), \ 797 RX_MPDU_INFO_3_TID_MASK, \ 798 RX_MPDU_INFO_3_TID_LSB)) 799 800 static uint32_t hal_rx_mpdu_start_tid_get_8074v2(uint8_t *buf) 801 { 802 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 803 struct rx_mpdu_start *mpdu_start = 804 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 805 uint32_t tid; 806 807 tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details); 808 809 return tid; 810 } 811 812 #define HAL_RX_MSDU_START_RECEPTION_TYPE_GET(_rx_msdu_start) \ 813 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \ 814 RX_MSDU_START_5_RECEPTION_TYPE_OFFSET)), \ 815 RX_MSDU_START_5_RECEPTION_TYPE_MASK, \ 816 RX_MSDU_START_5_RECEPTION_TYPE_LSB)) 817 818 /* 819 * hal_rx_msdu_start_reception_type_get(): API to get the reception type 820 * Interval from rx_msdu_start 821 * 822 * @buf: pointer to the start of RX PKT TLV header 823 * Return: uint32_t(reception_type) 824 */ 825 static uint32_t hal_rx_msdu_start_reception_type_get_8074v2(uint8_t *buf) 826 { 827 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 828 struct rx_msdu_start *msdu_start = 829 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 830 uint32_t reception_type; 831 832 reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start); 833 834 return reception_type; 835 } 836 837 /* RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_OFFSET */ 838 #define HAL_RX_MSDU_END_DA_IDX_GET(_rx_msdu_end) \ 839 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 840 RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_OFFSET)), \ 841 RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_MASK, \ 842 RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_LSB)) 843 /** 844 * hal_rx_msdu_end_da_idx_get_8074v2: API to get da_idx 845 * from rx_msdu_end TLV 846 * 847 * @ buf: pointer to the start of RX PKT TLV headers 848 * Return: da index 849 */ 850 static uint16_t hal_rx_msdu_end_da_idx_get_8074v2(uint8_t *buf) 851 { 852 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 853 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 854 uint16_t da_idx; 855 856 da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 857 858 return da_idx; 859 } 860