1 /* 2 * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #include "hal_hw_headers.h" 19 #include "hal_internal.h" 20 #include "cdp_txrx_mon_struct.h" 21 #include "qdf_trace.h" 22 #include "hal_rx.h" 23 #include "hal_tx.h" 24 #include "dp_types.h" 25 #include "hal_api_mon.h" 26 #ifndef QCA_WIFI_QCA6018 27 #include "phyrx_other_receive_info_su_evm_details.h" 28 #endif 29 30 #define HAL_RX_MPDU_GET_SEQUENCE_NUMBER(_rx_mpdu_info) \ 31 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 32 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_OFFSET)), \ 33 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_MASK, \ 34 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_LSB)) 35 36 #define HAL_RX_MSDU_END_DA_IS_MCBC_GET(_rx_msdu_end) \ 37 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 38 RX_MSDU_END_5_DA_IS_MCBC_OFFSET)), \ 39 RX_MSDU_END_5_DA_IS_MCBC_MASK, \ 40 RX_MSDU_END_5_DA_IS_MCBC_LSB)) 41 42 #define HAL_RX_MSDU_END_SA_IS_VALID_GET(_rx_msdu_end) \ 43 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 44 RX_MSDU_END_5_SA_IS_VALID_OFFSET)), \ 45 RX_MSDU_END_5_SA_IS_VALID_MASK, \ 46 RX_MSDU_END_5_SA_IS_VALID_LSB)) 47 48 #define HAL_RX_MSDU_END_SA_IDX_GET(_rx_msdu_end) \ 49 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 50 RX_MSDU_END_13_SA_IDX_OFFSET)), \ 51 RX_MSDU_END_13_SA_IDX_MASK, \ 52 RX_MSDU_END_13_SA_IDX_LSB)) 53 54 #define HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(_rx_msdu_end) \ 55 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 56 RX_MSDU_END_5_L3_HEADER_PADDING_OFFSET)), \ 57 RX_MSDU_END_5_L3_HEADER_PADDING_MASK, \ 58 RX_MSDU_END_5_L3_HEADER_PADDING_LSB)) 59 60 #define HAL_RX_MPDU_ENCRYPTION_INFO_VALID(_rx_mpdu_info) \ 61 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 62 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_OFFSET)), \ 63 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_MASK, \ 64 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_LSB)) 65 66 #define HAL_RX_MPDU_PN_31_0_GET(_rx_mpdu_info) \ 67 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 68 RX_MPDU_INFO_4_PN_31_0_OFFSET)), \ 69 RX_MPDU_INFO_4_PN_31_0_MASK, \ 70 RX_MPDU_INFO_4_PN_31_0_LSB)) 71 72 #define HAL_RX_MPDU_PN_63_32_GET(_rx_mpdu_info) \ 73 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 74 RX_MPDU_INFO_5_PN_63_32_OFFSET)), \ 75 RX_MPDU_INFO_5_PN_63_32_MASK, \ 76 RX_MPDU_INFO_5_PN_63_32_LSB)) 77 78 #define HAL_RX_MPDU_PN_95_64_GET(_rx_mpdu_info) \ 79 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 80 RX_MPDU_INFO_6_PN_95_64_OFFSET)), \ 81 RX_MPDU_INFO_6_PN_95_64_MASK, \ 82 RX_MPDU_INFO_6_PN_95_64_LSB)) 83 84 #define HAL_RX_MPDU_PN_127_96_GET(_rx_mpdu_info) \ 85 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 86 RX_MPDU_INFO_7_PN_127_96_OFFSET)), \ 87 RX_MPDU_INFO_7_PN_127_96_MASK, \ 88 RX_MPDU_INFO_7_PN_127_96_LSB)) 89 90 #define HAL_RX_MSDU_END_FIRST_MSDU_GET(_rx_msdu_end) \ 91 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 92 RX_MSDU_END_5_FIRST_MSDU_OFFSET)), \ 93 RX_MSDU_END_5_FIRST_MSDU_MASK, \ 94 RX_MSDU_END_5_FIRST_MSDU_LSB)) 95 96 #define HAL_RX_MSDU_START_MIMO_SS_BITMAP(_rx_msdu_start)\ 97 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ 98 RX_MSDU_START_5_MIMO_SS_BITMAP_OFFSET)), \ 99 RX_MSDU_START_5_MIMO_SS_BITMAP_MASK, \ 100 RX_MSDU_START_5_MIMO_SS_BITMAP_LSB)) 101 102 #define HAL_RX_MSDU_END_DA_IS_VALID_GET(_rx_msdu_end) \ 103 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 104 RX_MSDU_END_5_DA_IS_VALID_OFFSET)), \ 105 RX_MSDU_END_5_DA_IS_VALID_MASK, \ 106 RX_MSDU_END_5_DA_IS_VALID_LSB)) 107 108 #define HAL_RX_MSDU_END_LAST_MSDU_GET(_rx_msdu_end) \ 109 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 110 RX_MSDU_END_5_LAST_MSDU_OFFSET)), \ 111 RX_MSDU_END_5_LAST_MSDU_MASK, \ 112 RX_MSDU_END_5_LAST_MSDU_LSB)) 113 114 #define HAL_RX_MPDU_GET_MAC_AD4_VALID(_rx_mpdu_info) \ 115 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 116 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_OFFSET)), \ 117 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_MASK, \ 118 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_LSB)) 119 120 #define HAL_RX_MPDU_INFO_SW_PEER_ID_GET(_rx_mpdu_info) \ 121 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 122 RX_MPDU_INFO_1_SW_PEER_ID_OFFSET)), \ 123 RX_MPDU_INFO_1_SW_PEER_ID_MASK, \ 124 RX_MPDU_INFO_1_SW_PEER_ID_LSB)) 125 126 #define HAL_RX_MPDU_GET_TODS(_rx_mpdu_info) \ 127 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 128 RX_MPDU_INFO_2_TO_DS_OFFSET)), \ 129 RX_MPDU_INFO_2_TO_DS_MASK, \ 130 RX_MPDU_INFO_2_TO_DS_LSB)) 131 132 #define HAL_RX_MPDU_GET_FROMDS(_rx_mpdu_info) \ 133 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 134 RX_MPDU_INFO_2_FR_DS_OFFSET)), \ 135 RX_MPDU_INFO_2_FR_DS_MASK, \ 136 RX_MPDU_INFO_2_FR_DS_LSB)) 137 138 #define HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(_rx_mpdu_info) \ 139 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 140 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_OFFSET)), \ 141 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_MASK, \ 142 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_LSB)) 143 144 #define HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(_rx_mpdu_info) \ 145 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 146 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_OFFSET)), \ 147 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_MASK, \ 148 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_LSB)) 149 150 #define HAL_RX_MPDU_AD1_31_0_GET(_rx_mpdu_info) \ 151 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 152 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET)), \ 153 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK, \ 154 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB)) 155 156 #define HAL_RX_MPDU_AD1_47_32_GET(_rx_mpdu_info) \ 157 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 158 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET)), \ 159 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK, \ 160 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB)) 161 162 #define HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(_rx_mpdu_info) \ 163 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 164 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_OFFSET)), \ 165 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_MASK, \ 166 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_LSB)) 167 168 #define HAL_RX_MPDU_AD2_15_0_GET(_rx_mpdu_info) \ 169 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 170 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET)), \ 171 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK, \ 172 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB)) 173 174 #define HAL_RX_MPDU_AD2_47_16_GET(_rx_mpdu_info) \ 175 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 176 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET)), \ 177 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK, \ 178 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB)) 179 180 #define HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(_rx_mpdu_info) \ 181 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 182 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_OFFSET)), \ 183 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_MASK, \ 184 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_LSB)) 185 186 #define HAL_RX_MPDU_AD3_31_0_GET(_rx_mpdu_info) \ 187 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 188 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_OFFSET)), \ 189 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_MASK, \ 190 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_LSB)) 191 192 #define HAL_RX_MPDU_AD3_47_32_GET(_rx_mpdu_info) \ 193 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 194 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_OFFSET)), \ 195 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_MASK, \ 196 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_LSB)) 197 198 #define HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(_rx_mpdu_info) \ 199 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 200 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_OFFSET)), \ 201 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_MASK, \ 202 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_LSB)) 203 204 #define HAL_RX_MPDU_AD4_31_0_GET(_rx_mpdu_info) \ 205 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 206 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET)), \ 207 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK, \ 208 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB)) 209 210 #define HAL_RX_MPDU_AD4_47_32_GET(_rx_mpdu_info) \ 211 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 212 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET)), \ 213 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK, \ 214 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB)) 215 216 #define HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(_rx_mpdu_info) \ 217 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 218 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_OFFSET)), \ 219 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_MASK, \ 220 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_LSB)) 221 222 #define HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(_rx_mpdu_info) \ 223 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 224 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)), \ 225 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK, \ 226 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB)) 227 228 #define HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(_rx_msdu_end) \ 229 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 230 RX_MSDU_END_16_SA_SW_PEER_ID_OFFSET)), \ 231 RX_MSDU_END_16_SA_SW_PEER_ID_MASK, \ 232 RX_MSDU_END_16_SA_SW_PEER_ID_LSB)) 233 234 #define HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va) \ 235 (uint8_t *)(link_desc_va) + \ 236 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 237 238 #define HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0) \ 239 (uint8_t *)(msdu0) + \ 240 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 241 242 #define HAL_ENT_MPDU_DESC_INFO(ent_ring_desc) \ 243 (uint8_t *)(ent_ring_desc) + \ 244 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 245 246 #define HAL_DST_MPDU_DESC_INFO(dst_ring_desc) \ 247 (uint8_t *)(dst_ring_desc) + \ 248 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 249 250 #define HAL_RX_GET_FC_VALID(rx_mpdu_start) \ 251 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, MPDU_FRAME_CONTROL_VALID) 252 253 #define HAL_RX_GET_TO_DS_FLAG(rx_mpdu_start) \ 254 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, TO_DS) 255 256 #define HAL_RX_GET_MAC_ADDR2_VALID(rx_mpdu_start) \ 257 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, MAC_ADDR_AD2_VALID) 258 259 #define HAL_RX_GET_FILTER_CATEGORY(rx_mpdu_start) \ 260 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, RXPCU_MPDU_FILTER_IN_CATEGORY) 261 262 #define HAL_RX_GET_PPDU_ID(rx_mpdu_start) \ 263 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, PHY_PPDU_ID) 264 265 #define HAL_REO_R0_CONFIG(soc, reg_val, reo_params) \ 266 do { \ 267 reg_val &= \ 268 ~(HWIO_REO_R0_GENERAL_ENABLE_FRAGMENT_DEST_RING_BMSK |\ 269 HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK | \ 270 HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK); \ 271 reg_val |= \ 272 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 273 FRAGMENT_DEST_RING, \ 274 (reo_params)->frag_dst_ring) | \ 275 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 276 AGING_LIST_ENABLE, 1) |\ 277 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 278 AGING_FLUSH_ENABLE, 1);\ 279 HAL_REG_WRITE((soc), \ 280 HWIO_REO_R0_GENERAL_ENABLE_ADDR( \ 281 SEQ_WCSS_UMAC_REO_REG_OFFSET), \ 282 (reg_val)); \ 283 } while (0) 284 285 #define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \ 286 ((struct rx_msdu_desc_info *) \ 287 _OFFSET_TO_BYTE_PTR((msdu_details_ptr), \ 288 UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET)) 289 290 #define HAL_RX_LINK_DESC_MSDU0_PTR(link_desc) \ 291 ((struct rx_msdu_details *) \ 292 _OFFSET_TO_BYTE_PTR((link_desc),\ 293 UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET)) 294 295 #define HAL_RX_MSDU_END_FLOW_IDX_GET(_rx_msdu_end) \ 296 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 297 RX_MSDU_END_14_FLOW_IDX_OFFSET)), \ 298 RX_MSDU_END_14_FLOW_IDX_MASK, \ 299 RX_MSDU_END_14_FLOW_IDX_LSB)) 300 301 #define HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(_rx_msdu_end) \ 302 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 303 RX_MSDU_END_5_FLOW_IDX_INVALID_OFFSET)), \ 304 RX_MSDU_END_5_FLOW_IDX_INVALID_MASK, \ 305 RX_MSDU_END_5_FLOW_IDX_INVALID_LSB)) 306 307 #define HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(_rx_msdu_end) \ 308 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 309 RX_MSDU_END_5_FLOW_IDX_TIMEOUT_OFFSET)), \ 310 RX_MSDU_END_5_FLOW_IDX_TIMEOUT_MASK, \ 311 RX_MSDU_END_5_FLOW_IDX_TIMEOUT_LSB)) 312 313 #define HAL_RX_MSDU_END_FSE_METADATA_GET(_rx_msdu_end) \ 314 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 315 RX_MSDU_END_15_FSE_METADATA_OFFSET)), \ 316 RX_MSDU_END_15_FSE_METADATA_MASK, \ 317 RX_MSDU_END_15_FSE_METADATA_LSB)) 318 319 #define HAL_RX_MSDU_END_CCE_METADATA_GET(_rx_msdu_end) \ 320 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 321 RX_MSDU_END_16_CCE_METADATA_OFFSET)), \ 322 RX_MSDU_END_16_CCE_METADATA_MASK, \ 323 RX_MSDU_END_16_CCE_METADATA_LSB)) 324 325 #define HAL_RX_TLV_GET_TCP_CHKSUM(buf) \ 326 (_HAL_MS( \ 327 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 328 msdu_end_tlv.rx_msdu_end), \ 329 RX_MSDU_END_1_TCP_UDP_CHKSUM_OFFSET)), \ 330 RX_MSDU_END_1_TCP_UDP_CHKSUM_MASK, \ 331 RX_MSDU_END_1_TCP_UDP_CHKSUM_LSB)) 332 333 /* 334 * hal_rx_msdu_start_nss_get_8074v2(): API to get the NSS 335 * Interval from rx_msdu_start 336 * 337 * @buf: pointer to the start of RX PKT TLV header 338 * Return: uint32_t(nss) 339 */ 340 static uint32_t hal_rx_msdu_start_nss_get_8074v2(uint8_t *buf) 341 { 342 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 343 struct rx_msdu_start *msdu_start = 344 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 345 uint8_t mimo_ss_bitmap; 346 347 mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start); 348 349 return qdf_get_hweight8(mimo_ss_bitmap); 350 } 351 352 /** 353 * hal_rx_mon_hw_desc_get_mpdu_status_8074v2(): Retrieve MPDU status 354 * 355 * @ hw_desc_addr: Start address of Rx HW TLVs 356 * @ rs: Status for monitor mode 357 * 358 * Return: void 359 */ 360 static void hal_rx_mon_hw_desc_get_mpdu_status_8074v2(void *hw_desc_addr, 361 struct mon_rx_status *rs) 362 { 363 struct rx_msdu_start *rx_msdu_start; 364 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 365 uint32_t reg_value; 366 const uint32_t sgi_hw_to_cdp[] = { 367 CDP_SGI_0_8_US, 368 CDP_SGI_0_4_US, 369 CDP_SGI_1_6_US, 370 CDP_SGI_3_2_US, 371 }; 372 373 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 374 375 HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs); 376 377 rs->ant_signal_db = HAL_RX_GET(rx_msdu_start, 378 RX_MSDU_START_5, USER_RSSI); 379 rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC); 380 381 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI); 382 rs->sgi = sgi_hw_to_cdp[reg_value]; 383 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE); 384 rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0; 385 /* TODO: rs->beamformed should be set for SU beamforming also */ 386 } 387 388 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 389 static uint32_t hal_get_link_desc_size_8074v2(void) 390 { 391 return LINK_DESC_SIZE; 392 } 393 394 /* 395 * hal_rx_get_tlv_8074v2(): API to get the tlv 396 * 397 * @rx_tlv: TLV data extracted from the rx packet 398 * Return: uint8_t 399 */ 400 static uint8_t hal_rx_get_tlv_8074v2(void *rx_tlv) 401 { 402 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH); 403 } 404 405 #ifndef QCA_WIFI_QCA6018 406 #define HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, evm, pilot) \ 407 (ppdu_info)->evm_info.pilot_evm[pilot] = HAL_RX_GET(rx_tlv, \ 408 PHYRX_OTHER_RECEIVE_INFO, \ 409 SU_EVM_DETAILS_##evm##_PILOT_##pilot##_EVM) 410 411 static inline void 412 hal_rx_update_su_evm_info(void *rx_tlv, 413 void *ppdu_info_hdl) 414 { 415 struct hal_rx_ppdu_info *ppdu_info = 416 (struct hal_rx_ppdu_info *)ppdu_info_hdl; 417 418 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 1, 0); 419 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 2, 1); 420 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 3, 2); 421 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 4, 3); 422 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 5, 4); 423 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 6, 5); 424 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 7, 6); 425 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 8, 7); 426 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 9, 8); 427 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 10, 9); 428 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 11, 10); 429 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 12, 11); 430 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 13, 12); 431 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 14, 13); 432 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 15, 14); 433 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 16, 15); 434 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 17, 16); 435 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 18, 17); 436 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 19, 18); 437 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 20, 19); 438 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 21, 20); 439 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 22, 21); 440 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 23, 22); 441 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 24, 23); 442 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 25, 24); 443 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 26, 25); 444 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 27, 26); 445 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 28, 27); 446 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 29, 28); 447 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 30, 29); 448 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 31, 30); 449 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 32, 31); 450 } 451 /** 452 * hal_rx_proc_phyrx_other_receive_info_tlv_8074v2() 453 * -process other receive info TLV 454 * @rx_tlv_hdr: pointer to TLV header 455 * @ppdu_info: pointer to ppdu_info 456 * 457 * Return: None 458 */ 459 static 460 void hal_rx_proc_phyrx_other_receive_info_tlv_8074v2(void *rx_tlv_hdr, 461 void *ppdu_info_hdl) 462 { 463 uint16_t tlv_tag; 464 void *rx_tlv; 465 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 466 467 /* Skip TLV_HDR for OTHER_RECEIVE_INFO and follows the 468 * embedded TLVs inside 469 */ 470 rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 471 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv); 472 473 switch (tlv_tag) { 474 case WIFIPHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_E: 475 476 /* Skip TLV length to get TLV content */ 477 rx_tlv = (uint8_t *)rx_tlv + HAL_RX_TLV32_HDR_SIZE; 478 479 ppdu_info->evm_info.number_of_symbols = HAL_RX_GET(rx_tlv, 480 PHYRX_OTHER_RECEIVE_INFO, 481 SU_EVM_DETAILS_0_NUMBER_OF_SYMBOLS); 482 ppdu_info->evm_info.pilot_count = HAL_RX_GET(rx_tlv, 483 PHYRX_OTHER_RECEIVE_INFO, 484 SU_EVM_DETAILS_0_PILOT_COUNT); 485 ppdu_info->evm_info.nss_count = HAL_RX_GET(rx_tlv, 486 PHYRX_OTHER_RECEIVE_INFO, 487 SU_EVM_DETAILS_0_NSS_COUNT); 488 hal_rx_update_su_evm_info(rx_tlv, ppdu_info_hdl); 489 break; 490 } 491 } 492 #else 493 static inline 494 void hal_rx_proc_phyrx_other_receive_info_tlv_8074v2(void *rx_tlv_hdr, 495 void *ppdu_info_hdl) 496 { 497 } 498 #endif 499 500 /** 501 * hal_rx_dump_msdu_start_tlv_8074v2() : dump RX msdu_start TLV in structured 502 * human readable format. 503 * @ msdu_start: pointer the msdu_start TLV in pkt. 504 * @ dbg_level: log level. 505 * 506 * Return: void 507 */ 508 static void hal_rx_dump_msdu_start_tlv_8074v2(void *msdustart, 509 uint8_t dbg_level) 510 { 511 struct rx_msdu_start *msdu_start = (struct rx_msdu_start *)msdustart; 512 513 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 514 "rx_msdu_start tlv - " 515 "rxpcu_mpdu_filter_in_category: %d " 516 "sw_frame_group_id: %d " 517 "phy_ppdu_id: %d " 518 "msdu_length: %d " 519 "ipsec_esp: %d " 520 "l3_offset: %d " 521 "ipsec_ah: %d " 522 "l4_offset: %d " 523 "msdu_number: %d " 524 "decap_format: %d " 525 "ipv4_proto: %d " 526 "ipv6_proto: %d " 527 "tcp_proto: %d " 528 "udp_proto: %d " 529 "ip_frag: %d " 530 "tcp_only_ack: %d " 531 "da_is_bcast_mcast: %d " 532 "ip4_protocol_ip6_next_header: %d " 533 "toeplitz_hash_2_or_4: %d " 534 "flow_id_toeplitz: %d " 535 "user_rssi: %d " 536 "pkt_type: %d " 537 "stbc: %d " 538 "sgi: %d " 539 "rate_mcs: %d " 540 "receive_bandwidth: %d " 541 "reception_type: %d " 542 "ppdu_start_timestamp: %d " 543 "sw_phy_meta_data: %d ", 544 msdu_start->rxpcu_mpdu_filter_in_category, 545 msdu_start->sw_frame_group_id, 546 msdu_start->phy_ppdu_id, 547 msdu_start->msdu_length, 548 msdu_start->ipsec_esp, 549 msdu_start->l3_offset, 550 msdu_start->ipsec_ah, 551 msdu_start->l4_offset, 552 msdu_start->msdu_number, 553 msdu_start->decap_format, 554 msdu_start->ipv4_proto, 555 msdu_start->ipv6_proto, 556 msdu_start->tcp_proto, 557 msdu_start->udp_proto, 558 msdu_start->ip_frag, 559 msdu_start->tcp_only_ack, 560 msdu_start->da_is_bcast_mcast, 561 msdu_start->ip4_protocol_ip6_next_header, 562 msdu_start->toeplitz_hash_2_or_4, 563 msdu_start->flow_id_toeplitz, 564 msdu_start->user_rssi, 565 msdu_start->pkt_type, 566 msdu_start->stbc, 567 msdu_start->sgi, 568 msdu_start->rate_mcs, 569 msdu_start->receive_bandwidth, 570 msdu_start->reception_type, 571 msdu_start->ppdu_start_timestamp, 572 msdu_start->sw_phy_meta_data); 573 } 574 575 /** 576 * hal_rx_dump_msdu_end_tlv_8074v2: dump RX msdu_end TLV in structured 577 * human readable format. 578 * @ msdu_end: pointer the msdu_end TLV in pkt. 579 * @ dbg_level: log level. 580 * 581 * Return: void 582 */ 583 static void hal_rx_dump_msdu_end_tlv_8074v2(void *msduend, 584 uint8_t dbg_level) 585 { 586 struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend; 587 588 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 589 "rx_msdu_end tlv - " 590 "rxpcu_mpdu_filter_in_category: %d " 591 "sw_frame_group_id: %d " 592 "phy_ppdu_id: %d " 593 "ip_hdr_chksum: %d " 594 "tcp_udp_chksum: %d " 595 "key_id_octet: %d " 596 "cce_super_rule: %d " 597 "cce_classify_not_done_truncat: %d " 598 "cce_classify_not_done_cce_dis: %d " 599 "ext_wapi_pn_63_48: %d " 600 "ext_wapi_pn_95_64: %d " 601 "ext_wapi_pn_127_96: %d " 602 "reported_mpdu_length: %d " 603 "first_msdu: %d " 604 "last_msdu: %d " 605 "sa_idx_timeout: %d " 606 "da_idx_timeout: %d " 607 "msdu_limit_error: %d " 608 "flow_idx_timeout: %d " 609 "flow_idx_invalid: %d " 610 "wifi_parser_error: %d " 611 "amsdu_parser_error: %d " 612 "sa_is_valid: %d " 613 "da_is_valid: %d " 614 "da_is_mcbc: %d " 615 "l3_header_padding: %d " 616 "ipv6_options_crc: %d " 617 "tcp_seq_number: %d " 618 "tcp_ack_number: %d " 619 "tcp_flag: %d " 620 "lro_eligible: %d " 621 "window_size: %d " 622 "da_offset: %d " 623 "sa_offset: %d " 624 "da_offset_valid: %d " 625 "sa_offset_valid: %d " 626 "rule_indication_31_0: %d " 627 "rule_indication_63_32: %d " 628 "sa_idx: %d " 629 "msdu_drop: %d " 630 "reo_destination_indication: %d " 631 "flow_idx: %d " 632 "fse_metadata: %d " 633 "cce_metadata: %d " 634 "sa_sw_peer_id: %d ", 635 msdu_end->rxpcu_mpdu_filter_in_category, 636 msdu_end->sw_frame_group_id, 637 msdu_end->phy_ppdu_id, 638 msdu_end->ip_hdr_chksum, 639 msdu_end->tcp_udp_chksum, 640 msdu_end->key_id_octet, 641 msdu_end->cce_super_rule, 642 msdu_end->cce_classify_not_done_truncate, 643 msdu_end->cce_classify_not_done_cce_dis, 644 msdu_end->ext_wapi_pn_63_48, 645 msdu_end->ext_wapi_pn_95_64, 646 msdu_end->ext_wapi_pn_127_96, 647 msdu_end->reported_mpdu_length, 648 msdu_end->first_msdu, 649 msdu_end->last_msdu, 650 msdu_end->sa_idx_timeout, 651 msdu_end->da_idx_timeout, 652 msdu_end->msdu_limit_error, 653 msdu_end->flow_idx_timeout, 654 msdu_end->flow_idx_invalid, 655 msdu_end->wifi_parser_error, 656 msdu_end->amsdu_parser_error, 657 msdu_end->sa_is_valid, 658 msdu_end->da_is_valid, 659 msdu_end->da_is_mcbc, 660 msdu_end->l3_header_padding, 661 msdu_end->ipv6_options_crc, 662 msdu_end->tcp_seq_number, 663 msdu_end->tcp_ack_number, 664 msdu_end->tcp_flag, 665 msdu_end->lro_eligible, 666 msdu_end->window_size, 667 msdu_end->da_offset, 668 msdu_end->sa_offset, 669 msdu_end->da_offset_valid, 670 msdu_end->sa_offset_valid, 671 msdu_end->rule_indication_31_0, 672 msdu_end->rule_indication_63_32, 673 msdu_end->sa_idx, 674 msdu_end->msdu_drop, 675 msdu_end->reo_destination_indication, 676 msdu_end->flow_idx, 677 msdu_end->fse_metadata, 678 msdu_end->cce_metadata, 679 msdu_end->sa_sw_peer_id); 680 } 681 682 683 /* 684 * Get tid from RX_MPDU_START 685 */ 686 #define HAL_RX_MPDU_INFO_TID_GET(_rx_mpdu_info) \ 687 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 688 RX_MPDU_INFO_3_TID_OFFSET)), \ 689 RX_MPDU_INFO_3_TID_MASK, \ 690 RX_MPDU_INFO_3_TID_LSB)) 691 692 static uint32_t hal_rx_mpdu_start_tid_get_8074v2(uint8_t *buf) 693 { 694 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 695 struct rx_mpdu_start *mpdu_start = 696 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 697 uint32_t tid; 698 699 tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details); 700 701 return tid; 702 } 703 704 #define HAL_RX_MSDU_START_RECEPTION_TYPE_GET(_rx_msdu_start) \ 705 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \ 706 RX_MSDU_START_5_RECEPTION_TYPE_OFFSET)), \ 707 RX_MSDU_START_5_RECEPTION_TYPE_MASK, \ 708 RX_MSDU_START_5_RECEPTION_TYPE_LSB)) 709 710 /* 711 * hal_rx_msdu_start_reception_type_get(): API to get the reception type 712 * Interval from rx_msdu_start 713 * 714 * @buf: pointer to the start of RX PKT TLV header 715 * Return: uint32_t(reception_type) 716 */ 717 static uint32_t hal_rx_msdu_start_reception_type_get_8074v2(uint8_t *buf) 718 { 719 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 720 struct rx_msdu_start *msdu_start = 721 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 722 uint32_t reception_type; 723 724 reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start); 725 726 return reception_type; 727 } 728 729 /* RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_OFFSET */ 730 #define HAL_RX_MSDU_END_DA_IDX_GET(_rx_msdu_end) \ 731 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 732 RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_OFFSET)), \ 733 RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_MASK, \ 734 RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_LSB)) 735 /** 736 * hal_rx_msdu_end_da_idx_get_8074v2: API to get da_idx 737 * from rx_msdu_end TLV 738 * 739 * @ buf: pointer to the start of RX PKT TLV headers 740 * Return: da index 741 */ 742 static uint16_t hal_rx_msdu_end_da_idx_get_8074v2(uint8_t *buf) 743 { 744 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 745 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 746 uint16_t da_idx; 747 748 da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 749 750 return da_idx; 751 } 752