1 /* 2 * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #include "hal_hw_headers.h" 19 #include "hal_internal.h" 20 #include "hal_api.h" 21 #include "target_type.h" 22 #include "wcss_version.h" 23 #include "qdf_module.h" 24 25 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 26 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET 27 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 28 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK 29 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 30 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB 31 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 32 PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 33 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 34 PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 35 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 36 PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 37 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 38 PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 39 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 40 PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 41 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 42 PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 43 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 44 PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 45 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 46 PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 47 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 48 PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 49 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 50 PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 51 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 52 PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 53 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 54 RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 55 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 56 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 57 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 58 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 59 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 60 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 61 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 62 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 63 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER \ 64 STATUS_HEADER_REO_STATUS_NUMBER 65 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 66 STATUS_HEADER_TIMESTAMP 67 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 68 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 69 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 70 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 71 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 72 TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 73 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 74 TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 75 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 76 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 77 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 78 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 79 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 80 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 81 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 82 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 83 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 84 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 85 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 86 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 87 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 88 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 89 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 90 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 91 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 92 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 93 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 94 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 95 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 96 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 97 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 98 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 99 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 100 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 101 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 102 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 103 #include "hal_8074v2_tx.h" 104 #include "hal_8074v2_rx.h" 105 #include <hal_generic_api.h> 106 #include <hal_wbm.h> 107 108 struct hal_hw_txrx_ops qca8074v2_hal_hw_txrx_ops = { 109 110 /* init and setup */ 111 hal_srng_dst_hw_init_generic, 112 hal_srng_src_hw_init_generic, 113 hal_get_hw_hptp_generic, 114 hal_reo_setup_generic, 115 hal_setup_link_idle_list_generic, 116 117 /* tx */ 118 hal_tx_desc_set_dscp_tid_table_id_8074v2, 119 hal_tx_set_dscp_tid_map_8074v2, 120 hal_tx_update_dscp_tid_8074v2, 121 hal_tx_desc_set_lmac_id_8074v2, 122 hal_tx_desc_set_buf_addr_generic, 123 hal_tx_desc_set_search_type_generic, 124 hal_tx_desc_set_search_index_generic, 125 hal_tx_comp_get_status_generic, 126 hal_tx_comp_get_release_reason_generic, 127 128 /* rx */ 129 hal_rx_msdu_start_nss_get_8074v2, 130 hal_rx_mon_hw_desc_get_mpdu_status_8074v2, 131 hal_rx_get_tlv_8074v2, 132 hal_rx_proc_phyrx_other_receive_info_tlv_8074v2, 133 hal_rx_dump_msdu_start_tlv_8074v2, 134 hal_rx_dump_msdu_end_tlv_8074v2, 135 hal_get_link_desc_size_8074v2, 136 hal_rx_mpdu_start_tid_get_8074v2, 137 hal_rx_msdu_start_reception_type_get_8074v2, 138 hal_rx_msdu_end_da_idx_get_8074v2, 139 hal_rx_msdu_desc_info_get_ptr_generic, 140 hal_rx_link_desc_msdu0_ptr_generic, 141 hal_reo_status_get_header_generic, 142 hal_rx_status_get_tlv_info_generic, 143 hal_rx_wbm_err_info_get_generic, 144 hal_rx_dump_mpdu_start_tlv_generic, 145 146 hal_tx_set_pcp_tid_map_generic, 147 hal_tx_update_pcp_tid_generic, 148 hal_tx_update_tidmap_prty_generic, 149 }; 150 151 struct hal_hw_srng_config hw_srng_table_8074v2[] = { 152 /* TODO: max_rings can populated by querying HW capabilities */ 153 { /* REO_DST */ 154 .start_ring_id = HAL_SRNG_REO2SW1, 155 .max_rings = 4, 156 .entry_size = sizeof(struct reo_destination_ring) >> 2, 157 .lmac_ring = FALSE, 158 .ring_dir = HAL_SRNG_DST_RING, 159 .reg_start = { 160 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 161 SEQ_WCSS_UMAC_REO_REG_OFFSET), 162 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 163 SEQ_WCSS_UMAC_REO_REG_OFFSET) 164 }, 165 .reg_size = { 166 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 167 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 168 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 169 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 170 }, 171 .max_size = 172 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 173 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 174 }, 175 { /* REO_EXCEPTION */ 176 /* Designating REO2TCL ring as exception ring. This ring is 177 * similar to other REO2SW rings though it is named as REO2TCL. 178 * Any of theREO2SW rings can be used as exception ring. 179 */ 180 .start_ring_id = HAL_SRNG_REO2TCL, 181 .max_rings = 1, 182 .entry_size = sizeof(struct reo_destination_ring) >> 2, 183 .lmac_ring = FALSE, 184 .ring_dir = HAL_SRNG_DST_RING, 185 .reg_start = { 186 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 187 SEQ_WCSS_UMAC_REO_REG_OFFSET), 188 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 189 SEQ_WCSS_UMAC_REO_REG_OFFSET) 190 }, 191 /* Single ring - provide ring size if multiple rings of this 192 * type are supported 193 */ 194 .reg_size = {}, 195 .max_size = 196 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 197 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 198 }, 199 { /* REO_REINJECT */ 200 .start_ring_id = HAL_SRNG_SW2REO, 201 .max_rings = 1, 202 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 203 .lmac_ring = FALSE, 204 .ring_dir = HAL_SRNG_SRC_RING, 205 .reg_start = { 206 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 207 SEQ_WCSS_UMAC_REO_REG_OFFSET), 208 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 209 SEQ_WCSS_UMAC_REO_REG_OFFSET) 210 }, 211 /* Single ring - provide ring size if multiple rings of this 212 * type are supported 213 */ 214 .reg_size = {}, 215 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 216 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 217 }, 218 { /* REO_CMD */ 219 .start_ring_id = HAL_SRNG_REO_CMD, 220 .max_rings = 1, 221 .entry_size = (sizeof(struct tlv_32_hdr) + 222 sizeof(struct reo_get_queue_stats)) >> 2, 223 .lmac_ring = FALSE, 224 .ring_dir = HAL_SRNG_SRC_RING, 225 .reg_start = { 226 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 227 SEQ_WCSS_UMAC_REO_REG_OFFSET), 228 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 229 SEQ_WCSS_UMAC_REO_REG_OFFSET), 230 }, 231 /* Single ring - provide ring size if multiple rings of this 232 * type are supported 233 */ 234 .reg_size = {}, 235 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 236 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 237 }, 238 { /* REO_STATUS */ 239 .start_ring_id = HAL_SRNG_REO_STATUS, 240 .max_rings = 1, 241 .entry_size = (sizeof(struct tlv_32_hdr) + 242 sizeof(struct reo_get_queue_stats_status)) >> 2, 243 .lmac_ring = FALSE, 244 .ring_dir = HAL_SRNG_DST_RING, 245 .reg_start = { 246 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 247 SEQ_WCSS_UMAC_REO_REG_OFFSET), 248 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 249 SEQ_WCSS_UMAC_REO_REG_OFFSET), 250 }, 251 /* Single ring - provide ring size if multiple rings of this 252 * type are supported 253 */ 254 .reg_size = {}, 255 .max_size = 256 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 257 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 258 }, 259 { /* TCL_DATA */ 260 .start_ring_id = HAL_SRNG_SW2TCL1, 261 .max_rings = 3, 262 .entry_size = (sizeof(struct tlv_32_hdr) + 263 sizeof(struct tcl_data_cmd)) >> 2, 264 .lmac_ring = FALSE, 265 .ring_dir = HAL_SRNG_SRC_RING, 266 .reg_start = { 267 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 268 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 269 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 270 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 271 }, 272 .reg_size = { 273 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 274 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 275 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 276 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 277 }, 278 .max_size = 279 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 280 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 281 }, 282 { /* TCL_CMD */ 283 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 284 .max_rings = 1, 285 .entry_size = (sizeof(struct tlv_32_hdr) + 286 sizeof(struct tcl_gse_cmd)) >> 2, 287 .lmac_ring = FALSE, 288 .ring_dir = HAL_SRNG_SRC_RING, 289 .reg_start = { 290 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR( 291 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 292 HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR( 293 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 294 }, 295 /* Single ring - provide ring size if multiple rings of this 296 * type are supported 297 */ 298 .reg_size = {}, 299 .max_size = 300 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 301 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 302 }, 303 { /* TCL_STATUS */ 304 .start_ring_id = HAL_SRNG_TCL_STATUS, 305 .max_rings = 1, 306 .entry_size = (sizeof(struct tlv_32_hdr) + 307 sizeof(struct tcl_status_ring)) >> 2, 308 .lmac_ring = FALSE, 309 .ring_dir = HAL_SRNG_DST_RING, 310 .reg_start = { 311 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 312 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 313 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 314 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 315 }, 316 /* Single ring - provide ring size if multiple rings of this 317 * type are supported 318 */ 319 .reg_size = {}, 320 .max_size = 321 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 322 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 323 }, 324 { /* CE_SRC */ 325 .start_ring_id = HAL_SRNG_CE_0_SRC, 326 .max_rings = 12, 327 .entry_size = sizeof(struct ce_src_desc) >> 2, 328 .lmac_ring = FALSE, 329 .ring_dir = HAL_SRNG_SRC_RING, 330 .reg_start = { 331 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 332 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 333 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 334 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 335 }, 336 .reg_size = { 337 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 338 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 339 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 340 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 341 }, 342 .max_size = 343 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 344 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 345 }, 346 { /* CE_DST */ 347 .start_ring_id = HAL_SRNG_CE_0_DST, 348 .max_rings = 12, 349 .entry_size = 8 >> 2, 350 /*TODO: entry_size above should actually be 351 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 352 * of struct ce_dst_desc in HW header files 353 */ 354 .lmac_ring = FALSE, 355 .ring_dir = HAL_SRNG_SRC_RING, 356 .reg_start = { 357 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 358 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 359 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 360 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 361 }, 362 .reg_size = { 363 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 364 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 365 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 366 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 367 }, 368 .max_size = 369 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 370 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 371 }, 372 { /* CE_DST_STATUS */ 373 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 374 .max_rings = 12, 375 .entry_size = sizeof(struct ce_stat_desc) >> 2, 376 .lmac_ring = FALSE, 377 .ring_dir = HAL_SRNG_DST_RING, 378 .reg_start = { 379 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 380 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 381 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 382 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 383 }, 384 /* TODO: check destination status ring registers */ 385 .reg_size = { 386 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 387 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 388 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 389 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 390 }, 391 .max_size = 392 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 393 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 394 }, 395 { /* WBM_IDLE_LINK */ 396 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 397 .max_rings = 1, 398 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 399 .lmac_ring = FALSE, 400 .ring_dir = HAL_SRNG_SRC_RING, 401 .reg_start = { 402 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 403 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 404 }, 405 /* Single ring - provide ring size if multiple rings of this 406 * type are supported 407 */ 408 .reg_size = {}, 409 .max_size = 410 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 411 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 412 }, 413 { /* SW2WBM_RELEASE */ 414 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 415 .max_rings = 1, 416 .entry_size = sizeof(struct wbm_release_ring) >> 2, 417 .lmac_ring = FALSE, 418 .ring_dir = HAL_SRNG_SRC_RING, 419 .reg_start = { 420 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 421 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 422 }, 423 /* Single ring - provide ring size if multiple rings of this 424 * type are supported 425 */ 426 .reg_size = {}, 427 .max_size = 428 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 429 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 430 }, 431 { /* WBM2SW_RELEASE */ 432 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 433 .max_rings = 4, 434 .entry_size = sizeof(struct wbm_release_ring) >> 2, 435 .lmac_ring = FALSE, 436 .ring_dir = HAL_SRNG_DST_RING, 437 .reg_start = { 438 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 439 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 440 }, 441 .reg_size = { 442 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 443 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 444 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 445 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 446 }, 447 .max_size = 448 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 449 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 450 }, 451 { /* RXDMA_BUF */ 452 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 453 #ifdef IPA_OFFLOAD 454 .max_rings = 3, 455 #else 456 .max_rings = 2, 457 #endif 458 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 459 .lmac_ring = TRUE, 460 .ring_dir = HAL_SRNG_SRC_RING, 461 /* reg_start is not set because LMAC rings are not accessed 462 * from host 463 */ 464 .reg_start = {}, 465 .reg_size = {}, 466 .max_size = HAL_RXDMA_MAX_RING_SIZE, 467 }, 468 { /* RXDMA_DST */ 469 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 470 .max_rings = 1, 471 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 472 .lmac_ring = TRUE, 473 .ring_dir = HAL_SRNG_DST_RING, 474 /* reg_start is not set because LMAC rings are not accessed 475 * from host 476 */ 477 .reg_start = {}, 478 .reg_size = {}, 479 .max_size = HAL_RXDMA_MAX_RING_SIZE, 480 }, 481 { /* RXDMA_MONITOR_BUF */ 482 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 483 .max_rings = 1, 484 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 485 .lmac_ring = TRUE, 486 .ring_dir = HAL_SRNG_SRC_RING, 487 /* reg_start is not set because LMAC rings are not accessed 488 * from host 489 */ 490 .reg_start = {}, 491 .reg_size = {}, 492 .max_size = HAL_RXDMA_MAX_RING_SIZE, 493 }, 494 { /* RXDMA_MONITOR_STATUS */ 495 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 496 .max_rings = 1, 497 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 498 .lmac_ring = TRUE, 499 .ring_dir = HAL_SRNG_SRC_RING, 500 /* reg_start is not set because LMAC rings are not accessed 501 * from host 502 */ 503 .reg_start = {}, 504 .reg_size = {}, 505 .max_size = HAL_RXDMA_MAX_RING_SIZE, 506 }, 507 { /* RXDMA_MONITOR_DST */ 508 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 509 .max_rings = 1, 510 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 511 .lmac_ring = TRUE, 512 .ring_dir = HAL_SRNG_DST_RING, 513 /* reg_start is not set because LMAC rings are not accessed 514 * from host 515 */ 516 .reg_start = {}, 517 .reg_size = {}, 518 .max_size = HAL_RXDMA_MAX_RING_SIZE, 519 }, 520 { /* RXDMA_MONITOR_DESC */ 521 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 522 .max_rings = 1, 523 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 524 .lmac_ring = TRUE, 525 .ring_dir = HAL_SRNG_SRC_RING, 526 /* reg_start is not set because LMAC rings are not accessed 527 * from host 528 */ 529 .reg_start = {}, 530 .reg_size = {}, 531 .max_size = HAL_RXDMA_MAX_RING_SIZE, 532 }, 533 { /* DIR_BUF_RX_DMA_SRC */ 534 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 535 /* one ring for spectral and one ring for cfr */ 536 .max_rings = 2, 537 .entry_size = 2, 538 .lmac_ring = TRUE, 539 .ring_dir = HAL_SRNG_SRC_RING, 540 /* reg_start is not set because LMAC rings are not accessed 541 * from host 542 */ 543 .reg_start = {}, 544 .reg_size = {}, 545 .max_size = HAL_RXDMA_MAX_RING_SIZE, 546 }, 547 #ifdef WLAN_FEATURE_CIF_CFR 548 { /* WIFI_POS_SRC */ 549 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 550 .max_rings = 1, 551 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 552 .lmac_ring = TRUE, 553 .ring_dir = HAL_SRNG_SRC_RING, 554 /* reg_start is not set because LMAC rings are not accessed 555 * from host 556 */ 557 .reg_start = {}, 558 .reg_size = {}, 559 .max_size = HAL_RXDMA_MAX_RING_SIZE, 560 }, 561 #endif 562 }; 563 564 int32_t hal_hw_reg_offset_qca8074v2[] = { 565 /* dst */ 566 REG_OFFSET(DST, HP), 567 REG_OFFSET(DST, TP), 568 REG_OFFSET(DST, ID), 569 REG_OFFSET(DST, MISC), 570 REG_OFFSET(DST, HP_ADDR_LSB), 571 REG_OFFSET(DST, HP_ADDR_MSB), 572 REG_OFFSET(DST, MSI1_BASE_LSB), 573 REG_OFFSET(DST, MSI1_BASE_MSB), 574 REG_OFFSET(DST, MSI1_DATA), 575 REG_OFFSET(DST, BASE_LSB), 576 REG_OFFSET(DST, BASE_MSB), 577 REG_OFFSET(DST, PRODUCER_INT_SETUP), 578 /* src */ 579 REG_OFFSET(SRC, HP), 580 REG_OFFSET(SRC, TP), 581 REG_OFFSET(SRC, ID), 582 REG_OFFSET(SRC, MISC), 583 REG_OFFSET(SRC, TP_ADDR_LSB), 584 REG_OFFSET(SRC, TP_ADDR_MSB), 585 REG_OFFSET(SRC, MSI1_BASE_LSB), 586 REG_OFFSET(SRC, MSI1_BASE_MSB), 587 REG_OFFSET(SRC, MSI1_DATA), 588 REG_OFFSET(SRC, BASE_LSB), 589 REG_OFFSET(SRC, BASE_MSB), 590 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX0), 591 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX1), 592 }; 593 594 595 /** 596 * hal_qca8074v2_attach() - Attach 8074v2 target specific hal_soc ops, 597 * offset and srng table 598 */ 599 void hal_qca8074v2_attach(struct hal_soc *hal_soc) 600 { 601 hal_soc->hw_srng_table = hw_srng_table_8074v2; 602 hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca8074v2; 603 hal_soc->ops = &qca8074v2_hal_hw_txrx_ops; 604 } 605 606 607 608