1 /* 2 * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #include "hal_hw_headers.h" 19 #include "hal_internal.h" 20 #include "hal_api.h" 21 #include "target_type.h" 22 #include "wcss_version.h" 23 #include "qdf_module.h" 24 25 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 26 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET 27 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 28 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK 29 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 30 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB 31 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 32 PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 33 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 34 PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 35 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 36 PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 37 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 38 PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 39 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 40 PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 41 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 42 PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 43 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 44 PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 45 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 46 PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 47 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 48 PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 49 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 50 PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 51 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 52 PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 53 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 54 RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 55 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 56 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 57 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 58 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 59 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 60 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 61 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 62 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 63 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER \ 64 STATUS_HEADER_REO_STATUS_NUMBER 65 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 66 STATUS_HEADER_TIMESTAMP 67 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 68 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 69 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 70 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 71 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 72 TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 73 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 74 TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 75 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 76 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 77 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 78 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 79 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 80 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 81 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 82 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 83 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 84 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 85 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 86 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 87 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 88 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 89 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 90 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 91 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 92 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 93 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 94 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 95 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 96 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 97 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 98 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 99 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 100 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 101 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 102 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 103 #include "hal_8074v2_tx.h" 104 #include "hal_8074v2_rx.h" 105 #include <hal_generic_api.h> 106 #include <hal_wbm.h> 107 108 /** 109 * hal_rx_get_rx_fragment_number_8074v2(): Function to retrieve 110 * rx fragment number 111 * 112 * @nbuf: Network buffer 113 * Returns: rx fragment number 114 */ 115 static 116 uint8_t hal_rx_get_rx_fragment_number_8074v2(uint8_t *buf) 117 { 118 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 119 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 120 121 /* Return first 4 bits as fragment number */ 122 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & 123 DOT11_SEQ_FRAG_MASK; 124 } 125 126 /** 127 * hal_rx_msdu_end_da_is_mcbc_get_8074v2: API to check if pkt is MCBC 128 * from rx_msdu_end TLV 129 * 130 * @ buf: pointer to the start of RX PKT TLV headers 131 * Return: da_is_mcbc 132 */ 133 static uint8_t 134 hal_rx_msdu_end_da_is_mcbc_get_8074v2(uint8_t *buf) 135 { 136 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 137 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 138 139 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); 140 } 141 142 /** 143 * hal_rx_msdu_end_sa_is_valid_get_8074v2(): API to get_8074v2 the 144 * sa_is_valid bit from rx_msdu_end TLV 145 * 146 * @ buf: pointer to the start of RX PKT TLV headers 147 * Return: sa_is_valid bit 148 */ 149 static uint8_t 150 hal_rx_msdu_end_sa_is_valid_get_8074v2(uint8_t *buf) 151 { 152 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 153 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 154 uint8_t sa_is_valid; 155 156 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); 157 158 return sa_is_valid; 159 } 160 161 /** 162 * hal_rx_msdu_end_sa_idx_get_8074v2(): API to get_8074v2 the 163 * sa_idx from rx_msdu_end TLV 164 * 165 * @ buf: pointer to the start of RX PKT TLV headers 166 * Return: sa_idx (SA AST index) 167 */ 168 static uint16_t hal_rx_msdu_end_sa_idx_get_8074v2(uint8_t *buf) 169 { 170 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 171 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 172 uint16_t sa_idx; 173 174 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 175 176 return sa_idx; 177 } 178 179 /** 180 * hal_rx_desc_is_first_msdu_8074v2() - Check if first msdu 181 * 182 * @hal_soc_hdl: hal_soc handle 183 * @hw_desc_addr: hardware descriptor address 184 * 185 * Return: 0 - success/ non-zero failure 186 */ 187 static uint32_t hal_rx_desc_is_first_msdu_8074v2(void *hw_desc_addr) 188 { 189 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; 190 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; 191 192 return HAL_RX_GET(msdu_end, RX_MSDU_END_5, FIRST_MSDU); 193 } 194 195 /** 196 * hal_rx_msdu_end_l3_hdr_padding_get_8074v2(): API to get_8074v2 the 197 * l3_header padding from rx_msdu_end TLV 198 * 199 * @ buf: pointer to the start of RX PKT TLV headers 200 * Return: number of l3 header padding bytes 201 */ 202 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_8074v2(uint8_t *buf) 203 { 204 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 205 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 206 uint32_t l3_header_padding; 207 208 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 209 210 return l3_header_padding; 211 } 212 213 /* 214 * @ hal_rx_encryption_info_valid_8074v2: Returns encryption type. 215 * 216 * @ buf: rx_tlv_hdr of the received packet 217 * @ Return: encryption type 218 */ 219 static uint32_t hal_rx_encryption_info_valid_8074v2(uint8_t *buf) 220 { 221 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 222 struct rx_mpdu_start *mpdu_start = 223 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 224 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 225 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); 226 227 return encryption_info; 228 } 229 230 /* 231 * @ hal_rx_print_pn_8074v2: Prints the PN of rx packet. 232 * 233 * @ buf: rx_tlv_hdr of the received packet 234 * @ Return: void 235 */ 236 static void hal_rx_print_pn_8074v2(uint8_t *buf) 237 { 238 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 239 struct rx_mpdu_start *mpdu_start = 240 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 241 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 242 243 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); 244 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); 245 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); 246 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); 247 248 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ", 249 pn_127_96, pn_95_64, pn_63_32, pn_31_0); 250 } 251 252 /** 253 * hal_rx_msdu_end_first_msdu_get_8074v2: API to get first msdu status 254 * from rx_msdu_end TLV 255 * 256 * @ buf: pointer to the start of RX PKT TLV headers 257 * Return: first_msdu 258 */ 259 static uint8_t hal_rx_msdu_end_first_msdu_get_8074v2(uint8_t *buf) 260 { 261 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 262 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 263 uint8_t first_msdu; 264 265 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); 266 267 return first_msdu; 268 } 269 270 /** 271 * hal_rx_msdu_end_da_is_valid_get_8074v2: API to check if da is valid 272 * from rx_msdu_end TLV 273 * 274 * @ buf: pointer to the start of RX PKT TLV headers 275 * Return: da_is_valid 276 */ 277 static uint8_t hal_rx_msdu_end_da_is_valid_get_8074v2(uint8_t *buf) 278 { 279 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 280 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 281 uint8_t da_is_valid; 282 283 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); 284 285 return da_is_valid; 286 } 287 288 /** 289 * hal_rx_msdu_end_last_msdu_get_8074v2: API to get last msdu status 290 * from rx_msdu_end TLV 291 * 292 * @ buf: pointer to the start of RX PKT TLV headers 293 * Return: last_msdu 294 */ 295 static uint8_t hal_rx_msdu_end_last_msdu_get_8074v2(uint8_t *buf) 296 { 297 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 298 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 299 uint8_t last_msdu; 300 301 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); 302 303 return last_msdu; 304 } 305 306 /* 307 * hal_rx_get_mpdu_mac_ad4_valid_8074v2(): Retrieves if mpdu 4th addr is valid 308 * 309 * @nbuf: Network buffer 310 * Returns: value of mpdu 4th address valid field 311 */ 312 static bool hal_rx_get_mpdu_mac_ad4_valid_8074v2(uint8_t *buf) 313 { 314 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 315 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 316 bool ad4_valid = 0; 317 318 ad4_valid = HAL_RX_MPDU_GET_MAC_AD4_VALID(rx_mpdu_info); 319 320 return ad4_valid; 321 } 322 323 /** 324 * hal_rx_mpdu_start_sw_peer_id_get_8074v2: Retrieve sw peer_id 325 * @buf: network buffer 326 * 327 * Return: sw peer_id 328 */ 329 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_8074v2(uint8_t *buf) 330 { 331 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 332 struct rx_mpdu_start *mpdu_start = 333 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 334 335 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET( 336 &mpdu_start->rx_mpdu_info_details); 337 } 338 339 /* 340 * hal_rx_mpdu_get_to_ds_8074v2(): API to get the tods info 341 * from rx_mpdu_start 342 * 343 * @buf: pointer to the start of RX PKT TLV header 344 * Return: uint32_t(to_ds) 345 */ 346 static uint32_t hal_rx_mpdu_get_to_ds_8074v2(uint8_t *buf) 347 { 348 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 349 struct rx_mpdu_start *mpdu_start = 350 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 351 352 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 353 354 return HAL_RX_MPDU_GET_TODS(mpdu_info); 355 } 356 357 /* 358 * hal_rx_mpdu_get_fr_ds_8074v2(): API to get the from ds info 359 * from rx_mpdu_start 360 * 361 * @buf: pointer to the start of RX PKT TLV header 362 * Return: uint32_t(fr_ds) 363 */ 364 static uint32_t hal_rx_mpdu_get_fr_ds_8074v2(uint8_t *buf) 365 { 366 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 367 struct rx_mpdu_start *mpdu_start = 368 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 369 370 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 371 372 return HAL_RX_MPDU_GET_FROMDS(mpdu_info); 373 } 374 375 /* 376 * hal_rx_get_mpdu_frame_control_valid_8074v2(): Retrieves mpdu 377 * frame control valid 378 * 379 * @nbuf: Network buffer 380 * Returns: value of frame control valid field 381 */ 382 static uint8_t hal_rx_get_mpdu_frame_control_valid_8074v2(uint8_t *buf) 383 { 384 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 385 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 386 387 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); 388 } 389 390 /* 391 * hal_rx_mpdu_get_addr1_8074v2(): API to check get address1 of the mpdu 392 * 393 * @buf: pointer to the start of RX PKT TLV headera 394 * @mac_addr: pointer to mac address 395 * Return: success/failure 396 */ 397 static QDF_STATUS hal_rx_mpdu_get_addr1_8074v2(uint8_t *buf, uint8_t *mac_addr) 398 { 399 struct __attribute__((__packed__)) hal_addr1 { 400 uint32_t ad1_31_0; 401 uint16_t ad1_47_32; 402 }; 403 404 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 405 struct rx_mpdu_start *mpdu_start = 406 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 407 408 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 409 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; 410 uint32_t mac_addr_ad1_valid; 411 412 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); 413 414 if (mac_addr_ad1_valid) { 415 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); 416 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); 417 return QDF_STATUS_SUCCESS; 418 } 419 420 return QDF_STATUS_E_FAILURE; 421 } 422 423 /* 424 * hal_rx_mpdu_get_addr2_8074v2(): API to check get address2 of the mpdu 425 * in the packet 426 * 427 * @buf: pointer to the start of RX PKT TLV header 428 * @mac_addr: pointer to mac address 429 * Return: success/failure 430 */ 431 static QDF_STATUS hal_rx_mpdu_get_addr2_8074v2(uint8_t *buf, uint8_t *mac_addr) 432 { 433 struct __attribute__((__packed__)) hal_addr2 { 434 uint16_t ad2_15_0; 435 uint32_t ad2_47_16; 436 }; 437 438 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 439 struct rx_mpdu_start *mpdu_start = 440 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 441 442 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 443 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; 444 uint32_t mac_addr_ad2_valid; 445 446 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); 447 448 if (mac_addr_ad2_valid) { 449 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); 450 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); 451 return QDF_STATUS_SUCCESS; 452 } 453 454 return QDF_STATUS_E_FAILURE; 455 } 456 457 /* 458 * hal_rx_mpdu_get_addr3_8074v2(): API to get address3 of the mpdu 459 * in the packet 460 * 461 * @buf: pointer to the start of RX PKT TLV header 462 * @mac_addr: pointer to mac address 463 * Return: success/failure 464 */ 465 static QDF_STATUS hal_rx_mpdu_get_addr3_8074v2(uint8_t *buf, uint8_t *mac_addr) 466 { 467 struct __attribute__((__packed__)) hal_addr3 { 468 uint32_t ad3_31_0; 469 uint16_t ad3_47_32; 470 }; 471 472 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 473 struct rx_mpdu_start *mpdu_start = 474 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 475 476 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 477 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; 478 uint32_t mac_addr_ad3_valid; 479 480 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); 481 482 if (mac_addr_ad3_valid) { 483 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); 484 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); 485 return QDF_STATUS_SUCCESS; 486 } 487 488 return QDF_STATUS_E_FAILURE; 489 } 490 491 /* 492 * hal_rx_mpdu_get_addr4_8074v2(): API to get address4 of the mpdu 493 * in the packet 494 * 495 * @buf: pointer to the start of RX PKT TLV header 496 * @mac_addr: pointer to mac address 497 * Return: success/failure 498 */ 499 static QDF_STATUS hal_rx_mpdu_get_addr4_8074v2(uint8_t *buf, uint8_t *mac_addr) 500 { 501 struct __attribute__((__packed__)) hal_addr4 { 502 uint32_t ad4_31_0; 503 uint16_t ad4_47_32; 504 }; 505 506 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 507 struct rx_mpdu_start *mpdu_start = 508 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 509 510 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 511 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; 512 uint32_t mac_addr_ad4_valid; 513 514 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); 515 516 if (mac_addr_ad4_valid) { 517 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); 518 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); 519 return QDF_STATUS_SUCCESS; 520 } 521 522 return QDF_STATUS_E_FAILURE; 523 } 524 525 /* 526 * hal_rx_get_mpdu_sequence_control_valid_8074v2(): Get mpdu 527 * sequence control valid 528 * 529 * @nbuf: Network buffer 530 * Returns: value of sequence control valid field 531 */ 532 static uint8_t hal_rx_get_mpdu_sequence_control_valid_8074v2(uint8_t *buf) 533 { 534 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 535 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 536 537 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); 538 } 539 540 /** 541 * hal_rx_is_unicast_8074v2: check packet is unicast frame or not. 542 * 543 * @ buf: pointer to rx pkt TLV. 544 * 545 * Return: true on unicast. 546 */ 547 static bool hal_rx_is_unicast_8074v2(uint8_t *buf) 548 { 549 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 550 struct rx_mpdu_start *mpdu_start = 551 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 552 uint32_t grp_id; 553 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 554 555 grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 556 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_OFFSET)), 557 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_MASK, 558 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_LSB)); 559 560 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false; 561 } 562 563 /** 564 * hal_rx_tid_get_8074v2: get tid based on qos control valid. 565 * @hal_soc_hdl: hal soc handle 566 * @buf: pointer to rx pkt TLV. 567 * 568 * Return: tid 569 */ 570 static uint32_t hal_rx_tid_get_8074v2(hal_soc_handle_t hal_soc_hdl, 571 uint8_t *buf) 572 { 573 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 574 struct rx_mpdu_start *mpdu_start = 575 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 576 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 577 uint8_t qos_control_valid = 578 (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 579 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)), 580 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK, 581 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB)); 582 583 if (qos_control_valid) 584 return hal_rx_mpdu_start_tid_get_8074v2(buf); 585 586 return HAL_RX_NON_QOS_TID; 587 } 588 589 /** 590 * hal_rx_hw_desc_get_ppduid_get_8074v2(): retrieve ppdu id 591 * @hw_desc_addr: hw addr 592 * 593 * Return: ppdu id 594 */ 595 static uint32_t hal_rx_hw_desc_get_ppduid_get_8074v2(void *hw_desc_addr) 596 { 597 struct rx_mpdu_info *rx_mpdu_info; 598 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 599 600 rx_mpdu_info = 601 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 602 603 return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_0, PHY_PPDU_ID); 604 } 605 606 /** 607 * hal_reo_status_get_header_8074v2 - Process reo desc info 608 * @d - Pointer to reo descriptior 609 * @b - tlv type info 610 * @h1 - Pointer to hal_reo_status_header where info to be stored 611 * 612 * Return - none. 613 * 614 */ 615 static void hal_reo_status_get_header_8074v2(uint32_t *d, int b, void *h1) 616 { 617 uint32_t val1 = 0; 618 struct hal_reo_status_header *h = 619 (struct hal_reo_status_header *)h1; 620 621 switch (b) { 622 case HAL_REO_QUEUE_STATS_STATUS_TLV: 623 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, 624 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 625 break; 626 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 627 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, 628 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 629 break; 630 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 631 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, 632 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 633 break; 634 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 635 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, 636 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 637 break; 638 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 639 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, 640 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 641 break; 642 case HAL_REO_DESC_THRES_STATUS_TLV: 643 val1 = 644 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, 645 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 646 break; 647 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 648 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, 649 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 650 break; 651 default: 652 qdf_nofl_err("ERROR: Unknown tlv\n"); 653 break; 654 } 655 h->cmd_num = 656 HAL_GET_FIELD( 657 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, 658 val1); 659 h->exec_time = 660 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 661 CMD_EXECUTION_TIME, val1); 662 h->status = 663 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 664 REO_CMD_EXECUTION_STATUS, val1); 665 switch (b) { 666 case HAL_REO_QUEUE_STATS_STATUS_TLV: 667 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, 668 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 669 break; 670 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 671 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, 672 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 673 break; 674 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 675 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, 676 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 677 break; 678 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 679 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, 680 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 681 break; 682 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 683 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, 684 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 685 break; 686 case HAL_REO_DESC_THRES_STATUS_TLV: 687 val1 = 688 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, 689 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 690 break; 691 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 692 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, 693 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 694 break; 695 default: 696 qdf_nofl_err("ERROR: Unknown tlv\n"); 697 break; 698 } 699 h->tstamp = 700 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); 701 } 702 703 /** 704 * hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v2(): 705 * Retrieve qos control valid bit from the tlv. 706 * @buf: pointer to rx pkt TLV. 707 * 708 * Return: qos control value. 709 */ 710 static inline uint32_t 711 hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v2(uint8_t *buf) 712 { 713 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 714 struct rx_mpdu_start *mpdu_start = 715 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 716 717 return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET( 718 &mpdu_start->rx_mpdu_info_details); 719 } 720 721 /** 722 * hal_rx_msdu_end_sa_sw_peer_id_get_8074v2(): API to get the 723 * sa_sw_peer_id from rx_msdu_end TLV 724 * @buf: pointer to the start of RX PKT TLV headers 725 * 726 * Return: sa_sw_peer_id index 727 */ 728 static inline uint32_t 729 hal_rx_msdu_end_sa_sw_peer_id_get_8074v2(uint8_t *buf) 730 { 731 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 732 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 733 734 return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 735 } 736 737 /** 738 * hal_tx_desc_set_mesh_en_8074v2 - Set mesh_enable flag in Tx descriptor 739 * @desc: Handle to Tx Descriptor 740 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 741 * enabling the interpretation of the 'Mesh Control Present' bit 742 * (bit 8) of QoS Control (otherwise this bit is ignored), 743 * For native WiFi frames, this indicates that a 'Mesh Control' field 744 * is present between the header and the LLC. 745 * 746 * Return: void 747 */ 748 static inline 749 void hal_tx_desc_set_mesh_en_8074v2(void *desc, uint8_t en) 750 { 751 HAL_SET_FLD(desc, TCL_DATA_CMD_4, MESH_ENABLE) |= 752 HAL_TX_SM(TCL_DATA_CMD_4, MESH_ENABLE, en); 753 } 754 755 static 756 void *hal_rx_msdu0_buffer_addr_lsb_8074v2(void *link_desc_va) 757 { 758 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 759 } 760 761 static 762 void *hal_rx_msdu_desc_info_ptr_get_8074v2(void *msdu0) 763 { 764 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 765 } 766 767 static 768 void *hal_ent_mpdu_desc_info_8074v2(void *ent_ring_desc) 769 { 770 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 771 } 772 773 static 774 void *hal_dst_mpdu_desc_info_8074v2(void *dst_ring_desc) 775 { 776 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 777 } 778 779 static 780 uint8_t hal_rx_get_fc_valid_8074v2(uint8_t *buf) 781 { 782 return HAL_RX_GET_FC_VALID(buf); 783 } 784 785 static uint8_t hal_rx_get_to_ds_flag_8074v2(uint8_t *buf) 786 { 787 return HAL_RX_GET_TO_DS_FLAG(buf); 788 } 789 790 static uint8_t hal_rx_get_mac_addr2_valid_8074v2(uint8_t *buf) 791 { 792 return HAL_RX_GET_MAC_ADDR2_VALID(buf); 793 } 794 795 static uint8_t hal_rx_get_filter_category_8074v2(uint8_t *buf) 796 { 797 return HAL_RX_GET_FILTER_CATEGORY(buf); 798 } 799 800 static uint32_t 801 hal_rx_get_ppdu_id_8074v2(uint8_t *buf) 802 { 803 return HAL_RX_GET_PPDU_ID(buf); 804 } 805 806 /** 807 * hal_reo_config_8074v2(): Set reo config parameters 808 * @soc: hal soc handle 809 * @reg_val: value to be set 810 * @reo_params: reo parameters 811 * 812 * Return: void 813 */ 814 static void 815 hal_reo_config_8074v2(struct hal_soc *soc, 816 uint32_t reg_val, 817 struct hal_reo_params *reo_params) 818 { 819 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 820 } 821 822 /** 823 * hal_rx_msdu_desc_info_get_ptr_8074v2() - Get msdu desc info ptr 824 * @msdu_details_ptr - Pointer to msdu_details_ptr 825 * 826 * Return - Pointer to rx_msdu_desc_info structure. 827 * 828 */ 829 static void *hal_rx_msdu_desc_info_get_ptr_8074v2(void *msdu_details_ptr) 830 { 831 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 832 } 833 834 /** 835 * hal_rx_link_desc_msdu0_ptr_8074v2 - Get pointer to rx_msdu details 836 * @link_desc - Pointer to link desc 837 * 838 * Return - Pointer to rx_msdu_details structure 839 * 840 */ 841 static void *hal_rx_link_desc_msdu0_ptr_8074v2(void *link_desc) 842 { 843 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 844 } 845 846 /** 847 * hal_rx_msdu_flow_idx_get_8074v2: API to get flow index 848 * from rx_msdu_end TLV 849 * @buf: pointer to the start of RX PKT TLV headers 850 * 851 * Return: flow index value from MSDU END TLV 852 */ 853 static inline uint32_t hal_rx_msdu_flow_idx_get_8074v2(uint8_t *buf) 854 { 855 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 856 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 857 858 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 859 } 860 861 /** 862 * hal_rx_msdu_flow_idx_invalid_8074v2: API to get flow index invalid 863 * from rx_msdu_end TLV 864 * @buf: pointer to the start of RX PKT TLV headers 865 * 866 * Return: flow index invalid value from MSDU END TLV 867 */ 868 static bool hal_rx_msdu_flow_idx_invalid_8074v2(uint8_t *buf) 869 { 870 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 871 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 872 873 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 874 } 875 876 /** 877 * hal_rx_msdu_flow_idx_timeout_8074v2: API to get flow index timeout 878 * from rx_msdu_end TLV 879 * @buf: pointer to the start of RX PKT TLV headers 880 * 881 * Return: flow index timeout value from MSDU END TLV 882 */ 883 static bool hal_rx_msdu_flow_idx_timeout_8074v2(uint8_t *buf) 884 { 885 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 886 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 887 888 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 889 } 890 891 /** 892 * hal_rx_msdu_fse_metadata_get_8074v2: API to get FSE metadata 893 * from rx_msdu_end TLV 894 * @buf: pointer to the start of RX PKT TLV headers 895 * 896 * Return: fse metadata value from MSDU END TLV 897 */ 898 static uint32_t hal_rx_msdu_fse_metadata_get_8074v2(uint8_t *buf) 899 { 900 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 901 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 902 903 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end); 904 } 905 906 /** 907 * hal_rx_msdu_cce_metadata_get_8074v2: API to get CCE metadata 908 * from rx_msdu_end TLV 909 * @buf: pointer to the start of RX PKT TLV headers 910 * 911 * Return: cce_metadata 912 */ 913 static uint16_t 914 hal_rx_msdu_cce_metadata_get_8074v2(uint8_t *buf) 915 { 916 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 917 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 918 919 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end); 920 } 921 922 /** 923 * hal_rx_msdu_get_flow_params_8074v2: API to get flow index, flow index invalid 924 * and flow index timeout from rx_msdu_end TLV 925 * @buf: pointer to the start of RX PKT TLV headers 926 * @flow_invalid: pointer to return value of flow_idx_valid 927 * @flow_timeout: pointer to return value of flow_idx_timeout 928 * @flow_index: pointer to return value of flow_idx 929 * 930 * Return: none 931 */ 932 static inline void 933 hal_rx_msdu_get_flow_params_8074v2(uint8_t *buf, 934 bool *flow_invalid, 935 bool *flow_timeout, 936 uint32_t *flow_index) 937 { 938 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 939 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 940 941 *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 942 *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 943 *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 944 } 945 946 /** 947 * hal_rx_tlv_get_tcp_chksum_8074v2() - API to get tcp checksum 948 * @buf: rx_tlv_hdr 949 * 950 * Return: tcp checksum 951 */ 952 static uint16_t 953 hal_rx_tlv_get_tcp_chksum_8074v2(uint8_t *buf) 954 { 955 return HAL_RX_TLV_GET_TCP_CHKSUM(buf); 956 } 957 958 /** 959 * hal_rx_get_rx_sequence_8074v2(): Function to retrieve rx sequence number 960 * 961 * @nbuf: Network buffer 962 * Returns: rx sequence number 963 */ 964 static 965 uint16_t hal_rx_get_rx_sequence_8074v2(uint8_t *buf) 966 { 967 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 968 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 969 970 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info); 971 } 972 973 /** 974 * hal_get_window_address_8074v2(): Function to get hp/tp address 975 * @hal_soc: Pointer to hal_soc 976 * @addr: address offset of register 977 * 978 * Return: modified address offset of register 979 */ 980 static inline qdf_iomem_t hal_get_window_address_8074v2(struct hal_soc *hal_soc, 981 qdf_iomem_t addr) 982 { 983 return addr; 984 } 985 986 struct hal_hw_txrx_ops qca8074v2_hal_hw_txrx_ops = { 987 988 /* init and setup */ 989 hal_srng_dst_hw_init_generic, 990 hal_srng_src_hw_init_generic, 991 hal_get_hw_hptp_generic, 992 hal_reo_setup_generic, 993 hal_setup_link_idle_list_generic, 994 hal_get_window_address_8074v2, 995 996 /* tx */ 997 hal_tx_desc_set_dscp_tid_table_id_8074v2, 998 hal_tx_set_dscp_tid_map_8074v2, 999 hal_tx_update_dscp_tid_8074v2, 1000 hal_tx_desc_set_lmac_id_8074v2, 1001 hal_tx_desc_set_buf_addr_generic, 1002 hal_tx_desc_set_search_type_generic, 1003 hal_tx_desc_set_search_index_generic, 1004 hal_tx_desc_set_cache_set_num_generic, 1005 hal_tx_comp_get_status_generic, 1006 hal_tx_comp_get_release_reason_generic, 1007 hal_tx_desc_set_mesh_en_8074v2, 1008 1009 /* rx */ 1010 hal_rx_msdu_start_nss_get_8074v2, 1011 hal_rx_mon_hw_desc_get_mpdu_status_8074v2, 1012 hal_rx_get_tlv_8074v2, 1013 hal_rx_proc_phyrx_other_receive_info_tlv_8074v2, 1014 hal_rx_dump_msdu_start_tlv_8074v2, 1015 hal_rx_dump_msdu_end_tlv_8074v2, 1016 hal_get_link_desc_size_8074v2, 1017 hal_rx_mpdu_start_tid_get_8074v2, 1018 hal_rx_msdu_start_reception_type_get_8074v2, 1019 hal_rx_msdu_end_da_idx_get_8074v2, 1020 hal_rx_msdu_desc_info_get_ptr_8074v2, 1021 hal_rx_link_desc_msdu0_ptr_8074v2, 1022 hal_reo_status_get_header_8074v2, 1023 hal_rx_status_get_tlv_info_generic, 1024 hal_rx_wbm_err_info_get_generic, 1025 hal_rx_dump_mpdu_start_tlv_generic, 1026 1027 hal_tx_set_pcp_tid_map_generic, 1028 hal_tx_update_pcp_tid_generic, 1029 hal_tx_update_tidmap_prty_generic, 1030 hal_rx_get_rx_fragment_number_8074v2, 1031 hal_rx_msdu_end_da_is_mcbc_get_8074v2, 1032 hal_rx_msdu_end_sa_is_valid_get_8074v2, 1033 hal_rx_msdu_end_sa_idx_get_8074v2, 1034 hal_rx_desc_is_first_msdu_8074v2, 1035 hal_rx_msdu_end_l3_hdr_padding_get_8074v2, 1036 hal_rx_encryption_info_valid_8074v2, 1037 hal_rx_print_pn_8074v2, 1038 hal_rx_msdu_end_first_msdu_get_8074v2, 1039 hal_rx_msdu_end_da_is_valid_get_8074v2, 1040 hal_rx_msdu_end_last_msdu_get_8074v2, 1041 hal_rx_get_mpdu_mac_ad4_valid_8074v2, 1042 hal_rx_mpdu_start_sw_peer_id_get_8074v2, 1043 hal_rx_mpdu_get_to_ds_8074v2, 1044 hal_rx_mpdu_get_fr_ds_8074v2, 1045 hal_rx_get_mpdu_frame_control_valid_8074v2, 1046 hal_rx_mpdu_get_addr1_8074v2, 1047 hal_rx_mpdu_get_addr2_8074v2, 1048 hal_rx_mpdu_get_addr3_8074v2, 1049 hal_rx_mpdu_get_addr4_8074v2, 1050 hal_rx_get_mpdu_sequence_control_valid_8074v2, 1051 hal_rx_is_unicast_8074v2, 1052 hal_rx_tid_get_8074v2, 1053 hal_rx_hw_desc_get_ppduid_get_8074v2, 1054 hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v2, 1055 hal_rx_msdu_end_sa_sw_peer_id_get_8074v2, 1056 hal_rx_msdu0_buffer_addr_lsb_8074v2, 1057 hal_rx_msdu_desc_info_ptr_get_8074v2, 1058 hal_ent_mpdu_desc_info_8074v2, 1059 hal_dst_mpdu_desc_info_8074v2, 1060 hal_rx_get_fc_valid_8074v2, 1061 hal_rx_get_to_ds_flag_8074v2, 1062 hal_rx_get_mac_addr2_valid_8074v2, 1063 hal_rx_get_filter_category_8074v2, 1064 hal_rx_get_ppdu_id_8074v2, 1065 hal_reo_config_8074v2, 1066 hal_rx_msdu_flow_idx_get_8074v2, 1067 hal_rx_msdu_flow_idx_invalid_8074v2, 1068 hal_rx_msdu_flow_idx_timeout_8074v2, 1069 hal_rx_msdu_fse_metadata_get_8074v2, 1070 hal_rx_msdu_cce_metadata_get_8074v2, 1071 hal_rx_msdu_get_flow_params_8074v2, 1072 hal_rx_tlv_get_tcp_chksum_8074v2, 1073 hal_rx_get_rx_sequence_8074v2, 1074 #if defined(QCA_WIFI_QCA6018) && defined(WLAN_CFR_ENABLE) && \ 1075 defined(WLAN_ENH_CFR_ENABLE) 1076 hal_rx_get_bb_info_8074v2, 1077 hal_rx_get_rtt_info_8074v2, 1078 #else 1079 NULL, 1080 NULL, 1081 #endif 1082 }; 1083 1084 struct hal_hw_srng_config hw_srng_table_8074v2[] = { 1085 /* TODO: max_rings can populated by querying HW capabilities */ 1086 { /* REO_DST */ 1087 .start_ring_id = HAL_SRNG_REO2SW1, 1088 .max_rings = 4, 1089 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1090 .lmac_ring = FALSE, 1091 .ring_dir = HAL_SRNG_DST_RING, 1092 .reg_start = { 1093 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 1094 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1095 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 1096 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1097 }, 1098 .reg_size = { 1099 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 1100 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 1101 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 1102 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 1103 }, 1104 .max_size = 1105 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 1106 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 1107 }, 1108 { /* REO_EXCEPTION */ 1109 /* Designating REO2TCL ring as exception ring. This ring is 1110 * similar to other REO2SW rings though it is named as REO2TCL. 1111 * Any of theREO2SW rings can be used as exception ring. 1112 */ 1113 .start_ring_id = HAL_SRNG_REO2TCL, 1114 .max_rings = 1, 1115 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1116 .lmac_ring = FALSE, 1117 .ring_dir = HAL_SRNG_DST_RING, 1118 .reg_start = { 1119 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 1120 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1121 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 1122 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1123 }, 1124 /* Single ring - provide ring size if multiple rings of this 1125 * type are supported 1126 */ 1127 .reg_size = {}, 1128 .max_size = 1129 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 1130 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 1131 }, 1132 { /* REO_REINJECT */ 1133 .start_ring_id = HAL_SRNG_SW2REO, 1134 .max_rings = 1, 1135 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1136 .lmac_ring = FALSE, 1137 .ring_dir = HAL_SRNG_SRC_RING, 1138 .reg_start = { 1139 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 1140 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1141 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 1142 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1143 }, 1144 /* Single ring - provide ring size if multiple rings of this 1145 * type are supported 1146 */ 1147 .reg_size = {}, 1148 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 1149 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 1150 }, 1151 { /* REO_CMD */ 1152 .start_ring_id = HAL_SRNG_REO_CMD, 1153 .max_rings = 1, 1154 .entry_size = (sizeof(struct tlv_32_hdr) + 1155 sizeof(struct reo_get_queue_stats)) >> 2, 1156 .lmac_ring = FALSE, 1157 .ring_dir = HAL_SRNG_SRC_RING, 1158 .reg_start = { 1159 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 1160 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1161 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 1162 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1163 }, 1164 /* Single ring - provide ring size if multiple rings of this 1165 * type are supported 1166 */ 1167 .reg_size = {}, 1168 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1169 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1170 }, 1171 { /* REO_STATUS */ 1172 .start_ring_id = HAL_SRNG_REO_STATUS, 1173 .max_rings = 1, 1174 .entry_size = (sizeof(struct tlv_32_hdr) + 1175 sizeof(struct reo_get_queue_stats_status)) >> 2, 1176 .lmac_ring = FALSE, 1177 .ring_dir = HAL_SRNG_DST_RING, 1178 .reg_start = { 1179 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 1180 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1181 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 1182 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1183 }, 1184 /* Single ring - provide ring size if multiple rings of this 1185 * type are supported 1186 */ 1187 .reg_size = {}, 1188 .max_size = 1189 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1190 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1191 }, 1192 { /* TCL_DATA */ 1193 .start_ring_id = HAL_SRNG_SW2TCL1, 1194 .max_rings = 3, 1195 .entry_size = (sizeof(struct tlv_32_hdr) + 1196 sizeof(struct tcl_data_cmd)) >> 2, 1197 .lmac_ring = FALSE, 1198 .ring_dir = HAL_SRNG_SRC_RING, 1199 .reg_start = { 1200 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 1201 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1202 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 1203 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1204 }, 1205 .reg_size = { 1206 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 1207 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 1208 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 1209 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 1210 }, 1211 .max_size = 1212 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 1213 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 1214 }, 1215 { /* TCL_CMD */ 1216 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 1217 .max_rings = 1, 1218 .entry_size = (sizeof(struct tlv_32_hdr) + 1219 sizeof(struct tcl_gse_cmd)) >> 2, 1220 .lmac_ring = FALSE, 1221 .ring_dir = HAL_SRNG_SRC_RING, 1222 .reg_start = { 1223 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR( 1224 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1225 HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR( 1226 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1227 }, 1228 /* Single ring - provide ring size if multiple rings of this 1229 * type are supported 1230 */ 1231 .reg_size = {}, 1232 .max_size = 1233 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1234 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1235 }, 1236 { /* TCL_STATUS */ 1237 .start_ring_id = HAL_SRNG_TCL_STATUS, 1238 .max_rings = 1, 1239 .entry_size = (sizeof(struct tlv_32_hdr) + 1240 sizeof(struct tcl_status_ring)) >> 2, 1241 .lmac_ring = FALSE, 1242 .ring_dir = HAL_SRNG_DST_RING, 1243 .reg_start = { 1244 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 1245 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1246 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 1247 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1248 }, 1249 /* Single ring - provide ring size if multiple rings of this 1250 * type are supported 1251 */ 1252 .reg_size = {}, 1253 .max_size = 1254 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 1255 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 1256 }, 1257 { /* CE_SRC */ 1258 .start_ring_id = HAL_SRNG_CE_0_SRC, 1259 .max_rings = 12, 1260 .entry_size = sizeof(struct ce_src_desc) >> 2, 1261 .lmac_ring = FALSE, 1262 .ring_dir = HAL_SRNG_SRC_RING, 1263 .reg_start = { 1264 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1265 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1266 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1267 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1268 }, 1269 .reg_size = { 1270 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1271 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1272 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1273 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1274 }, 1275 .max_size = 1276 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1277 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1278 }, 1279 { /* CE_DST */ 1280 .start_ring_id = HAL_SRNG_CE_0_DST, 1281 .max_rings = 12, 1282 .entry_size = 8 >> 2, 1283 /*TODO: entry_size above should actually be 1284 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 1285 * of struct ce_dst_desc in HW header files 1286 */ 1287 .lmac_ring = FALSE, 1288 .ring_dir = HAL_SRNG_SRC_RING, 1289 .reg_start = { 1290 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1291 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1292 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1293 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1294 }, 1295 .reg_size = { 1296 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1297 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1298 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1299 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1300 }, 1301 .max_size = 1302 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1303 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1304 }, 1305 { /* CE_DST_STATUS */ 1306 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 1307 .max_rings = 12, 1308 .entry_size = sizeof(struct ce_stat_desc) >> 2, 1309 .lmac_ring = FALSE, 1310 .ring_dir = HAL_SRNG_DST_RING, 1311 .reg_start = { 1312 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 1313 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1314 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 1315 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1316 }, 1317 /* TODO: check destination status ring registers */ 1318 .reg_size = { 1319 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1320 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1321 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1322 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1323 }, 1324 .max_size = 1325 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1326 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1327 }, 1328 { /* WBM_IDLE_LINK */ 1329 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 1330 .max_rings = 1, 1331 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 1332 .lmac_ring = FALSE, 1333 .ring_dir = HAL_SRNG_SRC_RING, 1334 .reg_start = { 1335 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1336 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1337 }, 1338 /* Single ring - provide ring size if multiple rings of this 1339 * type are supported 1340 */ 1341 .reg_size = {}, 1342 .max_size = 1343 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 1344 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 1345 }, 1346 { /* SW2WBM_RELEASE */ 1347 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 1348 .max_rings = 1, 1349 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1350 .lmac_ring = FALSE, 1351 .ring_dir = HAL_SRNG_SRC_RING, 1352 .reg_start = { 1353 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1354 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1355 }, 1356 /* Single ring - provide ring size if multiple rings of this 1357 * type are supported 1358 */ 1359 .reg_size = {}, 1360 .max_size = 1361 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1362 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1363 }, 1364 { /* WBM2SW_RELEASE */ 1365 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 1366 .max_rings = 4, 1367 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1368 .lmac_ring = FALSE, 1369 .ring_dir = HAL_SRNG_DST_RING, 1370 .reg_start = { 1371 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1372 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1373 }, 1374 .reg_size = { 1375 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1376 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1377 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1378 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1379 }, 1380 .max_size = 1381 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1382 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1383 }, 1384 { /* RXDMA_BUF */ 1385 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 1386 #ifdef IPA_OFFLOAD 1387 .max_rings = 3, 1388 #else 1389 .max_rings = 2, 1390 #endif 1391 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1392 .lmac_ring = TRUE, 1393 .ring_dir = HAL_SRNG_SRC_RING, 1394 /* reg_start is not set because LMAC rings are not accessed 1395 * from host 1396 */ 1397 .reg_start = {}, 1398 .reg_size = {}, 1399 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1400 }, 1401 { /* RXDMA_DST */ 1402 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 1403 .max_rings = 1, 1404 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1405 .lmac_ring = TRUE, 1406 .ring_dir = HAL_SRNG_DST_RING, 1407 /* reg_start is not set because LMAC rings are not accessed 1408 * from host 1409 */ 1410 .reg_start = {}, 1411 .reg_size = {}, 1412 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1413 }, 1414 { /* RXDMA_MONITOR_BUF */ 1415 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 1416 .max_rings = 1, 1417 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1418 .lmac_ring = TRUE, 1419 .ring_dir = HAL_SRNG_SRC_RING, 1420 /* reg_start is not set because LMAC rings are not accessed 1421 * from host 1422 */ 1423 .reg_start = {}, 1424 .reg_size = {}, 1425 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1426 }, 1427 { /* RXDMA_MONITOR_STATUS */ 1428 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 1429 .max_rings = 1, 1430 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1431 .lmac_ring = TRUE, 1432 .ring_dir = HAL_SRNG_SRC_RING, 1433 /* reg_start is not set because LMAC rings are not accessed 1434 * from host 1435 */ 1436 .reg_start = {}, 1437 .reg_size = {}, 1438 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1439 }, 1440 { /* RXDMA_MONITOR_DST */ 1441 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 1442 .max_rings = 1, 1443 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1444 .lmac_ring = TRUE, 1445 .ring_dir = HAL_SRNG_DST_RING, 1446 /* reg_start is not set because LMAC rings are not accessed 1447 * from host 1448 */ 1449 .reg_start = {}, 1450 .reg_size = {}, 1451 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1452 }, 1453 { /* RXDMA_MONITOR_DESC */ 1454 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 1455 .max_rings = 1, 1456 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1457 .lmac_ring = TRUE, 1458 .ring_dir = HAL_SRNG_SRC_RING, 1459 /* reg_start is not set because LMAC rings are not accessed 1460 * from host 1461 */ 1462 .reg_start = {}, 1463 .reg_size = {}, 1464 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1465 }, 1466 { /* DIR_BUF_RX_DMA_SRC */ 1467 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 1468 /* one ring for spectral and one ring for cfr */ 1469 .max_rings = 2, 1470 .entry_size = 2, 1471 .lmac_ring = TRUE, 1472 .ring_dir = HAL_SRNG_SRC_RING, 1473 /* reg_start is not set because LMAC rings are not accessed 1474 * from host 1475 */ 1476 .reg_start = {}, 1477 .reg_size = {}, 1478 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1479 }, 1480 #ifdef WLAN_FEATURE_CIF_CFR 1481 { /* WIFI_POS_SRC */ 1482 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 1483 .max_rings = 1, 1484 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 1485 .lmac_ring = TRUE, 1486 .ring_dir = HAL_SRNG_SRC_RING, 1487 /* reg_start is not set because LMAC rings are not accessed 1488 * from host 1489 */ 1490 .reg_start = {}, 1491 .reg_size = {}, 1492 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1493 }, 1494 #endif 1495 }; 1496 1497 int32_t hal_hw_reg_offset_qca8074v2[] = { 1498 /* dst */ 1499 REG_OFFSET(DST, HP), 1500 REG_OFFSET(DST, TP), 1501 REG_OFFSET(DST, ID), 1502 REG_OFFSET(DST, MISC), 1503 REG_OFFSET(DST, HP_ADDR_LSB), 1504 REG_OFFSET(DST, HP_ADDR_MSB), 1505 REG_OFFSET(DST, MSI1_BASE_LSB), 1506 REG_OFFSET(DST, MSI1_BASE_MSB), 1507 REG_OFFSET(DST, MSI1_DATA), 1508 REG_OFFSET(DST, BASE_LSB), 1509 REG_OFFSET(DST, BASE_MSB), 1510 REG_OFFSET(DST, PRODUCER_INT_SETUP), 1511 /* src */ 1512 REG_OFFSET(SRC, HP), 1513 REG_OFFSET(SRC, TP), 1514 REG_OFFSET(SRC, ID), 1515 REG_OFFSET(SRC, MISC), 1516 REG_OFFSET(SRC, TP_ADDR_LSB), 1517 REG_OFFSET(SRC, TP_ADDR_MSB), 1518 REG_OFFSET(SRC, MSI1_BASE_LSB), 1519 REG_OFFSET(SRC, MSI1_BASE_MSB), 1520 REG_OFFSET(SRC, MSI1_DATA), 1521 REG_OFFSET(SRC, BASE_LSB), 1522 REG_OFFSET(SRC, BASE_MSB), 1523 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX0), 1524 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX1), 1525 }; 1526 1527 1528 /** 1529 * hal_qca8074v2_attach() - Attach 8074v2 target specific hal_soc ops, 1530 * offset and srng table 1531 */ 1532 void hal_qca8074v2_attach(struct hal_soc *hal_soc) 1533 { 1534 hal_soc->hw_srng_table = hw_srng_table_8074v2; 1535 hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca8074v2; 1536 hal_soc->ops = &qca8074v2_hal_hw_txrx_ops; 1537 } 1538