1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 #include "hal_li_hw_headers.h" 20 #include "hal_internal.h" 21 #include "hal_api.h" 22 #include "target_type.h" 23 #include "wcss_version.h" 24 #include "qdf_module.h" 25 #include "hal_flow.h" 26 #include "rx_flow_search_entry.h" 27 #include "hal_rx_flow_info.h" 28 29 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 30 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET 31 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 32 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK 33 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 34 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB 35 #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET \ 36 RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET 37 #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK \ 38 RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK 39 #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB \ 40 RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB 41 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 42 PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 43 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 44 PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 45 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 46 PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 47 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 48 PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 49 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 50 PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 51 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 52 PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 53 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 54 PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 55 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 56 PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 57 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 58 PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 59 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 60 PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 61 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 62 PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 63 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 64 RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 65 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 66 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 67 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 68 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 69 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 70 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 71 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 72 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 73 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER \ 74 STATUS_HEADER_REO_STATUS_NUMBER 75 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 76 STATUS_HEADER_TIMESTAMP 77 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 78 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 79 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 80 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 81 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 82 TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 83 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 84 TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 85 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 86 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 87 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 88 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 89 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 90 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 91 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 92 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 93 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 94 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 95 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 96 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 97 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 98 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 99 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 100 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 101 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 102 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 103 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 104 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 105 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 106 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 107 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 108 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 109 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 110 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 111 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 112 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 113 114 #include "hal_8074v2_tx.h" 115 #include "hal_8074v2_rx.h" 116 #include <hal_generic_api.h> 117 #include "hal_li_rx.h" 118 #include "hal_li_api.h" 119 #include "hal_li_generic_api.h" 120 121 /** 122 * hal_rx_get_rx_fragment_number_8074v2(): Function to retrieve 123 * rx fragment number 124 * 125 * @nbuf: Network buffer 126 * Returns: rx fragment number 127 */ 128 static 129 uint8_t hal_rx_get_rx_fragment_number_8074v2(uint8_t *buf) 130 { 131 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 132 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 133 134 /* Return first 4 bits as fragment number */ 135 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & 136 DOT11_SEQ_FRAG_MASK; 137 } 138 139 /** 140 * hal_rx_msdu_end_da_is_mcbc_get_8074v2: API to check if pkt is MCBC 141 * from rx_msdu_end TLV 142 * 143 * @ buf: pointer to the start of RX PKT TLV headers 144 * Return: da_is_mcbc 145 */ 146 static uint8_t 147 hal_rx_msdu_end_da_is_mcbc_get_8074v2(uint8_t *buf) 148 { 149 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 150 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 151 152 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); 153 } 154 155 /** 156 * hal_rx_msdu_end_sa_is_valid_get_8074v2(): API to get_8074v2 the 157 * sa_is_valid bit from rx_msdu_end TLV 158 * 159 * @ buf: pointer to the start of RX PKT TLV headers 160 * Return: sa_is_valid bit 161 */ 162 static uint8_t 163 hal_rx_msdu_end_sa_is_valid_get_8074v2(uint8_t *buf) 164 { 165 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 166 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 167 uint8_t sa_is_valid; 168 169 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); 170 171 return sa_is_valid; 172 } 173 174 /** 175 * hal_rx_msdu_end_sa_idx_get_8074v2(): API to get_8074v2 the 176 * sa_idx from rx_msdu_end TLV 177 * 178 * @ buf: pointer to the start of RX PKT TLV headers 179 * Return: sa_idx (SA AST index) 180 */ 181 static uint16_t hal_rx_msdu_end_sa_idx_get_8074v2(uint8_t *buf) 182 { 183 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 184 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 185 uint16_t sa_idx; 186 187 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 188 189 return sa_idx; 190 } 191 192 /** 193 * hal_rx_desc_is_first_msdu_8074v2() - Check if first msdu 194 * 195 * @hal_soc_hdl: hal_soc handle 196 * @hw_desc_addr: hardware descriptor address 197 * 198 * Return: 0 - success/ non-zero failure 199 */ 200 static uint32_t hal_rx_desc_is_first_msdu_8074v2(void *hw_desc_addr) 201 { 202 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; 203 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; 204 205 return HAL_RX_GET(msdu_end, RX_MSDU_END_5, FIRST_MSDU); 206 } 207 208 /** 209 * hal_rx_msdu_end_l3_hdr_padding_get_8074v2(): API to get_8074v2 the 210 * l3_header padding from rx_msdu_end TLV 211 * 212 * @ buf: pointer to the start of RX PKT TLV headers 213 * Return: number of l3 header padding bytes 214 */ 215 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_8074v2(uint8_t *buf) 216 { 217 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 218 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 219 uint32_t l3_header_padding; 220 221 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 222 223 return l3_header_padding; 224 } 225 226 /* 227 * @ hal_rx_encryption_info_valid_8074v2: Returns encryption type. 228 * 229 * @ buf: rx_tlv_hdr of the received packet 230 * @ Return: encryption type 231 */ 232 static uint32_t hal_rx_encryption_info_valid_8074v2(uint8_t *buf) 233 { 234 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 235 struct rx_mpdu_start *mpdu_start = 236 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 237 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 238 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); 239 240 return encryption_info; 241 } 242 243 /* 244 * @ hal_rx_print_pn_8074v2: Prints the PN of rx packet. 245 * 246 * @ buf: rx_tlv_hdr of the received packet 247 * @ Return: void 248 */ 249 static void hal_rx_print_pn_8074v2(uint8_t *buf) 250 { 251 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 252 struct rx_mpdu_start *mpdu_start = 253 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 254 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 255 256 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); 257 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); 258 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); 259 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); 260 261 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ", 262 pn_127_96, pn_95_64, pn_63_32, pn_31_0); 263 } 264 265 /** 266 * hal_rx_msdu_end_first_msdu_get_8074v2: API to get first msdu status 267 * from rx_msdu_end TLV 268 * 269 * @ buf: pointer to the start of RX PKT TLV headers 270 * Return: first_msdu 271 */ 272 static uint8_t hal_rx_msdu_end_first_msdu_get_8074v2(uint8_t *buf) 273 { 274 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 275 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 276 uint8_t first_msdu; 277 278 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); 279 280 return first_msdu; 281 } 282 283 /** 284 * hal_rx_msdu_end_da_is_valid_get_8074v2: API to check if da is valid 285 * from rx_msdu_end TLV 286 * 287 * @ buf: pointer to the start of RX PKT TLV headers 288 * Return: da_is_valid 289 */ 290 static uint8_t hal_rx_msdu_end_da_is_valid_get_8074v2(uint8_t *buf) 291 { 292 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 293 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 294 uint8_t da_is_valid; 295 296 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); 297 298 return da_is_valid; 299 } 300 301 /** 302 * hal_rx_msdu_end_last_msdu_get_8074v2: API to get last msdu status 303 * from rx_msdu_end TLV 304 * 305 * @ buf: pointer to the start of RX PKT TLV headers 306 * Return: last_msdu 307 */ 308 static uint8_t hal_rx_msdu_end_last_msdu_get_8074v2(uint8_t *buf) 309 { 310 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 311 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 312 uint8_t last_msdu; 313 314 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); 315 316 return last_msdu; 317 } 318 319 /* 320 * hal_rx_get_mpdu_mac_ad4_valid_8074v2(): Retrieves if mpdu 4th addr is valid 321 * 322 * @nbuf: Network buffer 323 * Returns: value of mpdu 4th address valid field 324 */ 325 static bool hal_rx_get_mpdu_mac_ad4_valid_8074v2(uint8_t *buf) 326 { 327 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 328 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 329 bool ad4_valid = 0; 330 331 ad4_valid = HAL_RX_MPDU_GET_MAC_AD4_VALID(rx_mpdu_info); 332 333 return ad4_valid; 334 } 335 336 /** 337 * hal_rx_mpdu_start_sw_peer_id_get_8074v2: Retrieve sw peer_id 338 * @buf: network buffer 339 * 340 * Return: sw peer_id 341 */ 342 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_8074v2(uint8_t *buf) 343 { 344 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 345 struct rx_mpdu_start *mpdu_start = 346 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 347 348 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET( 349 &mpdu_start->rx_mpdu_info_details); 350 } 351 352 /* 353 * hal_rx_mpdu_get_to_ds_8074v2(): API to get the tods info 354 * from rx_mpdu_start 355 * 356 * @buf: pointer to the start of RX PKT TLV header 357 * Return: uint32_t(to_ds) 358 */ 359 static uint32_t hal_rx_mpdu_get_to_ds_8074v2(uint8_t *buf) 360 { 361 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 362 struct rx_mpdu_start *mpdu_start = 363 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 364 365 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 366 367 return HAL_RX_MPDU_GET_TODS(mpdu_info); 368 } 369 370 /* 371 * hal_rx_mpdu_get_fr_ds_8074v2(): API to get the from ds info 372 * from rx_mpdu_start 373 * 374 * @buf: pointer to the start of RX PKT TLV header 375 * Return: uint32_t(fr_ds) 376 */ 377 static uint32_t hal_rx_mpdu_get_fr_ds_8074v2(uint8_t *buf) 378 { 379 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 380 struct rx_mpdu_start *mpdu_start = 381 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 382 383 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 384 385 return HAL_RX_MPDU_GET_FROMDS(mpdu_info); 386 } 387 388 /* 389 * hal_rx_get_mpdu_frame_control_valid_8074v2(): Retrieves mpdu 390 * frame control valid 391 * 392 * @nbuf: Network buffer 393 * Returns: value of frame control valid field 394 */ 395 static uint8_t hal_rx_get_mpdu_frame_control_valid_8074v2(uint8_t *buf) 396 { 397 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 398 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 399 400 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); 401 } 402 403 /** 404 * hal_rx_get_mpdu_frame_control_field_8074v2(): Function to 405 * retrieve frame control field 406 * 407 * @nbuf: Network buffer 408 * Returns: value of frame control field 409 * 410 */ 411 static uint16_t hal_rx_get_mpdu_frame_control_field_8074v2(uint8_t *buf) 412 { 413 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 414 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 415 uint16_t frame_ctrl = 0; 416 417 frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info); 418 419 return frame_ctrl; 420 } 421 422 /* 423 * hal_rx_mpdu_get_addr1_8074v2(): API to check get address1 of the mpdu 424 * 425 * @buf: pointer to the start of RX PKT TLV headera 426 * @mac_addr: pointer to mac address 427 * Return: success/failure 428 */ 429 static QDF_STATUS hal_rx_mpdu_get_addr1_8074v2(uint8_t *buf, uint8_t *mac_addr) 430 { 431 struct __attribute__((__packed__)) hal_addr1 { 432 uint32_t ad1_31_0; 433 uint16_t ad1_47_32; 434 }; 435 436 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 437 struct rx_mpdu_start *mpdu_start = 438 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 439 440 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 441 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; 442 uint32_t mac_addr_ad1_valid; 443 444 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); 445 446 if (mac_addr_ad1_valid) { 447 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); 448 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); 449 return QDF_STATUS_SUCCESS; 450 } 451 452 return QDF_STATUS_E_FAILURE; 453 } 454 455 /* 456 * hal_rx_mpdu_get_addr2_8074v2(): API to check get address2 of the mpdu 457 * in the packet 458 * 459 * @buf: pointer to the start of RX PKT TLV header 460 * @mac_addr: pointer to mac address 461 * Return: success/failure 462 */ 463 static QDF_STATUS hal_rx_mpdu_get_addr2_8074v2(uint8_t *buf, uint8_t *mac_addr) 464 { 465 struct __attribute__((__packed__)) hal_addr2 { 466 uint16_t ad2_15_0; 467 uint32_t ad2_47_16; 468 }; 469 470 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 471 struct rx_mpdu_start *mpdu_start = 472 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 473 474 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 475 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; 476 uint32_t mac_addr_ad2_valid; 477 478 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); 479 480 if (mac_addr_ad2_valid) { 481 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); 482 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); 483 return QDF_STATUS_SUCCESS; 484 } 485 486 return QDF_STATUS_E_FAILURE; 487 } 488 489 /* 490 * hal_rx_mpdu_get_addr3_8074v2(): API to get address3 of the mpdu 491 * in the packet 492 * 493 * @buf: pointer to the start of RX PKT TLV header 494 * @mac_addr: pointer to mac address 495 * Return: success/failure 496 */ 497 static QDF_STATUS hal_rx_mpdu_get_addr3_8074v2(uint8_t *buf, uint8_t *mac_addr) 498 { 499 struct __attribute__((__packed__)) hal_addr3 { 500 uint32_t ad3_31_0; 501 uint16_t ad3_47_32; 502 }; 503 504 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 505 struct rx_mpdu_start *mpdu_start = 506 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 507 508 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 509 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; 510 uint32_t mac_addr_ad3_valid; 511 512 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); 513 514 if (mac_addr_ad3_valid) { 515 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); 516 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); 517 return QDF_STATUS_SUCCESS; 518 } 519 520 return QDF_STATUS_E_FAILURE; 521 } 522 523 /* 524 * hal_rx_mpdu_get_addr4_8074v2(): API to get address4 of the mpdu 525 * in the packet 526 * 527 * @buf: pointer to the start of RX PKT TLV header 528 * @mac_addr: pointer to mac address 529 * Return: success/failure 530 */ 531 static QDF_STATUS hal_rx_mpdu_get_addr4_8074v2(uint8_t *buf, uint8_t *mac_addr) 532 { 533 struct __attribute__((__packed__)) hal_addr4 { 534 uint32_t ad4_31_0; 535 uint16_t ad4_47_32; 536 }; 537 538 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 539 struct rx_mpdu_start *mpdu_start = 540 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 541 542 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 543 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; 544 uint32_t mac_addr_ad4_valid; 545 546 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); 547 548 if (mac_addr_ad4_valid) { 549 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); 550 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); 551 return QDF_STATUS_SUCCESS; 552 } 553 554 return QDF_STATUS_E_FAILURE; 555 } 556 557 /* 558 * hal_rx_get_mpdu_sequence_control_valid_8074v2(): Get mpdu 559 * sequence control valid 560 * 561 * @nbuf: Network buffer 562 * Returns: value of sequence control valid field 563 */ 564 static uint8_t hal_rx_get_mpdu_sequence_control_valid_8074v2(uint8_t *buf) 565 { 566 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 567 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 568 569 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); 570 } 571 572 /** 573 * hal_rx_is_unicast_8074v2: check packet is unicast frame or not. 574 * 575 * @ buf: pointer to rx pkt TLV. 576 * 577 * Return: true on unicast. 578 */ 579 static bool hal_rx_is_unicast_8074v2(uint8_t *buf) 580 { 581 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 582 struct rx_mpdu_start *mpdu_start = 583 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 584 uint32_t grp_id; 585 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 586 587 grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 588 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_OFFSET)), 589 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_MASK, 590 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_LSB)); 591 592 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false; 593 } 594 595 /** 596 * hal_rx_tid_get_8074v2: get tid based on qos control valid. 597 * @hal_soc_hdl: hal soc handle 598 * @buf: pointer to rx pkt TLV. 599 * 600 * Return: tid 601 */ 602 static uint32_t hal_rx_tid_get_8074v2(hal_soc_handle_t hal_soc_hdl, 603 uint8_t *buf) 604 { 605 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 606 struct rx_mpdu_start *mpdu_start = 607 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 608 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 609 uint8_t qos_control_valid = 610 (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 611 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)), 612 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK, 613 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB)); 614 615 if (qos_control_valid) 616 return hal_rx_mpdu_start_tid_get_8074v2(buf); 617 618 return HAL_RX_NON_QOS_TID; 619 } 620 621 /** 622 * hal_rx_hw_desc_get_ppduid_get_8074v2(): retrieve ppdu id 623 * @rx_tlv_hdr: packtet rx tlv header 624 * @rxdma_dst_ring_desc: rxdma HW descriptor 625 * 626 * Return: ppdu id 627 */ 628 static uint32_t hal_rx_hw_desc_get_ppduid_get_8074v2(void *rx_tlv_hdr, 629 void *rxdma_dst_ring_desc) 630 { 631 struct rx_mpdu_info *rx_mpdu_info; 632 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 633 634 rx_mpdu_info = 635 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 636 637 return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_0, PHY_PPDU_ID); 638 } 639 640 /** 641 * hal_reo_status_get_header_8074v2 - Process reo desc info 642 * @ring_desc: REO status ring descriptor 643 * @b - tlv type info 644 * @h1 - Pointer to hal_reo_status_header where info to be stored 645 * 646 * Return - none. 647 * 648 */ 649 static void hal_reo_status_get_header_8074v2(hal_ring_desc_t ring_desc, int b, 650 void *h1) 651 { 652 uint32_t *d = (uint32_t *)ring_desc; 653 uint32_t val1 = 0; 654 struct hal_reo_status_header *h = 655 (struct hal_reo_status_header *)h1; 656 657 /* Offsets of descriptor fields defined in HW headers start 658 * from the field after TLV header 659 */ 660 d += HAL_GET_NUM_DWORDS(sizeof(struct tlv_32_hdr)); 661 662 switch (b) { 663 case HAL_REO_QUEUE_STATS_STATUS_TLV: 664 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, 665 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 666 break; 667 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 668 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, 669 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 670 break; 671 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 672 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, 673 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 674 break; 675 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 676 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, 677 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 678 break; 679 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 680 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, 681 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 682 break; 683 case HAL_REO_DESC_THRES_STATUS_TLV: 684 val1 = 685 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, 686 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 687 break; 688 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 689 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, 690 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 691 break; 692 default: 693 qdf_nofl_err("ERROR: Unknown tlv\n"); 694 break; 695 } 696 h->cmd_num = 697 HAL_GET_FIELD( 698 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, 699 val1); 700 h->exec_time = 701 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 702 CMD_EXECUTION_TIME, val1); 703 h->status = 704 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 705 REO_CMD_EXECUTION_STATUS, val1); 706 switch (b) { 707 case HAL_REO_QUEUE_STATS_STATUS_TLV: 708 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, 709 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 710 break; 711 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 712 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, 713 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 714 break; 715 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 716 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, 717 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 718 break; 719 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 720 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, 721 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 722 break; 723 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 724 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, 725 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 726 break; 727 case HAL_REO_DESC_THRES_STATUS_TLV: 728 val1 = 729 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, 730 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 731 break; 732 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 733 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, 734 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 735 break; 736 default: 737 qdf_nofl_err("ERROR: Unknown tlv\n"); 738 break; 739 } 740 h->tstamp = 741 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); 742 } 743 744 /** 745 * hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v2(): 746 * Retrieve qos control valid bit from the tlv. 747 * @buf: pointer to rx pkt TLV. 748 * 749 * Return: qos control value. 750 */ 751 static inline uint32_t 752 hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v2(uint8_t *buf) 753 { 754 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 755 struct rx_mpdu_start *mpdu_start = 756 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 757 758 return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET( 759 &mpdu_start->rx_mpdu_info_details); 760 } 761 762 /** 763 * hal_rx_msdu_end_sa_sw_peer_id_get_8074v2(): API to get the 764 * sa_sw_peer_id from rx_msdu_end TLV 765 * @buf: pointer to the start of RX PKT TLV headers 766 * 767 * Return: sa_sw_peer_id index 768 */ 769 static inline uint32_t 770 hal_rx_msdu_end_sa_sw_peer_id_get_8074v2(uint8_t *buf) 771 { 772 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 773 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 774 775 return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 776 } 777 778 /** 779 * hal_tx_desc_set_mesh_en_8074v2 - Set mesh_enable flag in Tx descriptor 780 * @desc: Handle to Tx Descriptor 781 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 782 * enabling the interpretation of the 'Mesh Control Present' bit 783 * (bit 8) of QoS Control (otherwise this bit is ignored), 784 * For native WiFi frames, this indicates that a 'Mesh Control' field 785 * is present between the header and the LLC. 786 * 787 * Return: void 788 */ 789 static inline 790 void hal_tx_desc_set_mesh_en_8074v2(void *desc, uint8_t en) 791 { 792 HAL_SET_FLD(desc, TCL_DATA_CMD_4, MESH_ENABLE) |= 793 HAL_TX_SM(TCL_DATA_CMD_4, MESH_ENABLE, en); 794 } 795 796 static 797 void *hal_rx_msdu0_buffer_addr_lsb_8074v2(void *link_desc_va) 798 { 799 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 800 } 801 802 static 803 void *hal_rx_msdu_desc_info_ptr_get_8074v2(void *msdu0) 804 { 805 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 806 } 807 808 static 809 void *hal_ent_mpdu_desc_info_8074v2(void *ent_ring_desc) 810 { 811 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 812 } 813 814 static 815 void *hal_dst_mpdu_desc_info_8074v2(void *dst_ring_desc) 816 { 817 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 818 } 819 820 static 821 uint8_t hal_rx_get_fc_valid_8074v2(uint8_t *buf) 822 { 823 return HAL_RX_GET_FC_VALID(buf); 824 } 825 826 static uint8_t hal_rx_get_to_ds_flag_8074v2(uint8_t *buf) 827 { 828 return HAL_RX_GET_TO_DS_FLAG(buf); 829 } 830 831 static uint8_t hal_rx_get_mac_addr2_valid_8074v2(uint8_t *buf) 832 { 833 return HAL_RX_GET_MAC_ADDR2_VALID(buf); 834 } 835 836 static uint8_t hal_rx_get_filter_category_8074v2(uint8_t *buf) 837 { 838 return HAL_RX_GET_FILTER_CATEGORY(buf); 839 } 840 841 static uint32_t 842 hal_rx_get_ppdu_id_8074v2(uint8_t *buf) 843 { 844 struct rx_mpdu_info *rx_mpdu_info; 845 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)buf; 846 847 rx_mpdu_info = 848 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 849 850 return HAL_RX_GET_PPDU_ID(rx_mpdu_info); 851 } 852 853 /** 854 * hal_reo_config_8074v2(): Set reo config parameters 855 * @soc: hal soc handle 856 * @reg_val: value to be set 857 * @reo_params: reo parameters 858 * 859 * Return: void 860 */ 861 static void 862 hal_reo_config_8074v2(struct hal_soc *soc, 863 uint32_t reg_val, 864 struct hal_reo_params *reo_params) 865 { 866 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 867 } 868 869 /** 870 * hal_rx_msdu_desc_info_get_ptr_8074v2() - Get msdu desc info ptr 871 * @msdu_details_ptr - Pointer to msdu_details_ptr 872 * 873 * Return - Pointer to rx_msdu_desc_info structure. 874 * 875 */ 876 static void *hal_rx_msdu_desc_info_get_ptr_8074v2(void *msdu_details_ptr) 877 { 878 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 879 } 880 881 /** 882 * hal_rx_link_desc_msdu0_ptr_8074v2 - Get pointer to rx_msdu details 883 * @link_desc - Pointer to link desc 884 * 885 * Return - Pointer to rx_msdu_details structure 886 * 887 */ 888 static void *hal_rx_link_desc_msdu0_ptr_8074v2(void *link_desc) 889 { 890 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 891 } 892 893 /** 894 * hal_rx_msdu_flow_idx_get_8074v2: API to get flow index 895 * from rx_msdu_end TLV 896 * @buf: pointer to the start of RX PKT TLV headers 897 * 898 * Return: flow index value from MSDU END TLV 899 */ 900 static inline uint32_t hal_rx_msdu_flow_idx_get_8074v2(uint8_t *buf) 901 { 902 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 903 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 904 905 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 906 } 907 908 /** 909 * hal_rx_msdu_flow_idx_invalid_8074v2: API to get flow index invalid 910 * from rx_msdu_end TLV 911 * @buf: pointer to the start of RX PKT TLV headers 912 * 913 * Return: flow index invalid value from MSDU END TLV 914 */ 915 static bool hal_rx_msdu_flow_idx_invalid_8074v2(uint8_t *buf) 916 { 917 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 918 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 919 920 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 921 } 922 923 /** 924 * hal_rx_msdu_flow_idx_timeout_8074v2: API to get flow index timeout 925 * from rx_msdu_end TLV 926 * @buf: pointer to the start of RX PKT TLV headers 927 * 928 * Return: flow index timeout value from MSDU END TLV 929 */ 930 static bool hal_rx_msdu_flow_idx_timeout_8074v2(uint8_t *buf) 931 { 932 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 933 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 934 935 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 936 } 937 938 /** 939 * hal_rx_msdu_fse_metadata_get_8074v2: API to get FSE metadata 940 * from rx_msdu_end TLV 941 * @buf: pointer to the start of RX PKT TLV headers 942 * 943 * Return: fse metadata value from MSDU END TLV 944 */ 945 static uint32_t hal_rx_msdu_fse_metadata_get_8074v2(uint8_t *buf) 946 { 947 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 948 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 949 950 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end); 951 } 952 953 /** 954 * hal_rx_msdu_cce_metadata_get_8074v2: API to get CCE metadata 955 * from rx_msdu_end TLV 956 * @buf: pointer to the start of RX PKT TLV headers 957 * 958 * Return: cce_metadata 959 */ 960 static uint16_t 961 hal_rx_msdu_cce_metadata_get_8074v2(uint8_t *buf) 962 { 963 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 964 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 965 966 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end); 967 } 968 969 /** 970 * hal_rx_msdu_get_flow_params_8074v2: API to get flow index, flow index invalid 971 * and flow index timeout from rx_msdu_end TLV 972 * @buf: pointer to the start of RX PKT TLV headers 973 * @flow_invalid: pointer to return value of flow_idx_valid 974 * @flow_timeout: pointer to return value of flow_idx_timeout 975 * @flow_index: pointer to return value of flow_idx 976 * 977 * Return: none 978 */ 979 static inline void 980 hal_rx_msdu_get_flow_params_8074v2(uint8_t *buf, 981 bool *flow_invalid, 982 bool *flow_timeout, 983 uint32_t *flow_index) 984 { 985 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 986 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 987 988 *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 989 *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 990 *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 991 } 992 993 /** 994 * hal_rx_tlv_get_tcp_chksum_8074v2() - API to get tcp checksum 995 * @buf: rx_tlv_hdr 996 * 997 * Return: tcp checksum 998 */ 999 static uint16_t 1000 hal_rx_tlv_get_tcp_chksum_8074v2(uint8_t *buf) 1001 { 1002 return HAL_RX_TLV_GET_TCP_CHKSUM(buf); 1003 } 1004 1005 /** 1006 * hal_rx_get_rx_sequence_8074v2(): Function to retrieve rx sequence number 1007 * 1008 * @nbuf: Network buffer 1009 * Returns: rx sequence number 1010 */ 1011 static 1012 uint16_t hal_rx_get_rx_sequence_8074v2(uint8_t *buf) 1013 { 1014 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 1015 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 1016 1017 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info); 1018 } 1019 1020 /** 1021 * hal_get_window_address_8074v2(): Function to get hp/tp address 1022 * @hal_soc: Pointer to hal_soc 1023 * @addr: address offset of register 1024 * 1025 * Return: modified address offset of register 1026 */ 1027 static inline qdf_iomem_t hal_get_window_address_8074v2(struct hal_soc *hal_soc, 1028 qdf_iomem_t addr) 1029 { 1030 return addr; 1031 } 1032 1033 /** 1034 * hal_rx_mpdu_start_tlv_tag_valid_8074v2 () - API to check if RX_MPDU_START 1035 * tlv tag is valid 1036 * 1037 * @rx_tlv_hdr: start address of rx_pkt_tlvs 1038 * 1039 * Return: true if RX_MPDU_START is valid, else false. 1040 */ 1041 uint8_t hal_rx_mpdu_start_tlv_tag_valid_8074v2(void *rx_tlv_hdr) 1042 { 1043 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 1044 uint32_t tlv_tag; 1045 1046 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(&rx_desc->mpdu_start_tlv); 1047 1048 return tlv_tag == WIFIRX_MPDU_START_E ? true : false; 1049 } 1050 1051 /** 1052 * hal_rx_flow_setup_fse_8074v2() - Setup a flow search entry in HW FST 1053 * @fst: Pointer to the Rx Flow Search Table 1054 * @table_offset: offset into the table where the flow is to be setup 1055 * @flow: Flow Parameters 1056 * 1057 * Return: Success/Failure 1058 */ 1059 static void * 1060 hal_rx_flow_setup_fse_8074v2(uint8_t *rx_fst, uint32_t table_offset, 1061 uint8_t *rx_flow) 1062 { 1063 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 1064 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 1065 uint8_t *fse; 1066 bool fse_valid; 1067 1068 if (table_offset >= fst->max_entries) { 1069 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 1070 "HAL FSE table offset %u exceeds max entries %u", 1071 table_offset, fst->max_entries); 1072 return NULL; 1073 } 1074 1075 fse = (uint8_t *)fst->base_vaddr + 1076 (table_offset * HAL_RX_FST_ENTRY_SIZE); 1077 1078 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1079 1080 if (fse_valid) { 1081 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 1082 "HAL FSE %pK already valid", fse); 1083 return NULL; 1084 } 1085 1086 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96) = 1087 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96, 1088 qdf_htonl(flow->tuple_info.src_ip_127_96)); 1089 1090 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64) = 1091 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64, 1092 qdf_htonl(flow->tuple_info.src_ip_95_64)); 1093 1094 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32) = 1095 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32, 1096 qdf_htonl(flow->tuple_info.src_ip_63_32)); 1097 1098 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0) = 1099 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0, 1100 qdf_htonl(flow->tuple_info.src_ip_31_0)); 1101 1102 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96) = 1103 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96, 1104 qdf_htonl(flow->tuple_info.dest_ip_127_96)); 1105 1106 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64) = 1107 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64, 1108 qdf_htonl(flow->tuple_info.dest_ip_95_64)); 1109 1110 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32) = 1111 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32, 1112 qdf_htonl(flow->tuple_info.dest_ip_63_32)); 1113 1114 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0) = 1115 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0, 1116 qdf_htonl(flow->tuple_info.dest_ip_31_0)); 1117 1118 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT); 1119 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT) |= 1120 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, DEST_PORT, 1121 (flow->tuple_info.dest_port)); 1122 1123 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT); 1124 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT) |= 1125 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, SRC_PORT, 1126 (flow->tuple_info.src_port)); 1127 1128 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL); 1129 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL) |= 1130 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL, 1131 flow->tuple_info.l4_protocol); 1132 1133 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER); 1134 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER) |= 1135 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER, 1136 flow->reo_destination_handler); 1137 1138 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1139 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID) |= 1140 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, VALID, 1); 1141 1142 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA); 1143 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA) = 1144 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_10, METADATA, 1145 flow->fse_metadata); 1146 1147 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, REO_DESTINATION_INDICATION); 1148 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, REO_DESTINATION_INDICATION) |= 1149 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_11, 1150 REO_DESTINATION_INDICATION, 1151 flow->reo_destination_indication); 1152 1153 /* Reset all the other fields in FSE */ 1154 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, RESERVED_9); 1155 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_DROP); 1156 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, RESERVED_11); 1157 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_COUNT); 1158 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_12, MSDU_BYTE_COUNT); 1159 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_13, TIMESTAMP); 1160 1161 return fse; 1162 } 1163 1164 static 1165 void hal_compute_reo_remap_ix2_ix3_8074v2(uint32_t *ring, uint32_t num_rings, 1166 uint32_t *remap1, uint32_t *remap2) 1167 { 1168 switch (num_rings) { 1169 case 1: 1170 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1171 HAL_REO_REMAP_IX2(ring[0], 17) | 1172 HAL_REO_REMAP_IX2(ring[0], 18) | 1173 HAL_REO_REMAP_IX2(ring[0], 19) | 1174 HAL_REO_REMAP_IX2(ring[0], 20) | 1175 HAL_REO_REMAP_IX2(ring[0], 21) | 1176 HAL_REO_REMAP_IX2(ring[0], 22) | 1177 HAL_REO_REMAP_IX2(ring[0], 23); 1178 1179 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1180 HAL_REO_REMAP_IX3(ring[0], 25) | 1181 HAL_REO_REMAP_IX3(ring[0], 26) | 1182 HAL_REO_REMAP_IX3(ring[0], 27) | 1183 HAL_REO_REMAP_IX3(ring[0], 28) | 1184 HAL_REO_REMAP_IX3(ring[0], 29) | 1185 HAL_REO_REMAP_IX3(ring[0], 30) | 1186 HAL_REO_REMAP_IX3(ring[0], 31); 1187 break; 1188 case 2: 1189 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1190 HAL_REO_REMAP_IX2(ring[0], 17) | 1191 HAL_REO_REMAP_IX2(ring[1], 18) | 1192 HAL_REO_REMAP_IX2(ring[1], 19) | 1193 HAL_REO_REMAP_IX2(ring[0], 20) | 1194 HAL_REO_REMAP_IX2(ring[0], 21) | 1195 HAL_REO_REMAP_IX2(ring[1], 22) | 1196 HAL_REO_REMAP_IX2(ring[1], 23); 1197 1198 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1199 HAL_REO_REMAP_IX3(ring[0], 25) | 1200 HAL_REO_REMAP_IX3(ring[1], 26) | 1201 HAL_REO_REMAP_IX3(ring[1], 27) | 1202 HAL_REO_REMAP_IX3(ring[0], 28) | 1203 HAL_REO_REMAP_IX3(ring[0], 29) | 1204 HAL_REO_REMAP_IX3(ring[1], 30) | 1205 HAL_REO_REMAP_IX3(ring[1], 31); 1206 break; 1207 case 3: 1208 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1209 HAL_REO_REMAP_IX2(ring[1], 17) | 1210 HAL_REO_REMAP_IX2(ring[2], 18) | 1211 HAL_REO_REMAP_IX2(ring[0], 19) | 1212 HAL_REO_REMAP_IX2(ring[1], 20) | 1213 HAL_REO_REMAP_IX2(ring[2], 21) | 1214 HAL_REO_REMAP_IX2(ring[0], 22) | 1215 HAL_REO_REMAP_IX2(ring[1], 23); 1216 1217 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) | 1218 HAL_REO_REMAP_IX3(ring[0], 25) | 1219 HAL_REO_REMAP_IX3(ring[1], 26) | 1220 HAL_REO_REMAP_IX3(ring[2], 27) | 1221 HAL_REO_REMAP_IX3(ring[0], 28) | 1222 HAL_REO_REMAP_IX3(ring[1], 29) | 1223 HAL_REO_REMAP_IX3(ring[2], 30) | 1224 HAL_REO_REMAP_IX3(ring[0], 31); 1225 break; 1226 case 4: 1227 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1228 HAL_REO_REMAP_IX2(ring[1], 17) | 1229 HAL_REO_REMAP_IX2(ring[2], 18) | 1230 HAL_REO_REMAP_IX2(ring[3], 19) | 1231 HAL_REO_REMAP_IX2(ring[0], 20) | 1232 HAL_REO_REMAP_IX2(ring[1], 21) | 1233 HAL_REO_REMAP_IX2(ring[2], 22) | 1234 HAL_REO_REMAP_IX2(ring[3], 23); 1235 1236 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1237 HAL_REO_REMAP_IX3(ring[1], 25) | 1238 HAL_REO_REMAP_IX3(ring[2], 26) | 1239 HAL_REO_REMAP_IX3(ring[3], 27) | 1240 HAL_REO_REMAP_IX3(ring[0], 28) | 1241 HAL_REO_REMAP_IX3(ring[1], 29) | 1242 HAL_REO_REMAP_IX3(ring[2], 30) | 1243 HAL_REO_REMAP_IX3(ring[3], 31); 1244 break; 1245 } 1246 } 1247 1248 static void hal_hw_txrx_ops_attach_qca8074v2(struct hal_soc *hal_soc) 1249 { 1250 1251 /* init and setup */ 1252 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic; 1253 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic; 1254 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic; 1255 hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_li; 1256 hal_soc->ops->hal_get_window_address = hal_get_window_address_8074v2; 1257 1258 /* tx */ 1259 hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id = 1260 hal_tx_desc_set_dscp_tid_table_id_8074v2; 1261 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_8074v2; 1262 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_8074v2; 1263 hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_8074v2; 1264 hal_soc->ops->hal_tx_desc_set_buf_addr = 1265 hal_tx_desc_set_buf_addr_generic_li; 1266 hal_soc->ops->hal_tx_desc_set_search_type = 1267 hal_tx_desc_set_search_type_generic_li; 1268 hal_soc->ops->hal_tx_desc_set_search_index = 1269 hal_tx_desc_set_search_index_generic_li; 1270 hal_soc->ops->hal_tx_desc_set_cache_set_num = 1271 hal_tx_desc_set_cache_set_num_generic_li; 1272 hal_soc->ops->hal_tx_comp_get_status = 1273 hal_tx_comp_get_status_generic_li; 1274 hal_soc->ops->hal_tx_comp_get_release_reason = 1275 hal_tx_comp_get_release_reason_generic_li; 1276 hal_soc->ops->hal_get_wbm_internal_error = 1277 hal_get_wbm_internal_error_generic_li; 1278 hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_8074v2; 1279 hal_soc->ops->hal_tx_init_cmd_credit_ring = 1280 hal_tx_init_cmd_credit_ring_8074v2; 1281 1282 /* rx */ 1283 hal_soc->ops->hal_rx_msdu_start_nss_get = 1284 hal_rx_msdu_start_nss_get_8074v2; 1285 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status = 1286 hal_rx_mon_hw_desc_get_mpdu_status_8074v2; 1287 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_8074v2; 1288 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv = 1289 hal_rx_proc_phyrx_other_receive_info_tlv_8074v2; 1290 hal_soc->ops->hal_rx_dump_msdu_start_tlv = 1291 hal_rx_dump_msdu_start_tlv_8074v2; 1292 hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_8074v2; 1293 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_8074v2; 1294 hal_soc->ops->hal_rx_mpdu_start_tid_get = 1295 hal_rx_mpdu_start_tid_get_8074v2; 1296 hal_soc->ops->hal_rx_msdu_start_reception_type_get = 1297 hal_rx_msdu_start_reception_type_get_8074v2; 1298 hal_soc->ops->hal_rx_msdu_end_da_idx_get = 1299 hal_rx_msdu_end_da_idx_get_8074v2; 1300 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = 1301 hal_rx_msdu_desc_info_get_ptr_8074v2; 1302 hal_soc->ops->hal_rx_link_desc_msdu0_ptr = 1303 hal_rx_link_desc_msdu0_ptr_8074v2; 1304 hal_soc->ops->hal_reo_status_get_header = 1305 hal_reo_status_get_header_8074v2; 1306 hal_soc->ops->hal_rx_status_get_tlv_info = 1307 hal_rx_status_get_tlv_info_generic_li; 1308 hal_soc->ops->hal_rx_wbm_err_info_get = 1309 hal_rx_wbm_err_info_get_generic_li; 1310 hal_soc->ops->hal_rx_dump_mpdu_start_tlv = 1311 hal_rx_dump_mpdu_start_tlv_generic_li; 1312 1313 hal_soc->ops->hal_tx_set_pcp_tid_map = 1314 hal_tx_set_pcp_tid_map_generic_li; 1315 hal_soc->ops->hal_tx_update_pcp_tid_map = 1316 hal_tx_update_pcp_tid_generic_li; 1317 hal_soc->ops->hal_tx_set_tidmap_prty = 1318 hal_tx_update_tidmap_prty_generic_li; 1319 hal_soc->ops->hal_rx_get_rx_fragment_number = 1320 hal_rx_get_rx_fragment_number_8074v2; 1321 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = 1322 hal_rx_msdu_end_da_is_mcbc_get_8074v2; 1323 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = 1324 hal_rx_msdu_end_sa_is_valid_get_8074v2; 1325 hal_soc->ops->hal_rx_msdu_end_sa_idx_get = 1326 hal_rx_msdu_end_sa_idx_get_8074v2; 1327 hal_soc->ops->hal_rx_desc_is_first_msdu = 1328 hal_rx_desc_is_first_msdu_8074v2; 1329 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get = 1330 hal_rx_msdu_end_l3_hdr_padding_get_8074v2; 1331 hal_soc->ops->hal_rx_encryption_info_valid = 1332 hal_rx_encryption_info_valid_8074v2; 1333 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_8074v2; 1334 hal_soc->ops->hal_rx_msdu_end_first_msdu_get = 1335 hal_rx_msdu_end_first_msdu_get_8074v2; 1336 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = 1337 hal_rx_msdu_end_da_is_valid_get_8074v2; 1338 hal_soc->ops->hal_rx_msdu_end_last_msdu_get = 1339 hal_rx_msdu_end_last_msdu_get_8074v2; 1340 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = 1341 hal_rx_get_mpdu_mac_ad4_valid_8074v2; 1342 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get = 1343 hal_rx_mpdu_start_sw_peer_id_get_8074v2; 1344 hal_soc->ops->hal_rx_tlv_peer_meta_data_get = 1345 hal_rx_mpdu_peer_meta_data_get_li; 1346 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_8074v2; 1347 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_8074v2; 1348 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid = 1349 hal_rx_get_mpdu_frame_control_valid_8074v2; 1350 hal_soc->ops->hal_rx_get_frame_ctrl_field = 1351 hal_rx_get_mpdu_frame_control_field_8074v2; 1352 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_8074v2; 1353 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_8074v2; 1354 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_8074v2; 1355 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_8074v2; 1356 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid = 1357 hal_rx_get_mpdu_sequence_control_valid_8074v2; 1358 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_8074v2; 1359 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_8074v2; 1360 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = 1361 hal_rx_hw_desc_get_ppduid_get_8074v2; 1362 hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get = 1363 hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v2; 1364 hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get = 1365 hal_rx_msdu_end_sa_sw_peer_id_get_8074v2; 1366 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = 1367 hal_rx_msdu0_buffer_addr_lsb_8074v2; 1368 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = 1369 hal_rx_msdu_desc_info_ptr_get_8074v2; 1370 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_8074v2; 1371 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_8074v2; 1372 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_8074v2; 1373 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_8074v2; 1374 hal_soc->ops->hal_rx_get_mac_addr2_valid = 1375 hal_rx_get_mac_addr2_valid_8074v2; 1376 hal_soc->ops->hal_rx_get_filter_category = 1377 hal_rx_get_filter_category_8074v2; 1378 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_8074v2; 1379 hal_soc->ops->hal_reo_config = hal_reo_config_8074v2; 1380 hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_8074v2; 1381 hal_soc->ops->hal_rx_msdu_flow_idx_invalid = 1382 hal_rx_msdu_flow_idx_invalid_8074v2; 1383 hal_soc->ops->hal_rx_msdu_flow_idx_timeout = 1384 hal_rx_msdu_flow_idx_timeout_8074v2; 1385 hal_soc->ops->hal_rx_msdu_fse_metadata_get = 1386 hal_rx_msdu_fse_metadata_get_8074v2; 1387 hal_soc->ops->hal_rx_msdu_cce_match_get = 1388 hal_rx_msdu_cce_match_get_li; 1389 hal_soc->ops->hal_rx_msdu_cce_metadata_get = 1390 hal_rx_msdu_cce_metadata_get_8074v2; 1391 hal_soc->ops->hal_rx_msdu_get_flow_params = 1392 hal_rx_msdu_get_flow_params_8074v2; 1393 hal_soc->ops->hal_rx_tlv_get_tcp_chksum = 1394 hal_rx_tlv_get_tcp_chksum_8074v2; 1395 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_8074v2; 1396 #if defined(QCA_WIFI_QCA6018) && defined(WLAN_CFR_ENABLE) && \ 1397 defined(WLAN_ENH_CFR_ENABLE) 1398 hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_8074v2; 1399 hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_8074v2; 1400 #endif 1401 /* rx - msdu fast path info fields */ 1402 hal_soc->ops->hal_rx_msdu_packet_metadata_get = 1403 hal_rx_msdu_packet_metadata_get_generic_li; 1404 hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid = 1405 hal_rx_mpdu_start_tlv_tag_valid_8074v2; 1406 1407 /* rx - TLV struct offsets */ 1408 hal_soc->ops->hal_rx_msdu_end_offset_get = 1409 hal_rx_msdu_end_offset_get_generic; 1410 hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic; 1411 hal_soc->ops->hal_rx_msdu_start_offset_get = 1412 hal_rx_msdu_start_offset_get_generic; 1413 hal_soc->ops->hal_rx_mpdu_start_offset_get = 1414 hal_rx_mpdu_start_offset_get_generic; 1415 hal_soc->ops->hal_rx_mpdu_end_offset_get = 1416 hal_rx_mpdu_end_offset_get_generic; 1417 #ifndef NO_RX_PKT_HDR_TLV 1418 hal_soc->ops->hal_rx_pkt_tlv_offset_get = 1419 hal_rx_pkt_tlv_offset_get_generic; 1420 #endif 1421 hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_8074v2; 1422 hal_soc->ops->hal_rx_flow_get_tuple_info = 1423 hal_rx_flow_get_tuple_info_li; 1424 hal_soc->ops->hal_rx_flow_delete_entry = 1425 hal_rx_flow_delete_entry_li; 1426 hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_li; 1427 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = 1428 hal_compute_reo_remap_ix2_ix3_8074v2; 1429 hal_soc->ops->hal_setup_link_idle_list = 1430 hal_setup_link_idle_list_generic_li; 1431 hal_soc->ops->hal_compute_reo_remap_ix0 = NULL; 1432 }; 1433 1434 struct hal_hw_srng_config hw_srng_table_8074v2[] = { 1435 /* TODO: max_rings can populated by querying HW capabilities */ 1436 { /* REO_DST */ 1437 .start_ring_id = HAL_SRNG_REO2SW1, 1438 .max_rings = 4, 1439 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1440 .lmac_ring = FALSE, 1441 .ring_dir = HAL_SRNG_DST_RING, 1442 .reg_start = { 1443 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 1444 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1445 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 1446 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1447 }, 1448 .reg_size = { 1449 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 1450 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 1451 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 1452 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 1453 }, 1454 .max_size = 1455 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 1456 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 1457 }, 1458 { /* REO_EXCEPTION */ 1459 /* Designating REO2TCL ring as exception ring. This ring is 1460 * similar to other REO2SW rings though it is named as REO2TCL. 1461 * Any of theREO2SW rings can be used as exception ring. 1462 */ 1463 .start_ring_id = HAL_SRNG_REO2TCL, 1464 .max_rings = 1, 1465 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1466 .lmac_ring = FALSE, 1467 .ring_dir = HAL_SRNG_DST_RING, 1468 .reg_start = { 1469 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 1470 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1471 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 1472 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1473 }, 1474 /* Single ring - provide ring size if multiple rings of this 1475 * type are supported 1476 */ 1477 .reg_size = {}, 1478 .max_size = 1479 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 1480 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 1481 }, 1482 { /* REO_REINJECT */ 1483 .start_ring_id = HAL_SRNG_SW2REO, 1484 .max_rings = 1, 1485 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1486 .lmac_ring = FALSE, 1487 .ring_dir = HAL_SRNG_SRC_RING, 1488 .reg_start = { 1489 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 1490 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1491 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 1492 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1493 }, 1494 /* Single ring - provide ring size if multiple rings of this 1495 * type are supported 1496 */ 1497 .reg_size = {}, 1498 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 1499 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 1500 }, 1501 { /* REO_CMD */ 1502 .start_ring_id = HAL_SRNG_REO_CMD, 1503 .max_rings = 1, 1504 .entry_size = (sizeof(struct tlv_32_hdr) + 1505 sizeof(struct reo_get_queue_stats)) >> 2, 1506 .lmac_ring = FALSE, 1507 .ring_dir = HAL_SRNG_SRC_RING, 1508 .reg_start = { 1509 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 1510 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1511 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 1512 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1513 }, 1514 /* Single ring - provide ring size if multiple rings of this 1515 * type are supported 1516 */ 1517 .reg_size = {}, 1518 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1519 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1520 }, 1521 { /* REO_STATUS */ 1522 .start_ring_id = HAL_SRNG_REO_STATUS, 1523 .max_rings = 1, 1524 .entry_size = (sizeof(struct tlv_32_hdr) + 1525 sizeof(struct reo_get_queue_stats_status)) >> 2, 1526 .lmac_ring = FALSE, 1527 .ring_dir = HAL_SRNG_DST_RING, 1528 .reg_start = { 1529 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 1530 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1531 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 1532 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1533 }, 1534 /* Single ring - provide ring size if multiple rings of this 1535 * type are supported 1536 */ 1537 .reg_size = {}, 1538 .max_size = 1539 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1540 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1541 }, 1542 { /* TCL_DATA */ 1543 .start_ring_id = HAL_SRNG_SW2TCL1, 1544 .max_rings = 3, 1545 .entry_size = (sizeof(struct tlv_32_hdr) + 1546 sizeof(struct tcl_data_cmd)) >> 2, 1547 .lmac_ring = FALSE, 1548 .ring_dir = HAL_SRNG_SRC_RING, 1549 .reg_start = { 1550 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 1551 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1552 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 1553 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1554 }, 1555 .reg_size = { 1556 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 1557 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 1558 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 1559 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 1560 }, 1561 .max_size = 1562 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 1563 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 1564 }, 1565 { /* TCL_CMD */ 1566 /* qca8074v2 and qcn9000 uses this ring for data commands */ 1567 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 1568 .max_rings = 1, 1569 .entry_size = (sizeof(struct tlv_32_hdr) + 1570 sizeof(struct tcl_data_cmd)) >> 2, 1571 .lmac_ring = FALSE, 1572 .ring_dir = HAL_SRNG_SRC_RING, 1573 .reg_start = { 1574 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR( 1575 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1576 HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR( 1577 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1578 }, 1579 /* Single ring - provide ring size if multiple rings of this 1580 * type are supported 1581 */ 1582 .reg_size = {}, 1583 .max_size = 1584 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1585 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1586 }, 1587 { /* TCL_STATUS */ 1588 .start_ring_id = HAL_SRNG_TCL_STATUS, 1589 .max_rings = 1, 1590 .entry_size = (sizeof(struct tlv_32_hdr) + 1591 sizeof(struct tcl_status_ring)) >> 2, 1592 .lmac_ring = FALSE, 1593 .ring_dir = HAL_SRNG_DST_RING, 1594 .reg_start = { 1595 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 1596 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1597 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 1598 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1599 }, 1600 /* Single ring - provide ring size if multiple rings of this 1601 * type are supported 1602 */ 1603 .reg_size = {}, 1604 .max_size = 1605 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 1606 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 1607 }, 1608 { /* CE_SRC */ 1609 .start_ring_id = HAL_SRNG_CE_0_SRC, 1610 .max_rings = 12, 1611 .entry_size = sizeof(struct ce_src_desc) >> 2, 1612 .lmac_ring = FALSE, 1613 .ring_dir = HAL_SRNG_SRC_RING, 1614 .reg_start = { 1615 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1616 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1617 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1618 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1619 }, 1620 .reg_size = { 1621 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1622 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1623 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1624 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1625 }, 1626 .max_size = 1627 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1628 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1629 }, 1630 { /* CE_DST */ 1631 .start_ring_id = HAL_SRNG_CE_0_DST, 1632 .max_rings = 12, 1633 .entry_size = 8 >> 2, 1634 /*TODO: entry_size above should actually be 1635 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 1636 * of struct ce_dst_desc in HW header files 1637 */ 1638 .lmac_ring = FALSE, 1639 .ring_dir = HAL_SRNG_SRC_RING, 1640 .reg_start = { 1641 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1642 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1643 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1644 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1645 }, 1646 .reg_size = { 1647 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1648 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1649 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1650 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1651 }, 1652 .max_size = 1653 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1654 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1655 }, 1656 { /* CE_DST_STATUS */ 1657 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 1658 .max_rings = 12, 1659 .entry_size = sizeof(struct ce_stat_desc) >> 2, 1660 .lmac_ring = FALSE, 1661 .ring_dir = HAL_SRNG_DST_RING, 1662 .reg_start = { 1663 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 1664 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1665 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 1666 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1667 }, 1668 /* TODO: check destination status ring registers */ 1669 .reg_size = { 1670 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1671 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1672 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1673 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1674 }, 1675 .max_size = 1676 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1677 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1678 }, 1679 { /* WBM_IDLE_LINK */ 1680 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 1681 .max_rings = 1, 1682 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 1683 .lmac_ring = FALSE, 1684 .ring_dir = HAL_SRNG_SRC_RING, 1685 .reg_start = { 1686 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1687 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1688 }, 1689 /* Single ring - provide ring size if multiple rings of this 1690 * type are supported 1691 */ 1692 .reg_size = {}, 1693 .max_size = 1694 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 1695 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 1696 }, 1697 { /* SW2WBM_RELEASE */ 1698 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 1699 .max_rings = 1, 1700 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1701 .lmac_ring = FALSE, 1702 .ring_dir = HAL_SRNG_SRC_RING, 1703 .reg_start = { 1704 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1705 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1706 }, 1707 /* Single ring - provide ring size if multiple rings of this 1708 * type are supported 1709 */ 1710 .reg_size = {}, 1711 .max_size = 1712 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1713 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1714 }, 1715 { /* WBM2SW_RELEASE */ 1716 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 1717 .max_rings = 5, 1718 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1719 .lmac_ring = FALSE, 1720 .ring_dir = HAL_SRNG_DST_RING, 1721 .reg_start = { 1722 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1723 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1724 }, 1725 .reg_size = { 1726 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1727 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1728 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1729 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1730 }, 1731 .max_size = 1732 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1733 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1734 }, 1735 { /* RXDMA_BUF */ 1736 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 1737 #ifdef IPA_OFFLOAD 1738 .max_rings = 3, 1739 #else 1740 .max_rings = 2, 1741 #endif 1742 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1743 .lmac_ring = TRUE, 1744 .ring_dir = HAL_SRNG_SRC_RING, 1745 /* reg_start is not set because LMAC rings are not accessed 1746 * from host 1747 */ 1748 .reg_start = {}, 1749 .reg_size = {}, 1750 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1751 }, 1752 { /* RXDMA_DST */ 1753 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 1754 .max_rings = 1, 1755 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1756 .lmac_ring = TRUE, 1757 .ring_dir = HAL_SRNG_DST_RING, 1758 /* reg_start is not set because LMAC rings are not accessed 1759 * from host 1760 */ 1761 .reg_start = {}, 1762 .reg_size = {}, 1763 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1764 }, 1765 { /* RXDMA_MONITOR_BUF */ 1766 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 1767 .max_rings = 1, 1768 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1769 .lmac_ring = TRUE, 1770 .ring_dir = HAL_SRNG_SRC_RING, 1771 /* reg_start is not set because LMAC rings are not accessed 1772 * from host 1773 */ 1774 .reg_start = {}, 1775 .reg_size = {}, 1776 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1777 }, 1778 { /* RXDMA_MONITOR_STATUS */ 1779 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 1780 .max_rings = 1, 1781 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1782 .lmac_ring = TRUE, 1783 .ring_dir = HAL_SRNG_SRC_RING, 1784 /* reg_start is not set because LMAC rings are not accessed 1785 * from host 1786 */ 1787 .reg_start = {}, 1788 .reg_size = {}, 1789 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1790 }, 1791 { /* RXDMA_MONITOR_DST */ 1792 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 1793 .max_rings = 1, 1794 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1795 .lmac_ring = TRUE, 1796 .ring_dir = HAL_SRNG_DST_RING, 1797 /* reg_start is not set because LMAC rings are not accessed 1798 * from host 1799 */ 1800 .reg_start = {}, 1801 .reg_size = {}, 1802 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1803 }, 1804 { /* RXDMA_MONITOR_DESC */ 1805 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 1806 .max_rings = 1, 1807 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1808 .lmac_ring = TRUE, 1809 .ring_dir = HAL_SRNG_SRC_RING, 1810 /* reg_start is not set because LMAC rings are not accessed 1811 * from host 1812 */ 1813 .reg_start = {}, 1814 .reg_size = {}, 1815 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1816 }, 1817 { /* DIR_BUF_RX_DMA_SRC */ 1818 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 1819 /* one ring for spectral and one ring for cfr */ 1820 .max_rings = 2, 1821 .entry_size = 2, 1822 .lmac_ring = TRUE, 1823 .ring_dir = HAL_SRNG_SRC_RING, 1824 /* reg_start is not set because LMAC rings are not accessed 1825 * from host 1826 */ 1827 .reg_start = {}, 1828 .reg_size = {}, 1829 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1830 }, 1831 #ifdef WLAN_FEATURE_CIF_CFR 1832 { /* WIFI_POS_SRC */ 1833 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 1834 .max_rings = 1, 1835 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 1836 .lmac_ring = TRUE, 1837 .ring_dir = HAL_SRNG_SRC_RING, 1838 /* reg_start is not set because LMAC rings are not accessed 1839 * from host 1840 */ 1841 .reg_start = {}, 1842 .reg_size = {}, 1843 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1844 }, 1845 #endif 1846 { /* REO2PPE */ 0}, 1847 { /* PPE2TCL */ 0}, 1848 { /* PPE_RELEASE */ 0}, 1849 { /* TX_MONITOR_BUF */ 0}, 1850 { /* TX_MONITOR_DST */ 0}, 1851 { /* SW2RXDMA_NEW */ 0}, 1852 }; 1853 1854 1855 /** 1856 * hal_qca8074v2_attach() - Attach 8074v2 target specific hal_soc ops, 1857 * offset and srng table 1858 */ 1859 void hal_qca8074v2_attach(struct hal_soc *hal_soc) 1860 { 1861 hal_soc->hw_srng_table = hw_srng_table_8074v2; 1862 hal_srng_hw_reg_offset_init_generic(hal_soc); 1863 hal_hw_txrx_default_ops_attach_li(hal_soc); 1864 hal_hw_txrx_ops_attach_qca8074v2(hal_soc); 1865 } 1866