1 /* 2 * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #include "hal_hw_headers.h" 19 #include "hal_internal.h" 20 #include "hal_api.h" 21 #include "target_type.h" 22 #include "wcss_version.h" 23 #include "qdf_module.h" 24 #include "hal_flow.h" 25 #include "rx_flow_search_entry.h" 26 #include "hal_rx_flow_info.h" 27 28 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 29 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET 30 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 31 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK 32 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 33 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB 34 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 35 PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 36 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 37 PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 38 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 39 PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 40 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 41 PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 42 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 43 PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 44 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 45 PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 46 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 47 PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 48 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 49 PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 50 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 51 PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 52 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 53 PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 54 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 55 PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 56 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 57 RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 58 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 59 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 60 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 61 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 62 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 63 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 64 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 65 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 66 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER \ 67 STATUS_HEADER_REO_STATUS_NUMBER 68 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 69 STATUS_HEADER_TIMESTAMP 70 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 71 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 72 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 73 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 74 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 75 TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 76 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 77 TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 78 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 79 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 80 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 81 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 82 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 83 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 84 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 85 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 86 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 87 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 88 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 89 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 90 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 91 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 92 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 93 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 94 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 95 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 96 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 97 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 98 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 99 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 100 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 101 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 102 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 103 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 104 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 105 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 106 #include "hal_8074v2_tx.h" 107 #include "hal_8074v2_rx.h" 108 #include <hal_generic_api.h> 109 #include <hal_wbm.h> 110 111 /** 112 * hal_rx_get_rx_fragment_number_8074v2(): Function to retrieve 113 * rx fragment number 114 * 115 * @nbuf: Network buffer 116 * Returns: rx fragment number 117 */ 118 static 119 uint8_t hal_rx_get_rx_fragment_number_8074v2(uint8_t *buf) 120 { 121 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 122 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 123 124 /* Return first 4 bits as fragment number */ 125 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & 126 DOT11_SEQ_FRAG_MASK; 127 } 128 129 /** 130 * hal_rx_msdu_end_da_is_mcbc_get_8074v2: API to check if pkt is MCBC 131 * from rx_msdu_end TLV 132 * 133 * @ buf: pointer to the start of RX PKT TLV headers 134 * Return: da_is_mcbc 135 */ 136 static uint8_t 137 hal_rx_msdu_end_da_is_mcbc_get_8074v2(uint8_t *buf) 138 { 139 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 140 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 141 142 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); 143 } 144 145 /** 146 * hal_rx_msdu_end_sa_is_valid_get_8074v2(): API to get_8074v2 the 147 * sa_is_valid bit from rx_msdu_end TLV 148 * 149 * @ buf: pointer to the start of RX PKT TLV headers 150 * Return: sa_is_valid bit 151 */ 152 static uint8_t 153 hal_rx_msdu_end_sa_is_valid_get_8074v2(uint8_t *buf) 154 { 155 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 156 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 157 uint8_t sa_is_valid; 158 159 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); 160 161 return sa_is_valid; 162 } 163 164 /** 165 * hal_rx_msdu_end_sa_idx_get_8074v2(): API to get_8074v2 the 166 * sa_idx from rx_msdu_end TLV 167 * 168 * @ buf: pointer to the start of RX PKT TLV headers 169 * Return: sa_idx (SA AST index) 170 */ 171 static uint16_t hal_rx_msdu_end_sa_idx_get_8074v2(uint8_t *buf) 172 { 173 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 174 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 175 uint16_t sa_idx; 176 177 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 178 179 return sa_idx; 180 } 181 182 /** 183 * hal_rx_desc_is_first_msdu_8074v2() - Check if first msdu 184 * 185 * @hal_soc_hdl: hal_soc handle 186 * @hw_desc_addr: hardware descriptor address 187 * 188 * Return: 0 - success/ non-zero failure 189 */ 190 static uint32_t hal_rx_desc_is_first_msdu_8074v2(void *hw_desc_addr) 191 { 192 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; 193 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; 194 195 return HAL_RX_GET(msdu_end, RX_MSDU_END_5, FIRST_MSDU); 196 } 197 198 /** 199 * hal_rx_msdu_end_l3_hdr_padding_get_8074v2(): API to get_8074v2 the 200 * l3_header padding from rx_msdu_end TLV 201 * 202 * @ buf: pointer to the start of RX PKT TLV headers 203 * Return: number of l3 header padding bytes 204 */ 205 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_8074v2(uint8_t *buf) 206 { 207 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 208 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 209 uint32_t l3_header_padding; 210 211 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 212 213 return l3_header_padding; 214 } 215 216 /* 217 * @ hal_rx_encryption_info_valid_8074v2: Returns encryption type. 218 * 219 * @ buf: rx_tlv_hdr of the received packet 220 * @ Return: encryption type 221 */ 222 static uint32_t hal_rx_encryption_info_valid_8074v2(uint8_t *buf) 223 { 224 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 225 struct rx_mpdu_start *mpdu_start = 226 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 227 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 228 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); 229 230 return encryption_info; 231 } 232 233 /* 234 * @ hal_rx_print_pn_8074v2: Prints the PN of rx packet. 235 * 236 * @ buf: rx_tlv_hdr of the received packet 237 * @ Return: void 238 */ 239 static void hal_rx_print_pn_8074v2(uint8_t *buf) 240 { 241 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 242 struct rx_mpdu_start *mpdu_start = 243 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 244 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 245 246 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); 247 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); 248 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); 249 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); 250 251 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ", 252 pn_127_96, pn_95_64, pn_63_32, pn_31_0); 253 } 254 255 /** 256 * hal_rx_msdu_end_first_msdu_get_8074v2: API to get first msdu status 257 * from rx_msdu_end TLV 258 * 259 * @ buf: pointer to the start of RX PKT TLV headers 260 * Return: first_msdu 261 */ 262 static uint8_t hal_rx_msdu_end_first_msdu_get_8074v2(uint8_t *buf) 263 { 264 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 265 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 266 uint8_t first_msdu; 267 268 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); 269 270 return first_msdu; 271 } 272 273 /** 274 * hal_rx_msdu_end_da_is_valid_get_8074v2: API to check if da is valid 275 * from rx_msdu_end TLV 276 * 277 * @ buf: pointer to the start of RX PKT TLV headers 278 * Return: da_is_valid 279 */ 280 static uint8_t hal_rx_msdu_end_da_is_valid_get_8074v2(uint8_t *buf) 281 { 282 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 283 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 284 uint8_t da_is_valid; 285 286 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); 287 288 return da_is_valid; 289 } 290 291 /** 292 * hal_rx_msdu_end_last_msdu_get_8074v2: API to get last msdu status 293 * from rx_msdu_end TLV 294 * 295 * @ buf: pointer to the start of RX PKT TLV headers 296 * Return: last_msdu 297 */ 298 static uint8_t hal_rx_msdu_end_last_msdu_get_8074v2(uint8_t *buf) 299 { 300 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 301 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 302 uint8_t last_msdu; 303 304 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); 305 306 return last_msdu; 307 } 308 309 /* 310 * hal_rx_get_mpdu_mac_ad4_valid_8074v2(): Retrieves if mpdu 4th addr is valid 311 * 312 * @nbuf: Network buffer 313 * Returns: value of mpdu 4th address valid field 314 */ 315 static bool hal_rx_get_mpdu_mac_ad4_valid_8074v2(uint8_t *buf) 316 { 317 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 318 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 319 bool ad4_valid = 0; 320 321 ad4_valid = HAL_RX_MPDU_GET_MAC_AD4_VALID(rx_mpdu_info); 322 323 return ad4_valid; 324 } 325 326 /** 327 * hal_rx_mpdu_start_sw_peer_id_get_8074v2: Retrieve sw peer_id 328 * @buf: network buffer 329 * 330 * Return: sw peer_id 331 */ 332 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_8074v2(uint8_t *buf) 333 { 334 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 335 struct rx_mpdu_start *mpdu_start = 336 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 337 338 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET( 339 &mpdu_start->rx_mpdu_info_details); 340 } 341 342 /* 343 * hal_rx_mpdu_get_to_ds_8074v2(): API to get the tods info 344 * from rx_mpdu_start 345 * 346 * @buf: pointer to the start of RX PKT TLV header 347 * Return: uint32_t(to_ds) 348 */ 349 static uint32_t hal_rx_mpdu_get_to_ds_8074v2(uint8_t *buf) 350 { 351 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 352 struct rx_mpdu_start *mpdu_start = 353 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 354 355 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 356 357 return HAL_RX_MPDU_GET_TODS(mpdu_info); 358 } 359 360 /* 361 * hal_rx_mpdu_get_fr_ds_8074v2(): API to get the from ds info 362 * from rx_mpdu_start 363 * 364 * @buf: pointer to the start of RX PKT TLV header 365 * Return: uint32_t(fr_ds) 366 */ 367 static uint32_t hal_rx_mpdu_get_fr_ds_8074v2(uint8_t *buf) 368 { 369 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 370 struct rx_mpdu_start *mpdu_start = 371 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 372 373 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 374 375 return HAL_RX_MPDU_GET_FROMDS(mpdu_info); 376 } 377 378 /* 379 * hal_rx_get_mpdu_frame_control_valid_8074v2(): Retrieves mpdu 380 * frame control valid 381 * 382 * @nbuf: Network buffer 383 * Returns: value of frame control valid field 384 */ 385 static uint8_t hal_rx_get_mpdu_frame_control_valid_8074v2(uint8_t *buf) 386 { 387 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 388 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 389 390 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); 391 } 392 393 /* 394 * hal_rx_mpdu_get_addr1_8074v2(): API to check get address1 of the mpdu 395 * 396 * @buf: pointer to the start of RX PKT TLV headera 397 * @mac_addr: pointer to mac address 398 * Return: success/failure 399 */ 400 static QDF_STATUS hal_rx_mpdu_get_addr1_8074v2(uint8_t *buf, uint8_t *mac_addr) 401 { 402 struct __attribute__((__packed__)) hal_addr1 { 403 uint32_t ad1_31_0; 404 uint16_t ad1_47_32; 405 }; 406 407 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 408 struct rx_mpdu_start *mpdu_start = 409 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 410 411 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 412 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; 413 uint32_t mac_addr_ad1_valid; 414 415 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); 416 417 if (mac_addr_ad1_valid) { 418 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); 419 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); 420 return QDF_STATUS_SUCCESS; 421 } 422 423 return QDF_STATUS_E_FAILURE; 424 } 425 426 /* 427 * hal_rx_mpdu_get_addr2_8074v2(): API to check get address2 of the mpdu 428 * in the packet 429 * 430 * @buf: pointer to the start of RX PKT TLV header 431 * @mac_addr: pointer to mac address 432 * Return: success/failure 433 */ 434 static QDF_STATUS hal_rx_mpdu_get_addr2_8074v2(uint8_t *buf, uint8_t *mac_addr) 435 { 436 struct __attribute__((__packed__)) hal_addr2 { 437 uint16_t ad2_15_0; 438 uint32_t ad2_47_16; 439 }; 440 441 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 442 struct rx_mpdu_start *mpdu_start = 443 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 444 445 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 446 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; 447 uint32_t mac_addr_ad2_valid; 448 449 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); 450 451 if (mac_addr_ad2_valid) { 452 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); 453 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); 454 return QDF_STATUS_SUCCESS; 455 } 456 457 return QDF_STATUS_E_FAILURE; 458 } 459 460 /* 461 * hal_rx_mpdu_get_addr3_8074v2(): API to get address3 of the mpdu 462 * in the packet 463 * 464 * @buf: pointer to the start of RX PKT TLV header 465 * @mac_addr: pointer to mac address 466 * Return: success/failure 467 */ 468 static QDF_STATUS hal_rx_mpdu_get_addr3_8074v2(uint8_t *buf, uint8_t *mac_addr) 469 { 470 struct __attribute__((__packed__)) hal_addr3 { 471 uint32_t ad3_31_0; 472 uint16_t ad3_47_32; 473 }; 474 475 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 476 struct rx_mpdu_start *mpdu_start = 477 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 478 479 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 480 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; 481 uint32_t mac_addr_ad3_valid; 482 483 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); 484 485 if (mac_addr_ad3_valid) { 486 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); 487 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); 488 return QDF_STATUS_SUCCESS; 489 } 490 491 return QDF_STATUS_E_FAILURE; 492 } 493 494 /* 495 * hal_rx_mpdu_get_addr4_8074v2(): API to get address4 of the mpdu 496 * in the packet 497 * 498 * @buf: pointer to the start of RX PKT TLV header 499 * @mac_addr: pointer to mac address 500 * Return: success/failure 501 */ 502 static QDF_STATUS hal_rx_mpdu_get_addr4_8074v2(uint8_t *buf, uint8_t *mac_addr) 503 { 504 struct __attribute__((__packed__)) hal_addr4 { 505 uint32_t ad4_31_0; 506 uint16_t ad4_47_32; 507 }; 508 509 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 510 struct rx_mpdu_start *mpdu_start = 511 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 512 513 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 514 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; 515 uint32_t mac_addr_ad4_valid; 516 517 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); 518 519 if (mac_addr_ad4_valid) { 520 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); 521 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); 522 return QDF_STATUS_SUCCESS; 523 } 524 525 return QDF_STATUS_E_FAILURE; 526 } 527 528 /* 529 * hal_rx_get_mpdu_sequence_control_valid_8074v2(): Get mpdu 530 * sequence control valid 531 * 532 * @nbuf: Network buffer 533 * Returns: value of sequence control valid field 534 */ 535 static uint8_t hal_rx_get_mpdu_sequence_control_valid_8074v2(uint8_t *buf) 536 { 537 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 538 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 539 540 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); 541 } 542 543 /** 544 * hal_rx_is_unicast_8074v2: check packet is unicast frame or not. 545 * 546 * @ buf: pointer to rx pkt TLV. 547 * 548 * Return: true on unicast. 549 */ 550 static bool hal_rx_is_unicast_8074v2(uint8_t *buf) 551 { 552 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 553 struct rx_mpdu_start *mpdu_start = 554 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 555 uint32_t grp_id; 556 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 557 558 grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 559 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_OFFSET)), 560 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_MASK, 561 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_LSB)); 562 563 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false; 564 } 565 566 /** 567 * hal_rx_tid_get_8074v2: get tid based on qos control valid. 568 * @hal_soc_hdl: hal soc handle 569 * @buf: pointer to rx pkt TLV. 570 * 571 * Return: tid 572 */ 573 static uint32_t hal_rx_tid_get_8074v2(hal_soc_handle_t hal_soc_hdl, 574 uint8_t *buf) 575 { 576 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 577 struct rx_mpdu_start *mpdu_start = 578 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 579 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 580 uint8_t qos_control_valid = 581 (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 582 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)), 583 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK, 584 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB)); 585 586 if (qos_control_valid) 587 return hal_rx_mpdu_start_tid_get_8074v2(buf); 588 589 return HAL_RX_NON_QOS_TID; 590 } 591 592 /** 593 * hal_rx_hw_desc_get_ppduid_get_8074v2(): retrieve ppdu id 594 * @rx_tlv_hdr: packtet rx tlv header 595 * @rxdma_dst_ring_desc: rxdma HW descriptor 596 * 597 * Return: ppdu id 598 */ 599 static uint32_t hal_rx_hw_desc_get_ppduid_get_8074v2(void *rx_tlv_hdr, 600 void *rxdma_dst_ring_desc) 601 { 602 struct rx_mpdu_info *rx_mpdu_info; 603 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 604 605 rx_mpdu_info = 606 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 607 608 return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_0, PHY_PPDU_ID); 609 } 610 611 /** 612 * hal_reo_status_get_header_8074v2 - Process reo desc info 613 * @d - Pointer to reo descriptior 614 * @b - tlv type info 615 * @h1 - Pointer to hal_reo_status_header where info to be stored 616 * 617 * Return - none. 618 * 619 */ 620 static void hal_reo_status_get_header_8074v2(uint32_t *d, int b, void *h1) 621 { 622 uint32_t val1 = 0; 623 struct hal_reo_status_header *h = 624 (struct hal_reo_status_header *)h1; 625 626 switch (b) { 627 case HAL_REO_QUEUE_STATS_STATUS_TLV: 628 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, 629 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 630 break; 631 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 632 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, 633 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 634 break; 635 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 636 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, 637 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 638 break; 639 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 640 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, 641 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 642 break; 643 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 644 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, 645 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 646 break; 647 case HAL_REO_DESC_THRES_STATUS_TLV: 648 val1 = 649 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, 650 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 651 break; 652 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 653 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, 654 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 655 break; 656 default: 657 qdf_nofl_err("ERROR: Unknown tlv\n"); 658 break; 659 } 660 h->cmd_num = 661 HAL_GET_FIELD( 662 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, 663 val1); 664 h->exec_time = 665 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 666 CMD_EXECUTION_TIME, val1); 667 h->status = 668 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 669 REO_CMD_EXECUTION_STATUS, val1); 670 switch (b) { 671 case HAL_REO_QUEUE_STATS_STATUS_TLV: 672 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, 673 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 674 break; 675 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 676 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, 677 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 678 break; 679 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 680 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, 681 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 682 break; 683 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 684 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, 685 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 686 break; 687 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 688 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, 689 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 690 break; 691 case HAL_REO_DESC_THRES_STATUS_TLV: 692 val1 = 693 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, 694 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 695 break; 696 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 697 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, 698 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 699 break; 700 default: 701 qdf_nofl_err("ERROR: Unknown tlv\n"); 702 break; 703 } 704 h->tstamp = 705 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); 706 } 707 708 /** 709 * hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v2(): 710 * Retrieve qos control valid bit from the tlv. 711 * @buf: pointer to rx pkt TLV. 712 * 713 * Return: qos control value. 714 */ 715 static inline uint32_t 716 hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v2(uint8_t *buf) 717 { 718 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 719 struct rx_mpdu_start *mpdu_start = 720 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 721 722 return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET( 723 &mpdu_start->rx_mpdu_info_details); 724 } 725 726 /** 727 * hal_rx_msdu_end_sa_sw_peer_id_get_8074v2(): API to get the 728 * sa_sw_peer_id from rx_msdu_end TLV 729 * @buf: pointer to the start of RX PKT TLV headers 730 * 731 * Return: sa_sw_peer_id index 732 */ 733 static inline uint32_t 734 hal_rx_msdu_end_sa_sw_peer_id_get_8074v2(uint8_t *buf) 735 { 736 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 737 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 738 739 return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 740 } 741 742 /** 743 * hal_tx_desc_set_mesh_en_8074v2 - Set mesh_enable flag in Tx descriptor 744 * @desc: Handle to Tx Descriptor 745 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 746 * enabling the interpretation of the 'Mesh Control Present' bit 747 * (bit 8) of QoS Control (otherwise this bit is ignored), 748 * For native WiFi frames, this indicates that a 'Mesh Control' field 749 * is present between the header and the LLC. 750 * 751 * Return: void 752 */ 753 static inline 754 void hal_tx_desc_set_mesh_en_8074v2(void *desc, uint8_t en) 755 { 756 HAL_SET_FLD(desc, TCL_DATA_CMD_4, MESH_ENABLE) |= 757 HAL_TX_SM(TCL_DATA_CMD_4, MESH_ENABLE, en); 758 } 759 760 static 761 void *hal_rx_msdu0_buffer_addr_lsb_8074v2(void *link_desc_va) 762 { 763 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 764 } 765 766 static 767 void *hal_rx_msdu_desc_info_ptr_get_8074v2(void *msdu0) 768 { 769 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 770 } 771 772 static 773 void *hal_ent_mpdu_desc_info_8074v2(void *ent_ring_desc) 774 { 775 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 776 } 777 778 static 779 void *hal_dst_mpdu_desc_info_8074v2(void *dst_ring_desc) 780 { 781 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 782 } 783 784 static 785 uint8_t hal_rx_get_fc_valid_8074v2(uint8_t *buf) 786 { 787 return HAL_RX_GET_FC_VALID(buf); 788 } 789 790 static uint8_t hal_rx_get_to_ds_flag_8074v2(uint8_t *buf) 791 { 792 return HAL_RX_GET_TO_DS_FLAG(buf); 793 } 794 795 static uint8_t hal_rx_get_mac_addr2_valid_8074v2(uint8_t *buf) 796 { 797 return HAL_RX_GET_MAC_ADDR2_VALID(buf); 798 } 799 800 static uint8_t hal_rx_get_filter_category_8074v2(uint8_t *buf) 801 { 802 return HAL_RX_GET_FILTER_CATEGORY(buf); 803 } 804 805 static uint32_t 806 hal_rx_get_ppdu_id_8074v2(uint8_t *buf) 807 { 808 struct rx_mpdu_info *rx_mpdu_info; 809 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)buf; 810 811 rx_mpdu_info = 812 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 813 814 return HAL_RX_GET_PPDU_ID(rx_mpdu_info); 815 } 816 817 /** 818 * hal_reo_config_8074v2(): Set reo config parameters 819 * @soc: hal soc handle 820 * @reg_val: value to be set 821 * @reo_params: reo parameters 822 * 823 * Return: void 824 */ 825 static void 826 hal_reo_config_8074v2(struct hal_soc *soc, 827 uint32_t reg_val, 828 struct hal_reo_params *reo_params) 829 { 830 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 831 } 832 833 /** 834 * hal_rx_msdu_desc_info_get_ptr_8074v2() - Get msdu desc info ptr 835 * @msdu_details_ptr - Pointer to msdu_details_ptr 836 * 837 * Return - Pointer to rx_msdu_desc_info structure. 838 * 839 */ 840 static void *hal_rx_msdu_desc_info_get_ptr_8074v2(void *msdu_details_ptr) 841 { 842 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 843 } 844 845 /** 846 * hal_rx_link_desc_msdu0_ptr_8074v2 - Get pointer to rx_msdu details 847 * @link_desc - Pointer to link desc 848 * 849 * Return - Pointer to rx_msdu_details structure 850 * 851 */ 852 static void *hal_rx_link_desc_msdu0_ptr_8074v2(void *link_desc) 853 { 854 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 855 } 856 857 /** 858 * hal_rx_msdu_flow_idx_get_8074v2: API to get flow index 859 * from rx_msdu_end TLV 860 * @buf: pointer to the start of RX PKT TLV headers 861 * 862 * Return: flow index value from MSDU END TLV 863 */ 864 static inline uint32_t hal_rx_msdu_flow_idx_get_8074v2(uint8_t *buf) 865 { 866 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 867 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 868 869 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 870 } 871 872 /** 873 * hal_rx_msdu_flow_idx_invalid_8074v2: API to get flow index invalid 874 * from rx_msdu_end TLV 875 * @buf: pointer to the start of RX PKT TLV headers 876 * 877 * Return: flow index invalid value from MSDU END TLV 878 */ 879 static bool hal_rx_msdu_flow_idx_invalid_8074v2(uint8_t *buf) 880 { 881 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 882 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 883 884 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 885 } 886 887 /** 888 * hal_rx_msdu_flow_idx_timeout_8074v2: API to get flow index timeout 889 * from rx_msdu_end TLV 890 * @buf: pointer to the start of RX PKT TLV headers 891 * 892 * Return: flow index timeout value from MSDU END TLV 893 */ 894 static bool hal_rx_msdu_flow_idx_timeout_8074v2(uint8_t *buf) 895 { 896 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 897 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 898 899 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 900 } 901 902 /** 903 * hal_rx_msdu_fse_metadata_get_8074v2: API to get FSE metadata 904 * from rx_msdu_end TLV 905 * @buf: pointer to the start of RX PKT TLV headers 906 * 907 * Return: fse metadata value from MSDU END TLV 908 */ 909 static uint32_t hal_rx_msdu_fse_metadata_get_8074v2(uint8_t *buf) 910 { 911 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 912 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 913 914 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end); 915 } 916 917 /** 918 * hal_rx_msdu_cce_metadata_get_8074v2: API to get CCE metadata 919 * from rx_msdu_end TLV 920 * @buf: pointer to the start of RX PKT TLV headers 921 * 922 * Return: cce_metadata 923 */ 924 static uint16_t 925 hal_rx_msdu_cce_metadata_get_8074v2(uint8_t *buf) 926 { 927 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 928 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 929 930 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end); 931 } 932 933 /** 934 * hal_rx_msdu_get_flow_params_8074v2: API to get flow index, flow index invalid 935 * and flow index timeout from rx_msdu_end TLV 936 * @buf: pointer to the start of RX PKT TLV headers 937 * @flow_invalid: pointer to return value of flow_idx_valid 938 * @flow_timeout: pointer to return value of flow_idx_timeout 939 * @flow_index: pointer to return value of flow_idx 940 * 941 * Return: none 942 */ 943 static inline void 944 hal_rx_msdu_get_flow_params_8074v2(uint8_t *buf, 945 bool *flow_invalid, 946 bool *flow_timeout, 947 uint32_t *flow_index) 948 { 949 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 950 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 951 952 *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 953 *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 954 *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 955 } 956 957 /** 958 * hal_rx_tlv_get_tcp_chksum_8074v2() - API to get tcp checksum 959 * @buf: rx_tlv_hdr 960 * 961 * Return: tcp checksum 962 */ 963 static uint16_t 964 hal_rx_tlv_get_tcp_chksum_8074v2(uint8_t *buf) 965 { 966 return HAL_RX_TLV_GET_TCP_CHKSUM(buf); 967 } 968 969 /** 970 * hal_rx_get_rx_sequence_8074v2(): Function to retrieve rx sequence number 971 * 972 * @nbuf: Network buffer 973 * Returns: rx sequence number 974 */ 975 static 976 uint16_t hal_rx_get_rx_sequence_8074v2(uint8_t *buf) 977 { 978 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 979 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 980 981 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info); 982 } 983 984 /** 985 * hal_get_window_address_8074v2(): Function to get hp/tp address 986 * @hal_soc: Pointer to hal_soc 987 * @addr: address offset of register 988 * 989 * Return: modified address offset of register 990 */ 991 static inline qdf_iomem_t hal_get_window_address_8074v2(struct hal_soc *hal_soc, 992 qdf_iomem_t addr) 993 { 994 return addr; 995 } 996 997 /** 998 * hal_rx_mpdu_start_tlv_tag_valid_8074v2 () - API to check if RX_MPDU_START 999 * tlv tag is valid 1000 * 1001 * @rx_tlv_hdr: start address of rx_pkt_tlvs 1002 * 1003 * Return: true if RX_MPDU_START is valied, else false. 1004 */ 1005 uint8_t hal_rx_mpdu_start_tlv_tag_valid_8074v2(void *rx_tlv_hdr) 1006 { 1007 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 1008 uint32_t tlv_tag; 1009 1010 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(&rx_desc->mpdu_start_tlv); 1011 1012 return tlv_tag == WIFIRX_MPDU_START_E ? true : false; 1013 } 1014 1015 /** 1016 * hal_rx_flow_setup_fse_8074v2() - Setup a flow search entry in HW FST 1017 * @fst: Pointer to the Rx Flow Search Table 1018 * @table_offset: offset into the table where the flow is to be setup 1019 * @flow: Flow Parameters 1020 * 1021 * Return: Success/Failure 1022 */ 1023 static void * 1024 hal_rx_flow_setup_fse_8074v2(uint8_t *rx_fst, uint32_t table_offset, 1025 uint8_t *rx_flow) 1026 { 1027 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 1028 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 1029 uint8_t *fse; 1030 bool fse_valid; 1031 1032 if (table_offset >= fst->max_entries) { 1033 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 1034 "HAL FSE table offset %u exceeds max entries %u", 1035 table_offset, fst->max_entries); 1036 return NULL; 1037 } 1038 1039 fse = (uint8_t *)fst->base_vaddr + 1040 (table_offset * HAL_RX_FST_ENTRY_SIZE); 1041 1042 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1043 1044 if (fse_valid) { 1045 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 1046 "HAL FSE %pK already valid", fse); 1047 return NULL; 1048 } 1049 1050 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96) = 1051 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96, 1052 qdf_htonl(flow->tuple_info.src_ip_127_96)); 1053 1054 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64) = 1055 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64, 1056 qdf_htonl(flow->tuple_info.src_ip_95_64)); 1057 1058 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32) = 1059 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32, 1060 qdf_htonl(flow->tuple_info.src_ip_63_32)); 1061 1062 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0) = 1063 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0, 1064 qdf_htonl(flow->tuple_info.src_ip_31_0)); 1065 1066 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96) = 1067 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96, 1068 qdf_htonl(flow->tuple_info.dest_ip_127_96)); 1069 1070 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64) = 1071 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64, 1072 qdf_htonl(flow->tuple_info.dest_ip_95_64)); 1073 1074 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32) = 1075 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32, 1076 qdf_htonl(flow->tuple_info.dest_ip_63_32)); 1077 1078 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0) = 1079 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0, 1080 qdf_htonl(flow->tuple_info.dest_ip_31_0)); 1081 1082 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT); 1083 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT) |= 1084 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, DEST_PORT, 1085 (flow->tuple_info.dest_port)); 1086 1087 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT); 1088 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT) |= 1089 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, SRC_PORT, 1090 (flow->tuple_info.src_port)); 1091 1092 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL); 1093 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL) |= 1094 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL, 1095 flow->tuple_info.l4_protocol); 1096 1097 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER); 1098 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER) |= 1099 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER, 1100 flow->reo_destination_handler); 1101 1102 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1103 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID) |= 1104 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, VALID, 1); 1105 1106 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA); 1107 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA) = 1108 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_10, METADATA, 1109 flow->fse_metadata); 1110 1111 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, REO_DESTINATION_INDICATION); 1112 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, REO_DESTINATION_INDICATION) |= 1113 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_11, 1114 REO_DESTINATION_INDICATION, 1115 flow->reo_destination_indication); 1116 1117 /* Reset all the other fields in FSE */ 1118 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, RESERVED_9); 1119 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_DROP); 1120 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, RESERVED_11); 1121 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_COUNT); 1122 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_12, MSDU_BYTE_COUNT); 1123 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_13, TIMESTAMP); 1124 1125 return fse; 1126 } 1127 1128 static 1129 void hal_compute_reo_remap_ix2_ix3_8074v2(uint32_t *ring, uint32_t num_rings, 1130 uint32_t *remap1, uint32_t *remap2) 1131 { 1132 switch (num_rings) { 1133 case 3: 1134 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1135 HAL_REO_REMAP_IX2(ring[1], 17) | 1136 HAL_REO_REMAP_IX2(ring[2], 18) | 1137 HAL_REO_REMAP_IX2(ring[0], 19) | 1138 HAL_REO_REMAP_IX2(ring[1], 20) | 1139 HAL_REO_REMAP_IX2(ring[2], 21) | 1140 HAL_REO_REMAP_IX2(ring[0], 22) | 1141 HAL_REO_REMAP_IX2(ring[1], 23); 1142 1143 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) | 1144 HAL_REO_REMAP_IX3(ring[0], 25) | 1145 HAL_REO_REMAP_IX3(ring[1], 26) | 1146 HAL_REO_REMAP_IX3(ring[2], 27) | 1147 HAL_REO_REMAP_IX3(ring[0], 28) | 1148 HAL_REO_REMAP_IX3(ring[1], 29) | 1149 HAL_REO_REMAP_IX3(ring[2], 30) | 1150 HAL_REO_REMAP_IX3(ring[0], 31); 1151 break; 1152 case 4: 1153 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1154 HAL_REO_REMAP_IX2(ring[1], 17) | 1155 HAL_REO_REMAP_IX2(ring[2], 18) | 1156 HAL_REO_REMAP_IX2(ring[3], 19) | 1157 HAL_REO_REMAP_IX2(ring[0], 20) | 1158 HAL_REO_REMAP_IX2(ring[1], 21) | 1159 HAL_REO_REMAP_IX2(ring[2], 22) | 1160 HAL_REO_REMAP_IX2(ring[3], 23); 1161 1162 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1163 HAL_REO_REMAP_IX3(ring[1], 25) | 1164 HAL_REO_REMAP_IX3(ring[2], 26) | 1165 HAL_REO_REMAP_IX3(ring[3], 27) | 1166 HAL_REO_REMAP_IX3(ring[0], 28) | 1167 HAL_REO_REMAP_IX3(ring[1], 29) | 1168 HAL_REO_REMAP_IX3(ring[2], 30) | 1169 HAL_REO_REMAP_IX3(ring[3], 31); 1170 break; 1171 } 1172 } 1173 1174 struct hal_hw_txrx_ops qca8074v2_hal_hw_txrx_ops = { 1175 1176 /* init and setup */ 1177 hal_srng_dst_hw_init_generic, 1178 hal_srng_src_hw_init_generic, 1179 hal_get_hw_hptp_generic, 1180 hal_reo_setup_generic, 1181 hal_setup_link_idle_list_generic, 1182 hal_get_window_address_8074v2, 1183 NULL, 1184 1185 /* tx */ 1186 hal_tx_desc_set_dscp_tid_table_id_8074v2, 1187 hal_tx_set_dscp_tid_map_8074v2, 1188 hal_tx_update_dscp_tid_8074v2, 1189 hal_tx_desc_set_lmac_id_8074v2, 1190 hal_tx_desc_set_buf_addr_generic, 1191 hal_tx_desc_set_search_type_generic, 1192 hal_tx_desc_set_search_index_generic, 1193 hal_tx_desc_set_cache_set_num_generic, 1194 hal_tx_comp_get_status_generic, 1195 hal_tx_comp_get_release_reason_generic, 1196 hal_get_wbm_internal_error_generic, 1197 hal_tx_desc_set_mesh_en_8074v2, 1198 hal_tx_init_cmd_credit_ring_8074v2, 1199 1200 /* rx */ 1201 hal_rx_msdu_start_nss_get_8074v2, 1202 hal_rx_mon_hw_desc_get_mpdu_status_8074v2, 1203 hal_rx_get_tlv_8074v2, 1204 hal_rx_proc_phyrx_other_receive_info_tlv_8074v2, 1205 hal_rx_dump_msdu_start_tlv_8074v2, 1206 hal_rx_dump_msdu_end_tlv_8074v2, 1207 hal_get_link_desc_size_8074v2, 1208 hal_rx_mpdu_start_tid_get_8074v2, 1209 hal_rx_msdu_start_reception_type_get_8074v2, 1210 hal_rx_msdu_end_da_idx_get_8074v2, 1211 hal_rx_msdu_desc_info_get_ptr_8074v2, 1212 hal_rx_link_desc_msdu0_ptr_8074v2, 1213 hal_reo_status_get_header_8074v2, 1214 hal_rx_status_get_tlv_info_generic, 1215 hal_rx_wbm_err_info_get_generic, 1216 hal_rx_dump_mpdu_start_tlv_generic, 1217 1218 hal_tx_set_pcp_tid_map_generic, 1219 hal_tx_update_pcp_tid_generic, 1220 hal_tx_update_tidmap_prty_generic, 1221 hal_rx_get_rx_fragment_number_8074v2, 1222 hal_rx_msdu_end_da_is_mcbc_get_8074v2, 1223 hal_rx_msdu_end_sa_is_valid_get_8074v2, 1224 hal_rx_msdu_end_sa_idx_get_8074v2, 1225 hal_rx_desc_is_first_msdu_8074v2, 1226 hal_rx_msdu_end_l3_hdr_padding_get_8074v2, 1227 hal_rx_encryption_info_valid_8074v2, 1228 hal_rx_print_pn_8074v2, 1229 hal_rx_msdu_end_first_msdu_get_8074v2, 1230 hal_rx_msdu_end_da_is_valid_get_8074v2, 1231 hal_rx_msdu_end_last_msdu_get_8074v2, 1232 hal_rx_get_mpdu_mac_ad4_valid_8074v2, 1233 hal_rx_mpdu_start_sw_peer_id_get_8074v2, 1234 hal_rx_mpdu_get_to_ds_8074v2, 1235 hal_rx_mpdu_get_fr_ds_8074v2, 1236 hal_rx_get_mpdu_frame_control_valid_8074v2, 1237 hal_rx_mpdu_get_addr1_8074v2, 1238 hal_rx_mpdu_get_addr2_8074v2, 1239 hal_rx_mpdu_get_addr3_8074v2, 1240 hal_rx_mpdu_get_addr4_8074v2, 1241 hal_rx_get_mpdu_sequence_control_valid_8074v2, 1242 hal_rx_is_unicast_8074v2, 1243 hal_rx_tid_get_8074v2, 1244 hal_rx_hw_desc_get_ppduid_get_8074v2, 1245 hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v2, 1246 hal_rx_msdu_end_sa_sw_peer_id_get_8074v2, 1247 hal_rx_msdu0_buffer_addr_lsb_8074v2, 1248 hal_rx_msdu_desc_info_ptr_get_8074v2, 1249 hal_ent_mpdu_desc_info_8074v2, 1250 hal_dst_mpdu_desc_info_8074v2, 1251 hal_rx_get_fc_valid_8074v2, 1252 hal_rx_get_to_ds_flag_8074v2, 1253 hal_rx_get_mac_addr2_valid_8074v2, 1254 hal_rx_get_filter_category_8074v2, 1255 hal_rx_get_ppdu_id_8074v2, 1256 hal_reo_config_8074v2, 1257 hal_rx_msdu_flow_idx_get_8074v2, 1258 hal_rx_msdu_flow_idx_invalid_8074v2, 1259 hal_rx_msdu_flow_idx_timeout_8074v2, 1260 hal_rx_msdu_fse_metadata_get_8074v2, 1261 hal_rx_msdu_cce_metadata_get_8074v2, 1262 hal_rx_msdu_get_flow_params_8074v2, 1263 hal_rx_tlv_get_tcp_chksum_8074v2, 1264 hal_rx_get_rx_sequence_8074v2, 1265 #if defined(QCA_WIFI_QCA6018) && defined(WLAN_CFR_ENABLE) && \ 1266 defined(WLAN_ENH_CFR_ENABLE) 1267 hal_rx_get_bb_info_8074v2, 1268 hal_rx_get_rtt_info_8074v2, 1269 #else 1270 NULL, 1271 NULL, 1272 #endif 1273 /* rx - msdu fast path info fields */ 1274 hal_rx_msdu_packet_metadata_get_generic, 1275 NULL, 1276 NULL, 1277 NULL, 1278 NULL, 1279 NULL, 1280 NULL, 1281 hal_rx_mpdu_start_tlv_tag_valid_8074v2, 1282 NULL, 1283 NULL, 1284 1285 /* rx - TLV struct offsets */ 1286 hal_rx_msdu_end_offset_get_generic, 1287 hal_rx_attn_offset_get_generic, 1288 hal_rx_msdu_start_offset_get_generic, 1289 hal_rx_mpdu_start_offset_get_generic, 1290 hal_rx_mpdu_end_offset_get_generic, 1291 hal_rx_flow_setup_fse_8074v2, 1292 hal_compute_reo_remap_ix2_ix3_8074v2 1293 }; 1294 1295 struct hal_hw_srng_config hw_srng_table_8074v2[] = { 1296 /* TODO: max_rings can populated by querying HW capabilities */ 1297 { /* REO_DST */ 1298 .start_ring_id = HAL_SRNG_REO2SW1, 1299 .max_rings = 4, 1300 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1301 .lmac_ring = FALSE, 1302 .ring_dir = HAL_SRNG_DST_RING, 1303 .reg_start = { 1304 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 1305 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1306 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 1307 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1308 }, 1309 .reg_size = { 1310 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 1311 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 1312 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 1313 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 1314 }, 1315 .max_size = 1316 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 1317 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 1318 }, 1319 { /* REO_EXCEPTION */ 1320 /* Designating REO2TCL ring as exception ring. This ring is 1321 * similar to other REO2SW rings though it is named as REO2TCL. 1322 * Any of theREO2SW rings can be used as exception ring. 1323 */ 1324 .start_ring_id = HAL_SRNG_REO2TCL, 1325 .max_rings = 1, 1326 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1327 .lmac_ring = FALSE, 1328 .ring_dir = HAL_SRNG_DST_RING, 1329 .reg_start = { 1330 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 1331 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1332 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 1333 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1334 }, 1335 /* Single ring - provide ring size if multiple rings of this 1336 * type are supported 1337 */ 1338 .reg_size = {}, 1339 .max_size = 1340 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 1341 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 1342 }, 1343 { /* REO_REINJECT */ 1344 .start_ring_id = HAL_SRNG_SW2REO, 1345 .max_rings = 1, 1346 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1347 .lmac_ring = FALSE, 1348 .ring_dir = HAL_SRNG_SRC_RING, 1349 .reg_start = { 1350 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 1351 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1352 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 1353 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1354 }, 1355 /* Single ring - provide ring size if multiple rings of this 1356 * type are supported 1357 */ 1358 .reg_size = {}, 1359 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 1360 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 1361 }, 1362 { /* REO_CMD */ 1363 .start_ring_id = HAL_SRNG_REO_CMD, 1364 .max_rings = 1, 1365 .entry_size = (sizeof(struct tlv_32_hdr) + 1366 sizeof(struct reo_get_queue_stats)) >> 2, 1367 .lmac_ring = FALSE, 1368 .ring_dir = HAL_SRNG_SRC_RING, 1369 .reg_start = { 1370 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 1371 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1372 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 1373 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1374 }, 1375 /* Single ring - provide ring size if multiple rings of this 1376 * type are supported 1377 */ 1378 .reg_size = {}, 1379 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1380 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1381 }, 1382 { /* REO_STATUS */ 1383 .start_ring_id = HAL_SRNG_REO_STATUS, 1384 .max_rings = 1, 1385 .entry_size = (sizeof(struct tlv_32_hdr) + 1386 sizeof(struct reo_get_queue_stats_status)) >> 2, 1387 .lmac_ring = FALSE, 1388 .ring_dir = HAL_SRNG_DST_RING, 1389 .reg_start = { 1390 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 1391 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1392 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 1393 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1394 }, 1395 /* Single ring - provide ring size if multiple rings of this 1396 * type are supported 1397 */ 1398 .reg_size = {}, 1399 .max_size = 1400 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1401 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1402 }, 1403 { /* TCL_DATA */ 1404 .start_ring_id = HAL_SRNG_SW2TCL1, 1405 .max_rings = 3, 1406 .entry_size = (sizeof(struct tlv_32_hdr) + 1407 sizeof(struct tcl_data_cmd)) >> 2, 1408 .lmac_ring = FALSE, 1409 .ring_dir = HAL_SRNG_SRC_RING, 1410 .reg_start = { 1411 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 1412 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1413 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 1414 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1415 }, 1416 .reg_size = { 1417 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 1418 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 1419 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 1420 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 1421 }, 1422 .max_size = 1423 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 1424 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 1425 }, 1426 { /* TCL_CMD */ 1427 /* qca8074v2 and qcn9000 uses this ring for data commands */ 1428 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 1429 .max_rings = 1, 1430 .entry_size = (sizeof(struct tlv_32_hdr) + 1431 sizeof(struct tcl_data_cmd)) >> 2, 1432 .lmac_ring = FALSE, 1433 .ring_dir = HAL_SRNG_SRC_RING, 1434 .reg_start = { 1435 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR( 1436 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1437 HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR( 1438 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1439 }, 1440 /* Single ring - provide ring size if multiple rings of this 1441 * type are supported 1442 */ 1443 .reg_size = {}, 1444 .max_size = 1445 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1446 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1447 }, 1448 { /* TCL_STATUS */ 1449 .start_ring_id = HAL_SRNG_TCL_STATUS, 1450 .max_rings = 1, 1451 .entry_size = (sizeof(struct tlv_32_hdr) + 1452 sizeof(struct tcl_status_ring)) >> 2, 1453 .lmac_ring = FALSE, 1454 .ring_dir = HAL_SRNG_DST_RING, 1455 .reg_start = { 1456 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 1457 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1458 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 1459 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1460 }, 1461 /* Single ring - provide ring size if multiple rings of this 1462 * type are supported 1463 */ 1464 .reg_size = {}, 1465 .max_size = 1466 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 1467 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 1468 }, 1469 { /* CE_SRC */ 1470 .start_ring_id = HAL_SRNG_CE_0_SRC, 1471 .max_rings = 12, 1472 .entry_size = sizeof(struct ce_src_desc) >> 2, 1473 .lmac_ring = FALSE, 1474 .ring_dir = HAL_SRNG_SRC_RING, 1475 .reg_start = { 1476 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1477 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1478 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1479 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1480 }, 1481 .reg_size = { 1482 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1483 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1484 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1485 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1486 }, 1487 .max_size = 1488 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1489 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1490 }, 1491 { /* CE_DST */ 1492 .start_ring_id = HAL_SRNG_CE_0_DST, 1493 .max_rings = 12, 1494 .entry_size = 8 >> 2, 1495 /*TODO: entry_size above should actually be 1496 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 1497 * of struct ce_dst_desc in HW header files 1498 */ 1499 .lmac_ring = FALSE, 1500 .ring_dir = HAL_SRNG_SRC_RING, 1501 .reg_start = { 1502 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1503 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1504 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1505 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1506 }, 1507 .reg_size = { 1508 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1509 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1510 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1511 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1512 }, 1513 .max_size = 1514 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1515 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1516 }, 1517 { /* CE_DST_STATUS */ 1518 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 1519 .max_rings = 12, 1520 .entry_size = sizeof(struct ce_stat_desc) >> 2, 1521 .lmac_ring = FALSE, 1522 .ring_dir = HAL_SRNG_DST_RING, 1523 .reg_start = { 1524 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 1525 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1526 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 1527 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1528 }, 1529 /* TODO: check destination status ring registers */ 1530 .reg_size = { 1531 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1532 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1533 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1534 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1535 }, 1536 .max_size = 1537 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1538 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1539 }, 1540 { /* WBM_IDLE_LINK */ 1541 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 1542 .max_rings = 1, 1543 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 1544 .lmac_ring = FALSE, 1545 .ring_dir = HAL_SRNG_SRC_RING, 1546 .reg_start = { 1547 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1548 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1549 }, 1550 /* Single ring - provide ring size if multiple rings of this 1551 * type are supported 1552 */ 1553 .reg_size = {}, 1554 .max_size = 1555 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 1556 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 1557 }, 1558 { /* SW2WBM_RELEASE */ 1559 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 1560 .max_rings = 1, 1561 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1562 .lmac_ring = FALSE, 1563 .ring_dir = HAL_SRNG_SRC_RING, 1564 .reg_start = { 1565 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1566 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1567 }, 1568 /* Single ring - provide ring size if multiple rings of this 1569 * type are supported 1570 */ 1571 .reg_size = {}, 1572 .max_size = 1573 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1574 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1575 }, 1576 { /* WBM2SW_RELEASE */ 1577 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 1578 .max_rings = 4, 1579 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1580 .lmac_ring = FALSE, 1581 .ring_dir = HAL_SRNG_DST_RING, 1582 .reg_start = { 1583 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1584 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1585 }, 1586 .reg_size = { 1587 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1588 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1589 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1590 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1591 }, 1592 .max_size = 1593 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1594 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1595 }, 1596 { /* RXDMA_BUF */ 1597 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 1598 #ifdef IPA_OFFLOAD 1599 .max_rings = 3, 1600 #else 1601 .max_rings = 2, 1602 #endif 1603 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1604 .lmac_ring = TRUE, 1605 .ring_dir = HAL_SRNG_SRC_RING, 1606 /* reg_start is not set because LMAC rings are not accessed 1607 * from host 1608 */ 1609 .reg_start = {}, 1610 .reg_size = {}, 1611 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1612 }, 1613 { /* RXDMA_DST */ 1614 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 1615 .max_rings = 1, 1616 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1617 .lmac_ring = TRUE, 1618 .ring_dir = HAL_SRNG_DST_RING, 1619 /* reg_start is not set because LMAC rings are not accessed 1620 * from host 1621 */ 1622 .reg_start = {}, 1623 .reg_size = {}, 1624 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1625 }, 1626 { /* RXDMA_MONITOR_BUF */ 1627 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 1628 .max_rings = 1, 1629 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1630 .lmac_ring = TRUE, 1631 .ring_dir = HAL_SRNG_SRC_RING, 1632 /* reg_start is not set because LMAC rings are not accessed 1633 * from host 1634 */ 1635 .reg_start = {}, 1636 .reg_size = {}, 1637 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1638 }, 1639 { /* RXDMA_MONITOR_STATUS */ 1640 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 1641 .max_rings = 1, 1642 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1643 .lmac_ring = TRUE, 1644 .ring_dir = HAL_SRNG_SRC_RING, 1645 /* reg_start is not set because LMAC rings are not accessed 1646 * from host 1647 */ 1648 .reg_start = {}, 1649 .reg_size = {}, 1650 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1651 }, 1652 { /* RXDMA_MONITOR_DST */ 1653 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 1654 .max_rings = 1, 1655 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1656 .lmac_ring = TRUE, 1657 .ring_dir = HAL_SRNG_DST_RING, 1658 /* reg_start is not set because LMAC rings are not accessed 1659 * from host 1660 */ 1661 .reg_start = {}, 1662 .reg_size = {}, 1663 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1664 }, 1665 { /* RXDMA_MONITOR_DESC */ 1666 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 1667 .max_rings = 1, 1668 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1669 .lmac_ring = TRUE, 1670 .ring_dir = HAL_SRNG_SRC_RING, 1671 /* reg_start is not set because LMAC rings are not accessed 1672 * from host 1673 */ 1674 .reg_start = {}, 1675 .reg_size = {}, 1676 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1677 }, 1678 { /* DIR_BUF_RX_DMA_SRC */ 1679 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 1680 /* one ring for spectral and one ring for cfr */ 1681 .max_rings = 2, 1682 .entry_size = 2, 1683 .lmac_ring = TRUE, 1684 .ring_dir = HAL_SRNG_SRC_RING, 1685 /* reg_start is not set because LMAC rings are not accessed 1686 * from host 1687 */ 1688 .reg_start = {}, 1689 .reg_size = {}, 1690 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1691 }, 1692 #ifdef WLAN_FEATURE_CIF_CFR 1693 { /* WIFI_POS_SRC */ 1694 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 1695 .max_rings = 1, 1696 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 1697 .lmac_ring = TRUE, 1698 .ring_dir = HAL_SRNG_SRC_RING, 1699 /* reg_start is not set because LMAC rings are not accessed 1700 * from host 1701 */ 1702 .reg_start = {}, 1703 .reg_size = {}, 1704 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1705 }, 1706 #endif 1707 }; 1708 1709 int32_t hal_hw_reg_offset_qca8074v2[] = { 1710 /* dst */ 1711 REG_OFFSET(DST, HP), 1712 REG_OFFSET(DST, TP), 1713 REG_OFFSET(DST, ID), 1714 REG_OFFSET(DST, MISC), 1715 REG_OFFSET(DST, HP_ADDR_LSB), 1716 REG_OFFSET(DST, HP_ADDR_MSB), 1717 REG_OFFSET(DST, MSI1_BASE_LSB), 1718 REG_OFFSET(DST, MSI1_BASE_MSB), 1719 REG_OFFSET(DST, MSI1_DATA), 1720 REG_OFFSET(DST, BASE_LSB), 1721 REG_OFFSET(DST, BASE_MSB), 1722 REG_OFFSET(DST, PRODUCER_INT_SETUP), 1723 /* src */ 1724 REG_OFFSET(SRC, HP), 1725 REG_OFFSET(SRC, TP), 1726 REG_OFFSET(SRC, ID), 1727 REG_OFFSET(SRC, MISC), 1728 REG_OFFSET(SRC, TP_ADDR_LSB), 1729 REG_OFFSET(SRC, TP_ADDR_MSB), 1730 REG_OFFSET(SRC, MSI1_BASE_LSB), 1731 REG_OFFSET(SRC, MSI1_BASE_MSB), 1732 REG_OFFSET(SRC, MSI1_DATA), 1733 REG_OFFSET(SRC, BASE_LSB), 1734 REG_OFFSET(SRC, BASE_MSB), 1735 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX0), 1736 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX1), 1737 }; 1738 1739 1740 /** 1741 * hal_qca8074v2_attach() - Attach 8074v2 target specific hal_soc ops, 1742 * offset and srng table 1743 */ 1744 void hal_qca8074v2_attach(struct hal_soc *hal_soc) 1745 { 1746 hal_soc->hw_srng_table = hw_srng_table_8074v2; 1747 hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca8074v2; 1748 hal_soc->ops = &qca8074v2_hal_hw_txrx_ops; 1749 } 1750