1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 #include "hal_li_hw_headers.h" 20 #include "hal_internal.h" 21 #include "hal_api.h" 22 #include "target_type.h" 23 #include "wcss_version.h" 24 #include "qdf_module.h" 25 #include "hal_flow.h" 26 #include "rx_flow_search_entry.h" 27 #include "hal_rx_flow_info.h" 28 29 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 30 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET 31 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 32 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK 33 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 34 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB 35 #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET \ 36 RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET 37 #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK \ 38 RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK 39 #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB \ 40 RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB 41 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 42 PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 43 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 44 PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 45 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 46 PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 47 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 48 PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 49 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 50 PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 51 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 52 PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 53 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 54 PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 55 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 56 PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 57 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 58 PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 59 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 60 PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 61 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 62 PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 63 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 64 RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 65 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 66 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 67 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 68 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 69 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 70 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 71 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 72 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 73 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER \ 74 STATUS_HEADER_REO_STATUS_NUMBER 75 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 76 STATUS_HEADER_TIMESTAMP 77 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 78 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 79 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 80 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 81 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 82 TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 83 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 84 TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 85 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 86 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 87 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 88 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 89 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 90 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 91 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 92 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 93 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 94 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 95 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 96 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 97 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 98 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 99 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 100 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 101 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 102 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 103 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 104 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 105 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 106 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 107 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 108 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 109 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 110 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 111 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 112 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 113 114 #include "hal_8074v2_tx.h" 115 #include "hal_8074v2_rx.h" 116 #include <hal_generic_api.h> 117 #include "hal_li_rx.h" 118 #include "hal_li_api.h" 119 #include "hal_li_generic_api.h" 120 121 /** 122 * hal_rx_get_rx_fragment_number_8074v2() - Function to retrieve 123 * rx fragment number 124 * @buf: Network buffer 125 * 126 * Return: rx fragment number 127 */ 128 static 129 uint8_t hal_rx_get_rx_fragment_number_8074v2(uint8_t *buf) 130 { 131 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 132 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 133 134 /* Return first 4 bits as fragment number */ 135 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & 136 DOT11_SEQ_FRAG_MASK; 137 } 138 139 /** 140 * hal_rx_msdu_end_da_is_mcbc_get_8074v2() - API to check if pkt is MCBC 141 * from rx_msdu_end TLV 142 * @buf: pointer to the start of RX PKT TLV headers 143 * 144 * Return: da_is_mcbc 145 */ 146 static uint8_t 147 hal_rx_msdu_end_da_is_mcbc_get_8074v2(uint8_t *buf) 148 { 149 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 150 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 151 152 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); 153 } 154 155 /** 156 * hal_rx_msdu_end_sa_is_valid_get_8074v2() - API to get_8074v2 the sa_is_valid 157 * bit from rx_msdu_end TLV 158 * @buf: pointer to the start of RX PKT TLV headers 159 * 160 * Return: sa_is_valid bit 161 */ 162 static uint8_t 163 hal_rx_msdu_end_sa_is_valid_get_8074v2(uint8_t *buf) 164 { 165 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 166 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 167 uint8_t sa_is_valid; 168 169 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); 170 171 return sa_is_valid; 172 } 173 174 /** 175 * hal_rx_msdu_end_sa_idx_get_8074v2() - API to get_8074v2 the sa_idx from 176 * rx_msdu_end TLV 177 * @buf: pointer to the start of RX PKT TLV headers 178 * 179 * Return: sa_idx (SA AST index) 180 */ 181 static uint16_t hal_rx_msdu_end_sa_idx_get_8074v2(uint8_t *buf) 182 { 183 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 184 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 185 uint16_t sa_idx; 186 187 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 188 189 return sa_idx; 190 } 191 192 /** 193 * hal_rx_desc_is_first_msdu_8074v2() - Check if first msdu 194 * @hw_desc_addr: hardware descriptor address 195 * 196 * Return: 0 - success/ non-zero failure 197 */ 198 static uint32_t hal_rx_desc_is_first_msdu_8074v2(void *hw_desc_addr) 199 { 200 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; 201 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; 202 203 return HAL_RX_GET(msdu_end, RX_MSDU_END_5, FIRST_MSDU); 204 } 205 206 /** 207 * hal_rx_msdu_end_l3_hdr_padding_get_8074v2() - API to get_8074v2 the 208 * l3_header padding from 209 * rx_msdu_end TLV 210 * @buf: pointer to the start of RX PKT TLV headers 211 * 212 * Return: number of l3 header padding bytes 213 */ 214 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_8074v2(uint8_t *buf) 215 { 216 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 217 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 218 uint32_t l3_header_padding; 219 220 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 221 222 return l3_header_padding; 223 } 224 225 /** 226 * hal_rx_encryption_info_valid_8074v2() - Returns encryption type. 227 * @buf: rx_tlv_hdr of the received packet 228 * 229 * Return: encryption type 230 */ 231 static uint32_t hal_rx_encryption_info_valid_8074v2(uint8_t *buf) 232 { 233 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 234 struct rx_mpdu_start *mpdu_start = 235 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 236 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 237 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); 238 239 return encryption_info; 240 } 241 242 /** 243 * hal_rx_print_pn_8074v2() - Prints the PN of rx packet. 244 * @buf: rx_tlv_hdr of the received packet 245 * 246 * Return: void 247 */ 248 static void hal_rx_print_pn_8074v2(uint8_t *buf) 249 { 250 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 251 struct rx_mpdu_start *mpdu_start = 252 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 253 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 254 255 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); 256 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); 257 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); 258 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); 259 260 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x", 261 pn_127_96, pn_95_64, pn_63_32, pn_31_0); 262 } 263 264 /** 265 * hal_rx_msdu_end_first_msdu_get_8074v2() - API to get first msdu status 266 * from rx_msdu_end TLV 267 * @buf: pointer to the start of RX PKT TLV headers 268 * 269 * Return: first_msdu 270 */ 271 static uint8_t hal_rx_msdu_end_first_msdu_get_8074v2(uint8_t *buf) 272 { 273 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 274 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 275 uint8_t first_msdu; 276 277 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); 278 279 return first_msdu; 280 } 281 282 /** 283 * hal_rx_msdu_end_da_is_valid_get_8074v2() - API to check if da is valid 284 * from rx_msdu_end TLV 285 * @buf: pointer to the start of RX PKT TLV headers 286 * 287 * Return: da_is_valid 288 */ 289 static uint8_t hal_rx_msdu_end_da_is_valid_get_8074v2(uint8_t *buf) 290 { 291 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 292 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 293 uint8_t da_is_valid; 294 295 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); 296 297 return da_is_valid; 298 } 299 300 /** 301 * hal_rx_msdu_end_last_msdu_get_8074v2() - API to get last msdu status 302 * from rx_msdu_end TLV 303 * @buf: pointer to the start of RX PKT TLV headers 304 * 305 * Return: last_msdu 306 */ 307 static uint8_t hal_rx_msdu_end_last_msdu_get_8074v2(uint8_t *buf) 308 { 309 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 310 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 311 uint8_t last_msdu; 312 313 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); 314 315 return last_msdu; 316 } 317 318 /** 319 * hal_rx_get_mpdu_mac_ad4_valid_8074v2() - Retrieves if mpdu 4th addr is valid 320 * @buf: Network buffer 321 * 322 * Return: value of mpdu 4th address valid field 323 */ 324 static bool hal_rx_get_mpdu_mac_ad4_valid_8074v2(uint8_t *buf) 325 { 326 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 327 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 328 bool ad4_valid = 0; 329 330 ad4_valid = HAL_RX_MPDU_GET_MAC_AD4_VALID(rx_mpdu_info); 331 332 return ad4_valid; 333 } 334 335 /** 336 * hal_rx_mpdu_start_sw_peer_id_get_8074v2() - Retrieve sw peer_id 337 * @buf: network buffer 338 * 339 * Return: sw peer_id 340 */ 341 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_8074v2(uint8_t *buf) 342 { 343 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 344 struct rx_mpdu_start *mpdu_start = 345 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 346 347 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET( 348 &mpdu_start->rx_mpdu_info_details); 349 } 350 351 /** 352 * hal_rx_mpdu_get_to_ds_8074v2() - API to get the tods info from rx_mpdu_start 353 * @buf: pointer to the start of RX PKT TLV header 354 * 355 * Return: uint32_t(to_ds) 356 */ 357 static uint32_t hal_rx_mpdu_get_to_ds_8074v2(uint8_t *buf) 358 { 359 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 360 struct rx_mpdu_start *mpdu_start = 361 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 362 363 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 364 365 return HAL_RX_MPDU_GET_TODS(mpdu_info); 366 } 367 368 /** 369 * hal_rx_mpdu_get_fr_ds_8074v2() - API to get the from ds info from 370 * rx_mpdu_start 371 * @buf: pointer to the start of RX PKT TLV header 372 * 373 * Return: uint32_t(fr_ds) 374 */ 375 static uint32_t hal_rx_mpdu_get_fr_ds_8074v2(uint8_t *buf) 376 { 377 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 378 struct rx_mpdu_start *mpdu_start = 379 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 380 381 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 382 383 return HAL_RX_MPDU_GET_FROMDS(mpdu_info); 384 } 385 386 /** 387 * hal_rx_get_mpdu_frame_control_valid_8074v2() - Retrieves mpdu 388 * frame control valid 389 * @buf: Network buffer 390 * 391 * Return: value of frame control valid field 392 */ 393 static uint8_t hal_rx_get_mpdu_frame_control_valid_8074v2(uint8_t *buf) 394 { 395 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 396 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 397 398 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); 399 } 400 401 /** 402 * hal_rx_get_mpdu_frame_control_field_8074v2() - Function to retrieve frame 403 * control field 404 * @buf: Network buffer 405 * 406 * Return: value of frame control field 407 * 408 */ 409 static uint16_t hal_rx_get_mpdu_frame_control_field_8074v2(uint8_t *buf) 410 { 411 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 412 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 413 uint16_t frame_ctrl = 0; 414 415 frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info); 416 417 return frame_ctrl; 418 } 419 420 /** 421 * hal_rx_mpdu_get_addr1_8074v2() - API to check get address1 of the mpdu 422 * @buf: pointer to the start of RX PKT TLV headera 423 * @mac_addr: pointer to mac address 424 * 425 * Return: success/failure 426 */ 427 static QDF_STATUS hal_rx_mpdu_get_addr1_8074v2(uint8_t *buf, uint8_t *mac_addr) 428 { 429 struct __attribute__((__packed__)) hal_addr1 { 430 uint32_t ad1_31_0; 431 uint16_t ad1_47_32; 432 }; 433 434 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 435 struct rx_mpdu_start *mpdu_start = 436 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 437 438 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 439 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; 440 uint32_t mac_addr_ad1_valid; 441 442 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); 443 444 if (mac_addr_ad1_valid) { 445 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); 446 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); 447 return QDF_STATUS_SUCCESS; 448 } 449 450 return QDF_STATUS_E_FAILURE; 451 } 452 453 /** 454 * hal_rx_mpdu_get_addr2_8074v2() - API to check get address2 of the mpdu 455 * in the packet 456 * @buf: pointer to the start of RX PKT TLV header 457 * @mac_addr: pointer to mac address 458 * 459 * Return: success/failure 460 */ 461 static QDF_STATUS hal_rx_mpdu_get_addr2_8074v2(uint8_t *buf, uint8_t *mac_addr) 462 { 463 struct __attribute__((__packed__)) hal_addr2 { 464 uint16_t ad2_15_0; 465 uint32_t ad2_47_16; 466 }; 467 468 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 469 struct rx_mpdu_start *mpdu_start = 470 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 471 472 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 473 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; 474 uint32_t mac_addr_ad2_valid; 475 476 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); 477 478 if (mac_addr_ad2_valid) { 479 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); 480 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); 481 return QDF_STATUS_SUCCESS; 482 } 483 484 return QDF_STATUS_E_FAILURE; 485 } 486 487 /** 488 * hal_rx_mpdu_get_addr3_8074v2() - API to get address3 of the mpdu 489 * in the packet 490 * @buf: pointer to the start of RX PKT TLV header 491 * @mac_addr: pointer to mac address 492 * 493 * Return: success/failure 494 */ 495 static QDF_STATUS hal_rx_mpdu_get_addr3_8074v2(uint8_t *buf, uint8_t *mac_addr) 496 { 497 struct __attribute__((__packed__)) hal_addr3 { 498 uint32_t ad3_31_0; 499 uint16_t ad3_47_32; 500 }; 501 502 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 503 struct rx_mpdu_start *mpdu_start = 504 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 505 506 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 507 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; 508 uint32_t mac_addr_ad3_valid; 509 510 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); 511 512 if (mac_addr_ad3_valid) { 513 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); 514 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); 515 return QDF_STATUS_SUCCESS; 516 } 517 518 return QDF_STATUS_E_FAILURE; 519 } 520 521 /** 522 * hal_rx_mpdu_get_addr4_8074v2() - API to get address4 of the mpdu 523 * in the packet 524 * @buf: pointer to the start of RX PKT TLV header 525 * @mac_addr: pointer to mac address 526 * 527 * Return: success/failure 528 */ 529 static QDF_STATUS hal_rx_mpdu_get_addr4_8074v2(uint8_t *buf, uint8_t *mac_addr) 530 { 531 struct __attribute__((__packed__)) hal_addr4 { 532 uint32_t ad4_31_0; 533 uint16_t ad4_47_32; 534 }; 535 536 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 537 struct rx_mpdu_start *mpdu_start = 538 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 539 540 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 541 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; 542 uint32_t mac_addr_ad4_valid; 543 544 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); 545 546 if (mac_addr_ad4_valid) { 547 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); 548 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); 549 return QDF_STATUS_SUCCESS; 550 } 551 552 return QDF_STATUS_E_FAILURE; 553 } 554 555 /** 556 * hal_rx_get_mpdu_sequence_control_valid_8074v2() - Get mpdu sequence control 557 * valid 558 * @buf: Network buffer 559 * 560 * Return: value of sequence control valid field 561 */ 562 static uint8_t hal_rx_get_mpdu_sequence_control_valid_8074v2(uint8_t *buf) 563 { 564 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 565 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 566 567 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); 568 } 569 570 /** 571 * hal_rx_is_unicast_8074v2() - check packet is unicast frame or not. 572 * @buf: pointer to rx pkt TLV. 573 * 574 * Return: true on unicast. 575 */ 576 static bool hal_rx_is_unicast_8074v2(uint8_t *buf) 577 { 578 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 579 struct rx_mpdu_start *mpdu_start = 580 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 581 uint32_t grp_id; 582 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 583 584 grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 585 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_OFFSET)), 586 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_MASK, 587 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_LSB)); 588 589 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false; 590 } 591 592 /** 593 * hal_rx_tid_get_8074v2() - get tid based on qos control valid. 594 * @hal_soc_hdl: hal soc handle 595 * @buf: pointer to rx pkt TLV. 596 * 597 * Return: tid 598 */ 599 static uint32_t hal_rx_tid_get_8074v2(hal_soc_handle_t hal_soc_hdl, 600 uint8_t *buf) 601 { 602 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 603 struct rx_mpdu_start *mpdu_start = 604 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 605 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 606 uint8_t qos_control_valid = 607 (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 608 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)), 609 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK, 610 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB)); 611 612 if (qos_control_valid) 613 return hal_rx_mpdu_start_tid_get_8074v2(buf); 614 615 return HAL_RX_NON_QOS_TID; 616 } 617 618 /** 619 * hal_rx_hw_desc_get_ppduid_get_8074v2() - retrieve ppdu id 620 * @rx_tlv_hdr: packtet rx tlv header 621 * @rxdma_dst_ring_desc: rxdma HW descriptor 622 * 623 * Return: ppdu id 624 */ 625 static uint32_t hal_rx_hw_desc_get_ppduid_get_8074v2(void *rx_tlv_hdr, 626 void *rxdma_dst_ring_desc) 627 { 628 struct rx_mpdu_info *rx_mpdu_info; 629 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 630 631 rx_mpdu_info = 632 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 633 634 return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_0, PHY_PPDU_ID); 635 } 636 637 /** 638 * hal_reo_status_get_header_8074v2() - Process reo desc info 639 * @ring_desc: REO status ring descriptor 640 * @b: tlv type info 641 * @h1: Pointer to hal_reo_status_header where info to be stored 642 * 643 * Return: none. 644 */ 645 static void hal_reo_status_get_header_8074v2(hal_ring_desc_t ring_desc, int b, 646 void *h1) 647 { 648 uint32_t *d = (uint32_t *)ring_desc; 649 uint32_t val1 = 0; 650 struct hal_reo_status_header *h = 651 (struct hal_reo_status_header *)h1; 652 653 /* Offsets of descriptor fields defined in HW headers start 654 * from the field after TLV header 655 */ 656 d += HAL_GET_NUM_DWORDS(sizeof(struct tlv_32_hdr)); 657 658 switch (b) { 659 case HAL_REO_QUEUE_STATS_STATUS_TLV: 660 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, 661 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 662 break; 663 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 664 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, 665 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 666 break; 667 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 668 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, 669 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 670 break; 671 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 672 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, 673 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 674 break; 675 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 676 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, 677 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 678 break; 679 case HAL_REO_DESC_THRES_STATUS_TLV: 680 val1 = 681 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, 682 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 683 break; 684 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 685 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, 686 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 687 break; 688 default: 689 qdf_nofl_err("ERROR: Unknown tlv\n"); 690 break; 691 } 692 h->cmd_num = 693 HAL_GET_FIELD( 694 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, 695 val1); 696 h->exec_time = 697 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 698 CMD_EXECUTION_TIME, val1); 699 h->status = 700 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 701 REO_CMD_EXECUTION_STATUS, val1); 702 switch (b) { 703 case HAL_REO_QUEUE_STATS_STATUS_TLV: 704 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, 705 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 706 break; 707 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 708 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, 709 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 710 break; 711 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 712 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, 713 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 714 break; 715 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 716 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, 717 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 718 break; 719 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 720 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, 721 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 722 break; 723 case HAL_REO_DESC_THRES_STATUS_TLV: 724 val1 = 725 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, 726 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 727 break; 728 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 729 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, 730 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 731 break; 732 default: 733 qdf_nofl_err("ERROR: Unknown tlv\n"); 734 break; 735 } 736 h->tstamp = 737 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); 738 } 739 740 /** 741 * hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v2() - 742 * Retrieve qos control valid bit from the tlv. 743 * @buf: pointer to rx pkt TLV. 744 * 745 * Return: qos control value. 746 */ 747 static inline uint32_t 748 hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v2(uint8_t *buf) 749 { 750 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 751 struct rx_mpdu_start *mpdu_start = 752 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 753 754 return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET( 755 &mpdu_start->rx_mpdu_info_details); 756 } 757 758 /** 759 * hal_rx_msdu_end_sa_sw_peer_id_get_8074v2() - API to get the sa_sw_peer_id 760 * from rx_msdu_end TLV 761 * @buf: pointer to the start of RX PKT TLV headers 762 * 763 * Return: sa_sw_peer_id index 764 */ 765 static inline uint32_t 766 hal_rx_msdu_end_sa_sw_peer_id_get_8074v2(uint8_t *buf) 767 { 768 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 769 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 770 771 return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 772 } 773 774 /** 775 * hal_tx_desc_set_mesh_en_8074v2() - Set mesh_enable flag in Tx descriptor 776 * @desc: Handle to Tx Descriptor 777 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 778 * enabling the interpretation of the 'Mesh Control Present' bit 779 * (bit 8) of QoS Control (otherwise this bit is ignored), 780 * For native WiFi frames, this indicates that a 'Mesh Control' field 781 * is present between the header and the LLC. 782 * 783 * Return: void 784 */ 785 static inline 786 void hal_tx_desc_set_mesh_en_8074v2(void *desc, uint8_t en) 787 { 788 HAL_SET_FLD(desc, TCL_DATA_CMD_4, MESH_ENABLE) |= 789 HAL_TX_SM(TCL_DATA_CMD_4, MESH_ENABLE, en); 790 } 791 792 static 793 void *hal_rx_msdu0_buffer_addr_lsb_8074v2(void *link_desc_va) 794 { 795 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 796 } 797 798 static 799 void *hal_rx_msdu_desc_info_ptr_get_8074v2(void *msdu0) 800 { 801 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 802 } 803 804 static 805 void *hal_ent_mpdu_desc_info_8074v2(void *ent_ring_desc) 806 { 807 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 808 } 809 810 static 811 void *hal_dst_mpdu_desc_info_8074v2(void *dst_ring_desc) 812 { 813 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 814 } 815 816 static 817 uint8_t hal_rx_get_fc_valid_8074v2(uint8_t *buf) 818 { 819 return HAL_RX_GET_FC_VALID(buf); 820 } 821 822 static uint8_t hal_rx_get_to_ds_flag_8074v2(uint8_t *buf) 823 { 824 return HAL_RX_GET_TO_DS_FLAG(buf); 825 } 826 827 static uint8_t hal_rx_get_mac_addr2_valid_8074v2(uint8_t *buf) 828 { 829 return HAL_RX_GET_MAC_ADDR2_VALID(buf); 830 } 831 832 static uint8_t hal_rx_get_filter_category_8074v2(uint8_t *buf) 833 { 834 return HAL_RX_GET_FILTER_CATEGORY(buf); 835 } 836 837 static uint32_t 838 hal_rx_get_ppdu_id_8074v2(uint8_t *buf) 839 { 840 struct rx_mpdu_info *rx_mpdu_info; 841 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)buf; 842 843 rx_mpdu_info = 844 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 845 846 return HAL_RX_GET_PPDU_ID(rx_mpdu_info); 847 } 848 849 /** 850 * hal_reo_config_8074v2() - Set reo config parameters 851 * @soc: hal soc handle 852 * @reg_val: value to be set 853 * @reo_params: reo parameters 854 * 855 * Return: void 856 */ 857 static void 858 hal_reo_config_8074v2(struct hal_soc *soc, 859 uint32_t reg_val, 860 struct hal_reo_params *reo_params) 861 { 862 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 863 } 864 865 /** 866 * hal_rx_msdu_desc_info_get_ptr_8074v2() - Get msdu desc info ptr 867 * @msdu_details_ptr: Pointer to msdu_details_ptr 868 * 869 * Return: Pointer to rx_msdu_desc_info structure. 870 * 871 */ 872 static void *hal_rx_msdu_desc_info_get_ptr_8074v2(void *msdu_details_ptr) 873 { 874 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 875 } 876 877 /** 878 * hal_rx_link_desc_msdu0_ptr_8074v2() - Get pointer to rx_msdu details 879 * @link_desc: Pointer to link desc 880 * 881 * Return: Pointer to rx_msdu_details structure 882 */ 883 static void *hal_rx_link_desc_msdu0_ptr_8074v2(void *link_desc) 884 { 885 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 886 } 887 888 /** 889 * hal_rx_msdu_flow_idx_get_8074v2() - API to get flow index 890 * from rx_msdu_end TLV 891 * @buf: pointer to the start of RX PKT TLV headers 892 * 893 * Return: flow index value from MSDU END TLV 894 */ 895 static inline uint32_t hal_rx_msdu_flow_idx_get_8074v2(uint8_t *buf) 896 { 897 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 898 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 899 900 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 901 } 902 903 /** 904 * hal_rx_msdu_flow_idx_invalid_8074v2() - API to get flow index invalid 905 * from rx_msdu_end TLV 906 * @buf: pointer to the start of RX PKT TLV headers 907 * 908 * Return: flow index invalid value from MSDU END TLV 909 */ 910 static bool hal_rx_msdu_flow_idx_invalid_8074v2(uint8_t *buf) 911 { 912 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 913 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 914 915 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 916 } 917 918 /** 919 * hal_rx_msdu_flow_idx_timeout_8074v2() - API to get flow index timeout 920 * from rx_msdu_end TLV 921 * @buf: pointer to the start of RX PKT TLV headers 922 * 923 * Return: flow index timeout value from MSDU END TLV 924 */ 925 static bool hal_rx_msdu_flow_idx_timeout_8074v2(uint8_t *buf) 926 { 927 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 928 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 929 930 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 931 } 932 933 /** 934 * hal_rx_msdu_fse_metadata_get_8074v2() - API to get FSE metadata 935 * from rx_msdu_end TLV 936 * @buf: pointer to the start of RX PKT TLV headers 937 * 938 * Return: fse metadata value from MSDU END TLV 939 */ 940 static uint32_t hal_rx_msdu_fse_metadata_get_8074v2(uint8_t *buf) 941 { 942 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 943 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 944 945 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end); 946 } 947 948 /** 949 * hal_rx_msdu_cce_metadata_get_8074v2() - API to get CCE metadata 950 * from rx_msdu_end TLV 951 * @buf: pointer to the start of RX PKT TLV headers 952 * 953 * Return: cce_metadata 954 */ 955 static uint16_t 956 hal_rx_msdu_cce_metadata_get_8074v2(uint8_t *buf) 957 { 958 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 959 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 960 961 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end); 962 } 963 964 /** 965 * hal_rx_msdu_get_flow_params_8074v2() - API to get flow index, flow index 966 * invalid and flow index timeout from 967 * rx_msdu_end TLV 968 * @buf: pointer to the start of RX PKT TLV headers 969 * @flow_invalid: pointer to return value of flow_idx_valid 970 * @flow_timeout: pointer to return value of flow_idx_timeout 971 * @flow_index: pointer to return value of flow_idx 972 * 973 * Return: none 974 */ 975 static inline void 976 hal_rx_msdu_get_flow_params_8074v2(uint8_t *buf, 977 bool *flow_invalid, 978 bool *flow_timeout, 979 uint32_t *flow_index) 980 { 981 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 982 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 983 984 *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 985 *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 986 *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 987 } 988 989 /** 990 * hal_rx_tlv_get_tcp_chksum_8074v2() - API to get tcp checksum 991 * @buf: rx_tlv_hdr 992 * 993 * Return: tcp checksum 994 */ 995 static uint16_t 996 hal_rx_tlv_get_tcp_chksum_8074v2(uint8_t *buf) 997 { 998 return HAL_RX_TLV_GET_TCP_CHKSUM(buf); 999 } 1000 1001 /** 1002 * hal_rx_get_rx_sequence_8074v2() - Function to retrieve rx sequence number 1003 * @buf: Network buffer 1004 * 1005 * Return: rx sequence number 1006 */ 1007 static 1008 uint16_t hal_rx_get_rx_sequence_8074v2(uint8_t *buf) 1009 { 1010 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 1011 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 1012 1013 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info); 1014 } 1015 1016 /** 1017 * hal_get_window_address_8074v2() - Function to get hp/tp address 1018 * @hal_soc: Pointer to hal_soc 1019 * @addr: address offset of register 1020 * 1021 * Return: modified address offset of register 1022 */ 1023 static inline qdf_iomem_t hal_get_window_address_8074v2(struct hal_soc *hal_soc, 1024 qdf_iomem_t addr) 1025 { 1026 return addr; 1027 } 1028 1029 /** 1030 * hal_rx_mpdu_start_tlv_tag_valid_8074v2 () - API to check if RX_MPDU_START 1031 * tlv tag is valid 1032 * 1033 * @rx_tlv_hdr: start address of rx_pkt_tlvs 1034 * 1035 * Return: true if RX_MPDU_START is valid, else false. 1036 */ 1037 uint8_t hal_rx_mpdu_start_tlv_tag_valid_8074v2(void *rx_tlv_hdr) 1038 { 1039 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 1040 uint32_t tlv_tag; 1041 1042 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(&rx_desc->mpdu_start_tlv); 1043 1044 return tlv_tag == WIFIRX_MPDU_START_E ? true : false; 1045 } 1046 1047 /** 1048 * hal_rx_flow_setup_fse_8074v2() - Setup a flow search entry in HW FST 1049 * @rx_fst: Pointer to the Rx Flow Search Table 1050 * @table_offset: offset into the table where the flow is to be setup 1051 * @rx_flow: Flow Parameters 1052 * 1053 * Return: Success/Failure 1054 */ 1055 static void * 1056 hal_rx_flow_setup_fse_8074v2(uint8_t *rx_fst, uint32_t table_offset, 1057 uint8_t *rx_flow) 1058 { 1059 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 1060 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 1061 uint8_t *fse; 1062 bool fse_valid; 1063 1064 if (table_offset >= fst->max_entries) { 1065 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 1066 "HAL FSE table offset %u exceeds max entries %u", 1067 table_offset, fst->max_entries); 1068 return NULL; 1069 } 1070 1071 fse = (uint8_t *)fst->base_vaddr + 1072 (table_offset * HAL_RX_FST_ENTRY_SIZE); 1073 1074 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1075 1076 if (fse_valid) { 1077 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 1078 "HAL FSE %pK already valid", fse); 1079 return NULL; 1080 } 1081 1082 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96) = 1083 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96, 1084 qdf_htonl(flow->tuple_info.src_ip_127_96)); 1085 1086 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64) = 1087 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64, 1088 qdf_htonl(flow->tuple_info.src_ip_95_64)); 1089 1090 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32) = 1091 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32, 1092 qdf_htonl(flow->tuple_info.src_ip_63_32)); 1093 1094 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0) = 1095 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0, 1096 qdf_htonl(flow->tuple_info.src_ip_31_0)); 1097 1098 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96) = 1099 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96, 1100 qdf_htonl(flow->tuple_info.dest_ip_127_96)); 1101 1102 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64) = 1103 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64, 1104 qdf_htonl(flow->tuple_info.dest_ip_95_64)); 1105 1106 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32) = 1107 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32, 1108 qdf_htonl(flow->tuple_info.dest_ip_63_32)); 1109 1110 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0) = 1111 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0, 1112 qdf_htonl(flow->tuple_info.dest_ip_31_0)); 1113 1114 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT); 1115 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT) |= 1116 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, DEST_PORT, 1117 (flow->tuple_info.dest_port)); 1118 1119 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT); 1120 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT) |= 1121 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, SRC_PORT, 1122 (flow->tuple_info.src_port)); 1123 1124 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL); 1125 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL) |= 1126 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL, 1127 flow->tuple_info.l4_protocol); 1128 1129 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER); 1130 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER) |= 1131 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER, 1132 flow->reo_destination_handler); 1133 1134 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1135 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID) |= 1136 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, VALID, 1); 1137 1138 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA); 1139 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA) = 1140 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_10, METADATA, 1141 flow->fse_metadata); 1142 1143 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, REO_DESTINATION_INDICATION); 1144 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, REO_DESTINATION_INDICATION) |= 1145 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_11, 1146 REO_DESTINATION_INDICATION, 1147 flow->reo_destination_indication); 1148 1149 /* Reset all the other fields in FSE */ 1150 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, RESERVED_9); 1151 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_DROP); 1152 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, RESERVED_11); 1153 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_COUNT); 1154 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_12, MSDU_BYTE_COUNT); 1155 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_13, TIMESTAMP); 1156 1157 return fse; 1158 } 1159 1160 static 1161 void hal_compute_reo_remap_ix2_ix3_8074v2(uint32_t *ring, uint32_t num_rings, 1162 uint32_t *remap1, uint32_t *remap2) 1163 { 1164 switch (num_rings) { 1165 case 1: 1166 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1167 HAL_REO_REMAP_IX2(ring[0], 17) | 1168 HAL_REO_REMAP_IX2(ring[0], 18) | 1169 HAL_REO_REMAP_IX2(ring[0], 19) | 1170 HAL_REO_REMAP_IX2(ring[0], 20) | 1171 HAL_REO_REMAP_IX2(ring[0], 21) | 1172 HAL_REO_REMAP_IX2(ring[0], 22) | 1173 HAL_REO_REMAP_IX2(ring[0], 23); 1174 1175 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1176 HAL_REO_REMAP_IX3(ring[0], 25) | 1177 HAL_REO_REMAP_IX3(ring[0], 26) | 1178 HAL_REO_REMAP_IX3(ring[0], 27) | 1179 HAL_REO_REMAP_IX3(ring[0], 28) | 1180 HAL_REO_REMAP_IX3(ring[0], 29) | 1181 HAL_REO_REMAP_IX3(ring[0], 30) | 1182 HAL_REO_REMAP_IX3(ring[0], 31); 1183 break; 1184 case 2: 1185 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1186 HAL_REO_REMAP_IX2(ring[0], 17) | 1187 HAL_REO_REMAP_IX2(ring[1], 18) | 1188 HAL_REO_REMAP_IX2(ring[1], 19) | 1189 HAL_REO_REMAP_IX2(ring[0], 20) | 1190 HAL_REO_REMAP_IX2(ring[0], 21) | 1191 HAL_REO_REMAP_IX2(ring[1], 22) | 1192 HAL_REO_REMAP_IX2(ring[1], 23); 1193 1194 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1195 HAL_REO_REMAP_IX3(ring[0], 25) | 1196 HAL_REO_REMAP_IX3(ring[1], 26) | 1197 HAL_REO_REMAP_IX3(ring[1], 27) | 1198 HAL_REO_REMAP_IX3(ring[0], 28) | 1199 HAL_REO_REMAP_IX3(ring[0], 29) | 1200 HAL_REO_REMAP_IX3(ring[1], 30) | 1201 HAL_REO_REMAP_IX3(ring[1], 31); 1202 break; 1203 case 3: 1204 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1205 HAL_REO_REMAP_IX2(ring[1], 17) | 1206 HAL_REO_REMAP_IX2(ring[2], 18) | 1207 HAL_REO_REMAP_IX2(ring[0], 19) | 1208 HAL_REO_REMAP_IX2(ring[1], 20) | 1209 HAL_REO_REMAP_IX2(ring[2], 21) | 1210 HAL_REO_REMAP_IX2(ring[0], 22) | 1211 HAL_REO_REMAP_IX2(ring[1], 23); 1212 1213 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) | 1214 HAL_REO_REMAP_IX3(ring[0], 25) | 1215 HAL_REO_REMAP_IX3(ring[1], 26) | 1216 HAL_REO_REMAP_IX3(ring[2], 27) | 1217 HAL_REO_REMAP_IX3(ring[0], 28) | 1218 HAL_REO_REMAP_IX3(ring[1], 29) | 1219 HAL_REO_REMAP_IX3(ring[2], 30) | 1220 HAL_REO_REMAP_IX3(ring[0], 31); 1221 break; 1222 case 4: 1223 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1224 HAL_REO_REMAP_IX2(ring[1], 17) | 1225 HAL_REO_REMAP_IX2(ring[2], 18) | 1226 HAL_REO_REMAP_IX2(ring[3], 19) | 1227 HAL_REO_REMAP_IX2(ring[0], 20) | 1228 HAL_REO_REMAP_IX2(ring[1], 21) | 1229 HAL_REO_REMAP_IX2(ring[2], 22) | 1230 HAL_REO_REMAP_IX2(ring[3], 23); 1231 1232 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1233 HAL_REO_REMAP_IX3(ring[1], 25) | 1234 HAL_REO_REMAP_IX3(ring[2], 26) | 1235 HAL_REO_REMAP_IX3(ring[3], 27) | 1236 HAL_REO_REMAP_IX3(ring[0], 28) | 1237 HAL_REO_REMAP_IX3(ring[1], 29) | 1238 HAL_REO_REMAP_IX3(ring[2], 30) | 1239 HAL_REO_REMAP_IX3(ring[3], 31); 1240 break; 1241 } 1242 } 1243 1244 static void hal_hw_txrx_ops_attach_qca8074v2(struct hal_soc *hal_soc) 1245 { 1246 1247 /* init and setup */ 1248 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic; 1249 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic; 1250 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic; 1251 hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_li; 1252 hal_soc->ops->hal_get_window_address = hal_get_window_address_8074v2; 1253 1254 /* tx */ 1255 hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id = 1256 hal_tx_desc_set_dscp_tid_table_id_8074v2; 1257 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_8074v2; 1258 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_8074v2; 1259 hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_8074v2; 1260 hal_soc->ops->hal_tx_desc_set_buf_addr = 1261 hal_tx_desc_set_buf_addr_generic_li; 1262 hal_soc->ops->hal_tx_desc_set_search_type = 1263 hal_tx_desc_set_search_type_generic_li; 1264 hal_soc->ops->hal_tx_desc_set_search_index = 1265 hal_tx_desc_set_search_index_generic_li; 1266 hal_soc->ops->hal_tx_desc_set_cache_set_num = 1267 hal_tx_desc_set_cache_set_num_generic_li; 1268 hal_soc->ops->hal_tx_comp_get_status = 1269 hal_tx_comp_get_status_generic_li; 1270 hal_soc->ops->hal_tx_comp_get_release_reason = 1271 hal_tx_comp_get_release_reason_generic_li; 1272 hal_soc->ops->hal_get_wbm_internal_error = 1273 hal_get_wbm_internal_error_generic_li; 1274 hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_8074v2; 1275 hal_soc->ops->hal_tx_init_cmd_credit_ring = 1276 hal_tx_init_cmd_credit_ring_8074v2; 1277 1278 /* rx */ 1279 hal_soc->ops->hal_rx_msdu_start_nss_get = 1280 hal_rx_msdu_start_nss_get_8074v2; 1281 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status = 1282 hal_rx_mon_hw_desc_get_mpdu_status_8074v2; 1283 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_8074v2; 1284 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv = 1285 hal_rx_proc_phyrx_other_receive_info_tlv_8074v2; 1286 hal_soc->ops->hal_rx_dump_msdu_start_tlv = 1287 hal_rx_dump_msdu_start_tlv_8074v2; 1288 hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_8074v2; 1289 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_8074v2; 1290 hal_soc->ops->hal_rx_mpdu_start_tid_get = 1291 hal_rx_mpdu_start_tid_get_8074v2; 1292 hal_soc->ops->hal_rx_msdu_start_reception_type_get = 1293 hal_rx_msdu_start_reception_type_get_8074v2; 1294 hal_soc->ops->hal_rx_msdu_end_da_idx_get = 1295 hal_rx_msdu_end_da_idx_get_8074v2; 1296 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = 1297 hal_rx_msdu_desc_info_get_ptr_8074v2; 1298 hal_soc->ops->hal_rx_link_desc_msdu0_ptr = 1299 hal_rx_link_desc_msdu0_ptr_8074v2; 1300 hal_soc->ops->hal_reo_status_get_header = 1301 hal_reo_status_get_header_8074v2; 1302 hal_soc->ops->hal_rx_status_get_tlv_info = 1303 hal_rx_status_get_tlv_info_generic_li; 1304 hal_soc->ops->hal_rx_wbm_err_info_get = 1305 hal_rx_wbm_err_info_get_generic_li; 1306 hal_soc->ops->hal_rx_dump_mpdu_start_tlv = 1307 hal_rx_dump_mpdu_start_tlv_generic_li; 1308 1309 hal_soc->ops->hal_tx_set_pcp_tid_map = 1310 hal_tx_set_pcp_tid_map_generic_li; 1311 hal_soc->ops->hal_tx_update_pcp_tid_map = 1312 hal_tx_update_pcp_tid_generic_li; 1313 hal_soc->ops->hal_tx_set_tidmap_prty = 1314 hal_tx_update_tidmap_prty_generic_li; 1315 hal_soc->ops->hal_rx_get_rx_fragment_number = 1316 hal_rx_get_rx_fragment_number_8074v2; 1317 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = 1318 hal_rx_msdu_end_da_is_mcbc_get_8074v2; 1319 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = 1320 hal_rx_msdu_end_sa_is_valid_get_8074v2; 1321 hal_soc->ops->hal_rx_msdu_end_sa_idx_get = 1322 hal_rx_msdu_end_sa_idx_get_8074v2; 1323 hal_soc->ops->hal_rx_desc_is_first_msdu = 1324 hal_rx_desc_is_first_msdu_8074v2; 1325 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get = 1326 hal_rx_msdu_end_l3_hdr_padding_get_8074v2; 1327 hal_soc->ops->hal_rx_encryption_info_valid = 1328 hal_rx_encryption_info_valid_8074v2; 1329 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_8074v2; 1330 hal_soc->ops->hal_rx_msdu_end_first_msdu_get = 1331 hal_rx_msdu_end_first_msdu_get_8074v2; 1332 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = 1333 hal_rx_msdu_end_da_is_valid_get_8074v2; 1334 hal_soc->ops->hal_rx_msdu_end_last_msdu_get = 1335 hal_rx_msdu_end_last_msdu_get_8074v2; 1336 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = 1337 hal_rx_get_mpdu_mac_ad4_valid_8074v2; 1338 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get = 1339 hal_rx_mpdu_start_sw_peer_id_get_8074v2; 1340 hal_soc->ops->hal_rx_tlv_peer_meta_data_get = 1341 hal_rx_mpdu_peer_meta_data_get_li; 1342 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_8074v2; 1343 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_8074v2; 1344 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid = 1345 hal_rx_get_mpdu_frame_control_valid_8074v2; 1346 hal_soc->ops->hal_rx_get_frame_ctrl_field = 1347 hal_rx_get_mpdu_frame_control_field_8074v2; 1348 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_8074v2; 1349 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_8074v2; 1350 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_8074v2; 1351 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_8074v2; 1352 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid = 1353 hal_rx_get_mpdu_sequence_control_valid_8074v2; 1354 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_8074v2; 1355 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_8074v2; 1356 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = 1357 hal_rx_hw_desc_get_ppduid_get_8074v2; 1358 hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get = 1359 hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v2; 1360 hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get = 1361 hal_rx_msdu_end_sa_sw_peer_id_get_8074v2; 1362 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = 1363 hal_rx_msdu0_buffer_addr_lsb_8074v2; 1364 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = 1365 hal_rx_msdu_desc_info_ptr_get_8074v2; 1366 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_8074v2; 1367 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_8074v2; 1368 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_8074v2; 1369 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_8074v2; 1370 hal_soc->ops->hal_rx_get_mac_addr2_valid = 1371 hal_rx_get_mac_addr2_valid_8074v2; 1372 hal_soc->ops->hal_rx_get_filter_category = 1373 hal_rx_get_filter_category_8074v2; 1374 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_8074v2; 1375 hal_soc->ops->hal_reo_config = hal_reo_config_8074v2; 1376 hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_8074v2; 1377 hal_soc->ops->hal_rx_msdu_flow_idx_invalid = 1378 hal_rx_msdu_flow_idx_invalid_8074v2; 1379 hal_soc->ops->hal_rx_msdu_flow_idx_timeout = 1380 hal_rx_msdu_flow_idx_timeout_8074v2; 1381 hal_soc->ops->hal_rx_msdu_fse_metadata_get = 1382 hal_rx_msdu_fse_metadata_get_8074v2; 1383 hal_soc->ops->hal_rx_msdu_cce_match_get = 1384 hal_rx_msdu_cce_match_get_li; 1385 hal_soc->ops->hal_rx_msdu_cce_metadata_get = 1386 hal_rx_msdu_cce_metadata_get_8074v2; 1387 hal_soc->ops->hal_rx_msdu_get_flow_params = 1388 hal_rx_msdu_get_flow_params_8074v2; 1389 hal_soc->ops->hal_rx_tlv_get_tcp_chksum = 1390 hal_rx_tlv_get_tcp_chksum_8074v2; 1391 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_8074v2; 1392 #if defined(QCA_WIFI_QCA6018) && defined(WLAN_CFR_ENABLE) && \ 1393 defined(WLAN_ENH_CFR_ENABLE) 1394 hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_8074v2; 1395 hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_8074v2; 1396 #endif 1397 /* rx - msdu fast path info fields */ 1398 hal_soc->ops->hal_rx_msdu_packet_metadata_get = 1399 hal_rx_msdu_packet_metadata_get_generic_li; 1400 hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid = 1401 hal_rx_mpdu_start_tlv_tag_valid_8074v2; 1402 1403 /* rx - TLV struct offsets */ 1404 hal_soc->ops->hal_rx_msdu_end_offset_get = 1405 hal_rx_msdu_end_offset_get_generic; 1406 hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic; 1407 hal_soc->ops->hal_rx_msdu_start_offset_get = 1408 hal_rx_msdu_start_offset_get_generic; 1409 hal_soc->ops->hal_rx_mpdu_start_offset_get = 1410 hal_rx_mpdu_start_offset_get_generic; 1411 hal_soc->ops->hal_rx_mpdu_end_offset_get = 1412 hal_rx_mpdu_end_offset_get_generic; 1413 #ifndef NO_RX_PKT_HDR_TLV 1414 hal_soc->ops->hal_rx_pkt_tlv_offset_get = 1415 hal_rx_pkt_tlv_offset_get_generic; 1416 #endif 1417 hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_8074v2; 1418 hal_soc->ops->hal_rx_flow_get_tuple_info = 1419 hal_rx_flow_get_tuple_info_li; 1420 hal_soc->ops->hal_rx_flow_delete_entry = 1421 hal_rx_flow_delete_entry_li; 1422 hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_li; 1423 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = 1424 hal_compute_reo_remap_ix2_ix3_8074v2; 1425 hal_soc->ops->hal_setup_link_idle_list = 1426 hal_setup_link_idle_list_generic_li; 1427 hal_soc->ops->hal_compute_reo_remap_ix0 = NULL; 1428 }; 1429 1430 struct hal_hw_srng_config hw_srng_table_8074v2[] = { 1431 /* TODO: max_rings can populated by querying HW capabilities */ 1432 { /* REO_DST */ 1433 .start_ring_id = HAL_SRNG_REO2SW1, 1434 .max_rings = 4, 1435 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1436 .lmac_ring = FALSE, 1437 .ring_dir = HAL_SRNG_DST_RING, 1438 .reg_start = { 1439 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 1440 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1441 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 1442 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1443 }, 1444 .reg_size = { 1445 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 1446 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 1447 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 1448 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 1449 }, 1450 .max_size = 1451 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 1452 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 1453 }, 1454 { /* REO_EXCEPTION */ 1455 /* Designating REO2TCL ring as exception ring. This ring is 1456 * similar to other REO2SW rings though it is named as REO2TCL. 1457 * Any of theREO2SW rings can be used as exception ring. 1458 */ 1459 .start_ring_id = HAL_SRNG_REO2TCL, 1460 .max_rings = 1, 1461 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1462 .lmac_ring = FALSE, 1463 .ring_dir = HAL_SRNG_DST_RING, 1464 .reg_start = { 1465 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 1466 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1467 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 1468 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1469 }, 1470 /* Single ring - provide ring size if multiple rings of this 1471 * type are supported 1472 */ 1473 .reg_size = {}, 1474 .max_size = 1475 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 1476 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 1477 }, 1478 { /* REO_REINJECT */ 1479 .start_ring_id = HAL_SRNG_SW2REO, 1480 .max_rings = 1, 1481 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1482 .lmac_ring = FALSE, 1483 .ring_dir = HAL_SRNG_SRC_RING, 1484 .reg_start = { 1485 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 1486 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1487 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 1488 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1489 }, 1490 /* Single ring - provide ring size if multiple rings of this 1491 * type are supported 1492 */ 1493 .reg_size = {}, 1494 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 1495 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 1496 }, 1497 { /* REO_CMD */ 1498 .start_ring_id = HAL_SRNG_REO_CMD, 1499 .max_rings = 1, 1500 .entry_size = (sizeof(struct tlv_32_hdr) + 1501 sizeof(struct reo_get_queue_stats)) >> 2, 1502 .lmac_ring = FALSE, 1503 .ring_dir = HAL_SRNG_SRC_RING, 1504 .reg_start = { 1505 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 1506 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1507 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 1508 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1509 }, 1510 /* Single ring - provide ring size if multiple rings of this 1511 * type are supported 1512 */ 1513 .reg_size = {}, 1514 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1515 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1516 }, 1517 { /* REO_STATUS */ 1518 .start_ring_id = HAL_SRNG_REO_STATUS, 1519 .max_rings = 1, 1520 .entry_size = (sizeof(struct tlv_32_hdr) + 1521 sizeof(struct reo_get_queue_stats_status)) >> 2, 1522 .lmac_ring = FALSE, 1523 .ring_dir = HAL_SRNG_DST_RING, 1524 .reg_start = { 1525 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 1526 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1527 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 1528 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1529 }, 1530 /* Single ring - provide ring size if multiple rings of this 1531 * type are supported 1532 */ 1533 .reg_size = {}, 1534 .max_size = 1535 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1536 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1537 }, 1538 { /* TCL_DATA */ 1539 .start_ring_id = HAL_SRNG_SW2TCL1, 1540 .max_rings = 3, 1541 .entry_size = (sizeof(struct tlv_32_hdr) + 1542 sizeof(struct tcl_data_cmd)) >> 2, 1543 .lmac_ring = FALSE, 1544 .ring_dir = HAL_SRNG_SRC_RING, 1545 .reg_start = { 1546 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 1547 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1548 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 1549 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1550 }, 1551 .reg_size = { 1552 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 1553 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 1554 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 1555 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 1556 }, 1557 .max_size = 1558 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 1559 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 1560 }, 1561 { /* TCL_CMD */ 1562 /* qca8074v2 and qcn9000 uses this ring for data commands */ 1563 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 1564 .max_rings = 1, 1565 .entry_size = (sizeof(struct tlv_32_hdr) + 1566 sizeof(struct tcl_data_cmd)) >> 2, 1567 .lmac_ring = FALSE, 1568 .ring_dir = HAL_SRNG_SRC_RING, 1569 .reg_start = { 1570 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR( 1571 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1572 HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR( 1573 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1574 }, 1575 /* Single ring - provide ring size if multiple rings of this 1576 * type are supported 1577 */ 1578 .reg_size = {}, 1579 .max_size = 1580 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1581 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1582 }, 1583 { /* TCL_STATUS */ 1584 .start_ring_id = HAL_SRNG_TCL_STATUS, 1585 .max_rings = 1, 1586 .entry_size = (sizeof(struct tlv_32_hdr) + 1587 sizeof(struct tcl_status_ring)) >> 2, 1588 .lmac_ring = FALSE, 1589 .ring_dir = HAL_SRNG_DST_RING, 1590 .reg_start = { 1591 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 1592 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1593 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 1594 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1595 }, 1596 /* Single ring - provide ring size if multiple rings of this 1597 * type are supported 1598 */ 1599 .reg_size = {}, 1600 .max_size = 1601 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 1602 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 1603 }, 1604 { /* CE_SRC */ 1605 .start_ring_id = HAL_SRNG_CE_0_SRC, 1606 .max_rings = 12, 1607 .entry_size = sizeof(struct ce_src_desc) >> 2, 1608 .lmac_ring = FALSE, 1609 .ring_dir = HAL_SRNG_SRC_RING, 1610 .reg_start = { 1611 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1612 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1613 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1614 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1615 }, 1616 .reg_size = { 1617 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1618 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1619 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1620 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1621 }, 1622 .max_size = 1623 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1624 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1625 }, 1626 { /* CE_DST */ 1627 .start_ring_id = HAL_SRNG_CE_0_DST, 1628 .max_rings = 12, 1629 .entry_size = 8 >> 2, 1630 /*TODO: entry_size above should actually be 1631 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 1632 * of struct ce_dst_desc in HW header files 1633 */ 1634 .lmac_ring = FALSE, 1635 .ring_dir = HAL_SRNG_SRC_RING, 1636 .reg_start = { 1637 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1638 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1639 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1640 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1641 }, 1642 .reg_size = { 1643 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1644 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1645 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1646 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1647 }, 1648 .max_size = 1649 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1650 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1651 }, 1652 { /* CE_DST_STATUS */ 1653 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 1654 .max_rings = 12, 1655 .entry_size = sizeof(struct ce_stat_desc) >> 2, 1656 .lmac_ring = FALSE, 1657 .ring_dir = HAL_SRNG_DST_RING, 1658 .reg_start = { 1659 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 1660 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1661 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 1662 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1663 }, 1664 /* TODO: check destination status ring registers */ 1665 .reg_size = { 1666 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1667 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1668 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1669 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1670 }, 1671 .max_size = 1672 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1673 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1674 }, 1675 { /* WBM_IDLE_LINK */ 1676 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 1677 .max_rings = 1, 1678 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 1679 .lmac_ring = FALSE, 1680 .ring_dir = HAL_SRNG_SRC_RING, 1681 .reg_start = { 1682 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1683 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1684 }, 1685 /* Single ring - provide ring size if multiple rings of this 1686 * type are supported 1687 */ 1688 .reg_size = {}, 1689 .max_size = 1690 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 1691 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 1692 }, 1693 { /* SW2WBM_RELEASE */ 1694 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 1695 .max_rings = 1, 1696 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1697 .lmac_ring = FALSE, 1698 .ring_dir = HAL_SRNG_SRC_RING, 1699 .reg_start = { 1700 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1701 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1702 }, 1703 /* Single ring - provide ring size if multiple rings of this 1704 * type are supported 1705 */ 1706 .reg_size = {}, 1707 .max_size = 1708 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1709 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1710 }, 1711 { /* WBM2SW_RELEASE */ 1712 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 1713 .max_rings = 5, 1714 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1715 .lmac_ring = FALSE, 1716 .ring_dir = HAL_SRNG_DST_RING, 1717 .reg_start = { 1718 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1719 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1720 }, 1721 .reg_size = { 1722 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1723 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1724 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1725 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1726 }, 1727 .max_size = 1728 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1729 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1730 }, 1731 { /* RXDMA_BUF */ 1732 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 1733 #ifdef IPA_OFFLOAD 1734 .max_rings = 3, 1735 #else 1736 .max_rings = 2, 1737 #endif 1738 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1739 .lmac_ring = TRUE, 1740 .ring_dir = HAL_SRNG_SRC_RING, 1741 /* reg_start is not set because LMAC rings are not accessed 1742 * from host 1743 */ 1744 .reg_start = {}, 1745 .reg_size = {}, 1746 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1747 }, 1748 { /* RXDMA_DST */ 1749 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 1750 .max_rings = 1, 1751 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1752 .lmac_ring = TRUE, 1753 .ring_dir = HAL_SRNG_DST_RING, 1754 /* reg_start is not set because LMAC rings are not accessed 1755 * from host 1756 */ 1757 .reg_start = {}, 1758 .reg_size = {}, 1759 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1760 }, 1761 { /* RXDMA_MONITOR_BUF */ 1762 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 1763 .max_rings = 1, 1764 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1765 .lmac_ring = TRUE, 1766 .ring_dir = HAL_SRNG_SRC_RING, 1767 /* reg_start is not set because LMAC rings are not accessed 1768 * from host 1769 */ 1770 .reg_start = {}, 1771 .reg_size = {}, 1772 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1773 }, 1774 { /* RXDMA_MONITOR_STATUS */ 1775 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 1776 .max_rings = 1, 1777 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1778 .lmac_ring = TRUE, 1779 .ring_dir = HAL_SRNG_SRC_RING, 1780 /* reg_start is not set because LMAC rings are not accessed 1781 * from host 1782 */ 1783 .reg_start = {}, 1784 .reg_size = {}, 1785 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1786 }, 1787 { /* RXDMA_MONITOR_DST */ 1788 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 1789 .max_rings = 1, 1790 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1791 .lmac_ring = TRUE, 1792 .ring_dir = HAL_SRNG_DST_RING, 1793 /* reg_start is not set because LMAC rings are not accessed 1794 * from host 1795 */ 1796 .reg_start = {}, 1797 .reg_size = {}, 1798 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1799 }, 1800 { /* RXDMA_MONITOR_DESC */ 1801 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 1802 .max_rings = 1, 1803 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1804 .lmac_ring = TRUE, 1805 .ring_dir = HAL_SRNG_SRC_RING, 1806 /* reg_start is not set because LMAC rings are not accessed 1807 * from host 1808 */ 1809 .reg_start = {}, 1810 .reg_size = {}, 1811 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1812 }, 1813 { /* DIR_BUF_RX_DMA_SRC */ 1814 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 1815 /* one ring for spectral and one ring for cfr */ 1816 .max_rings = 2, 1817 .entry_size = 2, 1818 .lmac_ring = TRUE, 1819 .ring_dir = HAL_SRNG_SRC_RING, 1820 /* reg_start is not set because LMAC rings are not accessed 1821 * from host 1822 */ 1823 .reg_start = {}, 1824 .reg_size = {}, 1825 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1826 }, 1827 #ifdef WLAN_FEATURE_CIF_CFR 1828 { /* WIFI_POS_SRC */ 1829 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 1830 .max_rings = 1, 1831 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 1832 .lmac_ring = TRUE, 1833 .ring_dir = HAL_SRNG_SRC_RING, 1834 /* reg_start is not set because LMAC rings are not accessed 1835 * from host 1836 */ 1837 .reg_start = {}, 1838 .reg_size = {}, 1839 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1840 }, 1841 #endif 1842 { /* REO2PPE */ 0}, 1843 { /* PPE2TCL */ 0}, 1844 { /* PPE_RELEASE */ 0}, 1845 { /* TX_MONITOR_BUF */ 0}, 1846 { /* TX_MONITOR_DST */ 0}, 1847 { /* SW2RXDMA_NEW */ 0}, 1848 { /* SW2RXDMA_LINK_RELEASE */ 0}, 1849 }; 1850 1851 1852 /** 1853 * hal_qca8074v2_attach() - Attach 8074v2 target specific hal_soc ops, 1854 * offset and srng table 1855 * @hal_soc: HAL SoC context 1856 */ 1857 void hal_qca8074v2_attach(struct hal_soc *hal_soc) 1858 { 1859 hal_soc->hw_srng_table = hw_srng_table_8074v2; 1860 hal_srng_hw_reg_offset_init_generic(hal_soc); 1861 hal_hw_txrx_default_ops_attach_li(hal_soc); 1862 hal_hw_txrx_ops_attach_qca8074v2(hal_soc); 1863 } 1864